ARM: dts: msm: Add sdhc1 for SDM630 QRD

Add sdhc1 to enable eMMC support for SDM630 QRD.

CRs-Fixed: 2005010
Change-Id: I8d6c9f1479d7bde36b86b5e482085fef033795a1
Signed-off-by: xiaonian <xiaonian@codeaurora.org>

diff --git a/arch/arm/boot/dts/qcom/sdm630-qrd.dtsi b/arch/arm/boot/dts/qcom/sdm630-qrd.dtsi
index 6d3b95b..cfac30c 100644 (file)
--- a/arch/arm/boot/dts/qcom/sdm630-qrd.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm630-qrd.dtsi
@@ -41,5 +41,31 @@
        status = "ok";
 };
 
+&sdhc_1 {
+       /* device core power supply */
+       vdd-supply = <&pm660l_l4>;
+       qcom,vdd-voltage-level = <2950000 2950000>;
+       qcom,vdd-current-level = <200 570000>;
+
+       /* device communication power supply */
+       vdd-io-supply = <&pm660_l8>;
+       qcom,vdd-io-always-on;
+       qcom,vdd-io-lpm-sup;
+       qcom,vdd-io-voltage-level = <1800000 1800000>;
+       qcom,vdd-io-current-level = <200 325000>;
+
+       pinctrl-names = "active", "sleep";
+       pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+       pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+       qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000
+                                                               384000000>;
+
+       qcom,nonremovable;
+       qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+       status = "ok";
+};
+
 &soc {
 };