}
class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat,
- InstrItinClass itin = NoItinerary>
+ InstrItinClass itin>
: I<o, F, outs, ins, asm, pat, itin>, TB, Requires<[Has3DNow]> {
}
defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw", I3DNOW_MISC_FUNC_ITINS, 1>;
def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms",
- [(int_x86_mmx_femms)]>;
+ [(int_x86_mmx_femms)], IIC_MMX_EMMS>;
+let SchedRW = [WriteLoad] in {
def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i8mem:$addr),
"prefetch\t$addr",
- [(prefetch addr:$addr, (i32 0), imm, (i32 1))]>;
-
+ [(prefetch addr:$addr, (i32 0), imm, (i32 1))],
+ IIC_SSE_PREFETCH>;
def PREFETCHW : I<0x0D, MRM1m, (outs), (ins i8mem:$addr), "prefetchw\t$addr",
- [(prefetch addr:$addr, (i32 1), (i32 3), (i32 1))]>, TB,
- Requires<[HasPrefetchW]>;
+ [(prefetch addr:$addr, (i32 1), (i32 3), (i32 1))],
+ IIC_SSE_PREFETCH>, TB, Requires<[HasPrefetchW]>;
+}
// "3DNowA" instructions
defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", I3DNOW_FCVT_F2I_ITINS, "a">;
}
declare x86_mmx @llvm.x86.3dnow.pmulhrw(x86_mmx, x86_mmx) nounwind readnone
+define void @test_prefetch(i8* %a0) optsize {
+; CHECK-LABEL: test_prefetch:
+; CHECK: # BB#0:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: prefetch (%rdi) # sched: [5:0.50]
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: retq # sched: [1:1.00]
+ tail call void asm sideeffect "prefetch $0", "*m"(i8 *%a0) nounwind
+ ret void
+}
+
+define void @test_prefetchw(i8* %a0) optsize {
+; CHECK-LABEL: test_prefetchw:
+; CHECK: # BB#0:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: prefetchw (%rdi) # sched: [5:0.50]
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: retq # sched: [1:1.00]
+ tail call void asm sideeffect "prefetchw $0", "*m"(i8 *%a0) nounwind
+ ret void
+}
+
define i64 @test_pswapd(x86_mmx* %a0) optsize {
; CHECK-LABEL: test_pswapd:
; CHECK: # BB#0: