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i965: Fix source depth reg setting for FSes reading and writing to depth.
authorEric Anholt <eric@anholt.net>
Thu, 6 Aug 2009 03:12:15 +0000 (20:12 -0700)
committerEric Anholt <eric@anholt.net>
Thu, 6 Aug 2009 03:20:02 +0000 (20:20 -0700)
For some IZ setups, we'd forget to account for the source depth register
being present, so we'd both read the wrong reg, and write output depth to
the wrong reg.

Bug #22603.

src/mesa/drivers/dri/i965/brw_wm.c
src/mesa/drivers/dri/i965/brw_wm.h
src/mesa/drivers/dri/i965/brw_wm_iz.c

index 14e05be..d381add 100644 (file)
@@ -202,6 +202,7 @@ static void brw_wm_populate_key( struct brw_context *brw,
    /* BRW_NEW_FRAGMENT_PROGRAM */
    const struct brw_fragment_program *fp = 
       (struct brw_fragment_program *)brw->fragment_program;
+   GLboolean uses_depth = (fp->program.Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
    GLuint lookup = 0;
    GLuint line_aa;
    GLuint i;
@@ -263,6 +264,7 @@ static void brw_wm_populate_key( struct brw_context *brw,
         
    brw_wm_lookup_iz(line_aa,
                    lookup,
+                   uses_depth,
                    key);
 
 
index ba49743..9eda2cb 100644 (file)
@@ -292,6 +292,7 @@ void brw_wm_print_program( struct brw_wm_compile *c,
 
 void brw_wm_lookup_iz( GLuint line_aa,
                       GLuint lookup,
+                      GLboolean ps_uses_depth,
                       struct brw_wm_prog_key *key );
 
 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp);
index 8fd067a..5e399ac 100644 (file)
@@ -122,6 +122,7 @@ const struct {
  */
 void brw_wm_lookup_iz( GLuint line_aa,
                       GLuint lookup,
+                      GLboolean ps_uses_depth,
                       struct brw_wm_prog_key *key )
 {
    GLuint reg = 2;
@@ -131,7 +132,7 @@ void brw_wm_lookup_iz( GLuint line_aa,
    if (lookup & IZ_PS_COMPUTES_DEPTH_BIT)
       key->computes_depth = 1;
 
-   if (wm_iz_table[lookup].sd_present) {
+   if (wm_iz_table[lookup].sd_present || ps_uses_depth) {
       key->source_depth_reg = reg;
       reg += 2;
    }