clocksource/drivers/exynos_mct: Bump up mct max irq number

Bump-up maximum number of MCT IRQ to match the binding
documentation. This make driver scalable for SoC which
has more than 12 timer irqs, like recently added FSD SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20220221174547.26176-2-alim.akhtar@samsung.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>

diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 341ee47..bcf2100 100644 (file)
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -64,7 +64,8 @@
 #define MCT_G0_IRQ     0
 /* Local timers count starts after global timer count */
 #define MCT_L0_IRQ     4
-#define MCT_NR_IRQS    12
+/* Max number of IRQ as per DT binding document */
+#define MCT_NR_IRQS    20
 
 enum {
        MCT_INT_SPI,