: &ARM::ValueMappings[ARM::SPR3OpsIdx];
break;
}
+ case G_FMA: {
+ LLT Ty = MRI.getType(MI.getOperand(0).getReg());
+ OperandsMapping =
+ Ty.getSizeInBits() == 64
+ ? getOperandsMapping({&ARM::ValueMappings[ARM::DPR3OpsIdx],
+ &ARM::ValueMappings[ARM::DPR3OpsIdx],
+ &ARM::ValueMappings[ARM::DPR3OpsIdx],
+ &ARM::ValueMappings[ARM::DPR3OpsIdx]})
+ : getOperandsMapping({&ARM::ValueMappings[ARM::SPR3OpsIdx],
+ &ARM::ValueMappings[ARM::SPR3OpsIdx],
+ &ARM::ValueMappings[ARM::SPR3OpsIdx],
+ &ARM::ValueMappings[ARM::SPR3OpsIdx]});
+ break;
+ }
case G_CONSTANT:
case G_FRAME_INDEX:
case G_GLOBAL_VALUE:
define void @test_fneg_s32() #0 { ret void }
define void @test_fneg_s64() #0 { ret void }
+ define void @test_fma_s32() #2 { ret void }
+ define void @test_fma_s64() #2 { ret void }
+
define void @test_soft_fp_s64() #0 { ret void }
attributes #0 = { "target-features"="+vfp2"}
attributes #1 = { "target-features"="+hwdiv-arm" }
+ attributes #2 = { "target-features"="+vfp4"}
...
---
name: test_add_s32
# CHECK: registers:
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
-
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
# CHECK: registers:
# CHECK: - { id: 0, class: fprb, preferred-register: '' }
# CHECK: - { id: 1, class: fprb, preferred-register: '' }
-
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
...
---
+name: test_fma_s32
+# CHECK-LABEL: name: test_fma_s32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+# CHECK: - { id: 2, class: fprb, preferred-register: '' }
+# CHECK: - { id: 3, class: fprb, preferred-register: '' }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+body: |
+ bb.0:
+ liveins: %s0, %s1, %s2
+
+ %0(s32) = COPY %s0
+ %1(s32) = COPY %s1
+ %2(s32) = COPY %s2
+ %3(s32) = G_FMA %0, %1, %2
+ %s0 = COPY %3(s32)
+ BX_RET 14, %noreg, implicit %s0
+...
+---
+name: test_fma_s64
+# CHECK-LABEL: name: test_fma_s64
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+# CHECK: - { id: 2, class: fprb, preferred-register: '' }
+# CHECK: - { id: 3, class: fprb, preferred-register: '' }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+ - { id: 3, class: _ }
+body: |
+ bb.0:
+ liveins: %d0, %d1, %d2
+
+ %0(s64) = COPY %d0
+ %1(s64) = COPY %d1
+ %2(s64) = COPY %d2
+ %3(s64) = G_FMA %0, %1, %2
+ %d0 = COPY %3(s64)
+ BX_RET 14, %noreg, implicit %d0
+...
+---
name: test_soft_fp_s64
# CHECK-LABEL: name: test_soft_fp_s64
legalized: true