Sink two variables only used in an assert into the assert itself. Should

fix the release builds with Werror.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212612 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index dc61577..4af854e 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -2413,7 +2413,6 @@ bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
 SDValue DAGTypeLegalizer::WidenVecOp_ZERO_EXTEND(SDNode *N) {
   SDLoc DL(N);
   EVT VT = N->getValueType(0);
-  unsigned NumElts = VT.getVectorNumElements();
 
   SDValue InOp = N->getOperand(0);
   // If some legalization strategy other than widening is used on the operand,
@@ -2422,8 +2421,9 @@ SDValue DAGTypeLegalizer::WidenVecOp_ZERO_EXTEND(SDNode *N) {
   if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
     return WidenVecOp_Convert(N);
   InOp = GetWidenedVector(InOp);
-  EVT InVT = InOp.getValueType();
-  assert(NumElts < InVT.getVectorNumElements() && "Input wasn't widened!");
+  assert(VT.getVectorNumElements() <
+             InOp.getValueType().getVectorNumElements() &&
+         "Input wasn't widened!");
 
   // Use a special DAG node to represent the operation of zero extending the
   // low lanes.