arm64/sysreg: Convert MVFR2_EL1 to automatic generation

Convert MVFR2_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-35-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index d4b787d..aabc6db 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -170,8 +170,6 @@
 #define SYS_ID_AFR0_EL1                        sys_reg(3, 0, 0, 1, 3)
 #define SYS_ID_MMFR5_EL1               sys_reg(3, 0, 0, 3, 6)
 
-#define SYS_MVFR2_EL1                  sys_reg(3, 0, 0, 3, 2)
-
 #define SYS_ACTLR_EL1                  sys_reg(3, 0, 1, 0, 1)
 #define SYS_RGSR_EL1                   sys_reg(3, 0, 1, 0, 5)
 #define SYS_GCR_EL1                    sys_reg(3, 0, 1, 0, 6)
@@ -708,9 +706,6 @@
 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT         ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
 #endif
 
-#define MVFR2_EL1_FPMisc_SHIFT         4
-#define MVFR2_EL1_SIMDMisc_SHIFT               0
-
 #define CPACR_EL1_FPEN_EL1EN   (BIT(20)) /* enable EL1 access */
 #define CPACR_EL1_FPEN_EL0EN   (BIT(21)) /* enable EL0 access, if EL1EN set */
 

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 3ca7e61..f0481f6 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -684,6 +684,23 @@ Enum       3:0     FPFtZ
 EndEnum
 EndSysreg
 
+Sysreg MVFR2_EL1       3       0       0       3       2
+Res0   63:8
+Enum   7:4     FPMisc
+       0b0000  NI
+       0b0001  FP
+       0b0010  FP_DIRECTED_ROUNDING
+       0b0011  FP_ROUNDING
+       0b0100  FP_MAX_MIN
+EndEnum
+Enum   3:0     SIMDMisc
+       0b0000  NI
+       0b0001  SIMD_DIRECTED_ROUNDING
+       0b0010  SIMD_ROUNDING
+       0b0011  SIMD_MAX_MIN
+EndEnum
+EndSysreg
+
 Sysreg ID_PFR2_EL1     3       0       0       3       4
 Res0   63:12
 Enum   11:8    RAS_frac