const std::string CpuName;
};
-TEST_F(MachineFunctionGeneratorTest, JitFunction) {
+TEST_F(MachineFunctionGeneratorTest, DISABLED_JitFunction) {
JitFunctionContext Context(createTargetMachine());
JitFunction Function(std::move(Context), {});
ASSERT_THAT(Function.getFunctionBytes().str(), ElementsAre(0xc3));
// Function();
}
-TEST_F(MachineFunctionGeneratorTest, JitFunctionXOR32rr) {
+TEST_F(MachineFunctionGeneratorTest, DISABLED_JitFunctionXOR32rr) {
JitFunctionContext Context(createTargetMachine());
JitFunction Function(
std::move(Context),
// Function();
}
-TEST_F(MachineFunctionGeneratorTest, JitFunctionMOV64ri) {
+TEST_F(MachineFunctionGeneratorTest, DISABLED_JitFunctionMOV64ri) {
JitFunctionContext Context(createTargetMachine());
JitFunction Function(std::move(Context),
{MCInstBuilder(MOV64ri32).addReg(RAX).addImm(42)});
// Function();
}
-TEST_F(MachineFunctionGeneratorTest, JitFunctionMOV32ri) {
+TEST_F(MachineFunctionGeneratorTest, DISABLED_JitFunctionMOV32ri) {
JitFunctionContext Context(createTargetMachine());
JitFunction Function(std::move(Context),
{MCInstBuilder(MOV32ri).addReg(EAX).addImm(42)});
size_t returnIndexZero(const size_t UpperBound) { return 0; }
-TEST_F(MCInstrDescViewTest, XOR64rr) {
+TEST_F(MCInstrDescViewTest, DISABLED_XOR64rr) {
const llvm::MCInstrDesc &InstrDesc = InstrInfo->get(llvm::X86::XOR64rr);
const auto Vars =
getVariables(*RegInfo, InstrDesc, llvm::BitVector(RegInfo->getNumRegs()));
EXPECT_THAT(Inst.getOperand(2), llvm::MCOperand::createReg(RAX));
}
-TEST_F(MCInstrDescViewTest, AAA) {
+TEST_F(MCInstrDescViewTest, DISABLED_AAA) {
const llvm::MCInstrDesc &InstrDesc = InstrInfo->get(llvm::X86::AAA);
const auto Vars =
getVariables(*RegInfo, InstrDesc, llvm::BitVector(RegInfo->getNumRegs()));
EXPECT_THAT(Inst.getNumOperands(), 0) << "All operands are implicit";
}
-TEST_F(MCInstrDescViewTest, ReservedRegisters) {
+TEST_F(MCInstrDescViewTest, DISABLED_ReservedRegisters) {
llvm::BitVector ReservedRegisters(RegInfo->getNumRegs());
const llvm::MCInstrDesc &InstrDesc = InstrInfo->get(llvm::X86::XOR64rr);