fifo adjustment

diff --git a/tools/qt_proj_test5/qt_proj_test5.qsf b/tools/qt_proj_test5/qt_proj_test5.qsf
index 323e28a..700acac 100644 (file)
--- a/tools/qt_proj_test5/qt_proj_test5.qsf
+++ b/tools/qt_proj_test5/qt_proj_test5.qsf
@@ -258,7 +258,6 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0\r
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0\r
 set_global_assignment -name VHDL_FILE sdram_controller.vhd\r
-set_global_assignment -name QIP_FILE vga_clk_gen.qip\r
 set_global_assignment -name QIP_FILE sdram_write_fifo.qip\r
 set_global_assignment -name VHDL_FILE motonesfpga_common.vhd\r
 set_global_assignment -name VHDL_FILE cpu_registers.vhd\r

diff --git a/tools/qt_proj_test5/qt_proj_test5.vhd b/tools/qt_proj_test5/qt_proj_test5.vhd
index b777bbb..b6f517c 100644 (file)
--- a/tools/qt_proj_test5/qt_proj_test5.vhd
+++ b/tools/qt_proj_test5/qt_proj_test5.vhd
@@ -272,12 +272,12 @@ begin
                 nes_b       \r
         );\r
 \r
-        vga_clk_gen_inst : vga_clk_gen\r
-        PORT map\r
-        (\r
-            --mem_clk_pll = 133.333 MHz.\r
-            base_clk, vga_clk_pll, sdram_clk, pll_locked\r
-        );\r
+--        vga_clk_gen_inst : vga_clk_gen\r
+--        PORT map\r
+--        (\r
+--            --mem_clk_pll = 133.333 MHz.\r
+--            base_clk, vga_clk_pll, sdram_clk, pll_locked\r
+--        );\r
     --- testbench pll clock..\r
 --    dummy_clock_p: process\r
 --    begin\r

diff --git a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
index 1cc415e..530bbe5 100644 (file)
--- a/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
+++ b/tools/qt_proj_test5/simulation/modelsim/qt_proj_test5_run_msim_gate_vhdl.do
@@ -54,9 +54,11 @@ add wave -divider sdram_ctl
 add wave -radix hex \\r
 sim:/testbench_qt_proj_test5/sim_board/dbg_wbs_adr_i \\r
 sim:/testbench_qt_proj_test5/sim_board/dbg_wbs_dat_i \\r
-sim:/testbench_qt_proj_test5/sim_board/dbg_wbs_we_i \\r
-sim:/testbench_qt_proj_test5/sim_board/dbg_wbs_tga_i \\r
-sim:/testbench_qt_proj_test5/sim_board/dbg_wbs_cyc_i \\r
+sim:/testbench_qt_proj_test5/sim_board/dbg_wbs_we_i\r
+\r
+add wave -radix decimal -unsigned sim:/testbench_qt_proj_test5/sim_board/dbg_wbs_tga_i\r
+\r
+add wave sim:/testbench_qt_proj_test5/sim_board/dbg_wbs_cyc_i \\r
 sim:/testbench_qt_proj_test5/sim_board/dbg_wbs_stb_i\r
 \r
 \r
@@ -74,7 +76,7 @@ view signals
 run 3 us\r
 wave zoom full\r
 \r
-run 40 us\r
+run 30 us\r
 \r
 ##run 400 us\r
 \r

diff --git a/tools/qt_proj_test5/vga.vhd b/tools/qt_proj_test5/vga.vhd
index 9480709..9272dfd 100644 (file)
--- a/tools/qt_proj_test5/vga.vhd
+++ b/tools/qt_proj_test5/vga.vhd
@@ -10,6 +10,7 @@ use ieee.std_logic_1164.all;
 use ieee.std_logic_unsigned.conv_integer;
 use ieee.std_logic_arith.conv_std_logic_vector;
 use work.motonesfpga_common.all;
+use ieee.std_logic_unsigned.all;\r
 
 entity vga_ctl is 
     port (  \r
@@ -163,8 +164,8 @@ constant sw_idle        : std_logic_vector(2 downto 0) := "000";
 constant sw_pop_fifo    : std_logic_vector(2 downto 0) := "001";\r
 constant sw_write       : std_logic_vector(2 downto 0) := "010";\r
 constant sw_write_ack   : std_logic_vector(2 downto 0) := "011";\r
-constant sw_write_burst1 : std_logic_vector(2 downto 0) := "100";\r
-constant sw_write_burst2 : std_logic_vector(2 downto 0) := "101";\r
+constant sw_write_burst : std_logic_vector(2 downto 0) := "100";\r
+constant sw_write_burst_last : std_logic_vector(2 downto 0) := "101";\r
 \r
 signal sw_state         : std_logic_vector(2 downto 0);\r
 \r
@@ -291,7 +292,7 @@ begin
                 --write to sdram status\r
                 case sw_state is\r
                 when sw_idle =>         --0: idle...\r
-                    if (f_emp = '1') then\r
+                    if (f_cnt < "00001000") then        --wait until fifo > 8\r
                         sw_state <= sw_idle;\r
                     else\r
                         sw_state <= sw_pop_fifo;\r
@@ -304,23 +305,16 @@ begin
                     sw_state <= sw_write_ack;\r
                     \r
                 when sw_write_ack =>    --3: push first data\r
-                    sw_state <= sw_write_burst1;\r
+                    sw_state <= sw_write_burst;\r
 \r
-                when sw_write_burst1 =>  --4-1: repeat...\r
-                    if (bst_wr_cnt(7 downto 1) = "0000000") then -- case 0 or 1\r
-                        sw_state <= sw_idle;\r
+                when sw_write_burst =>  --4: repeat...\r
+                    if (bst_wr_cnt > "00000001") then -- busrt write\r
+                        sw_state <= sw_write_burst;\r
                     else\r
-                        sw_state <= sw_write_burst2;\r
+                        sw_state <= sw_write_burst_last;\r
                     end if;\r
 \r
-                when sw_write_burst2 =>  --4-2: repeat...\r
-                    if (bst_wr_cnt(7 downto 1) = "0000000") then -- case 0 or 1\r
-                        sw_state <= sw_idle;\r
-                    else\r
-                        sw_state <= sw_write_burst2;\r
-                    end if;\r
-                \r
-                when others =>\r
+                when others =>      --other and burst last...\r
                     sw_state <= sw_idle;\r
                 end case;\r
     \r
@@ -331,33 +325,19 @@ begin
     end process;\r
 \r
     f_rd <= '0' when rst_n = '0' else\r
-            '1' when (sw_state = sw_pop_fifo or sw_state = sw_write_burst2) else\r
+            '1' when (sw_state = sw_pop_fifo) else\r
+            '1' when (sw_state = sw_write_burst) else\r
             '0';\r
-\r
     f_val_we_n <= not f_rd;\r
---    f_val_p : process (rst_n, mem_clk)\r
---    begin\r
---        if (rst_n = '0') then\r
---            f_val_we_n <= '1';\r
---        elsif (rising_edge(mem_clk)) then\r
---            if (f_rd = '1') then\r
---                f_val_we_n <= '0';\r
---            else\r
---                f_val_we_n <= '1';\r
---            end if;\r
---        end if;\r
---    end process;\r
+    sdram_addr_inc_n <= not f_rd;\r
 \r
     sdram_addr_res_n <= rst_n;\r
-    sdram_addr_inc_n <= '1' when rst_n = '0' else\r
-                        '0' when (sw_state(2) = '1') else --case sw_write_burst1 or sw_write_burst2\r
-                        '1';\r
     bst_wr_cnt_we_n <= '1' when rst_n = '0' else\r
                        '0' when sw_state = sw_idle else\r
                        '1';\r
-    wbs_adr_i <= sdram_write_addr;\r
+    wbs_adr_i <= sdram_write_addr - 1;\r
     wbs_dat_i <= "0000" & f_val;\r
-    wbs_tga_i <= bst_wr_cnt;\r
+    wbs_tga_i <= bst_wr_cnt + 1;\r
     wbs_cyc_i <= '0' when rst_n = '0' else\r
                  '1' when sw_state >= sw_write else\r
                  '0';\r