return program;
}
+const unsigned *
+blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
+ struct nir_shader *nir,
+ struct brw_vs_prog_data *vs_prog_data,
+ unsigned *program_size)
+{
+ const struct brw_compiler *compiler = blorp->compiler;
+
+ nir->options =
+ compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions;
+
+ nir = brw_preprocess_nir(compiler, nir);
+ nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+
+ vs_prog_data->inputs_read = nir->info->inputs_read;
+
+ brw_compute_vue_map(compiler->devinfo,
+ &vs_prog_data->base.vue_map,
+ nir->info->outputs_written,
+ nir->info->separate_shader);
+
+ struct brw_vs_prog_key vs_key = { 0, };
+
+ const unsigned *program =
+ brw_compile_vs(compiler, blorp->driver_ctx, mem_ctx,
+ &vs_key, vs_prog_data, nir,
+ NULL, false, -1, program_size, NULL);
+
+ return program;
+}
+
void
blorp_gen6_hiz_op(struct blorp_batch *batch,
struct blorp_surf *surf, unsigned level, unsigned layer,
const uint32_t *const inputs_src = (const uint32_t *)¶ms->wm_inputs;
uint32_t *inputs = blorp_alloc_vertex_buffer(batch, *size, addr);
- /* Zero data for the VUE header */
- memset(inputs, 0, 4 * sizeof(uint32_t));
+ /* Copy in the VS inputs */
+ assert(sizeof(params->vs_inputs) == 16);
+ memcpy(inputs, ¶ms->vs_inputs, sizeof(params->vs_inputs));
inputs += 4;
if (params->wm_prog_data) {
ve[0].Valid = true;
ve[0].SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT;
ve[0].SourceElementOffset = 0;
- ve[0].Component0Control = VFCOMP_STORE_0;
+ ve[0].Component0Control = VFCOMP_STORE_SRC;
/* From Gen8 onwards hardware is no more instructed to overwrite components
* using an element specifier. Instead one has separate 3DSTATE_VF_SGVS
#else
ve[0].Component1Control = VFCOMP_STORE_IID;
#endif
- ve[0].Component2Control = VFCOMP_STORE_0;
- ve[0].Component3Control = VFCOMP_STORE_0;
+ ve[0].Component2Control = VFCOMP_STORE_SRC;
+ ve[0].Component3Control = VFCOMP_STORE_SRC;
ve[1].VertexBufferIndex = 0;
ve[1].Valid = true;
}
static void
+blorp_emit_vs_config(struct blorp_batch *batch,
+ const struct blorp_params *params)
+{
+ struct brw_vs_prog_data *vs_prog_data = params->vs_prog_data;
+
+ blorp_emit(batch, GENX(3DSTATE_VS), vs) {
+ if (vs_prog_data) {
+ vs.FunctionEnable = true;
+
+ vs.KernelStartPointer = params->vs_prog_kernel;
+
+ vs.DispatchGRFStartRegisterForURBData =
+ vs_prog_data->base.base.dispatch_grf_start_reg;
+ vs.VertexURBEntryReadLength =
+ vs_prog_data->base.urb_read_length;
+ vs.VertexURBEntryReadOffset = 0;
+
+ vs.MaximumNumberofThreads =
+ batch->blorp->isl_dev->info->max_vs_threads - 1;
+
+#if GEN_GEN >= 8
+ vs.SIMD8DispatchEnable =
+ vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8;
+#endif
+ }
+ }
+}
+
+static void
blorp_emit_sf_config(struct blorp_batch *batch,
const struct blorp_params *params)
{
*
* We've already done one at the start of the BLORP operation.
*/
- blorp_emit(batch, GENX(3DSTATE_VS), vs);
+ blorp_emit_vs_config(batch, params);
#if GEN_GEN >= 7
blorp_emit(batch, GENX(3DSTATE_HS), hs);
blorp_emit(batch, GENX(3DSTATE_TE), te);
input; \
})
+struct blorp_vs_inputs {
+ uint32_t base_layer;
+ uint32_t _instance_id; /* Set in hardware by SGVS */
+ uint32_t pad[2];
+};
+
static inline unsigned
brw_blorp_get_urb_length(const struct brw_wm_prog_data *prog_data)
{
enum blorp_fast_clear_op fast_clear_op;
bool color_write_disable[4];
struct brw_blorp_wm_inputs wm_inputs;
+ struct blorp_vs_inputs vs_inputs;
unsigned num_samples;
unsigned num_draw_buffers;
unsigned num_layers;
+ uint32_t vs_prog_kernel;
+ struct brw_vs_prog_data *vs_prog_data;
uint32_t wm_prog_kernel;
struct brw_wm_prog_data *wm_prog_data;
};
struct brw_wm_prog_data *wm_prog_data,
unsigned *program_size);
+const unsigned *
+blorp_compile_vs(struct blorp_context *blorp, void *mem_ctx,
+ struct nir_shader *nir,
+ struct brw_vs_prog_data *vs_prog_data,
+ unsigned *program_size);
+
/** \} */
#ifdef __cplusplus