signal nt0_ce_n : std_logic;
signal nt1_ce_n : std_logic;
--- signal dbg_disp_nt, dbg_disp_attr : std_logic_vector (7 downto 0);
--- signal dbg_disp_ptn_h, dbg_disp_ptn_l : std_logic_vector (15 downto 0);
signal dbg_pcl, dbg_pch : std_logic_vector(7 downto 0);
signal dbg_stat_we_n : std_logic;
signal dbg_idl_h, dbg_idl_l : std_logic_vector (7 downto 0);
signal dbg_ea_carry_dummy : std_logic;
signal dbg_status_dummy : std_logic_vector(7 downto 0);
signal dbg_sp_dummy, dbg_x_dummy, dbg_y_dummy, dbg_acc_dummy : std_logic_vector(7 downto 0);\r
+ signal dbg_dec_val_dummy : std_logic_vector (7 downto 0);\r
\r
begin
dbg_status_dummy,
dbg_pcl, dbg_pch, dbg_sp_dummy, dbg_x_dummy, dbg_y, dbg_acc,
dbg_dec_oe_n,
- dbg_dec_val,
+ dbg_dec_val_dummy,
dbg_stat_we_n ,
dbg_idl_h, dbg_idl_l,
dbg_ppu_ce_n ,
dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status ,
dbg_ppu_addr ,
- dbg_ppu_data, dbg_ppu_scrl_x_dummy, dbg_ppu_scrl_y_dummy ,
+ dbg_ppu_data, dbg_ppu_scrl_x_dummy, dbg_ppu_scrl_y ,
dbg_nes_x ,
dbg_vga_x ,
dbg_nes_y ,
dbg_vga_y ,
dbg_disp_nt, dbg_disp_attr ,
- dbg_disp_ptn_h, dbg_disp_ptn_l_dummy ,
+ dbg_disp_ptn_h, dbg_disp_ptn_l ,
dbg_plt_ce_rn_wn ,
dbg_plt_addr ,
dbg_plt_data ,
dbg_exec_cycle(4) <= dbg_nes_y(8);\r
dbg_status <= dbg_nes_y(7 downto 0);\r
\r
- dbg_disp_ptn_l (7 downto 0) <= dbg_p_oam_addr;\r
- dbg_disp_ptn_l (15 downto 8) <= dbg_p_oam_data;\r
- dbg_int_d_bus(4 downto 0) <= dbg_s_oam_addr(4 downto 0);\r
- --dbg_ppu_scrl_y <= dbg_s_oam_data;\r
- dbg_ppu_scrl_y <= dbg_ppu_scrl_y_dummy;\r
-\r
dbg_ppu_scrl_x(0) <= ale_n;\r
dbg_ppu_scrl_x(1) <= rd_n;\r
dbg_ppu_scrl_x(2) <= wr_n;\r
dbg_ppu_scrl_x(3) <= nt0_ce_n;\r
\r
+ dbg_sp <= dbg_p_oam_addr;\r
+ dbg_x <= dbg_p_oam_data;\r
+ dbg_int_d_bus(4 downto 0) <= dbg_s_oam_addr(4 downto 0);\r
+ dbg_dec_val <= dbg_s_oam_data;\r
+ --dbg_ppu_scrl_y <= dbg_ppu_scrl_y_dummy;\r
+\r
--nmi_n <= dummy_nmi;\r
---------------\r
\r
s_oam_w_n <= '1';\r
s_oam_addr <= s_oam_addr_cpy + 1;\r
\r
+ --increment when nes_x = 0...3\r
if (nes_x (2) = '0') then\r
s_oam_addr_cpy_ce_n <= '0';\r
else\r
#add wave -label status -radix hex sim:/testbench_motones_sim/sim_board/dbg_status\r
\r
\r
-add wave -divider ppu\r
-add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/dbg_ppu_clk\r
-add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n\r
-add wave -label ppu_ctrl -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
-add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask\r
-add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status\r
-add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr\r
-add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data\r
+#add wave -divider ppu\r
+#add wave -label ppu_clk sim:/testbench_motones_sim/sim_board/dbg_ppu_clk\r
+#add wave -label ppu_ce_n sim:/testbench_motones_sim/sim_board/dbg_ppu_ce_n\r
+#add wave -label ppu_ctrl -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_ctrl\r
+#add wave -label ppu_mask -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_mask\r
+#add wave -label ppu_status -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_status\r
+#add wave -label ppu_addr -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_addr\r
+#add wave -label ppu_data -radix hex sim:/testbench_motones_sim/sim_board/dbg_ppu_data\r
#add wave -label ppu_scrl_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x\r
#add wave -label ppu_scrl_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y\r
\r
add wave -divider vram\r
+add wave -label emu_ppu_clk sim:/testbench_motones_sim/sim_board/dbg_emu_ppu_clk\r
add wave -label ale sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(0)\r
add wave -label rd_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(1)\r
add wave -label wr_n sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(2)\r
-\r
-add wave -label emu_ppu_clk sim:/testbench_motones_sim/sim_board/dbg_emu_ppu_clk\r
add wave -radix hex -label v_addr sim:/testbench_motones_sim/sim_board/dbg_v_addr\r
add wave -radix hex -label v_data sim:/testbench_motones_sim/sim_board/dbg_v_data\r
\r
sim:/testbench_motones_sim/sim_board/dbg_instruction(7 downto 0)}\r
add wave -label nes_y -radix decimal -unsigned {sim:/testbench_motones_sim/sim_board/dbg_exec_cycle(4) & \r
sim:/testbench_motones_sim/sim_board/dbg_status(7 downto 0)}\r
-#add wave -label dbg_disp_nt -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt\r
-#add wave -label dbg_disp_attr -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr\r
-#add wave -label dbg_disp_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h\r
-#add wave -label dbg_disp_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
-\r
-#add wave -divider oam\r
-#add wave -radix hex -label p_oam_addr {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (7 downto 0)}\r
-#add wave -radix hex -label p_oam_data {sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l (15 downto 8)}\r
-#add wave -radix hex -label s_oam_addr {sim:/testbench_motones_sim/sim_board/dbg_int_d_bus (4 downto 0)}\r
-#add wave -radix hex -label s_oam_data sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_y\r
-#\r
+add wave -divider oam\r
+add wave -radix hex -label p_oam_addr sim:/testbench_motones_sim/sim_board/dbg_sp\r
+add wave -radix hex -label p_oam_data sim:/testbench_motones_sim/sim_board/dbg_x\r
+add wave -radix hex -label s_oam_addr {sim:/testbench_motones_sim/sim_board/dbg_int_d_bus (4 downto 0)}\r
+add wave -radix hex -label s_oam_data sim:/testbench_motones_sim/sim_board/dbg_dec_val\r
+\r
+add wave -divider ppu_render\r
+add wave -label dbg_disp_nt -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_nt\r
+add wave -label dbg_disp_attr -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_attr\r
+add wave -label dbg_disp_ptn_h -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_h\r
+add wave -label dbg_disp_ptn_l -radix hex sim:/testbench_motones_sim/sim_board/dbg_disp_ptn_l\r
+\r
#add wave -divider vga_out\r
#add wave -label h_sync_n sim:/testbench_motones_sim/sim_board/v_sync_n\r
#add wave -label v_sync_n sim:/testbench_motones_sim/sim_board/h_sync_n\r
view structure\r
view signals\r
#run -all\r
-run 30 us\r
+run 4 us\r
wave zoom full\r
+run 88 us\r
\r
#wave zoom range 3339700 ps 5138320 ps\r
##wave addcursor 907923400 ps\r
-\r
-run 60 us\r
add wave -label v_addr -radix hex sim:/testbench_motones_sim/sim_board/v_addr\r
add wave -label v_data -radix hex sim:/testbench_motones_sim/sim_board/v_data\r
\r
-add wave -divider render\r
+add wave -divider vga_pos\r
#add wave -label vba_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_x\r
add wave -label nes_x -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_x\r
#add wave -label vga_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/vga_y\r
add wave -label nes_y -radix decimal -unsigned sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/nes_y\r
-#add wave -label disp_nt -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_nt\r
-#add wave -label disp_attr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/disp_attr\r
-#add wave -label attr_val -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/ppu_render_inst/attr_val\r
\r
add wave -divider ppu\r
add wave -label s_oam_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/s_oam_addr\r
add wave -label p_oam_addr -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/p_oam_addr\r
add wave -label p_oam_data -radix hex sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/p_oam_data\r
\r
+add wave -divider ppu_render\r
add wave -label s_oam_addr_cpy -radix decimal sim:/testbench_motones_sim/sim_board/ppu_inst/vga_render_inst/s_oam_addr_cpy\r
\r
\r
signal dbg_int_d_bus : std_logic_vector(7 downto 0);
signal dbg_exec_cycle : std_logic_vector (5 downto 0);
signal dbg_ea_carry : std_logic;
--- signal dbg_index_bus : std_logic_vector(7 downto 0);
--- signal dbg_acc_bus : std_logic_vector(7 downto 0);
signal dbg_status : std_logic_vector(7 downto 0);
signal dbg_pcl, dbg_pch, dbg_sp, dbg_x, dbg_y, dbg_acc : std_logic_vector(7 downto 0);
signal dbg_dec_oe_n : std_logic;
signal dbg_dec_val : std_logic_vector (7 downto 0);
signal dbg_int_dbus : std_logic_vector (7 downto 0);
--- signal dbg_status_val : std_logic_vector (7 downto 0);
signal dbg_stat_we_n : std_logic;
signal dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w : std_logic_vector (7 downto 0);
signal dbg_ppu_ce_n : std_logic;
dbg_int_d_bus,
dbg_exec_cycle ,
dbg_ea_carry ,
---dbg_index_bus ,
---dbg_acc_bus ,
dbg_status ,
---dbg_pcl, dbg_pch,
dbg_sp, dbg_x, dbg_y, dbg_acc ,
dbg_dec_oe_n ,
dbg_dec_val ,
dbg_int_dbus ,
---dbg_status_val ,
---dbg_stat_we_n ,
---dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w,
dbg_ppu_ce_n ,
dbg_ppu_ctrl, dbg_ppu_mask, dbg_ppu_status ,
dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y,
dbg_disp_nt, dbg_disp_attr ,
dbg_disp_ptn_h, dbg_disp_ptn_l ,
---dbg_ppu_addr_we_n,
---dbg_ppu_clk_cnt ,
dbg_nmi,
dummy_nmi,