[AArch64] Audit on rL333879 to fix FP16 64bit bitpatterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334488 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index a0b5bd3..683ab69 100644 (file)
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -7938,10 +7938,10 @@ multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> {
     let Inst{21-16} = imm{5-0};
     let Inst{23-22} = 0b11;
   }
-  def DHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
+  def DHr : BaseSIMDScalarShift<U, opc, {1,1,1,?,?,?,?},
                                 FPR64, FPR16, vecshiftR64, asm, []> {
     let Inst{21-16} = imm{5-0};
-    let Inst{23-22} = 0b11;
+    let Inst{23-22} = 0b01;
     let Inst{31} = 1;
   }
   def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},