ASoC: SOF: Intel: add d0i3_offset in chip_info

MTL has different d0i3 offset compared to cavs platforms.
Use d0i3_offset to unify the setting.

Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Signed-off-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20221107164154.21925-3-pierre-louis.bossart@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/sound/soc/sof/intel/apl.c b/sound/soc/sof/intel/apl.c
index d93b4ea..0e7a7e4 100644 (file)
--- a/sound/soc/sof/intel/apl.c
+++ b/sound/soc/sof/intel/apl.c
@@ -109,6 +109,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
        .rom_init_timeout       = 150,
        .ssp_count = APL_SSP_COUNT,
        .ssp_base_offset = APL_SSP_BASE_OFFSET,
+       .d0i3_offset = SOF_HDA_VS_D0I3C,
        .quirks = SOF_INTEL_PROCEN_FMT_QUIRK,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
        .cl_init = cl_dsp_init,

diff --git a/sound/soc/sof/intel/cnl.c b/sound/soc/sof/intel/cnl.c
index 2553afe..0aaa44b 100644 (file)
--- a/sound/soc/sof/intel/cnl.c
+++ b/sound/soc/sof/intel/cnl.c
@@ -456,6 +456,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .d0i3_offset = SOF_HDA_VS_D0I3C,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
        .cl_init = cl_dsp_init,
@@ -488,6 +489,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .d0i3_offset = SOF_HDA_VS_D0I3C,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
        .cl_init = cl_dsp_init,

diff --git a/sound/soc/sof/intel/icl.c b/sound/soc/sof/intel/icl.c
index f95b2ec..8dd51f4 100644 (file)
--- a/sound/soc/sof/intel/icl.c
+++ b/sound/soc/sof/intel/icl.c
@@ -180,6 +180,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .d0i3_offset = SOF_HDA_VS_D0I3C,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
        .cl_init = cl_dsp_init,

diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c
index 9161903..7452a7d 100644 (file)
--- a/sound/soc/sof/intel/mtl.c
+++ b/sound/soc/sof/intel/mtl.c
@@ -684,6 +684,7 @@ const struct sof_intel_dsp_desc mtl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE_ACE,
        .sdw_alh_base = SDW_ALH_BASE_ACE,
+       .d0i3_offset = MTL_HDA_VS_D0I3C,
        .check_sdw_irq = mtl_dsp_check_sdw_irq,
        .check_ipc_irq = mtl_dsp_check_ipc_irq,
        .cl_init = mtl_dsp_cl_init,

diff --git a/sound/soc/sof/intel/shim.h b/sound/soc/sof/intel/shim.h
index 3ceba5c..3e777c5 100644 (file)
--- a/sound/soc/sof/intel/shim.h
+++ b/sound/soc/sof/intel/shim.h
@@ -182,6 +182,7 @@ struct sof_intel_dsp_desc {
        int ssp_base_offset;            /* base address of the SSPs */
        u32 sdw_shim_base;
        u32 sdw_alh_base;
+       u32 d0i3_offset;
        u32 quirks;
        enum sof_intel_hw_ip_version hw_ip_version;
        bool (*check_sdw_irq)(struct snd_sof_dev *sdev);

diff --git a/sound/soc/sof/intel/tgl.c b/sound/soc/sof/intel/tgl.c
index 143447f..946044f 100644 (file)
--- a/sound/soc/sof/intel/tgl.c
+++ b/sound/soc/sof/intel/tgl.c
@@ -135,6 +135,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .d0i3_offset = SOF_HDA_VS_D0I3C,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
        .cl_init = cl_dsp_init,
@@ -160,6 +161,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .d0i3_offset = SOF_HDA_VS_D0I3C,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
        .cl_init = cl_dsp_init,
@@ -185,6 +187,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .d0i3_offset = SOF_HDA_VS_D0I3C,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
        .cl_init = cl_dsp_init,
@@ -210,6 +213,7 @@ const struct sof_intel_dsp_desc adls_chip_info = {
        .ssp_base_offset = CNL_SSP_BASE_OFFSET,
        .sdw_shim_base = SDW_SHIM_BASE,
        .sdw_alh_base = SDW_ALH_BASE,
+       .d0i3_offset = SOF_HDA_VS_D0I3C,
        .check_sdw_irq  = hda_common_check_sdw_irq,
        .check_ipc_irq  = hda_dsp_check_ipc_irq,
        .cl_init = cl_dsp_init,