AliasSetTracker.cpp \
Analysis.cpp \
BasicAliasAnalysis.cpp \
+ BlockFrequency.cpp \
BranchProbabilityInfo.cpp \
CFGPrinter.cpp \
CaptureTracking.cpp \
Passes.cpp \
PeepholeOptimizer.cpp \
PostRASchedulerList.cpp \
- PreAllocSplitting.cpp \
ProcessImplicitDefs.cpp \
PrologEpilogInserter.cpp \
PseudoSourceValue.cpp \
RegAllocPBQP.cpp \
RegisterCoalescer.cpp \
RegisterClassInfo.cpp \
+ RegisterCoalescer.cpp \
RegisterScavenging.cpp \
RenderMachineFunction.cpp \
ScheduleDAG.cpp \
ScoreboardHazardRecognizer.cpp \
ShadowStackGC.cpp \
ShrinkWrapping.cpp \
- SimpleRegisterCoalescing.cpp \
SjLjEHPrepare.cpp \
SlotIndexes.cpp \
Spiller.cpp \
MCWin64EH.cpp \
WinCOFFObjectWriter.cpp \
WinCOFFStreamer.cpp \
+ SubtargetFeature.cpp \
TargetAsmBackend.cpp
# For the host
unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op)
const {
- const TargetInstrDesc &TID = MI.getDesc();
+ const MCInstrDesc &MCID = MI.getDesc();
const MachineOperand &MO = MI.getOperand(Op);
- unsigned Reloc = (TID.Opcode == ARM::MOVi16 ?
+ unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
ARM::reloc_arm_movw : ARM::reloc_arm_movt);
if (!MO.isImm()) {
void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) {
// It's basically add r, pc, (LCPI - $+8)
- const TargetInstrDesc &TID = MI.getDesc();
+ const MCInstrDesc &MCID = MI.getDesc();
unsigned Binary = 0;
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
// Encode S bit if MI modifies CPSR.
- Binary |= getAddrModeSBit(MI, TID);
+ Binary |= getAddrModeSBit(MI, MCID);
// Encode Rd.
Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
- if (TID.Opcode == ARM::MOVi16 || TID.Opcode == ARM::MOVTi16) {
+ if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) {
emitWordLE(Binary);
return;
}
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
- if (TID.getOpcode() == ARM::LDMIA_RET) {
+ if (MCID.getOpcode() == ARM::LDMIA_RET) {
IsUpdating = true;
Binary |= 0x8B00000;
}
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
- if (TID.Opcode == ARM::B) {
+ if (MCID.Opcode == ARM::B) {
Binary = 0xEA000000;
}
arm_codegen_TBLGEN_TABLES := \
ARMGenAsmWriter.inc \
ARMGenMCCodeEmitter.inc \
- ARMGenRegisterInfo.h.inc\
- ARMGenRegisterNames.inc \
ARMGenRegisterInfo.inc \
- ARMGenInstrNames.inc \
ARMGenInstrInfo.inc \
ARMGenDAGISel.inc \
ARMGenFastISel.inc \
include $(CLEAR_TBLGEN_VARS)
TBLGEN_TABLES := \
- ARMGenInstrNames.inc \
- ARMGenRegisterNames.inc \
- ARMGenRegisterInfo.h.inc \
+ ARMGenInstrInfo.inc \
+ ARMGenRegisterInfo.inc \
ARMGenAsmMatcher.inc
arm_disassembler_TBLGEN_TABLES := \
ARMGenDecoderTables.inc \
ARMGenEDInfo.inc \
- ARMGenInstrNames.inc \
ARMGenInstrInfo.inc \
- ARMGenRegisterNames.inc \
- ARMGenRegisterInfo.h.inc
+ ARMGenRegisterInfo.inc
arm_disassembler_SRC_FILES := \
ARMDisassembler.cpp \
arm_asm_printer_TBLGEN_TABLES := \
ARMGenAsmWriter.inc \
- ARMGenRegisterNames.inc\
- ARMGenInstrNames.inc
+ ARMGenRegisterInfo.inc\
+ ARMGenInstrInfo.inc
arm_asm_printer_SRC_FILES := \
ARMInstPrinter.cpp
LOCAL_PATH := $(call my-dir)
arm_target_info_TBLGEN_TABLES := \
- ARMGenRegisterNames.inc \
- ARMGenInstrNames.inc
+ ARMGenRegisterInfo.inc \
+ ARMGenInstrInfo.inc
arm_target_info_SRC_FILES := \
ARMTargetInfo.cpp
target_SRC_FILES := \
Mangler.cpp \
- SubtargetFeature.cpp \
Target.cpp \
TargetAsmInfo.cpp \
TargetAsmLexer.cpp \
x86_codegen_TBLGEN_TABLES := \
X86GenAsmWriter.inc \
X86GenAsmWriter1.inc \
- X86GenRegisterInfo.h.inc \
- X86GenRegisterNames.inc \
X86GenRegisterInfo.inc \
- X86GenInstrNames.inc \
X86GenInstrInfo.inc \
X86GenDAGISel.inc \
X86GenFastISel.inc \
TBLGEN_TABLES := \
X86GenAsmMatcher.inc \
- X86GenInstrNames.inc \
- X86GenRegisterNames.inc
+ X86GenInstrInfo.inc \
+ X86GenRegisterInfo.inc
TBLGEN_TD_DIR := $(LOCAL_PATH)/..
x86_disassembler_TBLGEN_TABLES := \
X86GenDisassemblerTables.inc \
X86GenEDInfo.inc \
- X86GenRegisterNames.inc
+ X86GenRegisterInfo.inc
x86_disassembler_SRC_FILES := \
X86Disassembler.cpp \
x86_instprinter_TBLGEN_TABLES := \
X86GenAsmWriter.inc \
X86GenAsmWriter1.inc \
- X86GenInstrNames.inc \
- X86GenRegisterNames.inc \
- X86GenRegisterInfo.h.inc
+ X86GenInstrInfo.inc \
+ X86GenRegisterInfo.inc
x86_instprinter_SRC_FILES := \
X86ATTInstPrinter.cpp \
--- /dev/null
+#LOCAL_PATH := $(call my-dir)
+#
+#x86_codegen_SRC_FILES := \
+# X86TargetDesc.cpp
+#
+## For the host
+## =====================================================
+#include $(CLEAR_VARS)
+#include $(CLEAR_TBLGEN_VARS)
+#
+#TBLGEN_TABLES := $(x86_codegen_TBLGEN_TABLES)
+#
+#LOCAL_SRC_FILES := $(x86_codegen_SRC_FILES)
+#
+#LOCAL_MODULE:= libLLVMX86Desc
+#
+#LOCAL_MODULE_TAGS := optional
+#
+#include $(LLVM_HOST_BUILD_MK)
+#include $(BUILD_HOST_STATIC_LIBRARY)
+#
+## For the device only
+## =====================================================
+#ifeq ($(TARGET_ARCH),x86)
+#include $(CLEAR_VARS)
+#include $(CLEAR_TBLGEN_VARS)
+#
+#LOCAL_SRC_FILES := $(x86_codegen_SRC_FILES)
+#
+#LOCAL_MODULE:= libLLVMX86Desc
+#
+#LOCAL_MODULE_TAGS := optional
+#
+#include $(LLVM_DEVICE_BUILD_MK)
+#include $(BUILD_STATIC_LIBRARY)
+#endif
LOCAL_PATH := $(call my-dir)
x86_target_info_TBLGEN_TABLES := \
- X86GenRegisterNames.inc \
- X86GenInstrNames.inc
+ X86GenRegisterInfo.inc \
+ X86GenInstrInfo.inc
x86_target_info_SRC_FILES := \
X86TargetInfo.cpp
tblgen_source_dir := $(TBLGEN_TD_DIR)
endif
-ifneq ($(filter %GenRegisterNames.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenRegisterNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
- $(call transform-td-to-out,register-enums)
-endif
-
-ifneq ($(filter %GenRegisterInfo.h.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenRegisterInfo.h.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
- $(call transform-td-to-out,register-desc-header)
-endif
-
ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),)
$(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
- $(call transform-td-to-out,register-desc)
-endif
-
-ifneq ($(filter %GenInstrNames.inc,$(tblgen_gen_tables)),)
-$(intermediates)/%GenInstrNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
- $(call transform-td-to-out,instr-enums)
+ $(call transform-td-to-out,register-info)
endif
ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),)
$(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
- $(call transform-td-to-out,instr-desc)
+ $(call transform-td-to-out,instr-info)
endif
ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),)