clk: sh: Common Clock Framework support

Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 0390a07..7d5e7f3 100644 (file)
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -1,10 +1,12 @@
 #ifndef __ASM_SH_CLOCK_H
 #define __ASM_SH_CLOCK_H
 
+#if !defined(CONFIG_COMMON_CLK)
 #include <linux/sh_clk.h>
 
 /* Should be defined by processor-specific code */
 void __deprecated arch_init_clk_ops(struct sh_clk_ops **, int type);
+#endif
 int __init arch_clk_init(void);
 
 /* arch/sh/kernel/cpu/clock-cpg.c */

diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index accc7ca..4aa17ba 100644 (file)
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ARCH_SHMOBILE)   += shmobile/
 # Common interfaces.
 
 obj-$(CONFIG_SH_ADC)           += adc.o
+ifneq ($(CONFIG_COMMON_CLK),y)
 obj-$(CONFIG_SH_CLK_CPG_LEGACY)        += clock-cpg.o
-
+endif
 obj-y  += irq/ init.o clock.o fpu.o pfc.o proc.o

diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 4187cf4..93a8bfb 100644 (file)
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -17,13 +17,16 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/clk-provider.h>
 #include <asm/clock.h>
 #include <asm/machvec.h>
 
 int __init clk_init(void)
 {
-       int ret;
+       int ret = 0;
 
+#if !defined(CONFIG_COMMON_CLK)
        ret = arch_clk_init();
        if (unlikely(ret)) {
                pr_err("%s: CPU clock registration failed.\n", __func__);
@@ -44,7 +47,9 @@ int __init clk_init(void)
 
        /* Enable the necessary init clocks */
        clk_enable_init_clocks();
-
+#else
+       of_clk_init(NULL);
+#endif
        return ret;
 }
 

diff --git a/arch/sh/kernel/cpu/sh2/Makefile b/arch/sh/kernel/cpu/sh2/Makefile
index f0f059a..deedc23 100644 (file)
--- a/arch/sh/kernel/cpu/sh2/Makefile
+++ b/arch/sh/kernel/cpu/sh2/Makefile
@@ -4,4 +4,7 @@
 
 obj-y  := ex.o probe.o entry.o
 
-obj-$(CONFIG_CPU_SUBTYPE_SH7619) += setup-sh7619.o clock-sh7619.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7619) += setup-sh7619.o
+ifneq ($(CONFIG_COMMON_CLK),y)
+obj-y += clock-sh7619.o
+endif

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9897f35..0dcee84 100644 (file)
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -150,6 +150,12 @@ config COMMON_CLK_CDCE706
        ---help---
          This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
 
+config COMMON_CLK_SH
+       tristate "Clock driver for SuperH"
+       depends on COMMON_CLK && SUPERH
+       --help--
+         This driver supports Renesas Super H CPG
+
 source "drivers/clk/qcom/Kconfig"
 
 endmenu

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 3d00c25..b14fcf6 100644 (file)
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_COMMON_CLK_PXA)          += pxa/
 obj-$(CONFIG_COMMON_CLK_QCOM)          += qcom/
 obj-$(CONFIG_ARCH_ROCKCHIP)            += rockchip/
 obj-$(CONFIG_COMMON_CLK_SAMSUNG)       += samsung/
+obj-$(CONFIG_COMMON_CLK_SH)            += sh/
 obj-$(CONFIG_ARCH_SHMOBILE_MULTI)      += shmobile/
 obj-$(CONFIG_ARCH_SIRF)                        += sirf/
 obj-$(CONFIG_ARCH_SOCFPGA)             += socfpga/

diff --git a/drivers/clk/sh/Makefile b/drivers/clk/sh/Makefile
new file mode 100644 (file)
index 0000000..97464cd
--- /dev/null
+++ b/drivers/clk/sh/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CPU_SUBTYPE_SH7619) = clk-div.o clk-sh7619.o

diff --git a/drivers/clk/sh/clk-div.c b/drivers/clk/sh/clk-div.c
new file mode 100644 (file)
index 0000000..7551fd1
--- /dev/null
+++ b/drivers/clk/sh/clk-div.c
@@ -0,0 +1,60 @@
+/*
+ * SH7619 divide clock driver
+ *
+ * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/io.h>
+
+static DEFINE_SPINLOCK(clklock);
+
+static const struct clk_div_table sh7619_div_table[] = {
+        { .val = 0, .div = 1, },
+        { .val = 1, .div = 2, },
+        { .val = 3, .div = 4, },
+        { .val = 4, .div = 5, },
+};
+
+static void __init sh7619_div_clk_setup(struct device_node *node)
+{
+       unsigned int num_parents;
+       struct clk *clk;
+       const char *clk_name = node->name;
+       const char *parent_name;
+       void __iomem *freqcr = NULL;
+       int offset;
+
+       num_parents = of_clk_get_parent_count(node);
+       if (num_parents < 1) {
+               pr_err("%s: no parent found", clk_name);
+               return;
+       }
+
+       freqcr = of_iomap(node, 0);
+       if (freqcr == NULL) {
+               pr_err("%s: failed to map divide register", clk_name);
+               goto error;
+       }
+
+       parent_name = of_clk_get_parent_name(node, 0);
+       clk = clk_register_divider_table(NULL, clk_name, parent_name,
+                                        CLK_SET_RATE_GATE, freqcr, 16, 3,
+                                        0, sh7619_div_table, &clklock);
+       if (!IS_ERR(clk)) {
+               of_clk_add_provider(node, of_clk_src_simple_get, clk);
+               return;
+       }
+       pr_err("%s: failed to register %s div clock (%ld)\n",
+              __func__, clk_name, PTR_ERR(clk));
+error:
+       if (freqcr)
+               iounmap(freqcr);
+}
+
+CLK_OF_DECLARE(sh7619_div_clk, "renesas,sh7619-div-clock", sh7619_div_clk_setup);

diff --git a/drivers/clk/sh/clk-sh7619.c b/drivers/clk/sh/clk-sh7619.c
new file mode 100644 (file)
index 0000000..63971c0
--- /dev/null
+++ b/drivers/clk/sh/clk-sh7619.c
@@ -0,0 +1,153 @@
+/*
+ * SH7619 clock driver
+ *
+ * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/device.h>
+#include <linux/of_address.h>
+#include <asm/io.h>
+
+static DEFINE_SPINLOCK(clklock);
+
+#define MAX_FREQ 125000000
+#define MIN_FREQ  20000000
+
+struct pll_clock {
+       struct clk_hw hw;
+       int pll2_mult;
+       void __iomem *freqcr;
+       void __iomem *wdt;
+};
+
+#define to_pll_clock(_hw) container_of(_hw, struct pll_clock, hw)
+
+static unsigned long pll_recalc_rate(struct clk_hw *hw,
+               unsigned long parent_rate)
+{
+       struct pll_clock *pll_clock = to_pll_clock(hw);
+       int mul = 1 << ((ioread16(pll_clock->freqcr) >> 8) & 7);
+
+       return parent_rate * mul * pll_clock->pll2_mult;
+}
+
+static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long *prate)
+{
+       int i, m = -1;
+       long offset[2];
+
+       if (rate > MAX_FREQ)
+               rate = MAX_FREQ;
+       if (rate < MIN_FREQ)
+               rate = MIN_FREQ;
+
+       for (i = 0; i < 2; i++)
+               offset[i] = abs(rate - (*prate * (1 << i)));
+       for (i = 0; i < 2; i++)
+               if (m < 0)
+                       m = i;
+               else
+                       m = (offset[i] < offset[m])?i:m;
+
+       return *prate * (1 << m);
+}
+
+static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
+                       unsigned long parent_rate)
+{
+       int pll;
+       unsigned char val;
+       unsigned long flags;
+       struct pll_clock *pll_clock = to_pll_clock(hw);
+
+       pll = (((rate / parent_rate) / 2) & 0x01) << 8;
+       spin_lock_irqsave(&clklock, flags);
+       iowrite16(0x5a00, pll_clock->wdt);
+       iowrite16(0xa502, pll_clock->wdt + 2);
+       val = ioread16(pll_clock->freqcr);
+       val &= ~0x70;
+       val |= pll;
+       iowrite16(val, pll_clock->freqcr);
+       spin_unlock_irqrestore(&clklock, flags);
+       return 0;
+}
+
+static const struct clk_ops pll_ops = {
+       .recalc_rate = pll_recalc_rate,
+       .round_rate = pll_round_rate,
+       .set_rate = pll_set_rate,
+};
+
+static void __init sh7619_pll_clk_setup(struct device_node *node)
+{
+       unsigned int num_parents;
+       struct clk *clk;
+       const char *clk_name = node->name;
+       const char *parent_name;
+       struct pll_clock *pll_clock;
+       struct clk_init_data init;
+
+       num_parents = of_clk_get_parent_count(node);
+       if (num_parents < 1) {
+               pr_err("%s: no parent found", clk_name);
+               return;
+       }
+
+
+       pll_clock = kzalloc(sizeof(struct pll_clock), GFP_KERNEL);
+       if (!pll_clock) {
+               pr_err("%s: failed to alloc memory", clk_name);
+               return;
+       }
+
+       pll_clock->freqcr = of_iomap(node, 0);
+       if (pll_clock->freqcr == NULL) {
+               pr_err("%s: failed to map divide register", clk_name);
+               goto free_clock;
+       }
+
+       pll_clock->wdt = of_iomap(node, 1);
+       if (pll_clock->wdt == NULL) {
+               pr_err("%s: failed to map divide register", clk_name);
+               goto unmap_freqcr;
+       }
+
+       if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
+           test_mode_pin(MODE_PIN2 | MODE_PIN1))
+               pll_clock->pll2_mult = 2;
+       else if (test_mode_pin(MODE_PIN0) || test_mode_pin(MODE_PIN1))
+               pll_clock->pll2_mult = 4;
+
+       parent_name = of_clk_get_parent_name(node, 0);
+       init.name = clk_name;
+       init.ops = &pll_ops;
+       init.flags = CLK_IS_BASIC;
+       init.parent_names = &parent_name;
+       init.num_parents = 1;
+       pll_clock->hw.init = &init;
+
+       clk = clk_register(NULL, &pll_clock->hw);
+       if (IS_ERR(clk)) {
+               pr_err("%s: failed to register %s div clock (%ld)\n",
+                      __func__, clk_name, PTR_ERR(clk));
+               goto unmap_wdt;
+       }
+
+       of_clk_add_provider(node, of_clk_src_simple_get, clk);
+       return;
+
+unmap_wdt:
+       iounmap(pll_clock->pllcr);
+unmap_freqcr:
+       iounmap(pll_clock->sckcr);
+free_clock:
+       kfree(pll_clock);
+}
+
+CLK_OF_DECLARE(sh7619_pll_clk, "renesas,sh7619-pll-clock",
+              sh7619_pll_clk_setup);