x86/acpi/cstate: Add Zhaoxin processors support for cache flush policy in C3

Same as Intel, Zhaoxin MP CPUs support C3 share cache and on all
recent Zhaoxin platforms ARB_DISABLE is a nop. So set related
flags correctly in the same way as Intel does.

Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: "hpa@zytor.com" <hpa@zytor.com>
Cc: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>
Cc: "rjw@rjwysocki.net" <rjw@rjwysocki.net>
Cc: "lenb@kernel.org" <lenb@kernel.org>
Cc: David Wang <DavidWang@zhaoxin.com>
Cc: "Cooper Yan(BJ-RD)" <CooperYan@zhaoxin.com>
Cc: "Qiyuan Wang(BJ-RD)" <QiyuanWang@zhaoxin.com>
Cc: "Herry Yang(BJ-RD)" <HerryYang@zhaoxin.com>
Link: https://lkml.kernel.org/r/a370503660994669991a7f7cda7c5e98@zhaoxin.com

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index a5e5484..caf2edc 100644 (file)
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -64,6 +64,21 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
                    c->x86_stepping >= 0x0e))
                        flags->bm_check = 1;
        }
+
+       if (c->x86_vendor == X86_VENDOR_ZHAOXIN) {
+               /*
+                * All Zhaoxin CPUs that support C3 share cache.
+                * And caches should not be flushed by software while
+                * entering C3 type state.
+                */
+               flags->bm_check = 1;
+               /*
+                * On all recent Zhaoxin platforms, ARB_DISABLE is a nop.
+                * So, set bm_control to zero to indicate that ARB_DISABLE
+                * is not required while entering C3 type state.
+                */
+               flags->bm_control = 0;
+       }
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);