staging: comedi: adl_pci9111: prefer using the BIT macro

As suggested by checkpatch.pl, use the BIT macro to define the
register bits.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/comedi/drivers/adl_pci9111.c b/drivers/staging/comedi/drivers/adl_pci9111.c
index c9df3af..8ce54c0 100644 (file)
--- a/drivers/staging/comedi/drivers/adl_pci9111.c
+++ b/drivers/staging/comedi/drivers/adl_pci9111.c
@@ -89,23 +89,23 @@ TODO:
 #define PCI9111_EDIO_REG               0x04
 #define PCI9111_AI_CHANNEL_REG         0x06
 #define PCI9111_AI_RANGE_STAT_REG      0x08
-#define PCI9111_AI_STAT_AD_BUSY                (1 << 7)
-#define PCI9111_AI_STAT_FF_FF          (1 << 6)
-#define PCI9111_AI_STAT_FF_HF          (1 << 5)
-#define PCI9111_AI_STAT_FF_EF          (1 << 4)
+#define PCI9111_AI_STAT_AD_BUSY                BIT(7)
+#define PCI9111_AI_STAT_FF_FF          BIT(6)
+#define PCI9111_AI_STAT_FF_HF          BIT(5)
+#define PCI9111_AI_STAT_FF_EF          BIT(4)
 #define PCI9111_AI_RANGE_MASK          (7 << 0)
 #define PCI9111_AI_TRIG_CTRL_REG       0x0a
-#define PCI9111_AI_TRIG_CTRL_TRGEVENT  (1 << 5)
-#define PCI9111_AI_TRIG_CTRL_POTRG     (1 << 4)
-#define PCI9111_AI_TRIG_CTRL_PTRG      (1 << 3)
-#define PCI9111_AI_TRIG_CTRL_ETIS      (1 << 2)
-#define PCI9111_AI_TRIG_CTRL_TPST      (1 << 1)
-#define PCI9111_AI_TRIG_CTRL_ASCAN     (1 << 0)
+#define PCI9111_AI_TRIG_CTRL_TRGEVENT  BIT(5)
+#define PCI9111_AI_TRIG_CTRL_POTRG     BIT(4)
+#define PCI9111_AI_TRIG_CTRL_PTRG      BIT(3)
+#define PCI9111_AI_TRIG_CTRL_ETIS      BIT(2)
+#define PCI9111_AI_TRIG_CTRL_TPST      BIT(1)
+#define PCI9111_AI_TRIG_CTRL_ASCAN     BIT(0)
 #define PCI9111_INT_CTRL_REG           0x0c
-#define PCI9111_INT_CTRL_ISC2          (1 << 3)
-#define PCI9111_INT_CTRL_FFEN          (1 << 2)
-#define PCI9111_INT_CTRL_ISC1          (1 << 1)
-#define PCI9111_INT_CTRL_ISC0          (1 << 0)
+#define PCI9111_INT_CTRL_ISC2          BIT(3)
+#define PCI9111_INT_CTRL_FFEN          BIT(2)
+#define PCI9111_INT_CTRL_ISC1          BIT(1)
+#define PCI9111_INT_CTRL_ISC0          BIT(0)
 #define PCI9111_SOFT_TRIG_REG          0x0e
 #define PCI9111_8254_BASE_REG          0x40
 #define PCI9111_INT_CLR_REG            0x48