arm64: dts: imx8mq-evk: Enable the QuadSPI controller

Enable the Freescale/NXP QuadSPI controller with a proper pinctrl set on
the i.MX8MQ EVK board.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 00b2904..d3fcb88 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -158,6 +158,20 @@
        status = "okay";
 };
 
+&qspi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_qspi>;
+       status = "okay";
+
+       n25q256a: flash@0 {
+               reg = <0>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "micron,n25q256a", "jedec,spi-nor";
+               spi-max-frequency = <29000000>;
+       };
+};
+
 &usdhc1 {
        pinctrl-names = "default", "state_100mhz", "state_200mhz";
        pinctrl-0 = <&pinctrl_usdhc1>;
@@ -216,6 +230,18 @@
                >;
        };
 
+       pinctrl_qspi: qspigrp {
+               fsl,pins = <
+                       MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK       0x82
+                       MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B    0x82
+                       MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0   0x82
+                       MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1   0x82
+                       MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2   0x82
+                       MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3   0x82
+
+               >;
+       };
+
        pinctrl_reg_usdhc2: regusdhc2grpgpio {
                fsl,pins = <
                        MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19             0x41