clk: sunxi-ng: a83t: Fix PLL lock status register offset

The offset for the PLL lock status register was incorrectly set to
0x208, which actually points to an unused register. The correct
register offset is 0x20c.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index 4a201a7..a9c5cc8 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -28,7 +28,7 @@
 
 #include "ccu-sun8i-a83t.h"
 
-#define CCU_SUN8I_A83T_LOCK_REG        0x208
+#define CCU_SUN8I_A83T_LOCK_REG        0x20c
 
 /*
  * The CPU PLLs are actually NP clocks, with P being /1 or /4. However