clear_event(this, event_next_sector);
clear_event(this, event_seek_completed);
status_read_done(false);
- cdrom_debug_log(_T("EOT(%s/DMA)"), (by_signal) ? by_dma : by_event);
+ //cdrom_debug_log(_T("EOT(%s/DMA)"), (by_signal) ? by_dma : by_event);
+ out_debug_log(_T("EOT(%s/DMA)"), (by_signal) ? by_dma : by_event);
} else {
- cdrom_debug_log(_T("NEXT(%s/DMA)"), (by_signal) ? by_dma : by_event);
+ //cdrom_debug_log(_T("NEXT(%s/DMA)"), (by_signal) ? by_dma : by_event);
+ out_debug_log(_T("NEXT(%s/DMA)"), (by_signal) ? by_dma : by_event);
// TRY: Register after EOT. 20201123 K.O
// status_seek = true;
// register_event(this, EVENT_CDROM_SEEK_COMPLETED,
* 04C6h : Transfer control register.
*/
w_regs[addr & 0x0f] = data;
+ out_debug_log(_T("OUT8 %04X,%02X"), addr & 0xffff, data & 0xff);
switch(addr & 0x0f) {
case 0x00: // Master control register
//cdrom_debug_log(_T("PORT 04C0h <- %02X"), data);
pio_transfer_phase = true;
}
}
- cdrom_debug_log(_T("SET TRANSFER MODE to %02X"), data);
+ out_debug_log(_T("SET TRANSFER MODE to %02X"), data);
+// cdrom_debug_log(_T("SET TRANSFER MODE to %02X"), data);
// }
break;
}
void TOWNS_DMAC::write_io16(uint32_t addr, uint32_t data)
{
pair32_t _d, _bd;
+ out_debug_log(_T("OUT16 %04X,%04X"), addr & 0xffff, data & 0xffff);
// if(b16 != 0) {
switch(addr & 0x0f) {
case 0x02:
{
// if((addr & 0x0f) == 0x0c) out_debug_log("WRITE REG: %08X %08X", addr, data);
// out_debug_log("WRITE REG: %04X %02X", addr, data);
+ out_debug_log(_T("OUT8 %04X,%02X"), addr & 0xffff, data & 0xff);
uint naddr;
pair32_t _d;
pair32_t _bd;