arm64: dts: Using standard CCF interface to set vcodec clk

Using standard CCF interface to set vdec/venc parent clk
and clk rate.

Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
Signed-off-by: Qianqian Yan <qianqian.yan@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index c3c3601..94529b7 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -1307,6 +1307,15 @@
                                      "vencpll",
                                      "venc_lt_sel",
                                      "vdec_bus_clk_src";
+                       assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
+                                         <&topckgen CLK_TOP_CCI400_SEL>,
+                                         <&topckgen CLK_TOP_VDEC_SEL>,
+                                         <&apmixedsys CLK_APMIXED_VCODECPLL>,
+                                         <&apmixedsys CLK_APMIXED_VENCPLL>;
+                       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
+                                                <&topckgen CLK_TOP_UNIVPLL_D2>,
+                                                <&topckgen CLK_TOP_VCODECPLL>;
+                       assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
                };
 
                larb1: larb@16010000 {
@@ -1372,6 +1381,10 @@
                                      "venc_sel",
                                      "venc_lt_sel_src",
                                      "venc_lt_sel";
+                       assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
+                                         <&topckgen CLK_TOP_VENC_LT_SEL>;
+                       assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
+                                                <&topckgen CLK_TOP_UNIVPLL1_D2>;
                };
 
                vencltsys: clock-controller@19000000 {