{
struct dcn10_ipp *ippn10 = TO_DCN10_IPP(ipp);
- REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
REG_UPDATE(CM_CONTROL, CM_BYPASS_EN, 0);
}
IPP_SF(CM0_CM_DGAM_LUT_WRITE_EN_MASK, CM_DGAM_LUT_WRITE_SEL, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_INDEX, CM_DGAM_LUT_INDEX, mask_sh), \
IPP_SF(CM0_CM_DGAM_LUT_DATA, CM_DGAM_LUT_DATA, mask_sh), \
- IPP_SF(DPP_TOP0_DPP_CONTROL, DPP_CLOCK_ENABLE, mask_sh), \
IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \
type CM_DGAM_LUT_WRITE_SEL; \
type CM_DGAM_LUT_INDEX; \
type CM_DGAM_LUT_DATA; \
- type DPP_CLOCK_ENABLE; \
type CM_BYPASS_EN; \
type CM_BYPASS; \
type CNVC_SURFACE_PIXEL_FORMAT; \