+2008-08-14 Jie Zhang <jie.zhang@analog.com>
+
+ * bfin/Makefile.in: (top_srcdir): Define.
+ (mkinstalldirs): Define.
+ (BOARD_SCRIPTS): Define.
+ (BOARD_LDFLAGS): Define.
+ (BOARD_BSP): Define.
+ (BOARD_CRT0S): Define.
+ (BOARD_OBJS): Define.
+ (BOARD_TEST): Define.
+ (BOARD_INSTALL): Define.
+ (INCLUDES): Add -I$(srcdir)/include.
+ (all): Add ${BOARD_CRT0S} and ${BOARD_BSP}.
+ (.c.S): Remove target.
+ (crt0.o): New target.
+ (basiccrt.o): Likewise.
+ (basiccrtb.o): Likewise.
+ (basiccrts.o): Likewise.
+ (basiccrt561.o, basiccrt561s.o, basiccrt561b.o): Likewise
+ (clean mostlyclean): Remove ${BOARD_BSP}.
+ (install): Depend on ${BOARD_INSTALL}.
+ (install-sim): Reformat.
+ (install-board): New target.
+ * bfin/basiccrt.S: Remove useless __ADSPBF561_COREB__ in
+ workaround code for 05000229.
+ * bfin/syscalls.c (do_syscall): Use `EXCPT 0' instead of
+ `RAISE 0' for syscall.
+ * bfin/basiccrt.S: New file.
+ * bfin/bf5*ld: New file.
+ * bfin/bfin-common-mc.ld: New file.
+ * bfin/bfin-common-sc.ld: New file.
+ * bfin/include/blackfin.h: New file.
+ * bfin/include/cdefBF5*.h: New file.
+ * bfin/include/cdef_LPBlackfin.h: New file.
+ * bfin/include/cdefblackfin.h: New file.
+ * bfin/include/cplb.h: New file.
+ * bfin/include/cplbtab.h: New file.
+ * bfin/include/defBF5*.h: New files.
+ * bfin/include/def_LPBlackfin.h: New files.
+ * bfin/include/defblackfin.h: New file.
+ * bfin/include/sys/_adi_platform.h: New file.
+ * bfin/include/sys/anomaly_macros_rtl.h: New file.
+ * bfin/include/sys/excause.h: New file.
+ * bfin/include/sys/exception.h: New file.
+ * bfin/include/sys/mc_typedef.h: New file.
+ * bfin/include/sys/platform.h: New file.
+ * bfin/include/sys/pll.h: New file.
+ * bfin/include/sysreg.h: New file.
+ * libnosys/configure.in (MISSING_SYSCALL_NAMES): Don't define
+ for bfin.
+ * libnosys/configure: Regenerate.
+
2008-07-17 Ken Werner <ken.werner@de.ibm.com>
* spu/syscalls.c: Check and set the errno value.
objdir = .
srcroot = $(srcdir)/../..
objroot = $(objdir)/../..
+top_srcdir = @top_srcdir@
prefix = @prefix@
exec_prefix = @exec_prefix@
SHELL = /bin/sh
+mkinstalldirs = $(SHELL) $(top_srcdir)/../../mkinstalldirs
+
CC = @CC@
AS = @AS@
SIM_TEST = sim-test
SIM_INSTALL = install-sim
+# Here is all of the development board stuff
+# BF531, BF532, BF533, BF537
+BOARD_SCRIPTS = bfin-common-sc.ld bfin-common-mc.ld \
+ bf522.ld bf523.ld bf524.ld bf525.ld bf526.ld bf527.ld \
+ bf531.ld bf532.ld bf533.ld \
+ bf534.ld bf536.ld bf537.ld \
+ bf538.ld bf539.ld \
+ bf542.ld bf544.ld bf547.ld bf548.ld bf549.ld \
+ bf561.ld bf561a.ld bf561b.ld bf561m.ld
+BOARD_LDFLAGS =
+BOARD_BSP = # We actually use libnosys.a
+BOARD_CRT0S = basiccrt.o basiccrts.o
+BOARD_CRT0S += basiccrt561.o basiccrt561s.o basiccrt561b.o
+BOARD_OBJS =
+BOARD_TEST =
+BOARD_INSTALL = install-board
+
# Host specific makefile fragment comes in here.
@host_makefile_frag@
+INCLUDES += -I$(srcdir)/include
#
# build a test program for each target board. Just trying to get
# it to link is a good test, so we ignore all the errors for now.
#
-all: ${SIM_CRT0} ${SIM_BSP}
+all: ${SIM_CRT0} ${SIM_BSP} ${BOARD_CRT0S} ${BOARD_BSP}
#
# here's where we build the board support packages for each target
#
#
#
-.c.S:
- ${CC} ${CFLAGS_FOR_TARGET} -c $<
+crt0.o: crt0.S
+
+basiccrt.o: basiccrt.S
+ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
+ $(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -o $@ -c $<
+else
+ $(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf532-any -o $@ -c $<
+endif
+
+basiccrts.o: basiccrt.S
+ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
+ $(CC) -D__BFIN_SDRAM $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -o $@ -c $<
+else
+ $(CC) -D__BFIN_SDRAM $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf532-any -o $@ -c $<
+endif
+
+basiccrt561.o: basiccrt.S
+ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
+ $(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-none -o $@ -c $<
+else
+ $(CC) $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-any -o $@ -c $<
+endif
+
+basiccrt561s.o: basiccrt.S
+ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
+ $(CC) -D__BFIN_SDRAM $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-none -o $@ -c $<
+else
+ $(CC) -D__BFIN_SDRAM $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-any -o $@ -c $<
+endif
+
+
+basiccrt561b.o: basiccrt.S
+ifneq (,$(findstring mcpu=bf532-none,$(CFLAGS)))
+ $(CC) -D__ADSPBF561_COREB__ $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-none -o $@ -c $<
+else
+ $(CC) -D__ADSPBF561_COREB__ $(CFLAGS_FOR_TARGET) $(INCLUDES) $(CFLAGS) -mcpu=bf561-any -o $@ -c $<
+endif
clean mostlyclean:
- rm -f a.out core *.i *.o $(SIM_BSP)
+ rm -f a.out core *.i *.o ${SIM_BSP} ${BOARD_BSP}
distclean maintainer-clean realclean: clean
rm -f Makefile config.status *~
.PHONY: install info install-info clean-info
-install: ${SIM_INSTALL}
+install: ${SIM_INSTALL} ${BOARD_INSTALL}
install-sim:
- set -e; for x in ${SIM_CRT0} ${SIM_BSP} ${SIM_SCRIPTS}; do ${INSTALL_DATA} $$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/$$x; done
+ for x in ${SIM_CRT0} ${SIM_BSP} ${SIM_SCRIPTS}; do \
+ ${INSTALL_DATA} $$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/$$x; \
+ done
+
+install-board:
+ for x in ${BOARD_CRT0S} ${BOARD_BSP}; do \
+ ${INSTALL_DATA} $$x $(DESTDIR)${tooldir}/lib${MULTISUBDIR}/$$x; \
+ done
+ -if [ -z "${MULTISUBDIR}" ]; then \
+ for x in ${BOARD_SCRIPTS}; do \
+ ${INSTALL_DATA} ${srcdir}/$$x $(DESTDIR)${tooldir}/lib/$$x; \
+ done; \
+ ${mkinstalldirs} ${DESTDIR}${tooldir}/include; \
+ for i in ${srcdir}/include/*.h; do \
+ ${INSTALL_DATA} $$i ${DESTDIR}${tooldir}/include/`basename $$i`; \
+ done; \
+ ${mkinstalldirs} ${DESTDIR}${tooldir}/include/sys; \
+ for i in ${srcdir}/include/sys/*.h; do \
+ ${INSTALL_DATA} $$i ${DESTDIR}${tooldir}/include/sys/`basename $$i`; \
+ done; \
+ else true; fi
doc:
info:
--- /dev/null
+/*
+ * Basic startup code for Blackfin processor
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+// basic startup code which
+// - turns the cycle counter on
+// - loads up FP & SP (both supervisor and user)
+// - initialises the device drivers (FIOCRT)
+// - calls monstartup to set up the profiling routines (PROFCRT)
+// - calls the C++ startup (CPLUSCRT)
+// - initialises argc/argv (FIOCRT/normal)
+// - calls _main
+// - calls _exit (which calls monexit to dump accumulated prof data (PROFCRT))
+// - defines dummy IO routines (!FIOCRT)
+
+#include <sys/platform.h>
+#include <cplb.h>
+#include <sys/anomaly_macros_rtl.h>
+
+#define IVBh (EVT0 >> 16)
+#define IVBl (EVT0 & 0xFFFF)
+#define UNASSIGNED_VAL 0
+#define UNASSIGNED_FILL 0
+// just IVG15
+#define INTERRUPT_BITS 0x400
+#if defined(_ADI_THREADS) || \
+ !defined(__ADSPLPBLACKFIN__) || defined(__ADSPBF561__) || defined(__ADSPBF566__)
+#define SET_CLOCK_SPEED 0
+#else
+#define SET_CLOCK_SPEED 1
+#endif
+
+#if SET_CLOCK_SPEED == 1
+#include <sys/pll.h>
+#define SET_CLK_MSEL 0x16
+#define SET_CLK_DF 0
+#define SET_CLK_LOCK_COUNT 0x300
+#define SET_CLK_CSEL 0
+#define SET_CLK_SSEL 5
+
+/*
+** CLKIN == 27MHz on the EZ-Kits.
+** D==0 means CLKIN is passed to PLL without dividing.
+** MSEL==0x16 means VCO==27*0x16 == 594MHz
+** CSEL==0 means CCLK==VCO == 594MHz
+** SSEL==5 means SCLK==VCO/5 == 118MHz
+*/
+
+#endif
+
+#ifdef __ADSPBF561_COREB__
+ .section .b.text,"ax",@progbits
+ .align 2;
+ .global __coreb_start;
+ .type __coreb_start, STT_FUNC;
+__coreb_start:
+#else
+ .text;
+ .align 2;
+ .global __start;
+ .type __start, STT_FUNC;
+__start:
+#endif
+#if WA_05000109
+ // Avoid Anomaly ID 05000109.
+# define SYSCFG_VALUE 0x30
+ R1 = SYSCFG_VALUE;
+ SYSCFG = R1;
+#endif
+#if WA_05000229
+ // Avoid Anomaly 05-00-0229: DMA5_CONFIG and SPI_CTL not cleared on reset.
+ R1 = 0x400;
+#if defined(__ADSPBF538__) || defined(__ADSPBF539__)
+ P0.L = SPI0_CTL & 0xFFFF;
+ P0.H = SPI0_CTL >> 16;
+ W[P0] = R1.L;
+#else
+ P0.L = SPI_CTL & 0xFFFF;
+ P0.H = SPI_CTL >> 16;
+ W[P0] = R1.L;
+#endif
+ P0.L = DMA5_CONFIG & 0xFFFF;
+ P0.H = DMA5_CONFIG >> 16;
+ R1 = 0;
+ W[P0] = R1.L;
+#endif
+ // Zap loop counters to zero, to make sure that
+ // hw loops are disabled - it could be really baffling
+ // if the counters and bottom regs are set, and we happen
+ // to run into them.
+ R7 = 0;
+ LC0 = R7;
+ LC1 = R7;
+
+ // Clear the DAG Length regs too, so that it's safe to
+ // use I-regs without them wrapping around.
+ L0 = R7;
+ L1 = R7;
+ L2 = R7;
+ L3 = R7;
+
+ // Zero ITEST_COMMAND and DTEST_COMMAND
+ // (in case they have crud in them and
+ // does a write somewhere when we enable cache)
+ I0.L = (ITEST_COMMAND & 0xFFFF);
+ I0.H = (ITEST_COMMAND >> 16);
+ I1.L = (DTEST_COMMAND & 0xFFFF);
+ I1.H = (DTEST_COMMAND >> 16);
+ R7 = 0;
+ [I0] = R7;
+ [I1] = R7;
+ // It seems writing ITEST_COMMAND from SDRAM with icache enabled
+ // needs SSYNC.
+#ifdef __BFIN_SDRAM
+ SSYNC;
+#else
+ CSYNC;
+#endif
+
+ // Initialise the Event Vector table.
+ P0.H = IVBh;
+ P0.L = IVBl;
+
+ // Install __unknown_exception_occurred in EVT so that
+ // there is defined behaviour.
+ P0 += 2*4; // Skip Emulation and Reset
+ P1 = 13;
+ R1.L = __unknown_exception_occurred;
+ R1.H = __unknown_exception_occurred;
+ LSETUP (L$ivt,L$ivt) LC0 = P1;
+L$ivt: [P0++] = R1;
+ // Set IVG15's handler to be the start of the mode-change
+ // code. Then, before we return from the Reset back to user
+ // mode, we'll raise IVG15. This will mean we stay in supervisor
+ // mode, and continue from the mode-change point., but at a
+ // much lower priority.
+ P1.H = L$supervisor_mode;
+ P1.L = L$supervisor_mode;
+ [P0] = P1;
+
+ // Initialise the stack.
+ // Note: this points just past the end of the section.
+ // First write should be with [--SP].
+#ifdef __BFIN_SDRAM
+ SP.L = __end + 0x400000 - 12;
+ SP.H = __end + 0x400000 - 12;
+#else
+#ifdef __ADSPBF561_COREB__
+ SP.L=__coreb_stack_end - 12;
+ SP.H=__coreb_stack_end - 12;
+#else
+ SP.L=__stack_end - 12;
+ SP.H=__stack_end - 12;
+#endif
+#endif
+ usp = sp;
+
+ // We're still in supervisor mode at the moment, so the FP
+ // needs to point to the supervisor stack.
+ FP = SP;
+
+ // And make space for incoming "parameters" for functions
+ // we call from here:
+ SP += -12;
+
+ // Zero out bss section
+#ifdef __BFIN_SDRAM
+ R0.L = ___bss_start;
+ R0.H = ___bss_start;
+ R1.L = __end;
+ R1.H = __end;
+#else
+#ifdef __ADSPBF561_COREB__
+ R0.L = __coreb_bss_start;
+ R0.H = __coreb_bss_start;
+ R1.L = __coreb_bss_end;
+ R1.H = __coreb_bss_end;
+#else
+ R0.L = __bss_start;
+ R0.H = __bss_start;
+ R1.L = __bss_end;
+ R1.H = __bss_end;
+#endif
+#endif
+ R2 = R1 - R0;
+ R1 = 0;
+#ifdef __ADSPBF561_COREB__
+ CALL.X __coreb_memset;
+#else
+ CALL.X _memset;
+#endif
+
+ R0 = INTERRUPT_BITS;
+ R0 <<= 5; // Bits 0-4 not settable.
+ // CALL.X __install_default_handlers;
+ R4 = R0; // Save modified list
+
+ R0 = SYSCFG; // Enable the Cycle counter
+ BITSET(R0,1);
+ SYSCFG = R0;
+
+#if WA_05000137
+ // Avoid anomaly #05000137
+
+ // Set the port preferences of DAG0 and DAG1 to be
+ // different; this gives better performance when
+ // performing dual-dag operations on SDRAM.
+ P0.L = DMEM_CONTROL & 0xFFFF;
+ P0.H = DMEM_CONTROL >> 16;
+ R0 = [P0];
+ BITSET(R0, 12);
+ BITCLR(R0, 13);
+ [P0] = R0;
+ CSYNC;
+#endif
+
+ // Reinitialise data areas in RAM from ROM, if MemInit's
+ // been used.
+ // CALL.X _mi_initialize;
+
+#if defined(__ADSPLPBLACKFIN__)
+#if SET_CLOCK_SPEED == 1
+
+#if 0
+ // Check if this feature is enabled, i.e. ___clk_ctrl is defined to non-zero
+ P0.L = ___clk_ctrl;
+ P0.H = ___clk_ctrl;
+ R0 = MAX_IN_STARTUP;
+ R1 = [P0];
+ R0 = R0 - R1;
+ CC = R0;
+ IF CC JUMP L$clock_is_set;
+#endif
+
+ // Investigate whether we are a suitable revision
+ // for boosting the system clocks.
+ // speed.
+ P0.L = DSPID & 0xFFFF;
+ P0.H = DSPID >> 16;
+ R0 = [P0];
+ R0 = R0.L (Z);
+ CC = R0 < 2;
+ IF CC JUMP L$clock_is_set;
+
+ // Set the internal Voltage-Controlled Oscillator (VCO)
+ R0 = SET_CLK_MSEL (Z);
+ R1 = SET_CLK_DF (Z);
+ R2 = SET_CLK_LOCK_COUNT (Z);
+ CALL.X __pll_set_system_vco;
+
+ // Set the Core and System clocks
+ R0 = SET_CLK_CSEL (Z);
+ R1 = SET_CLK_SSEL (Z);
+ CALL.X __pll_set_system_clocks;
+
+L$clock_is_set:
+#endif
+#endif /* ADSPLPBLACKFIN */
+
+#if defined(__ADSPBF561__) || defined(__ADSPBF566__)
+ // Initialise the multi-core data tables.
+ // A dummy function will be called if we are not linking with
+ // -multicore
+ // CALL.X __mc_data_initialise;
+#endif
+
+#if 0
+ // Write the cplb exception handler to the EVT if approprate and
+ // initialise the CPLBs if they're needed. couldn't do
+ // this before we set up the stacks.
+ P2.H = ___cplb_ctrl;
+ P2.L = ___cplb_ctrl;
+ R0 = CPLB_ENABLE_ANY_CPLBS;
+ R6 = [P2];
+ R0 = R0 & R6;
+ CC = R0;
+ IF !CC JUMP L$no_cplbs;
+#if !defined(_ADI_THREADS)
+ P1.H = __cplb_hdr;
+ P1.L = __cplb_hdr;
+ P0.H = IVBh;
+ P0.L = IVBl;
+ [P0+12] = P1; // write exception handler
+#endif /* _ADI_THREADS */
+ R0 = R6;
+ CALL.X __cplb_init;
+#endif
+L$no_cplbs:
+ // Enable interrupts
+ STI R4; // Using the mask from default handlers
+ RAISE 15;
+
+ // Move the processor into user mode.
+ P0.L=L$still_interrupt_in_ipend;
+ P0.H=L$still_interrupt_in_ipend;
+ RETI=P0;
+
+L$still_interrupt_in_ipend:
+ rti; // keep doing 'rti' until we've 'finished' servicing all
+ // interrupts of priority higher than IVG15. Normally one
+ // would expect to only have the reset interrupt in IPEND
+ // being serviced, but occasionally when debugging this may
+ // not be the case - if restart is hit when servicing an
+ // interrupt.
+ //
+ // When we clear all bits from IPEND, we'll enter user mode,
+ // then we'll automatically jump to supervisor_mode to start
+ // servicing IVG15 (which we will 'service' for the whole
+ // program, so that the program is in supervisor mode.
+ //
+ // Need to do this to 'finish' servicing the reset interupt.
+
+L$supervisor_mode:
+ [--SP] = RETI; // re-enables the interrupt system
+
+ R0.L = UNASSIGNED_VAL;
+ R0.H = UNASSIGNED_VAL;
+#if UNASSIGNED_FILL
+ R2=R0;
+ R3=R0;
+ R4=R0;
+ R5=R0;
+ R6=R0;
+ R7=R0;
+ P0=R0;
+ P1=R0;
+ P2=R0;
+ P3=R0;
+ P4=R0;
+ P5=R0;
+#endif
+ // Push a RETS and Old FP onto the stack, for sanity.
+ [--SP]=R0;
+ [--SP]=R0;
+ // Make sure the FP is sensible.
+ FP = SP;
+
+ // And leave space for incoming "parameters"
+ SP += -12;
+
+#ifdef PROFCRT
+ CALL.X monstartup; // initialise profiling routines
+#endif /* PROFCRT */
+
+#ifndef __ADSPBF561_COREB__
+ CALL.X __init;
+
+ R0.L = __fini;
+ R0.H = __fini;
+ CALL.X _atexit;
+#endif
+
+#if !defined(_ADI_THREADS)
+#ifdef FIOCRT
+ // FILE IO provides access to real command-line arguments.
+ CALL.X __getargv;
+ r1.l=__Argv;
+ r1.h=__Argv;
+#else
+ // Default to having no arguments and a null list.
+ R0=0;
+#ifdef __ADSPBF561_COREB__
+ R1.L=L$argv_coreb;
+ R1.H=L$argv_coreb;
+#else
+ R1.L=L$argv;
+ R1.H=L$argv;
+#endif
+#endif /* FIOCRT */
+#endif /* _ADI_THREADS */
+
+ // At long last, call the application program.
+#ifdef __ADSPBF561_COREB__
+ CALL.X _coreb_main;
+#else
+ CALL.X _main;
+#endif
+
+#if !defined(_ADI_THREADS)
+#ifndef __ADSPBF561_COREB__
+ CALL.X _exit; // passing in main's return value
+#endif
+#endif
+
+#ifdef __ADSPBF561_COREB__
+ .size __coreb_start, .-__coreb_start
+#else
+ .size __start, .-__start
+#endif
+
+ .align 2
+ .type __unknown_exception_occurred, STT_FUNC;
+__unknown_exception_occurred:
+ // This function is invoked by the default exception
+ // handler, if it does not recognise the kind of
+ // exception that has occurred. In other words, the
+ // default handler only handles some of the system's
+ // exception types, and it does not expect any others
+ // to occur. If your application is going to be using
+ // other kinds of exceptions, you must replace the
+ // default handler with your own, that handles all the
+ // exceptions you will use.
+ //
+ // Since there's nothing we can do, we just loop here
+ // at what we hope is a suitably informative label.
+ IDLE;
+ CSYNC;
+ JUMP __unknown_exception_occurred;
+ RTS;
+ .size __unknown_exception_occurred, .-__unknown_exception_occurred
+
+#if defined(__ADSPLPBLACKFIN__)
+#if SET_CLOCK_SPEED == 1
+
+/*
+** CLKIN == 27MHz on the EZ-Kits.
+** D==0 means CLKIN is passed to PLL without dividing.
+** MSEL==0x16 means VCO==27*0x16 == 594MHz
+** CSEL==0 means CCLK==VCO == 594MHz
+** SSEL==5 means SCLK==VCO/5 == 118MHz
+*/
+
+// int pll_set_system_clocks(int csel, int ssel)
+// returns 0 for success, -1 for error.
+
+ .align 2
+ .type __pll_set_system_clocks, STT_FUNC;
+__pll_set_system_clocks:
+ P0.H = PLL_DIV >> 16;
+ P0.L = PLL_DIV & 0xFFFF;
+ R2 = W[P0] (Z);
+
+ // Plant CSEL and SSEL
+ R0 <<= 16;
+ R0.L = (4 << 8) | 2; // 2 bits, at posn 4
+ R1 <<= 16;
+ R1.L = 4; // 4 bits, at posn 0
+ R2 = DEPOSIT(R2, R0);
+
+#if defined(__WORKAROUND_DREG_COMP_LATENCY)
+ // Work around anomaly 05-00-0209 which affects the DEPOSIT
+ // instruction (and the EXTRACT, SIGNBITS, and EXPADJ instructions)
+ // if the previous instruction created any of its operands
+ NOP;
+#endif
+
+ R2 = DEPOSIT(R2, R1);
+
+ W[P0] = R2;
+ SSYNC;
+ RTS;
+ .size __pll_set_system_clocks, .-__pll_set_system_clocks
+
+// int pll_set_system_vco(int msel, int df, lockcnt)
+ .align 2
+ .type __pll_set_system_vco, STT_FUNC;
+__pll_set_system_vco:
+ P0.H = PLL_CTL >> 16;
+ P0.L = PLL_CTL & 0xFFFF;
+ R3 = W[P0] (Z);
+ P2 = R3; // Save copy
+ R3 >>= 1; // Drop old DF
+ R1 = ROT R1 BY -1; // Move DF into CC
+ R3 = ROT R3 BY 1; // and into ctl space.
+ R0 <<= 16; // Set up pattern reg
+ R0.L = (9<<8) | 6; // (6 bits at posn 9)
+ R1 = P2; // Get the old version
+ R3 = DEPOSIT(R3, R0);
+ CC = R1 == R3; // and if we haven't changed
+ IF CC JUMP L$done; // Anything, return
+
+ CC = R2 == 0; // Use default lockcount if
+ IF CC JUMP L$wakeup; // user one is zero.
+ P2.H = PLL_LOCKCNT >> 16;
+ P2.L = PLL_LOCKCNT & 0xFFFF;
+ W[P2] = R2; // Set the lock counter
+L$wakeup:
+ P2.H = SIC_IWR >> 16;
+ P2.L = SIC_IWR & 0xFFFF;
+ R2 = [P2];
+ BITSET(R2, 0); // enable PLL Wakeup
+ [P2] = R2;
+
+ W[P0] = R3; // Update PLL_CTL
+ SSYNC;
+
+ CLI R2; // Avoid unnecessary interrupts
+ IDLE; // Wait until PLL has locked
+ STI R2; // Restore interrupts.
+
+L$done:
+ RTS;
+ .size __pll_set_system_vco, .-__pll_set_system_vco
+#endif
+#endif /* ADSPLPBLACKFIN */
+
+#ifdef __ADSPBF561_COREB__
+ .section .b.text,"ax",@progbits
+ .type __coreb_memset, STT_FUNC
+__coreb_memset:
+ P0 = R0 ; /* P0 = address */
+ P2 = R2 ; /* P2 = count */
+ R3 = R0 + R2; /* end */
+ CC = R2 <= 7(IU);
+ IF CC JUMP .Ltoo_small;
+ R1 = R1.B (Z); /* R1 = fill char */
+ R2 = 3;
+ R2 = R0 & R2; /* addr bottom two bits */
+ CC = R2 == 0; /* AZ set if zero. */
+ IF !CC JUMP .Lforce_align ; /* Jump if addr not aligned. */
+
+.Laligned:
+ P1 = P2 >> 2; /* count = n/4 */
+ R2 = R1 << 8; /* create quad filler */
+ R2.L = R2.L + R1.L(NS);
+ R2.H = R2.L + R1.H(NS);
+ P2 = R3;
+
+ LSETUP (.Lquad_loop , .Lquad_loop) LC0=P1;
+.Lquad_loop:
+ [P0++] = R2;
+
+ CC = P0 == P2;
+ IF !CC JUMP .Lbytes_left;
+ RTS;
+
+.Lbytes_left:
+ R2 = R3; /* end point */
+ R3 = P0; /* current position */
+ R2 = R2 - R3; /* bytes left */
+ P2 = R2;
+
+.Ltoo_small:
+ CC = P2 == 0; /* Check zero count */
+ IF CC JUMP .Lfinished; /* Unusual */
+
+.Lbytes:
+ LSETUP (.Lbyte_loop , .Lbyte_loop) LC0=P2;
+.Lbyte_loop:
+ B[P0++] = R1;
+
+.Lfinished:
+ RTS;
+
+.Lforce_align:
+ CC = BITTST (R0, 0); /* odd byte */
+ R0 = 4;
+ R0 = R0 - R2;
+ P1 = R0;
+ R0 = P0; /* Recover return address */
+ IF !CC JUMP .Lskip1;
+ B[P0++] = R1;
+.Lskip1:
+ CC = R2 <= 2; /* 2 bytes */
+ P2 -= P1; /* reduce count */
+ IF !CC JUMP .Laligned;
+ B[P0++] = R1;
+ B[P0++] = R1;
+ JUMP .Laligned;
+.size __coreb_memset,.-__coreb_memset
+#endif
+
+#ifdef __ADSPBF561_COREB__
+ .section .b.bss,"aw",@progbits
+ .align 4
+ .type L$argv_coreb, @object
+ .size L$argv_coreb, 4
+L$argv_coreb:
+ .zero 4
+#else
+ .local L$argv
+ .comm L$argv,4,4
+#endif
+
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF522 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF523 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF522 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF525 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF522 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF527 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xc000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF531 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA08000, LENGTH = 0x4000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_A : ORIGIN = 0xFF804000, LENGTH = 0x4000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF532 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA08000, LENGTH = 0x8000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF904000, LENGTH = 0x4000
+ MEM_L1_DATA_A : ORIGIN = 0xFF804000, LENGTH = 0x4000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF533 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executable running on
+ * ADSP-BF534 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xC000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executable running on
+ * ADSP-BF536 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xC000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF904000, LENGTH = 0x4000
+ MEM_L1_DATA_A : ORIGIN = 0xFF804000, LENGTH = 0x4000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executable running on
+ * ADSP-BF537 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0xC000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executable running on
+ * ADSP-BF538 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executable running on
+ * ADSP-BF539 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x10000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF542 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF544 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF547 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF548 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF549 processor.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x8000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF561 processor (single core).
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x4000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * Core A of ADSP-BF561 processor (dual core).
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x4000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ B_MEM_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x0
+ B_MEM_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x0
+ B_MEM_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x0
+ B_MEM_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x0
+ B_MEM_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x0
+
+ MEM_L2 : ORIGIN = 0xFEB08000, LENGTH = 0x8000
+ MEM_L2_SHARED : ORIGIN = 0xFEB10000, LENGTH = 0x10000
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * Core B of ADSP-BF561 processor (dual core).
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ /* These B_MEM_* are Core A memory region with zero length.
+ They just provide dummy memory region to satisfy bfin-common-mc.ld. */
+ B_MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x0
+ B_MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x0
+ B_MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x0
+ B_MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x0
+ B_MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x0
+
+ MEM_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x4000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x8000
+ MEM_L2_SHARED : ORIGIN = 0xFEB10000, LENGTH = 0x10000
+}
--- /dev/null
+/*
+ * The default linker stript for standalone executables running on
+ * ADSP-BF561 processor (dual core).
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+MEMORY
+{
+ MEM_L1_CODE : ORIGIN = 0xFFA00000, LENGTH = 0x4000
+ MEM_L1_CODE_CACHE : ORIGIN = 0xFFA10000, LENGTH = 0x4000
+ MEM_L1_SCRATCH : ORIGIN = 0xFFB00000, LENGTH = 0x1000
+ MEM_L1_DATA_B : ORIGIN = 0xFF900000, LENGTH = 0x8000
+ MEM_L1_DATA_A : ORIGIN = 0xFF800000, LENGTH = 0x8000
+
+ B_MEM_L1_CODE : ORIGIN = 0xFF600000, LENGTH = 0x4000
+ B_MEM_L1_CODE_CACHE : ORIGIN = 0xFF610000, LENGTH = 0x4000
+ B_MEM_L1_SCRATCH : ORIGIN = 0xFF700000, LENGTH = 0x1000
+ B_MEM_L1_DATA_B : ORIGIN = 0xFF500000, LENGTH = 0x8000
+ B_MEM_L1_DATA_A : ORIGIN = 0xFF400000, LENGTH = 0x8000
+
+ MEM_L2 : ORIGIN = 0xFEB00000, LENGTH = 0x20000
+ MEM_L2_SHARED : ORIGIN = 0xFEB20000, LENGTH = 0x0
+}
--- /dev/null
+/*
+ * The common part of the default linker stripts for standalone executables
+ * running on single core Blackfin processors.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* The default linker script, for single core blackfin standalone executables */
+OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
+ "elf32-bfin")
+OUTPUT_ARCH(bfin)
+ENTRY(__start)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x0); . = 0x0;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .gnu.version_r : { *(.gnu.version_r) }
+ .rel.init : { *(.rel.init) }
+ .rela.init : { *(.rela.init) }
+ .rel.text : { *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) }
+ .rela.text : { *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) }
+ .rel.fini : { *(.rel.fini) }
+ .rela.fini : { *(.rela.fini) }
+ .rel.rodata : { *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) }
+ .rela.rodata : { *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) }
+ .rel.data.rel.ro : { *(.rel.data.rel.ro* .rel.gnu.linkonce.d.rel.ro.*) }
+ .rela.data.rel.ro : { *(.rela.data.rel.ro* .rela.gnu.linkonce.d.rel.ro.*) }
+ .rel.data : { *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) }
+ .rela.data : { *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) }
+ .rel.tdata : { *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) }
+ .rela.tdata : { *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) }
+ .rel.tbss : { *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) }
+ .rela.tbss : { *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.sdata : { *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*) }
+ .rela.sdata : { *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) }
+ .rel.sbss : { *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*) }
+ .rela.sbss : { *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) }
+ .rel.sdata2 : { *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*) }
+ .rela.sdata2 : { *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) }
+ .rel.sbss2 : { *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*) }
+ .rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
+ .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
+ .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .l2 :
+ {
+ *(.l2 .l2.*)
+ } >MEM_L2 =0
+ .l2_shared :
+ {
+ *(.l2_shared .l2_shared.*)
+ } >MEM_L2_SHARED =0
+ .b.text :
+ {
+ *(.b.text .b.text.*)
+ } >B_MEM_L1_CODE =0
+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } >MEM_L1_CODE =0
+ .init :
+ {
+ KEEP (*(.init))
+ } >MEM_L1_CODE =0
+ .plt : { *(.plt) } >MEM_L1_CODE
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >MEM_L1_CODE =0
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+ .b.rodata : { *(.b.rodata .b.rodata.*) } >B_MEM_L1_DATA_A
+ .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >MEM_L1_DATA_A
+ .rodata1 : { *(.rodata1) } >MEM_L1_DATA_A
+ .sdata2 :
+ {
+ *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+ } >MEM_L1_DATA_A
+ .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >MEM_L1_DATA_A
+ .eh_frame_hdr : { *(.eh_frame_hdr) } >MEM_L1_DATA_A
+ .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >MEM_L1_DATA_A
+ .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >MEM_L1_DATA_A
+ /* Adjust the address for the data segment. We want to adjust up to
+ the same address within the page on the next page up. */
+ . = ALIGN(0x1000) + (. & (0x1000 - 1));
+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >MEM_L1_DATA_A
+ .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >MEM_L1_DATA_A
+ /* Thread Local Storage sections */
+ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >MEM_L1_DATA_A
+ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >MEM_L1_DATA_A
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (___preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (___preinit_array_end = .);
+ } >MEM_L1_DATA_A
+ .init_array :
+ {
+ PROVIDE_HIDDEN (___init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE_HIDDEN (___init_array_end = .);
+ } >MEM_L1_DATA_A
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (___fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (___fini_array_end = .);
+ } >MEM_L1_DATA_A
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin*.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >MEM_L1_DATA_A
+ .dtors :
+ {
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >MEM_L1_DATA_A
+ .jcr : { KEEP (*(.jcr)) } >MEM_L1_DATA_A
+ .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) } >MEM_L1_DATA_A
+ .dynamic : { *(.dynamic) } >MEM_L1_DATA_A
+ .b.data :
+ {
+ *(.b.data .b.data.*)
+ } >B_MEM_L1_DATA_A
+ .data :
+ {
+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ } >MEM_L1_DATA_A
+ .data1 : { *(.data1) } >MEM_L1_DATA_A
+ .got : { *(.got.plt) *(.got) } >MEM_L1_DATA_A
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .sdata :
+ {
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ } >MEM_L1_DATA_A
+ __edata = .; PROVIDE (_edata = .);
+ .b.sbss :
+ {
+ __coreb_bss_start = .;
+ } >B_MEM_L1_DATA_A
+ .b.bss :
+ {
+ *(.b.bss .b.bss.*)
+ __coreb_bss_end = .;
+ } >B_MEM_L1_DATA_A
+ .sbss :
+ {
+ __bss_start = .;
+ *(.dynsbss)
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ } >MEM_L1_DATA_A
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections.
+ FIXME: Why do we need it? When there is no .bss section, we don't
+ pad the .data section. */
+ . = ALIGN(. != 0 ? 32 / 8 : 1);
+ __bss_end = .;
+ } >MEM_L1_DATA_A
+ . = ALIGN(32 / 8);
+ . = ALIGN(32 / 8);
+ __end = .; PROVIDE (_end = .);
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
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+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
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+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
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+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ __stack_end = ORIGIN(MEM_L1_SCRATCH) + LENGTH(MEM_L1_SCRATCH);
+ __coreb_stack_end = ORIGIN(B_MEM_L1_SCRATCH) + LENGTH(B_MEM_L1_SCRATCH);
+
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/*
+ * The common part of the default linker stripts for standalone executables
+ * running on single core Blackfin processors.
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* The default linker script, for single core blackfin standalone executables */
+OUTPUT_FORMAT("elf32-bfin", "elf32-bfin",
+ "elf32-bfin")
+OUTPUT_ARCH(bfin)
+ENTRY(__start)
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ PROVIDE (__executable_start = 0x0); . = 0x0;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
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+ .gnu.version_r : { *(.gnu.version_r) }
+ .rel.init : { *(.rel.init) }
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+ .rela.sbss2 : { *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) }
+ .rel.bss : { *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) }
+ .rela.bss : { *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .l2 :
+ {
+ *(.l2 .l2.*)
+ } >MEM_L2 =0
+ .text :
+ {
+ *(.text .stub .text.* .gnu.linkonce.t.*)
+ KEEP (*(.text.*personality*))
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ } >MEM_L1_CODE =0
+ .init :
+ {
+ KEEP (*(.init))
+ } >MEM_L1_CODE =0
+ .plt : { *(.plt) } >MEM_L1_CODE
+ .fini :
+ {
+ KEEP (*(.fini))
+ } >MEM_L1_CODE =0
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+ .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } >MEM_L1_DATA_A
+ .rodata1 : { *(.rodata1) } >MEM_L1_DATA_A
+ .sdata2 :
+ {
+ *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+ } >MEM_L1_DATA_A
+ .sbss2 : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) } >MEM_L1_DATA_A
+ .eh_frame_hdr : { *(.eh_frame_hdr) } >MEM_L1_DATA_A
+ .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } >MEM_L1_DATA_A
+ .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } >MEM_L1_DATA_A
+ /* Adjust the address for the data segment. We want to adjust up to
+ the same address within the page on the next page up. */
+ . = ALIGN(0x1000) + (. & (0x1000 - 1));
+ /* Exception handling */
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } >MEM_L1_DATA_A
+ .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } >MEM_L1_DATA_A
+ /* Thread Local Storage sections */
+ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } >MEM_L1_DATA_A
+ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } >MEM_L1_DATA_A
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (___preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (___preinit_array_end = .);
+ } >MEM_L1_DATA_A
+ .init_array :
+ {
+ PROVIDE_HIDDEN (___init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ PROVIDE_HIDDEN (___init_array_end = .);
+ } >MEM_L1_DATA_A
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (___fini_array_start = .);
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ PROVIDE_HIDDEN (___fini_array_end = .);
+ } >MEM_L1_DATA_A
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin*.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >MEM_L1_DATA_A
+ .dtors :
+ {
+ KEEP (*crtbegin*.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >MEM_L1_DATA_A
+ .jcr : { KEEP (*(.jcr)) } >MEM_L1_DATA_A
+ .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) } >MEM_L1_DATA_A
+ .dynamic : { *(.dynamic) } >MEM_L1_DATA_A
+ .data :
+ {
+ *(.data .data.* .gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ SORT(CONSTRUCTORS)
+ } >MEM_L1_DATA_A
+ .data1 : { *(.data1) } >MEM_L1_DATA_A
+ .got : { *(.got.plt) *(.got) } >MEM_L1_DATA_A
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .sdata :
+ {
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ } >MEM_L1_DATA_A
+ __edata = .; PROVIDE (_edata = .);
+ .sbss :
+ {
+ __bss_start = .;
+ *(.dynsbss)
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ } >MEM_L1_DATA_A
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ /* Align here to ensure that the .bss section occupies space up to
+ _end. Align after .bss to ensure correct alignment even if the
+ .bss section disappears because there are no input sections.
+ FIXME: Why do we need it? When there is no .bss section, we don't
+ pad the .data section. */
+ . = ALIGN(. != 0 ? 32 / 8 : 1);
+ __bss_end = .;
+ } >MEM_L1_DATA_A
+ . = ALIGN(32 / 8);
+ . = ALIGN(32 / 8);
+ __end = .; PROVIDE (_end = .);
+ /* Stabs debugging sections. */
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+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ __stack_end = ORIGIN(MEM_L1_SCRATCH) + LENGTH(MEM_L1_SCRATCH);
+
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
--- /dev/null
+/*
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#ifndef _BLACKFIN_H
+#define _BLACKFIN_H
+#include <sys/platform.h>
+#endif
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF522 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF522_H
+#define _CDEF_BF522_H
+
+/* include all Core registers and bit definitions */
+#include <defBF522.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
+
+/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <cdefBF52x_base.h>
+
+#endif /* _CDEF_BF522_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF525 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF525_H
+#define _CDEF_BF525_H
+
+/* include all Core registers and bit definitions */
+#include <defBF525.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
+
+/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <cdefBF52x_base.h>
+
+/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
+
+/* USB Control Registers */
+
+#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
+#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
+#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
+#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
+#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
+#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
+#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
+#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
+#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
+#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
+#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
+#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
+#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
+
+/* USB Packet Control Registers */
+
+#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
+#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
+#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
+#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
+#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
+#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
+#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
+#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
+#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
+#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
+#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
+#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
+#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
+
+/* USB Endpoint FIFO Registers */
+
+#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
+#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
+#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
+#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
+#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
+#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
+#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
+#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
+
+/* USB OTG Control Registers */
+
+#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
+#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
+#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
+
+/* USB Phy Control Registers */
+
+#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
+#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
+#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
+#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
+#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
+
+#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
+
+#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
+#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
+
+/* USB Endpoint 0 Control Registers */
+
+#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
+#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
+#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
+#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
+#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
+#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
+#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
+#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
+#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
+#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
+
+/* USB Endpoint 1 Control Registers */
+
+#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
+#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
+#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
+#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
+#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
+#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
+#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
+#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
+#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
+#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
+
+/* USB Endpoint 2 Control Registers */
+
+#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
+#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
+#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
+#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
+#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
+#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
+#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
+#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
+#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
+#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
+
+/* USB Endpoint 3 Control Registers */
+
+#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
+#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
+#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
+#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
+#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
+#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
+#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
+#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
+#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
+#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
+
+/* USB Endpoint 4 Control Registers */
+
+#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
+#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
+#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
+#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
+#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
+#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
+#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
+#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
+#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
+#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
+
+/* USB Endpoint 5 Control Registers */
+
+#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
+#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
+#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
+#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
+#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
+#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
+#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
+#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
+#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
+#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
+
+/* USB Endpoint 6 Control Registers */
+
+#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
+#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
+#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
+#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
+#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
+#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
+#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
+#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
+#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
+#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
+
+/* USB Endpoint 7 Control Registers */
+
+#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
+#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
+#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
+#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
+#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
+#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
+#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
+#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
+#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
+#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
+
+#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
+
+/* USB Channel 0 Config Registers */
+
+#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
+#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
+#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
+#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
+#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
+
+/* USB Channel 1 Config Registers */
+
+#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
+#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
+#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
+#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
+#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
+
+/* USB Channel 2 Config Registers */
+
+#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
+#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
+#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
+#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
+#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
+
+/* USB Channel 3 Config Registers */
+
+#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
+#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
+#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
+#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
+#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
+
+/* USB Channel 4 Config Registers */
+
+#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
+#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
+#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
+#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
+#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
+
+/* USB Channel 5 Config Registers */
+
+#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
+#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
+#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
+#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
+#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
+
+/* USB Channel 6 Config Registers */
+
+#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
+#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
+#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
+#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
+#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
+
+/* USB Channel 7 Config Registers */
+
+#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
+#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
+#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
+#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
+#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
+
+#endif /* _CDEF_BF525_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF527 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF527_H
+#define _CDEF_BF527_H
+
+/* include all Core registers and bit definitions */
+#include <defBF527.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
+
+/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <cdefBF52x_base.h>
+
+/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
+
+/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
+
+#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
+#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
+#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
+#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
+#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
+#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
+#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
+#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
+#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
+#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
+#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
+#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
+#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
+#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
+#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
+#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
+#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
+#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
+#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
+
+#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
+#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
+#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
+#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
+#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
+#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
+#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
+#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
+
+#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
+#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
+#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
+#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
+#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
+
+#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
+#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
+#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
+#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
+#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
+#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
+#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
+#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
+#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
+#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
+#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
+#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
+#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
+#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
+#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
+#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
+#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
+#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
+#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
+#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
+#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
+#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
+#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
+#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
+
+#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
+#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
+#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
+#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
+#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
+#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
+#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
+#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
+#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
+#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
+#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
+#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
+#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
+#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
+#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
+#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
+#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
+#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
+#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
+#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
+#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
+#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
+#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
+
+/* USB Control Registers */
+
+#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
+#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
+#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
+#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
+#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
+#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
+#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
+#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
+#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
+#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
+#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
+#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
+#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
+
+/* USB Packet Control Registers */
+
+#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
+#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
+#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
+#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
+#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
+#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
+#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
+#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
+#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
+#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
+#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
+#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
+#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
+
+/* USB Endpoint FIFO Registers */
+
+#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
+#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
+#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
+#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
+#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
+#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
+#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
+#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
+
+/* USB OTG Control Registers */
+
+#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
+#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
+#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
+
+/* USB Phy Control Registers */
+
+#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
+#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
+#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
+#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
+#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
+
+#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
+
+#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
+#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
+
+/* USB Endpoint 0 Control Registers */
+
+#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
+#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
+#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
+#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
+#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
+#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
+#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
+#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
+#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
+#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
+
+/* USB Endpoint 1 Control Registers */
+
+#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
+#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
+#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
+#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
+#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
+#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
+#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
+#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
+#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
+#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
+
+/* USB Endpoint 2 Control Registers */
+
+#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
+#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
+#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
+#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
+#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
+#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
+#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
+#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
+#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
+#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
+
+/* USB Endpoint 3 Control Registers */
+
+#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
+#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
+#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
+#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
+#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
+#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
+#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
+#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
+#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
+#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
+
+/* USB Endpoint 4 Control Registers */
+
+#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
+#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
+#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
+#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
+#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
+#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
+#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
+#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
+#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
+#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
+
+/* USB Endpoint 5 Control Registers */
+
+#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
+#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
+#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
+#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
+#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
+#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
+#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
+#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
+#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
+#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
+
+/* USB Endpoint 6 Control Registers */
+
+#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
+#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
+#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
+#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
+#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
+#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
+#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
+#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
+#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
+#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
+
+/* USB Endpoint 7 Control Registers */
+
+#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
+#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
+#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
+#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
+#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
+#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
+#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
+#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
+#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
+#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
+
+#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
+
+/* USB Channel 0 Config Registers */
+
+#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
+#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
+#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
+#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
+#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
+
+/* USB Channel 1 Config Registers */
+
+#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
+#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
+#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
+#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
+#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
+
+/* USB Channel 2 Config Registers */
+
+#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
+#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
+#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
+#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
+#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
+
+/* USB Channel 3 Config Registers */
+
+#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
+#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
+#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
+#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
+#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
+
+/* USB Channel 4 Config Registers */
+
+#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
+#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
+#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
+#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
+#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
+
+/* USB Channel 5 Config Registers */
+
+#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
+#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
+#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
+#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
+#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
+
+/* USB Channel 6 Config Registers */
+
+#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
+#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
+#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
+#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
+#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
+
+/* USB Channel 7 Config Registers */
+
+#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
+#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
+#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
+#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
+#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
+
+#endif /* _CDEF_BF527_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF52x_base.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the registers common to the ADSP-BF52x peripherals.
+**
+***************************************************************/
+
+#ifndef _CDEF_BF52X_H
+#define _CDEF_BF52X_H
+
+#include <defBF52x_base.h>
+
+/* ==== begin from cdefBF534.h ==== */
+
+#ifndef _PTR_TO_VOL_VOID_PTR
+#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
+#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
+#else
+#define _PTR_TO_VOL_VOID_PTR (volatile void **)
+#endif
+#endif
+
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+#define pCHIPID ((volatile unsigned long*)CHIPID)
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+
+#define pSIC_RVECT (_PTR_TO_VOL_VOID_PTR SIC_RVECT)
+#define pSIC_IMASK0 ((volatile unsigned long *)SIC_IMASK0)
+/* legacy register name (below) provided for backwards code compatibility */
+#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK0)
+
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
+
+#define pSIC_ISR0 ((volatile unsigned long *)SIC_ISR0)
+/* legacy register name (below) provided for backwards code compatibility */
+#define pSIC_ISR ((volatile unsigned long *)SIC_ISR0)
+
+#define pSIC_IWR0 ((volatile unsigned long *)SIC_IWR0)
+/* legacy register name (below) provided for backwards code compatibility */
+#define pSIC_IWR ((volatile unsigned long *)SIC_IWR0)
+
+/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
+
+#define pSIC_IMASK1 ((volatile unsigned long *)SIC_IMASK1)
+#define pSIC_IAR4 ((volatile unsigned long *)SIC_IAR4)
+#define pSIC_IAR5 ((volatile unsigned long *)SIC_IAR5)
+#define pSIC_IAR6 ((volatile unsigned long *)SIC_IAR6)
+#define pSIC_IAR7 ((volatile unsigned long *)SIC_IAR7)
+#define pSIC_ISR1 ((volatile unsigned long *)SIC_ISR1)
+#define pSIC_IWR1 ((volatile unsigned long *)SIC_IWR1)
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
+#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define pUART0_THR ((volatile unsigned short *)UART0_THR)
+#define pUART0_RBR ((volatile unsigned short *)UART0_RBR)
+#define pUART0_DLL ((volatile unsigned short *)UART0_DLL)
+#define pUART0_IER ((volatile unsigned short *)UART0_IER)
+#define pUART0_DLH ((volatile unsigned short *)UART0_DLH)
+#define pUART0_IIR ((volatile unsigned short *)UART0_IIR)
+#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
+#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
+#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
+#define pUART0_MSR ((volatile unsigned short *)UART0_LSR)
+#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
+#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
+
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
+#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
+#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
+#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
+#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
+#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
+#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
+
+
+/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+
+#define pTIMER3_CONFIG ((volatile unsigned short *)TIMER3_CONFIG)
+#define pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER)
+#define pTIMER3_PERIOD ((volatile unsigned long *)TIMER3_PERIOD)
+#define pTIMER3_WIDTH ((volatile unsigned long *)TIMER3_WIDTH)
+
+#define pTIMER4_CONFIG ((volatile unsigned short *)TIMER4_CONFIG)
+#define pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER)
+#define pTIMER4_PERIOD ((volatile unsigned long *)TIMER4_PERIOD)
+#define pTIMER4_WIDTH ((volatile unsigned long *)TIMER4_WIDTH)
+
+#define pTIMER5_CONFIG ((volatile unsigned short *)TIMER5_CONFIG)
+#define pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER)
+#define pTIMER5_PERIOD ((volatile unsigned long *)TIMER5_PERIOD)
+#define pTIMER5_WIDTH ((volatile unsigned long *)TIMER5_WIDTH)
+
+#define pTIMER6_CONFIG ((volatile unsigned short *)TIMER6_CONFIG)
+#define pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER)
+#define pTIMER6_PERIOD ((volatile unsigned long *)TIMER6_PERIOD)
+#define pTIMER6_WIDTH ((volatile unsigned long *)TIMER6_WIDTH)
+
+#define pTIMER7_CONFIG ((volatile unsigned short *)TIMER7_CONFIG)
+#define pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER)
+#define pTIMER7_PERIOD ((volatile unsigned long *)TIMER7_PERIOD)
+#define pTIMER7_WIDTH ((volatile unsigned long *)TIMER7_WIDTH)
+
+#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
+#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
+#define pTIMER_STATUS ((volatile unsigned long *)TIMER_STATUS)
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
+#define pPORTFIO ((volatile unsigned short *)PORTFIO)
+#define pPORTFIO_CLEAR ((volatile unsigned short *)PORTFIO_CLEAR)
+#define pPORTFIO_SET ((volatile unsigned short *)PORTFIO_SET)
+#define pPORTFIO_TOGGLE ((volatile unsigned short *)PORTFIO_TOGGLE)
+#define pPORTFIO_MASKA ((volatile unsigned short *)PORTFIO_MASKA)
+#define pPORTFIO_MASKA_CLEAR ((volatile unsigned short *)PORTFIO_MASKA_CLEAR)
+#define pPORTFIO_MASKA_SET ((volatile unsigned short *)PORTFIO_MASKA_SET)
+#define pPORTFIO_MASKA_TOGGLE ((volatile unsigned short *)PORTFIO_MASKA_TOGGLE)
+#define pPORTFIO_MASKB ((volatile unsigned short *)PORTFIO_MASKB)
+#define pPORTFIO_MASKB_CLEAR ((volatile unsigned short *)PORTFIO_MASKB_CLEAR)
+#define pPORTFIO_MASKB_SET ((volatile unsigned short *)PORTFIO_MASKB_SET)
+#define pPORTFIO_MASKB_TOGGLE ((volatile unsigned short *)PORTFIO_MASKB_TOGGLE)
+#define pPORTFIO_DIR ((volatile unsigned short *)PORTFIO_DIR)
+#define pPORTFIO_POLAR ((volatile unsigned short *)PORTFIO_POLAR)
+#define pPORTFIO_EDGE ((volatile unsigned short *)PORTFIO_EDGE)
+#define pPORTFIO_BOTH ((volatile unsigned short *)PORTFIO_BOTH)
+#define pPORTFIO_INEN ((volatile unsigned short *)PORTFIO_INEN)
+
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_TX32 ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX32 ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile unsigned long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile unsigned long *)SPORT1_RX)
+#define pSPORT1_TX32 ((volatile unsigned long *)SPORT1_TX)
+#define pSPORT1_RX32 ((volatile unsigned long *)SPORT1_RX)
+#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
+
+
+/* DMA Traffic Control Registers */
+#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER)
+#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
+#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
+
+/* DMA Controller */
+#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
+#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
+#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
+#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+
+#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
+#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
+#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
+#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+
+#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
+#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
+#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
+#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+
+#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
+#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
+#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
+#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+
+#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
+#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
+#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
+#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+
+#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
+#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
+#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
+#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+
+#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
+#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
+#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
+#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+
+#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
+#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
+#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
+#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+
+#define pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG)
+#define pDMA8_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA8_NEXT_DESC_PTR)
+#define pDMA8_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA8_START_ADDR)
+#define pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT)
+#define pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT)
+#define pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY)
+#define pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY)
+#define pDMA8_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA8_CURR_DESC_PTR)
+#define pDMA8_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA8_CURR_ADDR)
+#define pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT)
+#define pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT)
+#define pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS)
+#define pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
+
+#define pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG)
+#define pDMA9_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA9_NEXT_DESC_PTR)
+#define pDMA9_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA9_START_ADDR)
+#define pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT)
+#define pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT)
+#define pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY)
+#define pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY)
+#define pDMA9_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA9_CURR_DESC_PTR)
+#define pDMA9_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA9_CURR_ADDR)
+#define pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT)
+#define pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT)
+#define pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS)
+#define pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
+
+#define pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG)
+#define pDMA10_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA10_NEXT_DESC_PTR)
+#define pDMA10_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA10_START_ADDR)
+#define pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT)
+#define pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT)
+#define pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY)
+#define pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY)
+#define pDMA10_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA10_CURR_DESC_PTR)
+#define pDMA10_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA10_CURR_ADDR)
+#define pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT)
+#define pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT)
+#define pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS)
+#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
+
+#define pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG)
+#define pDMA11_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA11_NEXT_DESC_PTR)
+#define pDMA11_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA11_START_ADDR)
+#define pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT)
+#define pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT)
+#define pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY)
+#define pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY)
+#define pDMA11_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA11_CURR_DESC_PTR)
+#define pDMA11_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA11_CURR_ADDR)
+#define pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT)
+#define pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT)
+#define pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS)
+#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
+
+#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
+#define pMDMA_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
+#define pMDMA_D0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
+#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
+#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
+#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
+#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
+#define pMDMA_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
+#define pMDMA_D0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
+#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
+#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
+#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
+#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
+
+#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
+#define pMDMA_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
+#define pMDMA_S0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
+#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
+#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
+#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
+#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
+#define pMDMA_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
+#define pMDMA_S0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
+#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
+#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
+#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
+#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
+
+#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
+#define pMDMA_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
+#define pMDMA_D1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
+#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
+#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
+#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
+#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
+#define pMDMA_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
+#define pMDMA_D1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
+#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
+#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
+#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
+#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
+
+#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
+#define pMDMA_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
+#define pMDMA_S1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
+#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
+#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
+#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
+#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
+#define pMDMA_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
+#define pMDMA_S1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
+#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
+#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
+#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
+#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
+#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
+#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
+#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
+#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
+#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
+
+
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#define pTWI_CLKDIV ((volatile unsigned short *)TWI_CLKDIV)
+#define pTWI_CONTROL ((volatile unsigned short *)TWI_CONTROL)
+#define pTWI_SLAVE_CTL ((volatile unsigned short *)TWI_SLAVE_CTL)
+#define pTWI_SLAVE_STAT ((volatile unsigned short *)TWI_SLAVE_STAT)
+#define pTWI_SLAVE_ADDR ((volatile unsigned short *)TWI_SLAVE_ADDR)
+#define pTWI_MASTER_CTL ((volatile unsigned short *)TWI_MASTER_CTL)
+#define pTWI_MASTER_STAT ((volatile unsigned short *)TWI_MASTER_STAT)
+#define pTWI_MASTER_ADDR ((volatile unsigned short *)TWI_MASTER_ADDR)
+#define pTWI_INT_STAT ((volatile unsigned short *)TWI_INT_STAT)
+#define pTWI_INT_MASK ((volatile unsigned short *)TWI_INT_MASK)
+#define pTWI_FIFO_CTL ((volatile unsigned short *)TWI_FIFO_CTL)
+#define pTWI_FIFO_STAT ((volatile unsigned short *)TWI_FIFO_STAT)
+#define pTWI_XMT_DATA8 ((volatile unsigned short *)TWI_XMT_DATA8)
+#define pTWI_XMT_DATA16 ((volatile unsigned short *)TWI_XMT_DATA16)
+#define pTWI_RCV_DATA8 ((volatile unsigned short *)TWI_RCV_DATA8)
+#define pTWI_RCV_DATA16 ((volatile unsigned short *)TWI_RCV_DATA16)
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
+#define pPORTGIO ((volatile unsigned short *)PORTGIO)
+#define pPORTGIO_CLEAR ((volatile unsigned short *)PORTGIO_CLEAR)
+#define pPORTGIO_SET ((volatile unsigned short *)PORTGIO_SET)
+#define pPORTGIO_TOGGLE ((volatile unsigned short *)PORTGIO_TOGGLE)
+#define pPORTGIO_MASKA ((volatile unsigned short *)PORTGIO_MASKA)
+#define pPORTGIO_MASKA_CLEAR ((volatile unsigned short *)PORTGIO_MASKA_CLEAR)
+#define pPORTGIO_MASKA_SET ((volatile unsigned short *)PORTGIO_MASKA_SET)
+#define pPORTGIO_MASKA_TOGGLE ((volatile unsigned short *)PORTGIO_MASKA_TOGGLE)
+#define pPORTGIO_MASKB ((volatile unsigned short *)PORTGIO_MASKB)
+#define pPORTGIO_MASKB_CLEAR ((volatile unsigned short *)PORTGIO_MASKB_CLEAR)
+#define pPORTGIO_MASKB_SET ((volatile unsigned short *)PORTGIO_MASKB_SET)
+#define pPORTGIO_MASKB_TOGGLE ((volatile unsigned short *)PORTGIO_MASKB_TOGGLE)
+#define pPORTGIO_DIR ((volatile unsigned short *)PORTGIO_DIR)
+#define pPORTGIO_POLAR ((volatile unsigned short *)PORTGIO_POLAR)
+#define pPORTGIO_EDGE ((volatile unsigned short *)PORTGIO_EDGE)
+#define pPORTGIO_BOTH ((volatile unsigned short *)PORTGIO_BOTH)
+#define pPORTGIO_INEN ((volatile unsigned short *)PORTGIO_INEN)
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
+#define pPORTHIO ((volatile unsigned short *)PORTHIO)
+#define pPORTHIO_CLEAR ((volatile unsigned short *)PORTHIO_CLEAR)
+#define pPORTHIO_SET ((volatile unsigned short *)PORTHIO_SET)
+#define pPORTHIO_TOGGLE ((volatile unsigned short *)PORTHIO_TOGGLE)
+#define pPORTHIO_MASKA ((volatile unsigned short *)PORTHIO_MASKA)
+#define pPORTHIO_MASKA_CLEAR ((volatile unsigned short *)PORTHIO_MASKA_CLEAR)
+#define pPORTHIO_MASKA_SET ((volatile unsigned short *)PORTHIO_MASKA_SET)
+#define pPORTHIO_MASKA_TOGGLE ((volatile unsigned short *)PORTHIO_MASKA_TOGGLE)
+#define pPORTHIO_MASKB ((volatile unsigned short *)PORTHIO_MASKB)
+#define pPORTHIO_MASKB_CLEAR ((volatile unsigned short *)PORTHIO_MASKB_CLEAR)
+#define pPORTHIO_MASKB_SET ((volatile unsigned short *)PORTHIO_MASKB_SET)
+#define pPORTHIO_MASKB_TOGGLE ((volatile unsigned short *)PORTHIO_MASKB_TOGGLE)
+#define pPORTHIO_DIR ((volatile unsigned short *)PORTHIO_DIR)
+#define pPORTHIO_POLAR ((volatile unsigned short *)PORTHIO_POLAR)
+#define pPORTHIO_EDGE ((volatile unsigned short *)PORTHIO_EDGE)
+#define pPORTHIO_BOTH ((volatile unsigned short *)PORTHIO_BOTH)
+#define pPORTHIO_INEN ((volatile unsigned short *)PORTHIO_INEN)
+
+
+/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
+#define pUART1_THR ((volatile unsigned short *)UART1_THR)
+#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
+#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
+#define pUART1_IER ((volatile unsigned short *)UART1_IER)
+#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
+#define pUART1_IIR ((volatile unsigned short *)UART1_IIR)
+#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
+#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
+#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_MSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
+#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)
+
+/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
+
+/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
+#define pPORTF_FER ((volatile unsigned short *)PORTF_FER)
+#define pPORTG_FER ((volatile unsigned short *)PORTG_FER)
+#define pPORTH_FER ((volatile unsigned short *)PORTH_FER)
+
+
+/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
+#define pHMDMA0_CONTROL ((volatile unsigned short *)HMDMA0_CONTROL)
+#define pHMDMA0_ECINIT ((volatile unsigned short *)HMDMA0_ECINIT)
+#define pHMDMA0_BCINIT ((volatile unsigned short *)HMDMA0_BCINIT)
+#define pHMDMA0_ECURGENT ((volatile unsigned short *)HMDMA0_ECURGENT)
+#define pHMDMA0_ECOVERFLOW ((volatile unsigned short *)HMDMA0_ECOVERFLOW)
+#define pHMDMA0_ECOUNT ((volatile unsigned short *)HMDMA0_ECOUNT)
+#define pHMDMA0_BCOUNT ((volatile unsigned short *)HMDMA0_BCOUNT)
+
+#define pHMDMA1_CONTROL ((volatile unsigned short *)HMDMA1_CONTROL)
+#define pHMDMA1_ECINIT ((volatile unsigned short *)HMDMA1_ECINIT)
+#define pHMDMA1_BCINIT ((volatile unsigned short *)HMDMA1_BCINIT)
+#define pHMDMA1_ECURGENT ((volatile unsigned short *)HMDMA1_ECURGENT)
+#define pHMDMA1_ECOVERFLOW ((volatile unsigned short *)HMDMA1_ECOVERFLOW)
+#define pHMDMA1_ECOUNT ((volatile unsigned short *)HMDMA1_ECOUNT)
+#define pHMDMA1_BCOUNT ((volatile unsigned short *)HMDMA1_BCOUNT)
+
+/* ==== end from cdefBF534.h ==== */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+
+#define pPORTF_MUX ((volatile unsigned short *)PORTF_MUX)
+#define pPORTG_MUX ((volatile unsigned short *)PORTG_MUX)
+#define pPORTH_MUX ((volatile unsigned short *)PORTH_MUX)
+
+#define pPORTF_DRIVE ((volatile unsigned short *)PORTF_DRIVE)
+#define pPORTG_DRIVE ((volatile unsigned short *)PORTG_DRIVE)
+#define pPORTH_DRIVE ((volatile unsigned short *)PORTH_DRIVE)
+#define pPORTF_SLEW ((volatile unsigned short *)PORTF_SLEW)
+#define pPORTG_SLEW ((volatile unsigned short *)PORTG_SLEW)
+#define pPORTH_SLEW ((volatile unsigned short *)PORTH_SLEW)
+#define pPORTF_HYSTERESIS ((volatile unsigned short *)PORTF_HYSTERESIS)
+#define pPORTG_HYSTERESIS ((volatile unsigned short *)PORTG_HYSTERESIS)
+#define pPORTH_HYSTERESIS ((volatile unsigned short *)PORTH_HYSTERESIS)
+#define pNONGPIO_DRIVE ((volatile unsigned short *)NONGPIO_DRIVE)
+#define pNONGPIO_SLEW ((volatile unsigned short *)NONGPIO_SLEW)
+#define pNONGPIO_HYSTERESIS ((volatile unsigned short *)NONGPIO_HYSTERESIS)
+
+/* HOST Port Registers */
+
+#define pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
+#define pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
+#define pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
+
+/* Counter Registers */
+
+#define pCNT_CONFIG ((volatile unsigned short *)CNT_CONFIG)
+#define pCNT_IMASK ((volatile unsigned short *)CNT_IMASK)
+#define pCNT_STATUS ((volatile unsigned short *)CNT_STATUS)
+#define pCNT_COMMAND ((volatile unsigned short *)CNT_COMMAND)
+#define pCNT_DEBOUNCE ((volatile unsigned short *)CNT_DEBOUNCE)
+#define pCNT_COUNTER ((volatile unsigned long *)CNT_COUNTER)
+#define pCNT_MAX ((volatile unsigned long *)CNT_MAX)
+#define pCNT_MIN ((volatile unsigned long *)CNT_MIN)
+
+/* OTP/FUSE Registers */
+
+#define pOTP_CONTROL ((volatile unsigned short *)OTP_CONTROL)
+#define pOTP_BEN ((volatile unsigned short *)OTP_BEN)
+#define pOTP_STATUS ((volatile unsigned short *)OTP_STATUS)
+#define pOTP_TIMING ((volatile unsigned long *)OTP_TIMING)
+
+/* Security Registers */
+
+#define pSECURE_SYSSWT ((volatile unsigned long *)SECURE_SYSSWT)
+#define pSECURE_CONTROL ((volatile unsigned short *)SECURE_CONTROL)
+#define pSECURE_STATUS ((volatile unsigned short *)SECURE_STATUS)
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define pOTP_DATA0 ((volatile unsigned long *)OTP_DATA0)
+#define pOTP_DATA1 ((volatile unsigned long *)OTP_DATA1)
+#define pOTP_DATA2 ((volatile unsigned long *)OTP_DATA2)
+#define pOTP_DATA3 ((volatile unsigned long *)OTP_DATA3)
+
+/* NFC Registers */
+
+#define pNFC_CTL ((volatile unsigned short *)NFC_CTL)
+#define pNFC_STAT ((volatile unsigned short *)NFC_STAT)
+#define pNFC_IRQSTAT ((volatile unsigned short *)NFC_IRQSTAT)
+#define pNFC_IRQMASK ((volatile unsigned short *)NFC_IRQMASK)
+#define pNFC_ECC0 ((volatile unsigned short *)NFC_ECC0)
+#define pNFC_ECC1 ((volatile unsigned short *)NFC_ECC1)
+#define pNFC_ECC2 ((volatile unsigned short *)NFC_ECC2)
+#define pNFC_ECC3 ((volatile unsigned short *)NFC_ECC3)
+#define pNFC_COUNT ((volatile unsigned short *)NFC_COUNT)
+#define pNFC_RST ((volatile unsigned short *)NFC_RST)
+#define pNFC_PGCTL ((volatile unsigned short *)NFC_PGCTL)
+#define pNFC_READ ((volatile unsigned short *)NFC_READ)
+#define pNFC_ADDR ((volatile unsigned short *)NFC_ADDR)
+#define pNFC_CMD ((volatile unsigned short *)NFC_CMD)
+#define pNFC_DATA_WR ((volatile unsigned short *)NFC_DATA_WR)
+#define pNFC_DATA_RD ((volatile unsigned short *)NFC_DATA_RD)
+
+#endif /* _CDEF_BF52X_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * cdefBF531.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifndef _CDEFBF531_H
+#define _CDEFBF531_H
+
+#include <cdefBF532.h>
+
+#endif /* _CDEFBF531_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * cdefBF532.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifndef _CDEF_BF532_H
+#define _CDEF_BF532_H
+
+#if !defined(__ADSPLPBLACKFIN__)
+#warning cdefBF532.h should only be included for 532 compatible chips.
+#endif
+/* include all Core registers and bit definitions */
+#include <defBF532.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* include built-in mneumonic macros */
+#include <ccblkfn.h>
+
+#ifndef _PTR_TO_VOL_VOID_PTR
+#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
+#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
+#else
+#define _PTR_TO_VOL_VOID_PTR (volatile void **)
+#endif
+#endif
+
+/* Clock/Regulator Control */
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+
+
+/* System Interrupt Controller */
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+#define pSIC_RVECT ((void * volatile *)SIC_RVECT)
+#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
+#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
+
+
+/* Watchdog Timer */
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+
+/* Real Time Clock */
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
+#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
+
+
+/* UART Controller */
+#define pUART_THR ((volatile unsigned short *)UART_THR)
+#define pUART_RBR ((volatile unsigned short *)UART_RBR)
+#define pUART_DLL ((volatile unsigned short *)UART_DLL)
+#define pUART_IER ((volatile unsigned short *)UART_IER)
+#define pUART_DLH ((volatile unsigned short *)UART_DLH)
+#define pUART_IIR ((volatile unsigned short *)UART_IIR)
+#define pUART_LCR ((volatile unsigned short *)UART_LCR)
+#define pUART_MCR ((volatile unsigned short *)UART_MCR)
+#define pUART_LSR ((volatile unsigned short *)UART_LSR)
+/* #define UART_MSR */
+#define pUART_SCR ((volatile unsigned short *)UART_SCR)
+#define pUART_GCTL ((volatile unsigned short *)UART_GCTL)
+
+
+/* SPI Controller */
+#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
+#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
+#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
+#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
+#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
+#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
+#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
+
+
+/* TIMER 0, 1, 2 Registers */
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+
+#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
+#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
+#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS)
+
+
+/* General Purpose IO */
+#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D)
+#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
+#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
+#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T)
+#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D)
+#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
+#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
+#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T)
+#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D)
+#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
+#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
+#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T)
+#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
+#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
+#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
+#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
+#define pFIO_INEN ((volatile unsigned short *)FIO_INEN)
+
+
+/* SPORT0 Controller */
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+
+/* SPORT1 Controller */
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
+
+
+/* External Bus Interface Unit */
+/* Aysnchronous Memory Controller */
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+
+/* SDRAM Controller */
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
+
+
+/* DMA Traffic controls */
+#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER)
+#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
+#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
+
+
+/* DMA Controller */
+#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
+#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
+#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
+#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+
+#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
+#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
+#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
+#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+
+#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
+#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
+#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
+#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+
+#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
+#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
+#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
+#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+
+#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
+#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
+#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
+#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+
+#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
+#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
+#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
+#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+
+#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
+#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
+#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
+#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+
+#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
+#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
+#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
+#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+
+#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
+#define pMDMA_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
+#define pMDMA_D1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
+#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
+#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
+#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
+#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
+#define pMDMA_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
+#define pMDMA_D1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
+#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
+#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
+#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
+#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
+
+#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
+#define pMDMA_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
+#define pMDMA_S1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
+#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
+#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
+#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
+#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
+#define pMDMA_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
+#define pMDMA_S1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
+#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
+#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
+#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
+#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
+
+#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
+#define pMDMA_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
+#define pMDMA_D0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
+#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
+#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
+#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
+#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
+#define pMDMA_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
+#define pMDMA_D0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
+#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
+#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
+#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
+#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
+
+#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
+#define pMDMA_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
+#define pMDMA_S0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
+#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
+#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
+#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
+#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
+#define pMDMA_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
+#define pMDMA_S0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
+#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
+#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
+#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
+#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
+
+
+
+/* Parallel Peripheral Interface (PPI) */
+#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
+#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
+#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
+#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
+#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
+
+#endif /* _CDEF_BF532_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * cdefBF533.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifndef _CDEFBF533_H
+#define _CDEFBF533_H
+
+#include <cdefBF532.h>
+
+#endif /* _CDEFBF533_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access.
+**
+**/
+
+/**********************************************************************************
+** System MMR Register Map
+***********************************************************************************/
+
+#ifndef _CDEF_BF534_H
+#define _CDEF_BF534_H
+
+/* Include all Core registers and bit definitions */
+#include <defBF534.h>
+
+/* Include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+#ifndef _PTR_TO_VOL_VOID_PTR
+#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
+#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
+#else
+#define _PTR_TO_VOL_VOID_PTR (volatile void **)
+#endif
+#endif
+
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+#define pCHIPID ((volatile unsigned long*)CHIPID)
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+#define pSIC_RVECT (_PTR_TO_VOL_VOID_PTR SIC_RVECT)
+#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
+#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
+#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
+
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
+#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define pUART0_THR ((volatile unsigned short *)UART0_THR)
+#define pUART0_RBR ((volatile unsigned short *)UART0_RBR)
+#define pUART0_DLL ((volatile unsigned short *)UART0_DLL)
+#define pUART0_IER ((volatile unsigned short *)UART0_IER)
+#define pUART0_DLH ((volatile unsigned short *)UART0_DLH)
+#define pUART0_IIR ((volatile unsigned short *)UART0_IIR)
+#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
+#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
+#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
+#define pUART0_MSR ((volatile unsigned short *)UART0_LSR)
+#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
+#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
+
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define pSPI_CTL ((volatile unsigned short *)SPI_CTL)
+#define pSPI_FLG ((volatile unsigned short *)SPI_FLG)
+#define pSPI_STAT ((volatile unsigned short *)SPI_STAT)
+#define pSPI_TDBR ((volatile unsigned short *)SPI_TDBR)
+#define pSPI_RDBR ((volatile unsigned short *)SPI_RDBR)
+#define pSPI_BAUD ((volatile unsigned short *)SPI_BAUD)
+#define pSPI_SHADOW ((volatile unsigned short *)SPI_SHADOW)
+
+
+/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+
+#define pTIMER3_CONFIG ((volatile unsigned short *)TIMER3_CONFIG)
+#define pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER)
+#define pTIMER3_PERIOD ((volatile unsigned long *)TIMER3_PERIOD)
+#define pTIMER3_WIDTH ((volatile unsigned long *)TIMER3_WIDTH)
+
+#define pTIMER4_CONFIG ((volatile unsigned short *)TIMER4_CONFIG)
+#define pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER)
+#define pTIMER4_PERIOD ((volatile unsigned long *)TIMER4_PERIOD)
+#define pTIMER4_WIDTH ((volatile unsigned long *)TIMER4_WIDTH)
+
+#define pTIMER5_CONFIG ((volatile unsigned short *)TIMER5_CONFIG)
+#define pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER)
+#define pTIMER5_PERIOD ((volatile unsigned long *)TIMER5_PERIOD)
+#define pTIMER5_WIDTH ((volatile unsigned long *)TIMER5_WIDTH)
+
+#define pTIMER6_CONFIG ((volatile unsigned short *)TIMER6_CONFIG)
+#define pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER)
+#define pTIMER6_PERIOD ((volatile unsigned long *)TIMER6_PERIOD)
+#define pTIMER6_WIDTH ((volatile unsigned long *)TIMER6_WIDTH)
+
+#define pTIMER7_CONFIG ((volatile unsigned short *)TIMER7_CONFIG)
+#define pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER)
+#define pTIMER7_PERIOD ((volatile unsigned long *)TIMER7_PERIOD)
+#define pTIMER7_WIDTH ((volatile unsigned long *)TIMER7_WIDTH)
+
+#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
+#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
+#define pTIMER_STATUS ((volatile unsigned long *)TIMER_STATUS)
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
+#define pPORTFIO ((volatile unsigned short *)PORTFIO)
+#define pPORTFIO_CLEAR ((volatile unsigned short *)PORTFIO_CLEAR)
+#define pPORTFIO_SET ((volatile unsigned short *)PORTFIO_SET)
+#define pPORTFIO_TOGGLE ((volatile unsigned short *)PORTFIO_TOGGLE)
+#define pPORTFIO_MASKA ((volatile unsigned short *)PORTFIO_MASKA)
+#define pPORTFIO_MASKA_CLEAR ((volatile unsigned short *)PORTFIO_MASKA_CLEAR)
+#define pPORTFIO_MASKA_SET ((volatile unsigned short *)PORTFIO_MASKA_SET)
+#define pPORTFIO_MASKA_TOGGLE ((volatile unsigned short *)PORTFIO_MASKA_TOGGLE)
+#define pPORTFIO_MASKB ((volatile unsigned short *)PORTFIO_MASKB)
+#define pPORTFIO_MASKB_CLEAR ((volatile unsigned short *)PORTFIO_MASKB_CLEAR)
+#define pPORTFIO_MASKB_SET ((volatile unsigned short *)PORTFIO_MASKB_SET)
+#define pPORTFIO_MASKB_TOGGLE ((volatile unsigned short *)PORTFIO_MASKB_TOGGLE)
+#define pPORTFIO_DIR ((volatile unsigned short *)PORTFIO_DIR)
+#define pPORTFIO_POLAR ((volatile unsigned short *)PORTFIO_POLAR)
+#define pPORTFIO_EDGE ((volatile unsigned short *)PORTFIO_EDGE)
+#define pPORTFIO_BOTH ((volatile unsigned short *)PORTFIO_BOTH)
+#define pPORTFIO_INEN ((volatile unsigned short *)PORTFIO_INEN)
+
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_TX32 ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX32 ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile unsigned long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile unsigned long *)SPORT1_RX)
+#define pSPORT1_TX32 ((volatile unsigned long *)SPORT1_TX)
+#define pSPORT1_RX32 ((volatile unsigned long *)SPORT1_RX)
+#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
+
+
+/* DMA Traffic Control Registers */
+#define pDMA_TC_PER ((volatile unsigned short *)DMA_TC_PER)
+#define pDMA_TC_CNT ((volatile unsigned short *)DMA_TC_CNT)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define pDMA_TCPER ((volatile unsigned short *)DMA_TCPER)
+#define pDMA_TCCNT ((volatile unsigned short *)DMA_TCCNT)
+
+/* DMA Controller */
+#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
+#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
+#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
+#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+
+#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
+#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
+#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
+#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+
+#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
+#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
+#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
+#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+
+#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
+#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
+#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
+#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+
+#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
+#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
+#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
+#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+
+#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
+#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
+#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
+#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+
+#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
+#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
+#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
+#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+
+#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
+#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
+#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
+#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+
+#define pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG)
+#define pDMA8_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA8_NEXT_DESC_PTR)
+#define pDMA8_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA8_START_ADDR)
+#define pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT)
+#define pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT)
+#define pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY)
+#define pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY)
+#define pDMA8_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA8_CURR_DESC_PTR)
+#define pDMA8_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA8_CURR_ADDR)
+#define pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT)
+#define pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT)
+#define pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS)
+#define pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
+
+#define pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG)
+#define pDMA9_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA9_NEXT_DESC_PTR)
+#define pDMA9_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA9_START_ADDR)
+#define pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT)
+#define pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT)
+#define pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY)
+#define pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY)
+#define pDMA9_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA9_CURR_DESC_PTR)
+#define pDMA9_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA9_CURR_ADDR)
+#define pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT)
+#define pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT)
+#define pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS)
+#define pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
+
+#define pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG)
+#define pDMA10_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA10_NEXT_DESC_PTR)
+#define pDMA10_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA10_START_ADDR)
+#define pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT)
+#define pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT)
+#define pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY)
+#define pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY)
+#define pDMA10_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA10_CURR_DESC_PTR)
+#define pDMA10_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA10_CURR_ADDR)
+#define pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT)
+#define pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT)
+#define pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS)
+#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
+
+#define pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG)
+#define pDMA11_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA11_NEXT_DESC_PTR)
+#define pDMA11_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA11_START_ADDR)
+#define pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT)
+#define pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT)
+#define pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY)
+#define pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY)
+#define pDMA11_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA11_CURR_DESC_PTR)
+#define pDMA11_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA11_CURR_ADDR)
+#define pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT)
+#define pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT)
+#define pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS)
+#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
+
+#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
+#define pMDMA_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_NEXT_DESC_PTR)
+#define pMDMA_D0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_START_ADDR)
+#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
+#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
+#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
+#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
+#define pMDMA_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_DESC_PTR)
+#define pMDMA_D0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D0_CURR_ADDR)
+#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
+#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
+#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
+#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
+
+#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
+#define pMDMA_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_NEXT_DESC_PTR)
+#define pMDMA_S0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_START_ADDR)
+#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
+#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
+#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
+#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
+#define pMDMA_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_DESC_PTR)
+#define pMDMA_S0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S0_CURR_ADDR)
+#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
+#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
+#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
+#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
+
+#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
+#define pMDMA_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_NEXT_DESC_PTR)
+#define pMDMA_D1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_START_ADDR)
+#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
+#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
+#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
+#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
+#define pMDMA_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_DESC_PTR)
+#define pMDMA_D1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_D1_CURR_ADDR)
+#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
+#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
+#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
+#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
+
+#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
+#define pMDMA_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_NEXT_DESC_PTR)
+#define pMDMA_S1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_START_ADDR)
+#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
+#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
+#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
+#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
+#define pMDMA_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_DESC_PTR)
+#define pMDMA_S1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA_S1_CURR_ADDR)
+#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
+#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
+#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
+#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
+#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
+#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
+#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
+#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
+#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
+
+
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#define pTWI_CLKDIV ((volatile unsigned short *)TWI_CLKDIV)
+#define pTWI_CONTROL ((volatile unsigned short *)TWI_CONTROL)
+#define pTWI_SLAVE_CTL ((volatile unsigned short *)TWI_SLAVE_CTL)
+#define pTWI_SLAVE_STAT ((volatile unsigned short *)TWI_SLAVE_STAT)
+#define pTWI_SLAVE_ADDR ((volatile unsigned short *)TWI_SLAVE_ADDR)
+#define pTWI_MASTER_CTL ((volatile unsigned short *)TWI_MASTER_CTL)
+#define pTWI_MASTER_STAT ((volatile unsigned short *)TWI_MASTER_STAT)
+#define pTWI_MASTER_ADDR ((volatile unsigned short *)TWI_MASTER_ADDR)
+#define pTWI_INT_STAT ((volatile unsigned short *)TWI_INT_STAT)
+#define pTWI_INT_MASK ((volatile unsigned short *)TWI_INT_MASK)
+#define pTWI_FIFO_CTL ((volatile unsigned short *)TWI_FIFO_CTL)
+#define pTWI_FIFO_STAT ((volatile unsigned short *)TWI_FIFO_STAT)
+#define pTWI_XMT_DATA8 ((volatile unsigned short *)TWI_XMT_DATA8)
+#define pTWI_XMT_DATA16 ((volatile unsigned short *)TWI_XMT_DATA16)
+#define pTWI_RCV_DATA8 ((volatile unsigned short *)TWI_RCV_DATA8)
+#define pTWI_RCV_DATA16 ((volatile unsigned short *)TWI_RCV_DATA16)
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
+#define pPORTGIO ((volatile unsigned short *)PORTGIO)
+#define pPORTGIO_CLEAR ((volatile unsigned short *)PORTGIO_CLEAR)
+#define pPORTGIO_SET ((volatile unsigned short *)PORTGIO_SET)
+#define pPORTGIO_TOGGLE ((volatile unsigned short *)PORTGIO_TOGGLE)
+#define pPORTGIO_MASKA ((volatile unsigned short *)PORTGIO_MASKA)
+#define pPORTGIO_MASKA_CLEAR ((volatile unsigned short *)PORTGIO_MASKA_CLEAR)
+#define pPORTGIO_MASKA_SET ((volatile unsigned short *)PORTGIO_MASKA_SET)
+#define pPORTGIO_MASKA_TOGGLE ((volatile unsigned short *)PORTGIO_MASKA_TOGGLE)
+#define pPORTGIO_MASKB ((volatile unsigned short *)PORTGIO_MASKB)
+#define pPORTGIO_MASKB_CLEAR ((volatile unsigned short *)PORTGIO_MASKB_CLEAR)
+#define pPORTGIO_MASKB_SET ((volatile unsigned short *)PORTGIO_MASKB_SET)
+#define pPORTGIO_MASKB_TOGGLE ((volatile unsigned short *)PORTGIO_MASKB_TOGGLE)
+#define pPORTGIO_DIR ((volatile unsigned short *)PORTGIO_DIR)
+#define pPORTGIO_POLAR ((volatile unsigned short *)PORTGIO_POLAR)
+#define pPORTGIO_EDGE ((volatile unsigned short *)PORTGIO_EDGE)
+#define pPORTGIO_BOTH ((volatile unsigned short *)PORTGIO_BOTH)
+#define pPORTGIO_INEN ((volatile unsigned short *)PORTGIO_INEN)
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
+#define pPORTHIO ((volatile unsigned short *)PORTHIO)
+#define pPORTHIO_CLEAR ((volatile unsigned short *)PORTHIO_CLEAR)
+#define pPORTHIO_SET ((volatile unsigned short *)PORTHIO_SET)
+#define pPORTHIO_TOGGLE ((volatile unsigned short *)PORTHIO_TOGGLE)
+#define pPORTHIO_MASKA ((volatile unsigned short *)PORTHIO_MASKA)
+#define pPORTHIO_MASKA_CLEAR ((volatile unsigned short *)PORTHIO_MASKA_CLEAR)
+#define pPORTHIO_MASKA_SET ((volatile unsigned short *)PORTHIO_MASKA_SET)
+#define pPORTHIO_MASKA_TOGGLE ((volatile unsigned short *)PORTHIO_MASKA_TOGGLE)
+#define pPORTHIO_MASKB ((volatile unsigned short *)PORTHIO_MASKB)
+#define pPORTHIO_MASKB_CLEAR ((volatile unsigned short *)PORTHIO_MASKB_CLEAR)
+#define pPORTHIO_MASKB_SET ((volatile unsigned short *)PORTHIO_MASKB_SET)
+#define pPORTHIO_MASKB_TOGGLE ((volatile unsigned short *)PORTHIO_MASKB_TOGGLE)
+#define pPORTHIO_DIR ((volatile unsigned short *)PORTHIO_DIR)
+#define pPORTHIO_POLAR ((volatile unsigned short *)PORTHIO_POLAR)
+#define pPORTHIO_EDGE ((volatile unsigned short *)PORTHIO_EDGE)
+#define pPORTHIO_BOTH ((volatile unsigned short *)PORTHIO_BOTH)
+#define pPORTHIO_INEN ((volatile unsigned short *)PORTHIO_INEN)
+
+
+/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
+#define pUART1_THR ((volatile unsigned short *)UART1_THR)
+#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
+#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
+#define pUART1_IER ((volatile unsigned short *)UART1_IER)
+#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
+#define pUART1_IIR ((volatile unsigned short *)UART1_IIR)
+#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
+#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
+#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_MSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
+#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)
+
+
+/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
+/* For Mailboxes 0-15 */
+#define pCAN_MC1 ((volatile unsigned short *)CAN_MC1)
+#define pCAN_MD1 ((volatile unsigned short *)CAN_MD1)
+#define pCAN_TRS1 ((volatile unsigned short *)CAN_TRS1)
+#define pCAN_TRR1 ((volatile unsigned short *)CAN_TRR1)
+#define pCAN_TA1 ((volatile unsigned short *)CAN_TA1)
+#define pCAN_AA1 ((volatile unsigned short *)CAN_AA1)
+#define pCAN_RMP1 ((volatile unsigned short *)CAN_RMP1)
+#define pCAN_RML1 ((volatile unsigned short *)CAN_RML1)
+#define pCAN_MBTIF1 ((volatile unsigned short *)CAN_MBTIF1)
+#define pCAN_MBRIF1 ((volatile unsigned short *)CAN_MBRIF1)
+#define pCAN_MBIM1 ((volatile unsigned short *)CAN_MBIM1)
+#define pCAN_RFH1 ((volatile unsigned short *)CAN_RFH1)
+#define pCAN_OPSS1 ((volatile unsigned short *)CAN_OPSS1)
+
+/* For Mailboxes 16-31 */
+#define pCAN_MC2 ((volatile unsigned short *)CAN_MC2)
+#define pCAN_MD2 ((volatile unsigned short *)CAN_MD2)
+#define pCAN_TRS2 ((volatile unsigned short *)CAN_TRS2)
+#define pCAN_TRR2 ((volatile unsigned short *)CAN_TRR2)
+#define pCAN_TA2 ((volatile unsigned short *)CAN_TA2)
+#define pCAN_AA2 ((volatile unsigned short *)CAN_AA2)
+#define pCAN_RMP2 ((volatile unsigned short *)CAN_RMP2)
+#define pCAN_RML2 ((volatile unsigned short *)CAN_RML2)
+#define pCAN_MBTIF2 ((volatile unsigned short *)CAN_MBTIF2)
+#define pCAN_MBRIF2 ((volatile unsigned short *)CAN_MBRIF2)
+#define pCAN_MBIM2 ((volatile unsigned short *)CAN_MBIM2)
+#define pCAN_RFH2 ((volatile unsigned short *)CAN_RFH2)
+#define pCAN_OPSS2 ((volatile unsigned short *)CAN_OPSS2)
+
+#define pCAN_CLOCK ((volatile unsigned short *)CAN_CLOCK)
+#define pCAN_TIMING ((volatile unsigned short *)CAN_TIMING)
+#define pCAN_DEBUG ((volatile unsigned short *)CAN_DEBUG)
+#define pCAN_STATUS ((volatile unsigned short *)CAN_STATUS)
+#define pCAN_CEC ((volatile unsigned short *)CAN_CEC)
+#define pCAN_GIS ((volatile unsigned short *)CAN_GIS)
+#define pCAN_GIM ((volatile unsigned short *)CAN_GIM)
+#define pCAN_GIF ((volatile unsigned short *)CAN_GIF)
+#define pCAN_CONTROL ((volatile unsigned short *)CAN_CONTROL)
+#define pCAN_INTR ((volatile unsigned short *)CAN_INTR)
+#define pCAN_MBTD ((volatile unsigned short *)CAN_MBTD)
+#define pCAN_EWR ((volatile unsigned short *)CAN_EWR)
+#define pCAN_ESR ((volatile unsigned short *)CAN_ESR)
+#define pCAN_UCREG ((volatile unsigned short *)CAN_UCREG)
+#define pCAN_UCCNT ((volatile unsigned short *)CAN_UCCNT)
+#define pCAN_UCRC ((volatile unsigned short *)CAN_UCRC)
+#define pCAN_UCCNF ((volatile unsigned short *)CAN_UCCNF)
+
+/* Mailbox Acceptance Masks */
+#define pCAN_AM00L ((volatile unsigned short *)CAN_AM00L)
+#define pCAN_AM00H ((volatile unsigned short *)CAN_AM00H)
+#define pCAN_AM01L ((volatile unsigned short *)CAN_AM01L)
+#define pCAN_AM01H ((volatile unsigned short *)CAN_AM01H)
+#define pCAN_AM02L ((volatile unsigned short *)CAN_AM02L)
+#define pCAN_AM02H ((volatile unsigned short *)CAN_AM02H)
+#define pCAN_AM03L ((volatile unsigned short *)CAN_AM03L)
+#define pCAN_AM03H ((volatile unsigned short *)CAN_AM03H)
+#define pCAN_AM04L ((volatile unsigned short *)CAN_AM04L)
+#define pCAN_AM04H ((volatile unsigned short *)CAN_AM04H)
+#define pCAN_AM05L ((volatile unsigned short *)CAN_AM05L)
+#define pCAN_AM05H ((volatile unsigned short *)CAN_AM05H)
+#define pCAN_AM06L ((volatile unsigned short *)CAN_AM06L)
+#define pCAN_AM06H ((volatile unsigned short *)CAN_AM06H)
+#define pCAN_AM07L ((volatile unsigned short *)CAN_AM07L)
+#define pCAN_AM07H ((volatile unsigned short *)CAN_AM07H)
+#define pCAN_AM08L ((volatile unsigned short *)CAN_AM08L)
+#define pCAN_AM08H ((volatile unsigned short *)CAN_AM08H)
+#define pCAN_AM09L ((volatile unsigned short *)CAN_AM09L)
+#define pCAN_AM09H ((volatile unsigned short *)CAN_AM09H)
+#define pCAN_AM10L ((volatile unsigned short *)CAN_AM10L)
+#define pCAN_AM10H ((volatile unsigned short *)CAN_AM10H)
+#define pCAN_AM11L ((volatile unsigned short *)CAN_AM11L)
+#define pCAN_AM11H ((volatile unsigned short *)CAN_AM11H)
+#define pCAN_AM12L ((volatile unsigned short *)CAN_AM12L)
+#define pCAN_AM12H ((volatile unsigned short *)CAN_AM12H)
+#define pCAN_AM13L ((volatile unsigned short *)CAN_AM13L)
+#define pCAN_AM13H ((volatile unsigned short *)CAN_AM13H)
+#define pCAN_AM14L ((volatile unsigned short *)CAN_AM14L)
+#define pCAN_AM14H ((volatile unsigned short *)CAN_AM14H)
+#define pCAN_AM15L ((volatile unsigned short *)CAN_AM15L)
+#define pCAN_AM15H ((volatile unsigned short *)CAN_AM15H)
+
+#define pCAN_AM16L ((volatile unsigned short *)CAN_AM16L)
+#define pCAN_AM16H ((volatile unsigned short *)CAN_AM16H)
+#define pCAN_AM17L ((volatile unsigned short *)CAN_AM17L)
+#define pCAN_AM17H ((volatile unsigned short *)CAN_AM17H)
+#define pCAN_AM18L ((volatile unsigned short *)CAN_AM18L)
+#define pCAN_AM18H ((volatile unsigned short *)CAN_AM18H)
+#define pCAN_AM19L ((volatile unsigned short *)CAN_AM19L)
+#define pCAN_AM19H ((volatile unsigned short *)CAN_AM19H)
+#define pCAN_AM20L ((volatile unsigned short *)CAN_AM20L)
+#define pCAN_AM20H ((volatile unsigned short *)CAN_AM20H)
+#define pCAN_AM21L ((volatile unsigned short *)CAN_AM21L)
+#define pCAN_AM21H ((volatile unsigned short *)CAN_AM21H)
+#define pCAN_AM22L ((volatile unsigned short *)CAN_AM22L)
+#define pCAN_AM22H ((volatile unsigned short *)CAN_AM22H)
+#define pCAN_AM23L ((volatile unsigned short *)CAN_AM23L)
+#define pCAN_AM23H ((volatile unsigned short *)CAN_AM23H)
+#define pCAN_AM24L ((volatile unsigned short *)CAN_AM24L)
+#define pCAN_AM24H ((volatile unsigned short *)CAN_AM24H)
+#define pCAN_AM25L ((volatile unsigned short *)CAN_AM25L)
+#define pCAN_AM25H ((volatile unsigned short *)CAN_AM25H)
+#define pCAN_AM26L ((volatile unsigned short *)CAN_AM26L)
+#define pCAN_AM26H ((volatile unsigned short *)CAN_AM26H)
+#define pCAN_AM27L ((volatile unsigned short *)CAN_AM27L)
+#define pCAN_AM27H ((volatile unsigned short *)CAN_AM27H)
+#define pCAN_AM28L ((volatile unsigned short *)CAN_AM28L)
+#define pCAN_AM28H ((volatile unsigned short *)CAN_AM28H)
+#define pCAN_AM29L ((volatile unsigned short *)CAN_AM29L)
+#define pCAN_AM29H ((volatile unsigned short *)CAN_AM29H)
+#define pCAN_AM30L ((volatile unsigned short *)CAN_AM30L)
+#define pCAN_AM30H ((volatile unsigned short *)CAN_AM30H)
+#define pCAN_AM31L ((volatile unsigned short *)CAN_AM31L)
+#define pCAN_AM31H ((volatile unsigned short *)CAN_AM31H)
+
+/* CAN Acceptance Mask Area Macros */
+#define pCAN_AM_L(x) ((volatile unsigned short *)CAN_AM_L(x))
+#define pCAN_AM_H(x) ((volatile unsigned short *)CAN_AM_H(x))
+
+/* Mailbox Registers */
+#define pCAN_MB00_ID1 ((volatile unsigned short *)CAN_MB00_ID1)
+#define pCAN_MB00_ID0 ((volatile unsigned short *)CAN_MB00_ID0)
+#define pCAN_MB00_TIMESTAMP ((volatile unsigned short *)CAN_MB00_TIMESTAMP)
+#define pCAN_MB00_LENGTH ((volatile unsigned short *)CAN_MB00_LENGTH)
+#define pCAN_MB00_DATA3 ((volatile unsigned short *)CAN_MB00_DATA3)
+#define pCAN_MB00_DATA2 ((volatile unsigned short *)CAN_MB00_DATA2)
+#define pCAN_MB00_DATA1 ((volatile unsigned short *)CAN_MB00_DATA1)
+#define pCAN_MB00_DATA0 ((volatile unsigned short *)CAN_MB00_DATA0)
+
+#define pCAN_MB01_ID1 ((volatile unsigned short *)CAN_MB01_ID1)
+#define pCAN_MB01_ID0 ((volatile unsigned short *)CAN_MB01_ID0)
+#define pCAN_MB01_TIMESTAMP ((volatile unsigned short *)CAN_MB01_TIMESTAMP)
+#define pCAN_MB01_LENGTH ((volatile unsigned short *)CAN_MB01_LENGTH)
+#define pCAN_MB01_DATA3 ((volatile unsigned short *)CAN_MB01_DATA3)
+#define pCAN_MB01_DATA2 ((volatile unsigned short *)CAN_MB01_DATA2)
+#define pCAN_MB01_DATA1 ((volatile unsigned short *)CAN_MB01_DATA1)
+#define pCAN_MB01_DATA0 ((volatile unsigned short *)CAN_MB01_DATA0)
+
+#define pCAN_MB02_ID1 ((volatile unsigned short *)CAN_MB02_ID1)
+#define pCAN_MB02_ID0 ((volatile unsigned short *)CAN_MB02_ID0)
+#define pCAN_MB02_TIMESTAMP ((volatile unsigned short *)CAN_MB02_TIMESTAMP)
+#define pCAN_MB02_LENGTH ((volatile unsigned short *)CAN_MB02_LENGTH)
+#define pCAN_MB02_DATA3 ((volatile unsigned short *)CAN_MB02_DATA3)
+#define pCAN_MB02_DATA2 ((volatile unsigned short *)CAN_MB02_DATA2)
+#define pCAN_MB02_DATA1 ((volatile unsigned short *)CAN_MB02_DATA1)
+#define pCAN_MB02_DATA0 ((volatile unsigned short *)CAN_MB02_DATA0)
+
+#define pCAN_MB03_ID1 ((volatile unsigned short *)CAN_MB03_ID1)
+#define pCAN_MB03_ID0 ((volatile unsigned short *)CAN_MB03_ID0)
+#define pCAN_MB03_TIMESTAMP ((volatile unsigned short *)CAN_MB03_TIMESTAMP)
+#define pCAN_MB03_LENGTH ((volatile unsigned short *)CAN_MB03_LENGTH)
+#define pCAN_MB03_DATA3 ((volatile unsigned short *)CAN_MB03_DATA3)
+#define pCAN_MB03_DATA2 ((volatile unsigned short *)CAN_MB03_DATA2)
+#define pCAN_MB03_DATA1 ((volatile unsigned short *)CAN_MB03_DATA1)
+#define pCAN_MB03_DATA0 ((volatile unsigned short *)CAN_MB03_DATA0)
+
+#define pCAN_MB04_ID1 ((volatile unsigned short *)CAN_MB04_ID1)
+#define pCAN_MB04_ID0 ((volatile unsigned short *)CAN_MB04_ID0)
+#define pCAN_MB04_TIMESTAMP ((volatile unsigned short *)CAN_MB04_TIMESTAMP)
+#define pCAN_MB04_LENGTH ((volatile unsigned short *)CAN_MB04_LENGTH)
+#define pCAN_MB04_DATA3 ((volatile unsigned short *)CAN_MB04_DATA3)
+#define pCAN_MB04_DATA2 ((volatile unsigned short *)CAN_MB04_DATA2)
+#define pCAN_MB04_DATA1 ((volatile unsigned short *)CAN_MB04_DATA1)
+#define pCAN_MB04_DATA0 ((volatile unsigned short *)CAN_MB04_DATA0)
+
+#define pCAN_MB05_ID1 ((volatile unsigned short *)CAN_MB05_ID1)
+#define pCAN_MB05_ID0 ((volatile unsigned short *)CAN_MB05_ID0)
+#define pCAN_MB05_TIMESTAMP ((volatile unsigned short *)CAN_MB05_TIMESTAMP)
+#define pCAN_MB05_LENGTH ((volatile unsigned short *)CAN_MB05_LENGTH)
+#define pCAN_MB05_DATA3 ((volatile unsigned short *)CAN_MB05_DATA3)
+#define pCAN_MB05_DATA2 ((volatile unsigned short *)CAN_MB05_DATA2)
+#define pCAN_MB05_DATA1 ((volatile unsigned short *)CAN_MB05_DATA1)
+#define pCAN_MB05_DATA0 ((volatile unsigned short *)CAN_MB05_DATA0)
+
+#define pCAN_MB06_ID1 ((volatile unsigned short *)CAN_MB06_ID1)
+#define pCAN_MB06_ID0 ((volatile unsigned short *)CAN_MB06_ID0)
+#define pCAN_MB06_TIMESTAMP ((volatile unsigned short *)CAN_MB06_TIMESTAMP)
+#define pCAN_MB06_LENGTH ((volatile unsigned short *)CAN_MB06_LENGTH)
+#define pCAN_MB06_DATA3 ((volatile unsigned short *)CAN_MB06_DATA3)
+#define pCAN_MB06_DATA2 ((volatile unsigned short *)CAN_MB06_DATA2)
+#define pCAN_MB06_DATA1 ((volatile unsigned short *)CAN_MB06_DATA1)
+#define pCAN_MB06_DATA0 ((volatile unsigned short *)CAN_MB06_DATA0)
+
+#define pCAN_MB07_ID1 ((volatile unsigned short *)CAN_MB07_ID1)
+#define pCAN_MB07_ID0 ((volatile unsigned short *)CAN_MB07_ID0)
+#define pCAN_MB07_TIMESTAMP ((volatile unsigned short *)CAN_MB07_TIMESTAMP)
+#define pCAN_MB07_LENGTH ((volatile unsigned short *)CAN_MB07_LENGTH)
+#define pCAN_MB07_DATA3 ((volatile unsigned short *)CAN_MB07_DATA3)
+#define pCAN_MB07_DATA2 ((volatile unsigned short *)CAN_MB07_DATA2)
+#define pCAN_MB07_DATA1 ((volatile unsigned short *)CAN_MB07_DATA1)
+#define pCAN_MB07_DATA0 ((volatile unsigned short *)CAN_MB07_DATA0)
+
+#define pCAN_MB08_ID1 ((volatile unsigned short *)CAN_MB08_ID1)
+#define pCAN_MB08_ID0 ((volatile unsigned short *)CAN_MB08_ID0)
+#define pCAN_MB08_TIMESTAMP ((volatile unsigned short *)CAN_MB08_TIMESTAMP)
+#define pCAN_MB08_LENGTH ((volatile unsigned short *)CAN_MB08_LENGTH)
+#define pCAN_MB08_DATA3 ((volatile unsigned short *)CAN_MB08_DATA3)
+#define pCAN_MB08_DATA2 ((volatile unsigned short *)CAN_MB08_DATA2)
+#define pCAN_MB08_DATA1 ((volatile unsigned short *)CAN_MB08_DATA1)
+#define pCAN_MB08_DATA0 ((volatile unsigned short *)CAN_MB08_DATA0)
+
+#define pCAN_MB09_ID1 ((volatile unsigned short *)CAN_MB09_ID1)
+#define pCAN_MB09_ID0 ((volatile unsigned short *)CAN_MB09_ID0)
+#define pCAN_MB09_TIMESTAMP ((volatile unsigned short *)CAN_MB09_TIMESTAMP)
+#define pCAN_MB09_LENGTH ((volatile unsigned short *)CAN_MB09_LENGTH)
+#define pCAN_MB09_DATA3 ((volatile unsigned short *)CAN_MB09_DATA3)
+#define pCAN_MB09_DATA2 ((volatile unsigned short *)CAN_MB09_DATA2)
+#define pCAN_MB09_DATA1 ((volatile unsigned short *)CAN_MB09_DATA1)
+#define pCAN_MB09_DATA0 ((volatile unsigned short *)CAN_MB09_DATA0)
+
+#define pCAN_MB10_ID1 ((volatile unsigned short *)CAN_MB10_ID1)
+#define pCAN_MB10_ID0 ((volatile unsigned short *)CAN_MB10_ID0)
+#define pCAN_MB10_TIMESTAMP ((volatile unsigned short *)CAN_MB10_TIMESTAMP)
+#define pCAN_MB10_LENGTH ((volatile unsigned short *)CAN_MB10_LENGTH)
+#define pCAN_MB10_DATA3 ((volatile unsigned short *)CAN_MB10_DATA3)
+#define pCAN_MB10_DATA2 ((volatile unsigned short *)CAN_MB10_DATA2)
+#define pCAN_MB10_DATA1 ((volatile unsigned short *)CAN_MB10_DATA1)
+#define pCAN_MB10_DATA0 ((volatile unsigned short *)CAN_MB10_DATA0)
+
+#define pCAN_MB11_ID1 ((volatile unsigned short *)CAN_MB11_ID1)
+#define pCAN_MB11_ID0 ((volatile unsigned short *)CAN_MB11_ID0)
+#define pCAN_MB11_TIMESTAMP ((volatile unsigned short *)CAN_MB11_TIMESTAMP)
+#define pCAN_MB11_LENGTH ((volatile unsigned short *)CAN_MB11_LENGTH)
+#define pCAN_MB11_DATA3 ((volatile unsigned short *)CAN_MB11_DATA3)
+#define pCAN_MB11_DATA2 ((volatile unsigned short *)CAN_MB11_DATA2)
+#define pCAN_MB11_DATA1 ((volatile unsigned short *)CAN_MB11_DATA1)
+#define pCAN_MB11_DATA0 ((volatile unsigned short *)CAN_MB11_DATA0)
+
+#define pCAN_MB12_ID1 ((volatile unsigned short *)CAN_MB12_ID1)
+#define pCAN_MB12_ID0 ((volatile unsigned short *)CAN_MB12_ID0)
+#define pCAN_MB12_TIMESTAMP ((volatile unsigned short *)CAN_MB12_TIMESTAMP)
+#define pCAN_MB12_LENGTH ((volatile unsigned short *)CAN_MB12_LENGTH)
+#define pCAN_MB12_DATA3 ((volatile unsigned short *)CAN_MB12_DATA3)
+#define pCAN_MB12_DATA2 ((volatile unsigned short *)CAN_MB12_DATA2)
+#define pCAN_MB12_DATA1 ((volatile unsigned short *)CAN_MB12_DATA1)
+#define pCAN_MB12_DATA0 ((volatile unsigned short *)CAN_MB12_DATA0)
+
+#define pCAN_MB13_ID1 ((volatile unsigned short *)CAN_MB13_ID1)
+#define pCAN_MB13_ID0 ((volatile unsigned short *)CAN_MB13_ID0)
+#define pCAN_MB13_TIMESTAMP ((volatile unsigned short *)CAN_MB13_TIMESTAMP)
+#define pCAN_MB13_LENGTH ((volatile unsigned short *)CAN_MB13_LENGTH)
+#define pCAN_MB13_DATA3 ((volatile unsigned short *)CAN_MB13_DATA3)
+#define pCAN_MB13_DATA2 ((volatile unsigned short *)CAN_MB13_DATA2)
+#define pCAN_MB13_DATA1 ((volatile unsigned short *)CAN_MB13_DATA1)
+#define pCAN_MB13_DATA0 ((volatile unsigned short *)CAN_MB13_DATA0)
+
+#define pCAN_MB14_ID1 ((volatile unsigned short *)CAN_MB14_ID1)
+#define pCAN_MB14_ID0 ((volatile unsigned short *)CAN_MB14_ID0)
+#define pCAN_MB14_TIMESTAMP ((volatile unsigned short *)CAN_MB14_TIMESTAMP)
+#define pCAN_MB14_LENGTH ((volatile unsigned short *)CAN_MB14_LENGTH)
+#define pCAN_MB14_DATA3 ((volatile unsigned short *)CAN_MB14_DATA3)
+#define pCAN_MB14_DATA2 ((volatile unsigned short *)CAN_MB14_DATA2)
+#define pCAN_MB14_DATA1 ((volatile unsigned short *)CAN_MB14_DATA1)
+#define pCAN_MB14_DATA0 ((volatile unsigned short *)CAN_MB14_DATA0)
+
+#define pCAN_MB15_ID1 ((volatile unsigned short *)CAN_MB15_ID1)
+#define pCAN_MB15_ID0 ((volatile unsigned short *)CAN_MB15_ID0)
+#define pCAN_MB15_TIMESTAMP ((volatile unsigned short *)CAN_MB15_TIMESTAMP)
+#define pCAN_MB15_LENGTH ((volatile unsigned short *)CAN_MB15_LENGTH)
+#define pCAN_MB15_DATA3 ((volatile unsigned short *)CAN_MB15_DATA3)
+#define pCAN_MB15_DATA2 ((volatile unsigned short *)CAN_MB15_DATA2)
+#define pCAN_MB15_DATA1 ((volatile unsigned short *)CAN_MB15_DATA1)
+#define pCAN_MB15_DATA0 ((volatile unsigned short *)CAN_MB15_DATA0)
+
+#define pCAN_MB16_ID1 ((volatile unsigned short *)CAN_MB16_ID1)
+#define pCAN_MB16_ID0 ((volatile unsigned short *)CAN_MB16_ID0)
+#define pCAN_MB16_TIMESTAMP ((volatile unsigned short *)CAN_MB16_TIMESTAMP)
+#define pCAN_MB16_LENGTH ((volatile unsigned short *)CAN_MB16_LENGTH)
+#define pCAN_MB16_DATA3 ((volatile unsigned short *)CAN_MB16_DATA3)
+#define pCAN_MB16_DATA2 ((volatile unsigned short *)CAN_MB16_DATA2)
+#define pCAN_MB16_DATA1 ((volatile unsigned short *)CAN_MB16_DATA1)
+#define pCAN_MB16_DATA0 ((volatile unsigned short *)CAN_MB16_DATA0)
+
+#define pCAN_MB17_ID1 ((volatile unsigned short *)CAN_MB17_ID1)
+#define pCAN_MB17_ID0 ((volatile unsigned short *)CAN_MB17_ID0)
+#define pCAN_MB17_TIMESTAMP ((volatile unsigned short *)CAN_MB17_TIMESTAMP)
+#define pCAN_MB17_LENGTH ((volatile unsigned short *)CAN_MB17_LENGTH)
+#define pCAN_MB17_DATA3 ((volatile unsigned short *)CAN_MB17_DATA3)
+#define pCAN_MB17_DATA2 ((volatile unsigned short *)CAN_MB17_DATA2)
+#define pCAN_MB17_DATA1 ((volatile unsigned short *)CAN_MB17_DATA1)
+#define pCAN_MB17_DATA0 ((volatile unsigned short *)CAN_MB17_DATA0)
+
+#define pCAN_MB18_ID1 ((volatile unsigned short *)CAN_MB18_ID1)
+#define pCAN_MB18_ID0 ((volatile unsigned short *)CAN_MB18_ID0)
+#define pCAN_MB18_TIMESTAMP ((volatile unsigned short *)CAN_MB18_TIMESTAMP)
+#define pCAN_MB18_LENGTH ((volatile unsigned short *)CAN_MB18_LENGTH)
+#define pCAN_MB18_DATA3 ((volatile unsigned short *)CAN_MB18_DATA3)
+#define pCAN_MB18_DATA2 ((volatile unsigned short *)CAN_MB18_DATA2)
+#define pCAN_MB18_DATA1 ((volatile unsigned short *)CAN_MB18_DATA1)
+#define pCAN_MB18_DATA0 ((volatile unsigned short *)CAN_MB18_DATA0)
+
+#define pCAN_MB19_ID1 ((volatile unsigned short *)CAN_MB19_ID1)
+#define pCAN_MB19_ID0 ((volatile unsigned short *)CAN_MB19_ID0)
+#define pCAN_MB19_TIMESTAMP ((volatile unsigned short *)CAN_MB19_TIMESTAMP)
+#define pCAN_MB19_LENGTH ((volatile unsigned short *)CAN_MB19_LENGTH)
+#define pCAN_MB19_DATA3 ((volatile unsigned short *)CAN_MB19_DATA3)
+#define pCAN_MB19_DATA2 ((volatile unsigned short *)CAN_MB19_DATA2)
+#define pCAN_MB19_DATA1 ((volatile unsigned short *)CAN_MB19_DATA1)
+#define pCAN_MB19_DATA0 ((volatile unsigned short *)CAN_MB19_DATA0)
+
+#define pCAN_MB20_ID1 ((volatile unsigned short *)CAN_MB20_ID1)
+#define pCAN_MB20_ID0 ((volatile unsigned short *)CAN_MB20_ID0)
+#define pCAN_MB20_TIMESTAMP ((volatile unsigned short *)CAN_MB20_TIMESTAMP)
+#define pCAN_MB20_LENGTH ((volatile unsigned short *)CAN_MB20_LENGTH)
+#define pCAN_MB20_DATA3 ((volatile unsigned short *)CAN_MB20_DATA3)
+#define pCAN_MB20_DATA2 ((volatile unsigned short *)CAN_MB20_DATA2)
+#define pCAN_MB20_DATA1 ((volatile unsigned short *)CAN_MB20_DATA1)
+#define pCAN_MB20_DATA0 ((volatile unsigned short *)CAN_MB20_DATA0)
+
+#define pCAN_MB21_ID1 ((volatile unsigned short *)CAN_MB21_ID1)
+#define pCAN_MB21_ID0 ((volatile unsigned short *)CAN_MB21_ID0)
+#define pCAN_MB21_TIMESTAMP ((volatile unsigned short *)CAN_MB21_TIMESTAMP)
+#define pCAN_MB21_LENGTH ((volatile unsigned short *)CAN_MB21_LENGTH)
+#define pCAN_MB21_DATA3 ((volatile unsigned short *)CAN_MB21_DATA3)
+#define pCAN_MB21_DATA2 ((volatile unsigned short *)CAN_MB21_DATA2)
+#define pCAN_MB21_DATA1 ((volatile unsigned short *)CAN_MB21_DATA1)
+#define pCAN_MB21_DATA0 ((volatile unsigned short *)CAN_MB21_DATA0)
+
+#define pCAN_MB22_ID1 ((volatile unsigned short *)CAN_MB22_ID1)
+#define pCAN_MB22_ID0 ((volatile unsigned short *)CAN_MB22_ID0)
+#define pCAN_MB22_TIMESTAMP ((volatile unsigned short *)CAN_MB22_TIMESTAMP)
+#define pCAN_MB22_LENGTH ((volatile unsigned short *)CAN_MB22_LENGTH)
+#define pCAN_MB22_DATA3 ((volatile unsigned short *)CAN_MB22_DATA3)
+#define pCAN_MB22_DATA2 ((volatile unsigned short *)CAN_MB22_DATA2)
+#define pCAN_MB22_DATA1 ((volatile unsigned short *)CAN_MB22_DATA1)
+#define pCAN_MB22_DATA0 ((volatile unsigned short *)CAN_MB22_DATA0)
+
+#define pCAN_MB23_ID1 ((volatile unsigned short *)CAN_MB23_ID1)
+#define pCAN_MB23_ID0 ((volatile unsigned short *)CAN_MB23_ID0)
+#define pCAN_MB23_TIMESTAMP ((volatile unsigned short *)CAN_MB23_TIMESTAMP)
+#define pCAN_MB23_LENGTH ((volatile unsigned short *)CAN_MB23_LENGTH)
+#define pCAN_MB23_DATA3 ((volatile unsigned short *)CAN_MB23_DATA3)
+#define pCAN_MB23_DATA2 ((volatile unsigned short *)CAN_MB23_DATA2)
+#define pCAN_MB23_DATA1 ((volatile unsigned short *)CAN_MB23_DATA1)
+#define pCAN_MB23_DATA0 ((volatile unsigned short *)CAN_MB23_DATA0)
+
+#define pCAN_MB24_ID1 ((volatile unsigned short *)CAN_MB24_ID1)
+#define pCAN_MB24_ID0 ((volatile unsigned short *)CAN_MB24_ID0)
+#define pCAN_MB24_TIMESTAMP ((volatile unsigned short *)CAN_MB24_TIMESTAMP)
+#define pCAN_MB24_LENGTH ((volatile unsigned short *)CAN_MB24_LENGTH)
+#define pCAN_MB24_DATA3 ((volatile unsigned short *)CAN_MB24_DATA3)
+#define pCAN_MB24_DATA2 ((volatile unsigned short *)CAN_MB24_DATA2)
+#define pCAN_MB24_DATA1 ((volatile unsigned short *)CAN_MB24_DATA1)
+#define pCAN_MB24_DATA0 ((volatile unsigned short *)CAN_MB24_DATA0)
+
+#define pCAN_MB25_ID1 ((volatile unsigned short *)CAN_MB25_ID1)
+#define pCAN_MB25_ID0 ((volatile unsigned short *)CAN_MB25_ID0)
+#define pCAN_MB25_TIMESTAMP ((volatile unsigned short *)CAN_MB25_TIMESTAMP)
+#define pCAN_MB25_LENGTH ((volatile unsigned short *)CAN_MB25_LENGTH)
+#define pCAN_MB25_DATA3 ((volatile unsigned short *)CAN_MB25_DATA3)
+#define pCAN_MB25_DATA2 ((volatile unsigned short *)CAN_MB25_DATA2)
+#define pCAN_MB25_DATA1 ((volatile unsigned short *)CAN_MB25_DATA1)
+#define pCAN_MB25_DATA0 ((volatile unsigned short *)CAN_MB25_DATA0)
+
+#define pCAN_MB26_ID1 ((volatile unsigned short *)CAN_MB26_ID1)
+#define pCAN_MB26_ID0 ((volatile unsigned short *)CAN_MB26_ID0)
+#define pCAN_MB26_TIMESTAMP ((volatile unsigned short *)CAN_MB26_TIMESTAMP)
+#define pCAN_MB26_LENGTH ((volatile unsigned short *)CAN_MB26_LENGTH)
+#define pCAN_MB26_DATA3 ((volatile unsigned short *)CAN_MB26_DATA3)
+#define pCAN_MB26_DATA2 ((volatile unsigned short *)CAN_MB26_DATA2)
+#define pCAN_MB26_DATA1 ((volatile unsigned short *)CAN_MB26_DATA1)
+#define pCAN_MB26_DATA0 ((volatile unsigned short *)CAN_MB26_DATA0)
+
+#define pCAN_MB27_ID1 ((volatile unsigned short *)CAN_MB27_ID1)
+#define pCAN_MB27_ID0 ((volatile unsigned short *)CAN_MB27_ID0)
+#define pCAN_MB27_TIMESTAMP ((volatile unsigned short *)CAN_MB27_TIMESTAMP)
+#define pCAN_MB27_LENGTH ((volatile unsigned short *)CAN_MB27_LENGTH)
+#define pCAN_MB27_DATA3 ((volatile unsigned short *)CAN_MB27_DATA3)
+#define pCAN_MB27_DATA2 ((volatile unsigned short *)CAN_MB27_DATA2)
+#define pCAN_MB27_DATA1 ((volatile unsigned short *)CAN_MB27_DATA1)
+#define pCAN_MB27_DATA0 ((volatile unsigned short *)CAN_MB27_DATA0)
+
+#define pCAN_MB28_ID1 ((volatile unsigned short *)CAN_MB28_ID1)
+#define pCAN_MB28_ID0 ((volatile unsigned short *)CAN_MB28_ID0)
+#define pCAN_MB28_TIMESTAMP ((volatile unsigned short *)CAN_MB28_TIMESTAMP)
+#define pCAN_MB28_LENGTH ((volatile unsigned short *)CAN_MB28_LENGTH)
+#define pCAN_MB28_DATA3 ((volatile unsigned short *)CAN_MB28_DATA3)
+#define pCAN_MB28_DATA2 ((volatile unsigned short *)CAN_MB28_DATA2)
+#define pCAN_MB28_DATA1 ((volatile unsigned short *)CAN_MB28_DATA1)
+#define pCAN_MB28_DATA0 ((volatile unsigned short *)CAN_MB28_DATA0)
+
+#define pCAN_MB29_ID1 ((volatile unsigned short *)CAN_MB29_ID1)
+#define pCAN_MB29_ID0 ((volatile unsigned short *)CAN_MB29_ID0)
+#define pCAN_MB29_TIMESTAMP ((volatile unsigned short *)CAN_MB29_TIMESTAMP)
+#define pCAN_MB29_LENGTH ((volatile unsigned short *)CAN_MB29_LENGTH)
+#define pCAN_MB29_DATA3 ((volatile unsigned short *)CAN_MB29_DATA3)
+#define pCAN_MB29_DATA2 ((volatile unsigned short *)CAN_MB29_DATA2)
+#define pCAN_MB29_DATA1 ((volatile unsigned short *)CAN_MB29_DATA1)
+#define pCAN_MB29_DATA0 ((volatile unsigned short *)CAN_MB29_DATA0)
+
+#define pCAN_MB30_ID1 ((volatile unsigned short *)CAN_MB30_ID1)
+#define pCAN_MB30_ID0 ((volatile unsigned short *)CAN_MB30_ID0)
+#define pCAN_MB30_TIMESTAMP ((volatile unsigned short *)CAN_MB30_TIMESTAMP)
+#define pCAN_MB30_LENGTH ((volatile unsigned short *)CAN_MB30_LENGTH)
+#define pCAN_MB30_DATA3 ((volatile unsigned short *)CAN_MB30_DATA3)
+#define pCAN_MB30_DATA2 ((volatile unsigned short *)CAN_MB30_DATA2)
+#define pCAN_MB30_DATA1 ((volatile unsigned short *)CAN_MB30_DATA1)
+#define pCAN_MB30_DATA0 ((volatile unsigned short *)CAN_MB30_DATA0)
+
+#define pCAN_MB31_ID1 ((volatile unsigned short *)CAN_MB31_ID1)
+#define pCAN_MB31_ID0 ((volatile unsigned short *)CAN_MB31_ID0)
+#define pCAN_MB31_TIMESTAMP ((volatile unsigned short *)CAN_MB31_TIMESTAMP)
+#define pCAN_MB31_LENGTH ((volatile unsigned short *)CAN_MB31_LENGTH)
+#define pCAN_MB31_DATA3 ((volatile unsigned short *)CAN_MB31_DATA3)
+#define pCAN_MB31_DATA2 ((volatile unsigned short *)CAN_MB31_DATA2)
+#define pCAN_MB31_DATA1 ((volatile unsigned short *)CAN_MB31_DATA1)
+#define pCAN_MB31_DATA0 ((volatile unsigned short *)CAN_MB31_DATA0)
+
+/* CAN Mailbox Area Macros */
+#define pCAN_MB_ID1(x) ((volatile unsigned short *)CAN_MB_ID1(x))
+#define pCAN_MB_ID0(x) ((volatile unsigned short *)CAN_MB_ID0(x))
+#define pCAN_MB_TIMESTAMP(x) ((volatile unsigned short *)CAN_MB_TIMESTAMP(x))
+#define pCAN_MB_LENGTH(x) ((volatile unsigned short *)CAN_MB_LENGTH(x))
+#define pCAN_MB_DATA3(x) ((volatile unsigned short *)CAN_MB_DATA3(x))
+#define pCAN_MB_DATA2(x) ((volatile unsigned short *)CAN_MB_DATA2(x))
+#define pCAN_MB_DATA1(x) ((volatile unsigned short *)CAN_MB_DATA1(x))
+#define pCAN_MB_DATA0(x) ((volatile unsigned short *)CAN_MB_DATA0(x))
+
+
+/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
+#define pPORTF_FER ((volatile unsigned short *)PORTF_FER)
+#define pPORTG_FER ((volatile unsigned short *)PORTG_FER)
+#define pPORTH_FER ((volatile unsigned short *)PORTH_FER)
+#define pPORT_MUX ((volatile unsigned short *)PORT_MUX)
+
+
+/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
+#define pHMDMA0_CONTROL ((volatile unsigned short *)HMDMA0_CONTROL)
+#define pHMDMA0_ECINIT ((volatile unsigned short *)HMDMA0_ECINIT)
+#define pHMDMA0_BCINIT ((volatile unsigned short *)HMDMA0_BCINIT)
+#define pHMDMA0_ECURGENT ((volatile unsigned short *)HMDMA0_ECURGENT)
+#define pHMDMA0_ECOVERFLOW ((volatile unsigned short *)HMDMA0_ECOVERFLOW)
+#define pHMDMA0_ECOUNT ((volatile unsigned short *)HMDMA0_ECOUNT)
+#define pHMDMA0_BCOUNT ((volatile unsigned short *)HMDMA0_BCOUNT)
+
+#define pHMDMA1_CONTROL ((volatile unsigned short *)HMDMA1_CONTROL)
+#define pHMDMA1_ECINIT ((volatile unsigned short *)HMDMA1_ECINIT)
+#define pHMDMA1_BCINIT ((volatile unsigned short *)HMDMA1_BCINIT)
+#define pHMDMA1_ECURGENT ((volatile unsigned short *)HMDMA1_ECURGENT)
+#define pHMDMA1_ECOVERFLOW ((volatile unsigned short *)HMDMA1_ECOVERFLOW)
+#define pHMDMA1_ECOUNT ((volatile unsigned short *)HMDMA1_ECOUNT)
+#define pHMDMA1_BCOUNT ((volatile unsigned short *)HMDMA1_BCOUNT)
+
+#endif /* _CDEF_BF534_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * cdefBF535.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifndef _CDEF_BF535_H
+#define _CDEF_BF535_H
+
+/* include all Core registers and bit definitions */
+#if defined(__ADSPLPBLACKFIN__)
+#warning cdefBF535.h should only be included for 535 compatible chips.
+#endif
+#include <defBF535.h>
+
+/* include core specific register pointer definitions */
+#include <cdefblackfin.h>
+
+#ifndef _PTR_TO_VOL_VOID_PTR
+#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
+#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
+#else
+#define _PTR_TO_VOL_VOID_PTR (volatile void **)
+#endif
+#endif
+
+/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
+#define pPLL_CTL ((volatile unsigned long *)PLL_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+#define pPLL_IOCKR ((volatile unsigned short *)PLL_IOCKR)
+#define pPLL_IOCK ((volatile unsigned short *)PLL_IOCK)
+
+/* JTAG/Debug Communication Channel (0xFFC0 0800-0xFFC0 0BFF) */
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+
+/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_IMASK ((volatile unsigned long *)SIC_IMASK)
+#define pSIC_ISR ((volatile unsigned long *)SIC_ISR)
+#define pSIC_IWR ((volatile unsigned long *)SIC_IWR)
+
+/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
+
+/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
+#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
+#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
+#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
+#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
+#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
+#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
+#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
+#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
+#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
+#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
+
+/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+
+/* USB Registers (0xFFC0 4400 - 0xFFC0 47FF) */
+#define pUSBD_ID ((volatile unsigned short *)USBD_ID)
+#define pUSBD_FRM ((volatile unsigned short *)USBD_FRM)
+#define pUSBD_FRMAT ((volatile unsigned short *)USBD_FRMAT)
+#define pUSBD_EPBUF ((volatile unsigned short *)USBD_EPBUF)
+#define pUSBD_STAT ((volatile unsigned short *)USBD_STAT)
+#define pUSBD_CTRL ((volatile unsigned short *)USBD_CTRL)
+#define pUSBD_GINTR ((volatile unsigned short *)USBD_GINTR)
+#define pUSBD_GMASK ((volatile unsigned short *)USBD_GMASK)
+#define pUSBD_DMACFG ((volatile unsigned short *)USBD_DMACFG)
+#define pUSBD_DMABL ((volatile unsigned short *)USBD_DMABL)
+#define pUSBD_DMABH ((volatile unsigned short *)USBD_DMABH)
+#define pUSBD_DMACT ((volatile unsigned short *)USBD_DMACT)
+#define pUSBD_DMAIRQ ((volatile unsigned short *)USBD_DMAIRQ)
+#define pUSBD_INTR0 ((volatile unsigned short *)USBD_INTR0)
+#define pUSBD_MASK0 ((volatile unsigned short *)USBD_MASK0)
+#define pUSBD_EPCFG0 ((volatile unsigned short *)USBD_EPCFG0)
+#define pUSBD_EPADR0 ((volatile unsigned short *)USBD_EPADR0)
+#define pUSBD_EPLEN0 ((volatile unsigned short *)USBD_EPLEN0)
+#define pUSBD_INTR1 ((volatile unsigned short *)USBD_INTR1)
+#define pUSBD_MASK1 ((volatile unsigned short *)USBD_MASK1)
+#define pUSBD_EPCFG1 ((volatile unsigned short *)USBD_EPCFG1)
+#define pUSBD_EPADR1 ((volatile unsigned short *)USBD_EPADR1)
+#define pUSBD_EPLEN1 ((volatile unsigned short *)USBD_EPLEN1)
+#define pUSBD_INTR2 ((volatile unsigned short *)USBD_INTR2)
+#define pUSBD_MASK2 ((volatile unsigned short *)USBD_MASK2)
+#define pUSBD_EPCFG2 ((volatile unsigned short *)USBD_EPCFG2)
+#define pUSBD_EPADR2 ((volatile unsigned short *)USBD_EPADR2)
+#define pUSBD_EPLEN2 ((volatile unsigned short *)USBD_EPLEN2)
+#define pUSBD_INTR3 ((volatile unsigned short *)USBD_INTR3)
+#define pUSBD_MASK3 ((volatile unsigned short *)USBD_MASK3)
+#define pUSBD_EPCFG3 ((volatile unsigned short *)USBD_EPCFG3)
+#define pUSBD_EPADR3 ((volatile unsigned short *)USBD_EPADR3)
+#define pUSBD_EPLEN3 ((volatile unsigned short *)USBD_EPLEN3)
+#define pUSBD_INTR4 ((volatile unsigned short *)USBD_INTR4)
+#define pUSBD_MASK4 ((volatile unsigned short *)USBD_MASK4)
+#define pUSBD_EPCFG4 ((volatile unsigned short *)USBD_EPCFG4)
+#define pUSBD_EPADR4 ((volatile unsigned short *)USBD_EPADR4)
+#define pUSBD_EPLEN4 ((volatile unsigned short *)USBD_EPLEN4)
+#define pUSBD_INTR5 ((volatile unsigned short *)USBD_INTR5)
+#define pUSBD_MASK5 ((volatile unsigned short *)USBD_MASK5)
+#define pUSBD_EPCFG5 ((volatile unsigned short *)USBD_EPCFG5)
+#define pUSBD_EPADR5 ((volatile unsigned short *)USBD_EPADR5)
+#define pUSBD_EPLEN5 ((volatile unsigned short *)USBD_EPLEN5)
+#define pUSBD_INTR6 ((volatile unsigned short *)USBD_INTR6)
+#define pUSBD_MASK6 ((volatile unsigned short *)USBD_MASK6)
+#define pUSBD_EPCFG6 ((volatile unsigned short *)USBD_EPCFG6)
+#define pUSBD_EPADR6 ((volatile unsigned short *)USBD_EPADR6)
+#define pUSBD_EPLEN6 ((volatile unsigned short *)USBD_EPLEN6)
+#define pUSBD_INTR7 ((volatile unsigned short *)USBD_INTR7)
+#define pUSBD_MASK7 ((volatile unsigned short *)USBD_MASK7)
+#define pUSBD_EPCFG7 ((volatile unsigned short *)USBD_EPCFG7)
+#define pUSBD_EPADR7 ((volatile unsigned short *)USBD_EPADR7)
+#define pUSBD_EPLEN7 ((volatile unsigned short *)USBD_EPLEN7)
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
+#define pEBIU_SDBCTL ((volatile unsigned long *)EBIU_SDBCTL)
+
+/* Memory Map */
+
+/* Core MMRs */
+#define pCOREMMR_BASE ((volatile void *)COREMMR_BASE)
+
+/* System MMRs */
+#define pSYSMMR_BASE ((volatile void *)SYSMMR_BASE)
+
+/* L1 cache/SRAM internal memory */
+#define pL1_DATA_A ((void *)L1_DATA_A)
+#define pL1_DATA_B ((void *)L1_DATA_B)
+#define pL1_CODE ((void *)L1_CODE)
+#define pL1_SCRATCH ((void *)L1_SCRATCH)
+
+/* L2 SRAM external memory */
+#define pL2_BASE ((void *)L2_BASE)
+
+/* PCI Spaces */
+#define pPCI_CONFIG_SPACE_PORT ((volatile void *)PCI_CONFIG_SPACE_PORT)
+#define pPCI_CONFIG_BASE ((volatile void *)PCI_CONFIG_BASE)
+#define pPCI_IO_BASE ((volatile void *)PCI_IO_BASE)
+#define pPCI_MEM_BASE ((volatile void *)PCI_MEM_BASE)
+
+/* Async Memory Banks */
+#define pASYNC_BANK3_BASE ((void *)ASYNC_BANK3_BASE)
+#define pASYNC_BANK2_BASE ((void *)ASYNC_BANK2_BASE)
+#define pASYNC_BANK1_BASE ((void *)ASYNC_BANK1_BASE)
+#define pASYNC_BANK0_BASE ((void *)ASYNC_BANK0_BASE)
+
+/* Sync DRAM Banks */
+#define pSDRAM_BANK3_BASE ((void *)SDRAM_BANK3_BASE)
+#define pSDRAM_BANK2_BASE ((void *)SDRAM_BANK2_BASE)
+#define pSDRAM_BANK1_BASE ((void *)SDRAM_BANK1_BASE)
+#define pSDRAM_BANK0_BASE ((void *)SDRAM_BANK0_BASE)
+
+/* UART 0 Controller (0xFFC0 1800-0xFFC0 1BFF) */
+#define pUART0_THR ((volatile unsigned short *)UART0_THR)
+#define pUART0_RBR ((volatile unsigned short *)UART0_RBR)
+#define pUART0_DLL ((volatile unsigned short *)UART0_DLL)
+#define pUART0_IER ((volatile unsigned short *)UART0_IER)
+#define pUART0_DLH ((volatile unsigned short *)UART0_DLH)
+#define pUART0_IIR ((volatile unsigned short *)UART0_IIR)
+#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
+#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
+#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
+#define pUART0_MSR ((volatile unsigned short *)UART0_MSR)
+#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
+#define pUART0_IRCR ((volatile unsigned short *)UART0_IRCR)
+#define pUART0_CURR_PTR_RX ((volatile unsigned short *)UART0_CURR_PTR_RX)
+#define pUART0_CONFIG_RX ((volatile unsigned short *)UART0_CONFIG_RX)
+#define pUART0_START_ADDR_HI_RX ((volatile unsigned short *)UART0_START_ADDR_HI_RX)
+#define pUART0_START_ADDR_LO_RX ((volatile unsigned short *)UART0_START_ADDR_LO_RX)
+#define pUART0_COUNT_RX ((volatile unsigned short *)UART0_COUNT_RX)
+#define pUART0_NEXT_DESCR_RX ((volatile unsigned short *)UART0_NEXT_DESCR_RX)
+#define pUART0_DESCR_RDY_RX ((volatile unsigned short *)UART0_DESCR_RDY_RX)
+#define pUART0_IRQSTAT_RX ((volatile unsigned short *)UART0_IRQSTAT_RX)
+#define pUART0_CURR_PTR_TX ((volatile unsigned short *)UART0_CURR_PTR_TX)
+#define pUART0_CONFIG_TX ((volatile unsigned short *)UART0_CONFIG_TX)
+#define pUART0_START_ADDR_HI_TX ((volatile unsigned short *)UART0_START_ADDR_HI_TX)
+#define pUART0_START_ADDR_LO_TX ((volatile unsigned short *)UART0_START_ADDR_LO_TX)
+#define pUART0_COUNT_TX ((volatile unsigned short *)UART0_COUNT_TX)
+#define pUART0_NEXT_DESCR_TX ((volatile unsigned short *)UART0_NEXT_DESCR_TX)
+#define pUART0_DESCR_RDY_TX ((volatile unsigned short *)UART0_DESCR_RDY_TX)
+#define pUART0_IRQSTAT_TX ((volatile unsigned short *)UART0_IRQSTAT_TX)
+
+/* UART 1 Controller (0xFFC0 1C00-0xFFC0 1FFF) */
+#define pUART1_THR ((volatile unsigned short *)UART1_THR)
+#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
+#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
+#define pUART1_IER ((volatile unsigned short *)UART1_IER)
+#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
+#define pUART1_IIR ((volatile unsigned short *)UART1_IIR)
+#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
+#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
+#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_MSR ((volatile unsigned short *)UART1_MSR)
+#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
+#define pUART1_CURR_PTR_RX ((volatile unsigned short *)UART1_CURR_PTR_RX)
+#define pUART1_CONFIG_RX ((volatile unsigned short *)UART1_CONFIG_RX)
+#define pUART1_START_ADDR_HI_RX ((volatile unsigned short *)UART1_START_ADDR_HI_RX)
+#define pUART1_START_ADDR_LO_RX ((volatile unsigned short *)UART1_START_ADDR_LO_RX)
+#define pUART1_COUNT_RX ((volatile unsigned short *)UART1_COUNT_RX)
+#define pUART1_NEXT_DESCR_RX ((volatile unsigned short *)UART1_NEXT_DESCR_RX)
+#define pUART1_DESCR_RDY_RX ((volatile unsigned short *)UART1_DESCR_RDY_RX)
+#define pUART1_IRQSTAT_RX ((volatile unsigned short *)UART1_IRQSTAT_RX)
+#define pUART1_CURR_PTR_TX ((volatile unsigned short *)UART1_CURR_PTR_TX)
+#define pUART1_CONFIG_TX ((volatile unsigned short *)UART1_CONFIG_TX)
+#define pUART1_START_ADDR_HI_TX ((volatile unsigned short *)UART1_START_ADDR_HI_TX)
+#define pUART1_START_ADDR_LO_TX ((volatile unsigned short *)UART1_START_ADDR_LO_TX)
+#define pUART1_COUNT_TX ((volatile unsigned short *)UART1_COUNT_TX)
+#define pUART1_NEXT_DESCR_TX ((volatile unsigned short *)UART1_NEXT_DESCR_TX)
+#define pUART1_DESCR_RDY_TX ((volatile unsigned short *)UART1_DESCR_RDY_TX)
+#define pUART1_IRQSTAT_TX ((volatile unsigned short *)UART1_IRQSTAT_TX)
+
+/* TIMER 0, 1, 2 Registers (0xFFC0 2000-0xFFC0 23FF) */
+#define pTIMER0_STATUS ((volatile unsigned short *)TIMER0_STATUS)
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER_LO ((volatile unsigned short *)TIMER0_COUNTER_LO)
+#define pTIMER0_COUNTER_HI ((volatile unsigned short *)TIMER0_COUNTER_HI)
+#define pTIMER0_PERIOD_LO ((volatile unsigned short *)TIMER0_PERIOD_LO)
+#define pTIMER0_PERIOD_HI ((volatile unsigned short *)TIMER0_PERIOD_HI)
+#define pTIMER0_WIDTH_LO ((volatile unsigned short *)TIMER0_WIDTH_LO)
+#define pTIMER0_WIDTH_HI ((volatile unsigned short *)TIMER0_WIDTH_HI)
+#define pTIMER1_STATUS ((volatile unsigned short *)TIMER1_STATUS)
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER_LO ((volatile unsigned short *)TIMER1_COUNTER_LO)
+#define pTIMER1_COUNTER_HI ((volatile unsigned short *)TIMER1_COUNTER_HI)
+#define pTIMER1_PERIOD_LO ((volatile unsigned short *)TIMER1_PERIOD_LO)
+#define pTIMER1_PERIOD_HI ((volatile unsigned short *)TIMER1_PERIOD_HI)
+#define pTIMER1_WIDTH_LO ((volatile unsigned short *)TIMER1_WIDTH_LO)
+#define pTIMER1_WIDTH_HI ((volatile unsigned short *)TIMER1_WIDTH_HI)
+#define pTIMER2_STATUS ((volatile unsigned short *)TIMER2_STATUS)
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER_LO ((volatile unsigned short *)TIMER2_COUNTER_LO)
+#define pTIMER2_COUNTER_HI ((volatile unsigned short *)TIMER2_COUNTER_HI)
+#define pTIMER2_PERIOD_LO ((volatile unsigned short *)TIMER2_PERIOD_LO)
+#define pTIMER2_PERIOD_HI ((volatile unsigned short *)TIMER2_PERIOD_HI)
+#define pTIMER2_WIDTH_LO ((volatile unsigned short *)TIMER2_WIDTH_LO)
+#define pTIMER2_WIDTH_HI ((volatile unsigned short *)TIMER2_WIDTH_HI)
+
+/* SPORT0 Controller (0xFFC0 2800-0xFFC0 2BFF) */
+#define pSPORT0_TX_CONFIG ((volatile unsigned short *)SPORT0_TX_CONFIG)
+#define pSPORT0_RX_CONFIG ((volatile unsigned short *)SPORT0_RX_CONFIG)
+#define pSPORT0_TX ((volatile short *)SPORT0_TX)
+#define pSPORT0_RX ((volatile short *)SPORT0_RX)
+#define pSPORT0_TSCLKDIV ((volatile unsigned short *)SPORT0_TSCLKDIV)
+#define pSPORT0_RSCLKDIV ((volatile unsigned short *)SPORT0_RSCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_MTCS0 ((volatile unsigned short *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned short *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned short *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned short *)SPORT0_MTCS3)
+#define pSPORT0_MTCS4 ((volatile unsigned short *)SPORT0_MTCS4)
+#define pSPORT0_MTCS5 ((volatile unsigned short *)SPORT0_MTCS5)
+#define pSPORT0_MTCS6 ((volatile unsigned short *)SPORT0_MTCS6)
+#define pSPORT0_MTCS7 ((volatile unsigned short *)SPORT0_MTCS7)
+#define pSPORT0_MRCS0 ((volatile unsigned short *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned short *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned short *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned short *)SPORT0_MRCS3)
+#define pSPORT0_MRCS4 ((volatile unsigned short *)SPORT0_MRCS4)
+#define pSPORT0_MRCS5 ((volatile unsigned short *)SPORT0_MRCS5)
+#define pSPORT0_MRCS6 ((volatile unsigned short *)SPORT0_MRCS6)
+#define pSPORT0_MRCS7 ((volatile unsigned short *)SPORT0_MRCS7)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_CURR_PTR_RX ((volatile unsigned short *)SPORT0_CURR_PTR_RX)
+#define pSPORT0_CONFIG_DMA_RX ((volatile unsigned short *)SPORT0_CONFIG_DMA_RX)
+#define pSPORT0_START_ADDR_HI_RX ((volatile unsigned short *)SPORT0_START_ADDR_HI_RX)
+#define pSPORT0_START_ADDR_LO_RX ((volatile unsigned short *)SPORT0_START_ADDR_LO_RX)
+#define pSPORT0_COUNT_RX ((volatile unsigned short *)SPORT0_COUNT_RX)
+#define pSPORT0_NEXT_DESCR_RX ((volatile unsigned short *)SPORT0_NEXT_DESCR_RX)
+#define pSPORT0_DESCR_RDY_RX ((volatile unsigned short *)SPORT0_DESCR_RDY_RX)
+#define pSPORT0_IRQSTAT_RX ((volatile unsigned short *)SPORT0_IRQSTAT_RX)
+#define pSPORT0_CURR_PTR_TX ((volatile unsigned short *)SPORT0_CURR_PTR_TX)
+#define pSPORT0_CONFIG_DMA_TX ((volatile unsigned short *)SPORT0_CONFIG_DMA_TX)
+#define pSPORT0_START_ADDR_HI_TX ((volatile unsigned short *)SPORT0_START_ADDR_HI_TX)
+#define pSPORT0_START_ADDR_LO_TX ((volatile unsigned short *)SPORT0_START_ADDR_LO_TX)
+#define pSPORT0_COUNT_TX ((volatile unsigned short *)SPORT0_COUNT_TX)
+#define pSPORT0_NEXT_DESCR_TX ((volatile unsigned short *)SPORT0_NEXT_DESCR_TX)
+#define pSPORT0_DESCR_RDY_TX ((volatile unsigned short *)SPORT0_DESCR_RDY_TX)
+#define pSPORT0_IRQSTAT_TX ((volatile unsigned short *)SPORT0_IRQSTAT_TX)
+
+/* SPORT1 Controller (0xFFC0 2C00-0xFFC0 2FFF) */
+#define pSPORT1_TX_CONFIG ((volatile unsigned short *)SPORT1_TX_CONFIG)
+#define pSPORT1_RX_CONFIG ((volatile unsigned short *)SPORT1_RX_CONFIG)
+#define pSPORT1_TX ((volatile short *)SPORT1_TX)
+#define pSPORT1_RX ((volatile short *)SPORT1_RX)
+#define pSPORT1_TSCLKDIV ((volatile unsigned short *)SPORT1_TSCLKDIV)
+#define pSPORT1_RSCLKDIV ((volatile unsigned short *)SPORT1_RSCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_MTCS0 ((volatile unsigned short *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned short *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned short *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned short *)SPORT1_MTCS3)
+#define pSPORT1_MTCS4 ((volatile unsigned short *)SPORT1_MTCS4)
+#define pSPORT1_MTCS5 ((volatile unsigned short *)SPORT1_MTCS5)
+#define pSPORT1_MTCS6 ((volatile unsigned short *)SPORT1_MTCS6)
+#define pSPORT1_MTCS7 ((volatile unsigned short *)SPORT1_MTCS7)
+#define pSPORT1_MRCS0 ((volatile unsigned short *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned short *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned short *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned short *)SPORT1_MRCS3)
+#define pSPORT1_MRCS4 ((volatile unsigned short *)SPORT1_MRCS4)
+#define pSPORT1_MRCS5 ((volatile unsigned short *)SPORT1_MRCS5)
+#define pSPORT1_MRCS6 ((volatile unsigned short *)SPORT1_MRCS6)
+#define pSPORT1_MRCS7 ((volatile unsigned short *)SPORT1_MRCS7)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_CURR_PTR_RX ((volatile unsigned short *)SPORT1_CURR_PTR_RX)
+#define pSPORT1_CONFIG_DMA_RX ((volatile unsigned short *)SPORT1_CONFIG_DMA_RX)
+#define pSPORT1_START_ADDR_HI_RX ((volatile unsigned short *)SPORT1_START_ADDR_HI_RX)
+#define pSPORT1_START_ADDR_LO_RX ((volatile unsigned short *)SPORT1_START_ADDR_LO_RX)
+#define pSPORT1_COUNT_RX ((volatile unsigned short *)SPORT1_COUNT_RX)
+#define pSPORT1_NEXT_DESCR_RX ((volatile unsigned short *)SPORT1_NEXT_DESCR_RX)
+#define pSPORT1_DESCR_RDY_RX ((volatile unsigned short *)SPORT1_DESCR_RDY_RX)
+#define pSPORT1_IRQSTAT_RX ((volatile unsigned short *)SPORT1_IRQSTAT_RX)
+#define pSPORT1_CURR_PTR_TX ((volatile unsigned short *)SPORT1_CURR_PTR_TX)
+#define pSPORT1_CONFIG_DMA_TX ((volatile unsigned short *)SPORT1_CONFIG_DMA_TX)
+#define pSPORT1_START_ADDR_HI_TX ((volatile unsigned short *)SPORT1_START_ADDR_HI_TX)
+#define pSPORT1_START_ADDR_LO_TX ((volatile unsigned short *)SPORT1_START_ADDR_LO_TX)
+#define pSPORT1_COUNT_TX ((volatile unsigned short *)SPORT1_COUNT_TX)
+#define pSPORT1_NEXT_DESCR_TX ((volatile unsigned short *)SPORT1_NEXT_DESCR_TX)
+#define pSPORT1_DESCR_RDY_TX ((volatile unsigned short *)SPORT1_DESCR_RDY_TX)
+#define pSPORT1_IRQSTAT_TX ((volatile unsigned short *)SPORT1_IRQSTAT_TX)
+
+/* SPI 0 Controller (0xFFC0 3000-0xFFC0 33FF) */
+#define pSPI0_CTL ((volatile unsigned short *)SPI0_CTL)
+#define pSPI0_FLG ((volatile unsigned short *)SPI0_FLG)
+#define pSPI0_ST ((volatile unsigned short *)SPI0_ST)
+#define pSPI0_TDBR ((volatile unsigned short *)SPI0_TDBR)
+#define pSPI0_RDBR ((volatile unsigned short *)SPI0_RDBR)
+#define pSPI0_BAUD ((volatile unsigned short *)SPI0_BAUD)
+#define pSPI0_SHADOW ((volatile unsigned short *)SPI0_SHADOW)
+#define pSPI0_CURR_PTR ((volatile unsigned short *)SPI0_CURR_PTR)
+#define pSPI0_CONFIG ((volatile unsigned short *)SPI0_CONFIG)
+#define pSPI0_START_ADDR_HI ((volatile unsigned short *)SPI0_START_ADDR_HI)
+#define pSPI0_START_ADDR_LO ((volatile unsigned short *)SPI0_START_ADDR_LO)
+#define pSPI0_COUNT ((volatile unsigned short *)SPI0_COUNT)
+#define pSPI0_NEXT_DESCR ((volatile unsigned short *)SPI0_NEXT_DESCR)
+#define pSPI0_DESCR_RDY ((volatile unsigned short *)SPI0_DESCR_RDY)
+#define pSPI0_DMA_INT ((volatile unsigned short *)SPI0_DMA_INT)
+
+/* SPI 1 Controller (0xFFC0 3400-0xFFC0 37FF) */
+#define pSPI1_CTL ((volatile unsigned short *)SPI1_CTL)
+#define pSPI1_FLG ((volatile unsigned short *)SPI1_FLG)
+#define pSPI1_ST ((volatile unsigned short *)SPI1_ST)
+#define pSPI1_TDBR ((volatile unsigned short *)SPI1_TDBR)
+#define pSPI1_RDBR ((volatile unsigned short *)SPI1_RDBR)
+#define pSPI1_BAUD ((volatile unsigned short *)SPI1_BAUD)
+#define pSPI1_SHADOW ((volatile unsigned short *)SPI1_SHADOW)
+#define pSPI1_CURR_PTR ((volatile unsigned short *)SPI1_CURR_PTR)
+#define pSPI1_CONFIG ((volatile unsigned short *)SPI1_CONFIG)
+#define pSPI1_START_ADDR_HI ((volatile unsigned short *)SPI1_START_ADDR_HI)
+#define pSPI1_START_ADDR_LO ((volatile unsigned short *)SPI1_START_ADDR_LO)
+#define pSPI1_COUNT ((volatile unsigned short *)SPI1_COUNT)
+#define pSPI1_NEXT_DESCR ((volatile unsigned short *)SPI1_NEXT_DESCR)
+#define pSPI1_DESCR_RDY ((volatile unsigned short *)SPI1_DESCR_RDY)
+#define pSPI1_DMA_INT ((volatile unsigned short *)SPI1_DMA_INT)
+
+/* Memory DMA Controller (0xFFC0 3800-0xFFC0 3BFF) */
+#define pMDD_DCP ((volatile unsigned short *)MDD_DCP)
+#define pMDD_DCFG ((volatile unsigned short *)MDD_DCFG)
+#define pMDD_DSAH ((volatile unsigned short *)MDD_DSAH)
+#define pMDD_DSAL ((volatile unsigned short *)MDD_DSAL)
+#define pMDD_DCT ((volatile unsigned short *)MDD_DCT)
+#define pMDD_DND ((volatile unsigned short *)MDD_DND)
+#define pMDD_DDR ((volatile unsigned short *)MDD_DDR)
+#define pMDD_DI ((volatile unsigned short *)MDD_DI)
+#define pMDS_DCP ((volatile unsigned short *)MDS_DCP)
+#define pMDS_DCFG ((volatile unsigned short *)MDS_DCFG)
+#define pMDS_DSAH ((volatile unsigned short *)MDS_DSAH)
+#define pMDS_DSAL ((volatile unsigned short *)MDS_DSAL)
+#define pMDS_DCT ((volatile unsigned short *)MDS_DCT)
+#define pMDS_DND ((volatile unsigned short *)MDS_DND)
+#define pMDS_DDR ((volatile unsigned short *)MDS_DDR)
+#define pMDS_DI ((volatile unsigned short *)MDS_DI)
+
+/* PCI Bridge PAB Registers (0xFFC0 4000-0xFFC0 43FF) */
+#define pPCI_CTL ((volatile unsigned short *)PCI_CTL)
+#define pPCI_STAT ((volatile unsigned long *)PCI_STAT)
+#define pPCI_ICTL ((volatile unsigned long *)PCI_ICTL)
+#define pPCI_MBAP (_PTR_TO_VOL_VOID_PTR PCI_MBAP)
+#define pPCI_IBAP (_PTR_TO_VOL_VOID_PTR PCI_IBAP)
+#define pPCI_CBAP (_PTR_TO_VOL_VOID_PTR PCI_CBAP)
+#define pPCI_TMBAP (_PTR_TO_VOL_VOID_PTR PCI_TMBAP)
+#define pPCI_TIBAP (_PTR_TO_VOL_VOID_PTR PCI_TIBAP)
+
+/* PCI Bridge External Access Bus Registers (0xEEFF FF00-0xEEFF FFFF) */
+#define pPCI_DMBARM ((volatile unsigned long *)PCI_DMBARM)
+#define pPCI_DIBARM ((volatile unsigned long *)PCI_DIBARM)
+#define pPCI_CFG_DIC ((volatile unsigned long *)PCI_CFG_DIC)
+#define pPCI_CFG_VIC ((volatile unsigned long *)PCI_CFG_VIC)
+#define pPCI_CFG_STAT ((volatile unsigned long *)PCI_CFG_STAT)
+#define pPCI_CFG_CMD ((volatile unsigned long *)PCI_CFG_CMD)
+#define pPCI_CFG_CC ((volatile unsigned long *)PCI_CFG_CC)
+#define pPCI_CFG_RID ((volatile unsigned long *)PCI_CFG_RID)
+#define pPCI_CFG_BIST ((volatile unsigned long *)PCI_CFG_BIST)
+#define pPCI_CFG_HT ((volatile unsigned long *)PCI_CFG_HT)
+#define pPCI_CFG_MLT ((volatile unsigned long *)PCI_CFG_MLT)
+#define pPCI_CFG_CLS ((volatile unsigned long *)PCI_CFG_CLS)
+#define pPCI_CFG_MBAR ((volatile unsigned long *)PCI_CFG_MBAR)
+#define pPCI_CFG_IBAR ((volatile unsigned long *)PCI_CFG_IBAR)
+#define pPCI_CFG_SID ((volatile unsigned long *)PCI_CFG_SID)
+#define pPCI_CFG_SVID ((volatile unsigned long *)PCI_CFG_SVID)
+#define pPCI_CFG_MAXL ((volatile unsigned long *)PCI_CFG_MAXL)
+#define pPCI_CFG_MING ((volatile unsigned long *)PCI_CFG_MING)
+#define pPCI_CFG_IP ((volatile unsigned long *)PCI_CFG_IP)
+#define pPCI_CFG_IL ((volatile unsigned long *)PCI_CFG_IL)
+#define pPCI_HMCTL ((volatile unsigned long *)PCI_HMCTL)
+
+/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
+#define pDMA_DBP ((volatile unsigned short *)DMA_DBP)
+#define pDB_ACOMP (_PTR_TO_VOL_VOID_PTR DB_ACOMP)
+#define pDB_CCOMP ((volatile unsigned long *)DB_CCOMP)
+
+#endif /* _CDEF_BF535_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access.
+**
+**/
+/**********************************************************************************
+** System MMR Register Map
+***********************************************************************************/
+
+#ifndef _CDEF_BF536_H
+#define _CDEF_BF536_H
+
+/* MMR Space Identical to BF537 Processor */
+#include <cdefBF537.h>
+
+#endif /* _CDEF_BF536_H */
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access.
+**
+**/
+
+/**********************************************************************************
+** System MMR Register Map
+***********************************************************************************/
+
+#ifndef _CDEF_BF537_H
+#define _CDEF_BF537_H
+
+/* Include MMRs Common to BF534 */
+#include <cdefBF534.h>
+
+/* Include all Core registers and bit definitions */
+#include <defBF537.h>
+
+/* Include Macro "Defines" For EMAC (Unique to BF536/BF537 */
+/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
+#define pEMAC_OPMODE ((volatile unsigned long *)EMAC_OPMODE)
+#define pEMAC_ADDRLO ((volatile unsigned long *)EMAC_ADDRLO)
+#define pEMAC_ADDRHI ((volatile unsigned long *)EMAC_ADDRHI)
+#define pEMAC_HASHLO ((volatile unsigned long *)EMAC_HASHLO)
+#define pEMAC_HASHHI ((volatile unsigned long *)EMAC_HASHHI)
+#define pEMAC_STAADD ((volatile unsigned long *)EMAC_STAADD)
+#define pEMAC_STADAT ((volatile unsigned long *)EMAC_STADAT)
+#define pEMAC_FLC ((volatile unsigned long *)EMAC_FLC)
+#define pEMAC_VLAN1 ((volatile unsigned long *)EMAC_VLAN1)
+#define pEMAC_VLAN2 ((volatile unsigned long *)EMAC_VLAN2)
+#define pEMAC_WKUP_CTL ((volatile unsigned long *)EMAC_WKUP_CTL)
+#define pEMAC_WKUP_FFMSK0 ((volatile unsigned long *)EMAC_WKUP_FFMSK0)
+#define pEMAC_WKUP_FFMSK1 ((volatile unsigned long *)EMAC_WKUP_FFMSK1)
+#define pEMAC_WKUP_FFMSK2 ((volatile unsigned long *)EMAC_WKUP_FFMSK2)
+#define pEMAC_WKUP_FFMSK3 ((volatile unsigned long *)EMAC_WKUP_FFMSK3)
+#define pEMAC_WKUP_FFCMD ((volatile unsigned long *)EMAC_WKUP_FFCMD)
+#define pEMAC_WKUP_FFOFF ((volatile unsigned long *)EMAC_WKUP_FFOFF)
+#define pEMAC_WKUP_FFCRC0 ((volatile unsigned long *)EMAC_WKUP_FFCRC0)
+#define pEMAC_WKUP_FFCRC1 ((volatile unsigned long *)EMAC_WKUP_FFCRC1)
+
+#define pEMAC_SYSCTL ((volatile unsigned long *)EMAC_SYSCTL)
+#define pEMAC_SYSTAT ((volatile unsigned long *)EMAC_SYSTAT)
+#define pEMAC_RX_STAT ((volatile unsigned long *)EMAC_RX_STAT)
+#define pEMAC_RX_STKY ((volatile unsigned long *)EMAC_RX_STKY)
+#define pEMAC_RX_IRQE ((volatile unsigned long *)EMAC_RX_IRQE)
+#define pEMAC_TX_STAT ((volatile unsigned long *)EMAC_TX_STAT)
+#define pEMAC_TX_STKY ((volatile unsigned long *)EMAC_TX_STKY)
+#define pEMAC_TX_IRQE ((volatile unsigned long *)EMAC_TX_IRQE)
+
+#define pEMAC_MMC_CTL ((volatile unsigned long *)EMAC_MMC_CTL)
+#define pEMAC_MMC_RIRQS ((volatile unsigned long *)EMAC_MMC_RIRQS)
+#define pEMAC_MMC_RIRQE ((volatile unsigned long *)EMAC_MMC_RIRQE)
+#define pEMAC_MMC_TIRQS ((volatile unsigned long *)EMAC_MMC_TIRQS)
+#define pEMAC_MMC_TIRQE ((volatile unsigned long *)EMAC_MMC_TIRQE)
+
+#define pEMAC_RXC_OK ((volatile unsigned long *)EMAC_RXC_OK)
+#define pEMAC_RXC_FCS ((volatile unsigned long *)EMAC_RXC_FCS)
+#define pEMAC_RXC_ALIGN ((volatile unsigned long *)EMAC_RXC_ALIGN)
+#define pEMAC_RXC_OCTET ((volatile unsigned long *)EMAC_RXC_OCTET)
+#define pEMAC_RXC_DMAOVF ((volatile unsigned long *)EMAC_RXC_DMAOVF)
+#define pEMAC_RXC_UNICST ((volatile unsigned long *)EMAC_RXC_UNICST)
+#define pEMAC_RXC_MULTI ((volatile unsigned long *)EMAC_RXC_MULTI)
+#define pEMAC_RXC_BROAD ((volatile unsigned long *)EMAC_RXC_BROAD)
+#define pEMAC_RXC_LNERRI ((volatile unsigned long *)EMAC_RXC_LNERRI)
+#define pEMAC_RXC_LNERRO ((volatile unsigned long *)EMAC_RXC_LNERRO)
+#define pEMAC_RXC_LONG ((volatile unsigned long *)EMAC_RXC_LONG)
+#define pEMAC_RXC_MACCTL ((volatile unsigned long *)EMAC_RXC_MACCTL)
+#define pEMAC_RXC_OPCODE ((volatile unsigned long *)EMAC_RXC_OPCODE)
+#define pEMAC_RXC_PAUSE ((volatile unsigned long *)EMAC_RXC_PAUSE)
+#define pEMAC_RXC_ALLFRM ((volatile unsigned long *)EMAC_RXC_ALLFRM)
+#define pEMAC_RXC_ALLOCT ((volatile unsigned long *)EMAC_RXC_ALLOCT)
+#define pEMAC_RXC_TYPED ((volatile unsigned long *)EMAC_RXC_TYPED)
+#define pEMAC_RXC_SHORT ((volatile unsigned long *)EMAC_RXC_SHORT)
+#define pEMAC_RXC_EQ64 ((volatile unsigned long *)EMAC_RXC_EQ64)
+#define pEMAC_RXC_LT128 ((volatile unsigned long *)EMAC_RXC_LT128)
+#define pEMAC_RXC_LT256 ((volatile unsigned long *)EMAC_RXC_LT256)
+#define pEMAC_RXC_LT512 ((volatile unsigned long *)EMAC_RXC_LT512)
+#define pEMAC_RXC_LT1024 ((volatile unsigned long *)EMAC_RXC_LT1024)
+#define pEMAC_RXC_GE1024 ((volatile unsigned long *)EMAC_RXC_GE1024)
+
+#define pEMAC_TXC_OK ((volatile unsigned long *)EMAC_TXC_OK)
+#define pEMAC_TXC_1COL ((volatile unsigned long *)EMAC_TXC_1COL)
+#define pEMAC_TXC_GT1COL ((volatile unsigned long *)EMAC_TXC_GT1COL)
+#define pEMAC_TXC_OCTET ((volatile unsigned long *)EMAC_TXC_OCTET)
+#define pEMAC_TXC_DEFER ((volatile unsigned long *)EMAC_TXC_DEFER)
+#define pEMAC_TXC_LATECL ((volatile unsigned long *)EMAC_TXC_LATECL)
+#define pEMAC_TXC_XS_COL ((volatile unsigned long *)EMAC_TXC_XS_COL)
+#define pEMAC_TXC_DMAUND ((volatile unsigned long *)EMAC_TXC_DMAUND)
+#define pEMAC_TXC_CRSERR ((volatile unsigned long *)EMAC_TXC_CRSERR)
+#define pEMAC_TXC_UNICST ((volatile unsigned long *)EMAC_TXC_UNICST)
+#define pEMAC_TXC_MULTI ((volatile unsigned long *)EMAC_TXC_MULTI)
+#define pEMAC_TXC_BROAD ((volatile unsigned long *)EMAC_TXC_BROAD)
+#define pEMAC_TXC_XS_DFR ((volatile unsigned long *)EMAC_TXC_XS_DFR)
+#define pEMAC_TXC_MACCTL ((volatile unsigned long *)EMAC_TXC_MACCTL)
+#define pEMAC_TXC_ALLFRM ((volatile unsigned long *)EMAC_TXC_ALLFRM)
+#define pEMAC_TXC_ALLOCT ((volatile unsigned long *)EMAC_TXC_ALLOCT)
+#define pEMAC_TXC_EQ64 ((volatile unsigned long *)EMAC_TXC_EQ64)
+#define pEMAC_TXC_LT128 ((volatile unsigned long *)EMAC_TXC_LT128)
+#define pEMAC_TXC_LT256 ((volatile unsigned long *)EMAC_TXC_LT256)
+#define pEMAC_TXC_LT512 ((volatile unsigned long *)EMAC_TXC_LT512)
+#define pEMAC_TXC_LT1024 ((volatile unsigned long *)EMAC_TXC_LT1024)
+#define pEMAC_TXC_GE1024 ((volatile unsigned long *)EMAC_TXC_GE1024)
+#define pEMAC_TXC_ABORT ((volatile unsigned long *)EMAC_TXC_ABORT)
+
+#endif /* _CDEF_BF537_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * cdefBF538.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF538 */
+
+#ifndef _CDEF_BF538_H
+#define _CDEF_BF538_H
+
+/* include all Core registers and bit definitions */
+#include <defBF538.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* include common system register pointer definitions from ADSP-BF532 */
+#include <cdefBF532.h>
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+/* ADSP-BF538 SIC0 is same as SIC on ADSP-BF532 */
+#define pSIC_IMASK0 pSIC_IMASK
+#define pSIC_ISR0 pSIC_ISR
+#define pSIC_IWR0 pSIC_IWR
+/* ADSP-BF538 SIC1 Registers */
+#define pSIC_IMASK1 ((volatile unsigned long *)SIC_IMASK1)
+#define pSIC_ISR1 ((volatile unsigned long *)SIC_ISR1)
+#define pSIC_IWR1 ((volatile unsigned long *)SIC_IWR1)
+#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
+#define pSIC_IAR4 ((volatile unsigned long *)SIC_IAR4)
+#define pSIC_IAR5 ((volatile unsigned long *)SIC_IAR5)
+#define pSIC_IAR6 ((volatile unsigned long *)SIC_IAR6)
+
+
+/* UART0 Controller */
+/* ADSP-BF538 UART0 is same as UART on ADSP-BF532 */
+#define pUART0_THR pUART_THR
+#define pUART0_RBR pUART_RBR
+#define pUART0_DLL pUART_DLL
+#define pUART0_IER pUART_IER
+#define pUART0_DLH pUART_DLH
+#define pUART0_IIR pUART_IIR
+#define pUART0_LCR pUART_LCR
+#define pUART0_MCR pUART_MCR
+#define pUART0_LSR pUART_LSR
+#define pUART0_SCR pUART_SCR
+#define pUART0_GCTL pUART_GCTL
+
+
+/* SPI0 Controller */
+/* ADSP-BF538 SPI0 is same as SPI on ADSP-BF532 */
+#define pSPI0_CTL pSPI_CTL
+#define pSPI0_FLG pSPI_FLG
+#define pSPI0_STAT pSPI_STAT
+#define pSPI0_TDBR pSPI_TDBR
+#define pSPI0_RDBR pSPI_RDBR
+#define pSPI0_BAUD pSPI_BAUD
+#define pSPI0_SHADOW pSPI_SHADOW
+
+
+/* General-Purpose Input/Output Ports (GPIO) */
+/* ADSP-BF538 Refers to FIO as GPIO Port F */
+#define pPORTFIO pFIO_FLAG_D
+#define pPORTFIO_CLEAR pFIO_FLAG_C
+#define pPORTFIO_SET pFIO_FLAG_S
+#define pPORTFIO_TOGGLE pFIO_FLAG_T
+#define pPORTFIO_MASKA pFIO_MASKA_D
+#define pPORTFIO_MASKA_CLEAR pFIO_MASKA_C
+#define pPORTFIO_MASKA_SET pFIO_MASKA_S
+#define pPORTFIO_MASKA_TOGGLE pFIO_MASKA_T
+#define pPORTFIO_MASKB pFIO_MASKB_D
+#define pPORTFIO_MASKB_CLEAR pFIO_MASKB_C
+#define pPORTFIO_MASKB_SET pFIO_MASKB_S
+#define pPORTFIO_MASKB_TOGGLE pFIO_MASKB_T
+#define pPORTFIO_DIR pFIO_DIR
+#define pPORTFIO_POLAR pFIO_POLAR
+#define pPORTFIO_EDGE pFIO_EDGE
+#define pPORTFIO_BOTH pFIO_BOTH
+#define pPORTFIO_INEN pFIO_INEN
+
+
+/* DMA0 Traffic Control Registers */
+/* ADSP-BF538 DMA0 Controller is same as DMA Controller on ADSP-BF532 */
+#define pDMAC0_TC_PER pDMA_TC_PER
+#define pDMAC0_TC_CNT pDMA_TC_CNT
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define pDMA0_TC_PER pDMAC0_TC_PER
+#define pDMA0_TC_CNT pDMAC0_TC_CNT
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define pDMA0_TCPER pDMA0_TC_PER /* Traffic Control Periods Register */
+#define pDMA0_TCCNT pDMA0_TC_CNT /* Traffic Control Current Counts Register */
+
+/* Must Enumerate MemDMA Controllers As Well */
+#define pMDMA0_D0_NEXT_DESC_PTR pMDMA_D0_NEXT_DESC_PTR
+#define pMDMA0_D0_START_ADDR pMDMA_D0_START_ADDR
+#define pMDMA0_D0_CONFIG pMDMA_D0_CONFIG
+#define pMDMA0_D0_X_COUNT pMDMA_D0_X_COUNT
+#define pMDMA0_D0_X_MODIFY pMDMA_D0_X_MODIFY
+#define pMDMA0_D0_Y_COUNT pMDMA_D0_Y_COUNT
+#define pMDMA0_D0_Y_MODIFY pMDMA_D0_Y_MODIFY
+#define pMDMA0_D0_CURR_DESC_PTR pMDMA_D0_CURR_DESC_PTR
+#define pMDMA0_D0_CURR_ADDR pMDMA_D0_CURR_ADDR
+#define pMDMA0_D0_IRQ_STATUS pMDMA_D0_IRQ_STATUS
+#define pMDMA0_D0_PERIPHERAL_MAP pMDMA_D0_PERIPHERAL_MAP
+#define pMDMA0_D0_CURR_X_COUNT pMDMA_D0_CURR_X_COUNT
+#define pMDMA0_D0_CURR_Y_COUNT pMDMA_D0_CURR_Y_COUNT
+
+#define pMDMA0_S0_NEXT_DESC_PTR pMDMA_S0_NEXT_DESC_PTR
+#define pMDMA0_S0_START_ADDR pMDMA_S0_START_ADDR
+#define pMDMA0_S0_CONFIG pMDMA_S0_CONFIG
+#define pMDMA0_S0_X_COUNT pMDMA_S0_X_COUNT
+#define pMDMA0_S0_X_MODIFY pMDMA_S0_X_MODIFY
+#define pMDMA0_S0_Y_COUNT pMDMA_S0_Y_COUNT
+#define pMDMA0_S0_Y_MODIFY pMDMA_S0_Y_MODIFY
+#define pMDMA0_S0_CURR_DESC_PTR pMDMA_S0_CURR_DESC_PTR
+#define pMDMA0_S0_CURR_ADDR pMDMA_S0_CURR_ADDR
+#define pMDMA0_S0_IRQ_STATUS pMDMA_S0_IRQ_STATUS
+#define pMDMA0_S0_PERIPHERAL_MAP pMDMA_S0_PERIPHERAL_MAP
+#define pMDMA0_S0_CURR_X_COUNT pMDMA_S0_CURR_X_COUNT
+#define pMDMA0_S0_CURR_Y_COUNT pMDMA_S0_CURR_Y_COUNT
+
+#define pMDMA0_D1_NEXT_DESC_PTR pMDMA_D1_NEXT_DESC_PTR
+#define pMDMA0_D1_START_ADDR pMDMA_D1_START_ADDR
+#define pMDMA0_D1_CONFIG pMDMA_D1_CONFIG
+#define pMDMA0_D1_X_COUNT pMDMA_D1_X_COUNT
+#define pMDMA0_D1_X_MODIFY pMDMA_D1_X_MODIFY
+#define pMDMA0_D1_Y_COUNT pMDMA_D1_Y_COUNT
+#define pMDMA0_D1_Y_MODIFY pMDMA_D1_Y_MODIFY
+#define pMDMA0_D1_CURR_DESC_PTR pMDMA_D1_CURR_DESC_PTR
+#define pMDMA0_D1_CURR_ADDR pMDMA_D1_CURR_ADDR
+#define pMDMA0_D1_IRQ_STATUS pMDMA_D1_IRQ_STATUS
+#define pMDMA0_D1_PERIPHERAL_MAP pMDMA_D1_PERIPHERAL_MAP
+#define pMDMA0_D1_CURR_X_COUNT pMDMA_D1_CURR_X_COUNT
+#define pMDMA0_D1_CURR_Y_COUNT pMDMA_D1_CURR_Y_COUNT
+
+#define pMDMA0_S1_NEXT_DESC_PTR pMDMA_S1_NEXT_DESC_PTR
+#define pMDMA0_S1_START_ADDR pMDMA_S1_START_ADDR
+#define pMDMA0_S1_CONFIG pMDMA_S1_CONFIG
+#define pMDMA0_S1_X_COUNT pMDMA_S1_X_COUNT
+#define pMDMA0_S1_X_MODIFY pMDMA_S1_X_MODIFY
+#define pMDMA0_S1_Y_COUNT pMDMA_S1_Y_COUNT
+#define pMDMA0_S1_Y_MODIFY pMDMA_S1_Y_MODIFY
+#define pMDMA0_S1_CURR_DESC_PTR pMDMA_S1_CURR_DESC_PTR
+#define pMDMA0_S1_CURR_ADDR pMDMA_S1_CURR_ADDR
+#define pMDMA0_S1_IRQ_STATUS pMDMA_S1_IRQ_STATUS
+#define pMDMA0_S1_PERIPHERAL_MAP pMDMA_S1_PERIPHERAL_MAP
+#define pMDMA0_S1_CURR_X_COUNT pMDMA_S1_CURR_X_COUNT
+#define pMDMA0_S1_CURR_Y_COUNT pMDMA_S1_CURR_Y_COUNT
+
+
+/* Two-Wire Interface 0 */
+#define pTWI0_CLKDIV ((volatile unsigned short *)TWI0_CLKDIV)
+#define pTWI0_CONTROL ((volatile unsigned short *)TWI0_CONTROL)
+#define pTWI0_SLAVE_CTRL ((volatile unsigned short *)TWI0_SLAVE_CTRL)
+#define pTWI0_SLAVE_STAT ((volatile unsigned short *)TWI0_SLAVE_STAT)
+#define pTWI0_SLAVE_ADDR ((volatile unsigned short *)TWI0_SLAVE_ADDR)
+#define pTWI0_MASTER_CTRL ((volatile unsigned short *)TWI0_MASTER_CTRL)
+#define pTWI0_MASTER_STAT ((volatile unsigned short *)TWI0_MASTER_STAT)
+#define pTWI0_MASTER_ADDR ((volatile unsigned short *)TWI0_MASTER_ADDR)
+#define pTWI0_INT_STAT ((volatile unsigned short *)TWI0_INT_STAT)
+#define pTWI0_INT_MASK ((volatile unsigned short *)TWI0_INT_MASK)
+#define pTWI0_FIFO_CTRL ((volatile unsigned short *)TWI0_FIFO_CTRL)
+#define pTWI0_FIFO_STAT ((volatile unsigned short *)TWI0_FIFO_STAT)
+#define pTWI0_XMT_DATA8 ((volatile unsigned short *)TWI0_XMT_DATA8)
+#define pTWI0_XMT_DATA16 ((volatile unsigned short *)TWI0_XMT_DATA16)
+#define pTWI0_RCV_DATA8 ((volatile unsigned short *)TWI0_RCV_DATA8)
+#define pTWI0_RCV_DATA16 ((volatile unsigned short *)TWI0_RCV_DATA16)
+
+
+/* General Purpose IO Ports C, D, and E */
+#define pPORTCIO_FER ((volatile unsigned short *)PORTCIO_FER)
+#define pPORTCIO ((volatile unsigned short *)PORTCIO)
+#define pPORTCIO_CLEAR ((volatile unsigned short *)PORTCIO_CLEAR)
+#define pPORTCIO_SET ((volatile unsigned short *)PORTCIO_SET)
+#define pPORTCIO_TOGGLE ((volatile unsigned short *)PORTCIO_TOGGLE)
+#define pPORTCIO_DIR ((volatile unsigned short *)PORTCIO_DIR)
+#define pPORTCIO_INEN ((volatile unsigned short *)PORTCIO_INEN)
+
+#define pPORTDIO_FER ((volatile unsigned short *)PORTDIO_FER)
+#define pPORTDIO ((volatile unsigned short *)PORTDIO)
+#define pPORTDIO_CLEAR ((volatile unsigned short *)PORTDIO_CLEAR)
+#define pPORTDIO_SET ((volatile unsigned short *)PORTDIO_SET)
+#define pPORTDIO_TOGGLE ((volatile unsigned short *)PORTDIO_TOGGLE)
+#define pPORTDIO_DIR ((volatile unsigned short *)PORTDIO_DIR)
+#define pPORTDIO_INEN ((volatile unsigned short *)PORTDIO_INEN)
+
+#define pPORTEIO_FER ((volatile unsigned short *)PORTEIO_FER)
+#define pPORTEIO ((volatile unsigned short *)PORTEIO)
+#define pPORTEIO_CLEAR ((volatile unsigned short *)PORTEIO_CLEAR)
+#define pPORTEIO_SET ((volatile unsigned short *)PORTEIO_SET)
+#define pPORTEIO_TOGGLE ((volatile unsigned short *)PORTEIO_TOGGLE)
+#define pPORTEIO_DIR ((volatile unsigned short *)PORTEIO_DIR)
+#define pPORTEIO_INEN ((volatile unsigned short *)PORTEIO_INEN)
+
+
+/* DMA1 Traffic Control Registers */
+#define pDMAC1_TC_PER ((volatile unsigned short *)DMAC1_TC_PER)
+#define pDMAC1_TC_CNT ((volatile unsigned short *)DMAC1_TC_CNT)
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define pDMA1_TC_PER pDMAC1_TC_PER /* Traffic Control Periods Register */
+#define pDMA1_TC_CNT pDMAC1_TC_CNT /* Traffic Control Current Counts Register */
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define pDMA1_TCPER pDMA1_TC_PER /* Traffic Control Periods Register */
+#define pDMA1_TCCNT pDMA1_TC_CNT /* Traffic Control Current Counts Register */
+
+/* DMA Controller 1 */
+#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR)
+#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR)
+#define pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG)
+#define pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT)
+#define pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY)
+#define pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT)
+#define pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY)
+#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR)
+#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR)
+#define pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS)
+#define pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
+#define pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT)
+#define pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT)
+
+#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR)
+#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR)
+#define pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG)
+#define pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT)
+#define pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY)
+#define pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT)
+#define pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY)
+#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR)
+#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR)
+#define pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS)
+#define pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
+#define pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT)
+#define pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT)
+
+#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR)
+#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR)
+#define pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG)
+#define pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT)
+#define pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY)
+#define pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT)
+#define pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY)
+#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR)
+#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR)
+#define pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS)
+#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
+#define pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT)
+#define pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT)
+
+#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR)
+#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR)
+#define pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG)
+#define pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT)
+#define pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY)
+#define pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT)
+#define pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY)
+#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR)
+#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR)
+#define pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS)
+#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
+#define pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT)
+#define pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT)
+
+#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR)
+#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR)
+#define pDMA12_CONFIG ((volatile unsigned short *)DMA12_CONFIG)
+#define pDMA12_X_COUNT ((volatile unsigned short *)DMA12_X_COUNT)
+#define pDMA12_X_MODIFY ((volatile signed short *)DMA12_X_MODIFY)
+#define pDMA12_Y_COUNT ((volatile unsigned short *)DMA12_Y_COUNT)
+#define pDMA12_Y_MODIFY ((volatile signed short *)DMA12_Y_MODIFY)
+#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR)
+#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR)
+#define pDMA12_IRQ_STATUS ((volatile unsigned short *)DMA12_IRQ_STATUS)
+#define pDMA12_PERIPHERAL_MAP ((volatile unsigned short *)DMA12_PERIPHERAL_MAP)
+#define pDMA12_CURR_X_COUNT ((volatile unsigned short *)DMA12_CURR_X_COUNT)
+#define pDMA12_CURR_Y_COUNT ((volatile unsigned short *)DMA12_CURR_Y_COUNT)
+
+#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR)
+#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR)
+#define pDMA13_CONFIG ((volatile unsigned short *)DMA13_CONFIG)
+#define pDMA13_X_COUNT ((volatile unsigned short *)DMA13_X_COUNT)
+#define pDMA13_X_MODIFY ((volatile signed short *)DMA13_X_MODIFY)
+#define pDMA13_Y_COUNT ((volatile unsigned short *)DMA13_Y_COUNT)
+#define pDMA13_Y_MODIFY ((volatile signed short *)DMA13_Y_MODIFY)
+#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR)
+#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR)
+#define pDMA13_IRQ_STATUS ((volatile unsigned short *)DMA13_IRQ_STATUS)
+#define pDMA13_PERIPHERAL_MAP ((volatile unsigned short *)DMA13_PERIPHERAL_MAP)
+#define pDMA13_CURR_X_COUNT ((volatile unsigned short *)DMA13_CURR_X_COUNT)
+#define pDMA13_CURR_Y_COUNT ((volatile unsigned short *)DMA13_CURR_Y_COUNT)
+
+#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR)
+#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR)
+#define pDMA14_CONFIG ((volatile unsigned short *)DMA14_CONFIG)
+#define pDMA14_X_COUNT ((volatile unsigned short *)DMA14_X_COUNT)
+#define pDMA14_X_MODIFY ((volatile signed short *)DMA14_X_MODIFY)
+#define pDMA14_Y_COUNT ((volatile unsigned short *)DMA14_Y_COUNT)
+#define pDMA14_Y_MODIFY ((volatile signed short *)DMA14_Y_MODIFY)
+#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR)
+#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR)
+#define pDMA14_IRQ_STATUS ((volatile unsigned short *)DMA14_IRQ_STATUS)
+#define pDMA14_PERIPHERAL_MAP ((volatile unsigned short *)DMA14_PERIPHERAL_MAP)
+#define pDMA14_CURR_X_COUNT ((volatile unsigned short *)DMA14_CURR_X_COUNT)
+#define pDMA14_CURR_Y_COUNT ((volatile unsigned short *)DMA14_CURR_Y_COUNT)
+
+#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR)
+#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR)
+#define pDMA15_CONFIG ((volatile unsigned short *)DMA15_CONFIG)
+#define pDMA15_X_COUNT ((volatile unsigned short *)DMA15_X_COUNT)
+#define pDMA15_X_MODIFY ((volatile signed short *)DMA15_X_MODIFY)
+#define pDMA15_Y_COUNT ((volatile unsigned short *)DMA15_Y_COUNT)
+#define pDMA15_Y_MODIFY ((volatile signed short *)DMA15_Y_MODIFY)
+#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR)
+#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR)
+#define pDMA15_IRQ_STATUS ((volatile unsigned short *)DMA15_IRQ_STATUS)
+#define pDMA15_PERIPHERAL_MAP ((volatile unsigned short *)DMA15_PERIPHERAL_MAP)
+#define pDMA15_CURR_X_COUNT ((volatile unsigned short *)DMA15_CURR_X_COUNT)
+#define pDMA15_CURR_Y_COUNT ((volatile unsigned short *)DMA15_CURR_Y_COUNT)
+
+#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR)
+#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR)
+#define pDMA16_CONFIG ((volatile unsigned short *)DMA16_CONFIG)
+#define pDMA16_X_COUNT ((volatile unsigned short *)DMA16_X_COUNT)
+#define pDMA16_X_MODIFY ((volatile signed short *)DMA16_X_MODIFY)
+#define pDMA16_Y_COUNT ((volatile unsigned short *)DMA16_Y_COUNT)
+#define pDMA16_Y_MODIFY ((volatile signed short *)DMA16_Y_MODIFY)
+#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR)
+#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR)
+#define pDMA16_IRQ_STATUS ((volatile unsigned short *)DMA16_IRQ_STATUS)
+#define pDMA16_PERIPHERAL_MAP ((volatile unsigned short *)DMA16_PERIPHERAL_MAP)
+#define pDMA16_CURR_X_COUNT ((volatile unsigned short *)DMA16_CURR_X_COUNT)
+#define pDMA16_CURR_Y_COUNT ((volatile unsigned short *)DMA16_CURR_Y_COUNT)
+
+#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR)
+#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR)
+#define pDMA17_CONFIG ((volatile unsigned short *)DMA17_CONFIG)
+#define pDMA17_X_COUNT ((volatile unsigned short *)DMA17_X_COUNT)
+#define pDMA17_X_MODIFY ((volatile signed short *)DMA17_X_MODIFY)
+#define pDMA17_Y_COUNT ((volatile unsigned short *)DMA17_Y_COUNT)
+#define pDMA17_Y_MODIFY ((volatile signed short *)DMA17_Y_MODIFY)
+#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR)
+#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR)
+#define pDMA17_IRQ_STATUS ((volatile unsigned short *)DMA17_IRQ_STATUS)
+#define pDMA17_PERIPHERAL_MAP ((volatile unsigned short *)DMA17_PERIPHERAL_MAP)
+#define pDMA17_CURR_X_COUNT ((volatile unsigned short *)DMA17_CURR_X_COUNT)
+#define pDMA17_CURR_Y_COUNT ((volatile unsigned short *)DMA17_CURR_Y_COUNT)
+
+#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR)
+#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR)
+#define pDMA18_CONFIG ((volatile unsigned short *)DMA18_CONFIG)
+#define pDMA18_X_COUNT ((volatile unsigned short *)DMA18_X_COUNT)
+#define pDMA18_X_MODIFY ((volatile signed short *)DMA18_X_MODIFY)
+#define pDMA18_Y_COUNT ((volatile unsigned short *)DMA18_Y_COUNT)
+#define pDMA18_Y_MODIFY ((volatile signed short *)DMA18_Y_MODIFY)
+#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR)
+#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR)
+#define pDMA18_IRQ_STATUS ((volatile unsigned short *)DMA18_IRQ_STATUS)
+#define pDMA18_PERIPHERAL_MAP ((volatile unsigned short *)DMA18_PERIPHERAL_MAP)
+#define pDMA18_CURR_X_COUNT ((volatile unsigned short *)DMA18_CURR_X_COUNT)
+#define pDMA18_CURR_Y_COUNT ((volatile unsigned short *)DMA18_CURR_Y_COUNT)
+
+#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR)
+#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR)
+#define pDMA19_CONFIG ((volatile unsigned short *)DMA19_CONFIG)
+#define pDMA19_X_COUNT ((volatile unsigned short *)DMA19_X_COUNT)
+#define pDMA19_X_MODIFY ((volatile signed short *)DMA19_X_MODIFY)
+#define pDMA19_Y_COUNT ((volatile unsigned short *)DMA19_Y_COUNT)
+#define pDMA19_Y_MODIFY ((volatile signed short *)DMA19_Y_MODIFY)
+#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR)
+#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR)
+#define pDMA19_IRQ_STATUS ((volatile unsigned short *)DMA19_IRQ_STATUS)
+#define pDMA19_PERIPHERAL_MAP ((volatile unsigned short *)DMA19_PERIPHERAL_MAP)
+#define pDMA19_CURR_X_COUNT ((volatile unsigned short *)DMA19_CURR_X_COUNT)
+#define pDMA19_CURR_Y_COUNT ((volatile unsigned short *)DMA19_CURR_Y_COUNT)
+
+#define pMDMA1_D0_NEXT_DESC_PTR ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR)
+#define pMDMA1_D0_START_ADDR ((void * volatile *)MDMA1_D0_START_ADDR)
+#define pMDMA1_D0_CONFIG ((volatile unsigned short *)MDMA1_D0_CONFIG)
+#define pMDMA1_D0_X_COUNT ((volatile unsigned short *)MDMA1_D0_X_COUNT)
+#define pMDMA1_D0_X_MODIFY ((volatile signed short *)MDMA1_D0_X_MODIFY)
+#define pMDMA1_D0_Y_COUNT ((volatile unsigned short *)MDMA1_D0_Y_COUNT)
+#define pMDMA1_D0_Y_MODIFY ((volatile signed short *)MDMA1_D0_Y_MODIFY)
+#define pMDMA1_D0_CURR_DESC_PTR ((void * volatile *)MDMA1_D0_CURR_DESC_PTR)
+#define pMDMA1_D0_CURR_ADDR ((void * volatile *)MDMA1_D0_CURR_ADDR)
+#define pMDMA1_D0_IRQ_STATUS ((volatile unsigned short *)MDMA1_D0_IRQ_STATUS)
+#define pMDMA1_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP)
+#define pMDMA1_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA1_D0_CURR_X_COUNT)
+#define pMDMA1_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT)
+
+#define pMDMA1_S0_NEXT_DESC_PTR ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR)
+#define pMDMA1_S0_START_ADDR ((void * volatile *)MDMA1_S0_START_ADDR)
+#define pMDMA1_S0_CONFIG ((volatile unsigned short *)MDMA1_S0_CONFIG)
+#define pMDMA1_S0_X_COUNT ((volatile unsigned short *)MDMA1_S0_X_COUNT)
+#define pMDMA1_S0_X_MODIFY ((volatile signed short *)MDMA1_S0_X_MODIFY)
+#define pMDMA1_S0_Y_COUNT ((volatile unsigned short *)MDMA1_S0_Y_COUNT)
+#define pMDMA1_S0_Y_MODIFY ((volatile signed short *)MDMA1_S0_Y_MODIFY)
+#define pMDMA1_S0_CURR_DESC_PTR ((void * volatile *)MDMA1_S0_CURR_DESC_PTR)
+#define pMDMA1_S0_CURR_ADDR ((void * volatile *)MDMA1_S0_CURR_ADDR)
+#define pMDMA1_S0_IRQ_STATUS ((volatile unsigned short *)MDMA1_S0_IRQ_STATUS)
+#define pMDMA1_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP)
+#define pMDMA1_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA1_S0_CURR_X_COUNT)
+#define pMDMA1_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT)
+
+#define pMDMA1_D1_NEXT_DESC_PTR ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR)
+#define pMDMA1_D1_START_ADDR ((void * volatile *)MDMA1_D1_START_ADDR)
+#define pMDMA1_D1_CONFIG ((volatile unsigned short *)MDMA1_D1_CONFIG)
+#define pMDMA1_D1_X_COUNT ((volatile unsigned short *)MDMA1_D1_X_COUNT)
+#define pMDMA1_D1_X_MODIFY ((volatile signed short *)MDMA1_D1_X_MODIFY)
+#define pMDMA1_D1_Y_COUNT ((volatile unsigned short *)MDMA1_D1_Y_COUNT)
+#define pMDMA1_D1_Y_MODIFY ((volatile signed short *)MDMA1_D1_Y_MODIFY)
+#define pMDMA1_D1_CURR_DESC_PTR ((void * volatile *)MDMA1_D1_CURR_DESC_PTR)
+#define pMDMA1_D1_CURR_ADDR ((void * volatile *)MDMA1_D1_CURR_ADDR)
+#define pMDMA1_D1_IRQ_STATUS ((volatile unsigned short *)MDMA1_D1_IRQ_STATUS)
+#define pMDMA1_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP)
+#define pMDMA1_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA1_D1_CURR_X_COUNT)
+#define pMDMA1_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT)
+
+#define pMDMA1_S1_NEXT_DESC_PTR ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR)
+#define pMDMA1_S1_START_ADDR ((void * volatile *)MDMA1_S1_START_ADDR)
+#define pMDMA1_S1_CONFIG ((volatile unsigned short *)MDMA1_S1_CONFIG)
+#define pMDMA1_S1_X_COUNT ((volatile unsigned short *)MDMA1_S1_X_COUNT)
+#define pMDMA1_S1_X_MODIFY ((volatile signed short *)MDMA1_S1_X_MODIFY)
+#define pMDMA1_S1_Y_COUNT ((volatile unsigned short *)MDMA1_S1_Y_COUNT)
+#define pMDMA1_S1_Y_MODIFY ((volatile signed short *)MDMA1_S1_Y_MODIFY)
+#define pMDMA1_S1_CURR_DESC_PTR ((void * volatile *)MDMA1_S1_CURR_DESC_PTR)
+#define pMDMA1_S1_CURR_ADDR ((void * volatile *)MDMA1_S1_CURR_ADDR)
+#define pMDMA1_S1_IRQ_STATUS ((volatile unsigned short *)MDMA1_S1_IRQ_STATUS)
+#define pMDMA1_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP)
+#define pMDMA1_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA1_S1_CURR_X_COUNT)
+#define pMDMA1_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT)
+
+
+/* UART1 Controller */
+#define pUART1_THR ((volatile unsigned short *)UART1_THR)
+#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
+#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
+#define pUART1_IER ((volatile unsigned short *)UART1_IER)
+#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
+#define pUART1_IIR ((volatile unsigned short *)UART1_IIR)
+#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
+#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
+#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
+#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)
+
+
+/* UART2 Controller */
+#define pUART2_THR ((volatile unsigned short *)UART2_THR)
+#define pUART2_RBR ((volatile unsigned short *)UART2_RBR)
+#define pUART2_DLL ((volatile unsigned short *)UART2_DLL)
+#define pUART2_IER ((volatile unsigned short *)UART2_IER)
+#define pUART2_DLH ((volatile unsigned short *)UART2_DLH)
+#define pUART2_IIR ((volatile unsigned short *)UART2_IIR)
+#define pUART2_LCR ((volatile unsigned short *)UART2_LCR)
+#define pUART2_MCR ((volatile unsigned short *)UART2_MCR)
+#define pUART2_LSR ((volatile unsigned short *)UART2_LSR)
+#define pUART2_SCR ((volatile unsigned short *)UART2_SCR)
+#define pUART2_GCTL ((volatile unsigned short *)UART2_GCTL)
+
+
+/* Two-Wire Interface 1 */
+#define pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
+#define pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
+#define pTWI1_SLAVE_CTRL ((volatile unsigned short *)TWI1_SLAVE_CTRL)
+#define pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
+#define pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
+#define pTWI1_MASTER_CTRL ((volatile unsigned short *)TWI1_MASTER_CTRL)
+#define pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
+#define pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
+#define pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
+#define pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
+#define pTWI1_FIFO_CTRL ((volatile unsigned short *)TWI1_FIFO_CTRL)
+#define pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
+#define pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
+#define pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
+#define pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
+#define pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
+
+
+/* SPI1 Controller */
+#define pSPI1_CTL ((volatile unsigned short *)SPI1_CTL)
+#define pSPI1_FLG ((volatile unsigned short *)SPI1_FLG)
+#define pSPI1_STAT ((volatile unsigned short *)SPI1_STAT)
+#define pSPI1_TDBR ((volatile unsigned short *)SPI1_TDBR)
+#define pSPI1_RDBR ((volatile unsigned short *)SPI1_RDBR)
+#define pSPI1_BAUD ((volatile unsigned short *)SPI1_BAUD)
+#define pSPI1_SHADOW ((volatile unsigned short *)SPI1_SHADOW)
+
+
+/* SPI2 Controller */
+#define pSPI2_CTL ((volatile unsigned short *)SPI2_CTL)
+#define pSPI2_FLG ((volatile unsigned short *)SPI2_FLG)
+#define pSPI2_STAT ((volatile unsigned short *)SPI2_STAT)
+#define pSPI2_TDBR ((volatile unsigned short *)SPI2_TDBR)
+#define pSPI2_RDBR ((volatile unsigned short *)SPI2_RDBR)
+#define pSPI2_BAUD ((volatile unsigned short *)SPI2_BAUD)
+#define pSPI2_SHADOW ((volatile unsigned short *)SPI2_SHADOW)
+
+
+/* SPORT2 Controller */
+#define pSPORT2_TCR1 ((volatile unsigned short *)SPORT2_TCR1)
+#define pSPORT2_TCR2 ((volatile unsigned short *)SPORT2_TCR2)
+#define pSPORT2_TCLKDIV ((volatile unsigned short *)SPORT2_TCLKDIV)
+#define pSPORT2_TFSDIV ((volatile unsigned short *)SPORT2_TFSDIV)
+#define pSPORT2_TX ((volatile unsigned long *)SPORT2_TX)
+#define pSPORT2_RX ((volatile unsigned long *)SPORT2_RX)
+#define pSPORT2_TX32 ((volatile unsigned long *)SPORT2_TX)
+#define pSPORT2_RX32 ((volatile unsigned long *)SPORT2_RX)
+#define pSPORT2_TX16 ((volatile unsigned short *)SPORT2_TX)
+#define pSPORT2_RX16 ((volatile unsigned short *)SPORT2_RX)
+#define pSPORT2_RCR1 ((volatile unsigned short *)SPORT2_RCR1)
+#define pSPORT2_RCR2 ((volatile unsigned short *)SPORT2_RCR2)
+#define pSPORT2_RCLKDIV ((volatile unsigned short *)SPORT2_RCLKDIV)
+#define pSPORT2_RFSDIV ((volatile unsigned short *)SPORT2_RFSDIV)
+#define pSPORT2_STAT ((volatile unsigned short *)SPORT2_STAT)
+#define pSPORT2_CHNL ((volatile unsigned short *)SPORT2_CHNL)
+#define pSPORT2_MCMC1 ((volatile unsigned short *)SPORT2_MCMC1)
+#define pSPORT2_MCMC2 ((volatile unsigned short *)SPORT2_MCMC2)
+#define pSPORT2_MTCS0 ((volatile unsigned long *)SPORT2_MTCS0)
+#define pSPORT2_MTCS1 ((volatile unsigned long *)SPORT2_MTCS1)
+#define pSPORT2_MTCS2 ((volatile unsigned long *)SPORT2_MTCS2)
+#define pSPORT2_MTCS3 ((volatile unsigned long *)SPORT2_MTCS3)
+#define pSPORT2_MRCS0 ((volatile unsigned long *)SPORT2_MRCS0)
+#define pSPORT2_MRCS1 ((volatile unsigned long *)SPORT2_MRCS1)
+#define pSPORT2_MRCS2 ((volatile unsigned long *)SPORT2_MRCS2)
+#define pSPORT2_MRCS3 ((volatile unsigned long *)SPORT2_MRCS3)
+
+
+/* SPORT3 Controller */
+#define pSPORT3_TCR1 ((volatile unsigned short *)SPORT3_TCR1)
+#define pSPORT3_TCR2 ((volatile unsigned short *)SPORT3_TCR2)
+#define pSPORT3_TCLKDIV ((volatile unsigned short *)SPORT3_TCLKDIV)
+#define pSPORT3_TFSDIV ((volatile unsigned short *)SPORT3_TFSDIV)
+#define pSPORT3_TX ((volatile unsigned long *)SPORT3_TX)
+#define pSPORT3_RX ((volatile unsigned long *)SPORT3_RX)
+#define pSPORT3_TX32 ((volatile unsigned long *)SPORT3_TX)
+#define pSPORT3_RX32 ((volatile unsigned long *)SPORT3_RX)
+#define pSPORT3_TX16 ((volatile unsigned short *)SPORT3_TX)
+#define pSPORT3_RX16 ((volatile unsigned short *)SPORT3_RX)
+#define pSPORT3_RCR1 ((volatile unsigned short *)SPORT3_RCR1)
+#define pSPORT3_RCR2 ((volatile unsigned short *)SPORT3_RCR2)
+#define pSPORT3_RCLKDIV ((volatile unsigned short *)SPORT3_RCLKDIV)
+#define pSPORT3_RFSDIV ((volatile unsigned short *)SPORT3_RFSDIV)
+#define pSPORT3_STAT ((volatile unsigned short *)SPORT3_STAT)
+#define pSPORT3_CHNL ((volatile unsigned short *)SPORT3_CHNL)
+#define pSPORT3_MCMC1 ((volatile unsigned short *)SPORT3_MCMC1)
+#define pSPORT3_MCMC2 ((volatile unsigned short *)SPORT3_MCMC2)
+#define pSPORT3_MTCS0 ((volatile unsigned long *)SPORT3_MTCS0)
+#define pSPORT3_MTCS1 ((volatile unsigned long *)SPORT3_MTCS1)
+#define pSPORT3_MTCS2 ((volatile unsigned long *)SPORT3_MTCS2)
+#define pSPORT3_MTCS3 ((volatile unsigned long *)SPORT3_MTCS3)
+#define pSPORT3_MRCS0 ((volatile unsigned long *)SPORT3_MRCS0)
+#define pSPORT3_MRCS1 ((volatile unsigned long *)SPORT3_MRCS1)
+#define pSPORT3_MRCS2 ((volatile unsigned long *)SPORT3_MRCS2)
+#define pSPORT3_MRCS3 ((volatile unsigned long *)SPORT3_MRCS3)
+
+
+/* CAN Controller */
+/* For Mailboxes 0-15 */
+#define pCAN_MC1 ((volatile unsigned short *)CAN_MC1)
+#define pCAN_MD1 ((volatile unsigned short *)CAN_MD1)
+#define pCAN_TRS1 ((volatile unsigned short *)CAN_TRS1)
+#define pCAN_TRR1 ((volatile unsigned short *)CAN_TRR1)
+#define pCAN_TA1 ((volatile unsigned short *)CAN_TA1)
+#define pCAN_AA1 ((volatile unsigned short *)CAN_AA1)
+#define pCAN_RMP1 ((volatile unsigned short *)CAN_RMP1)
+#define pCAN_RML1 ((volatile unsigned short *)CAN_RML1)
+#define pCAN_MBTIF1 ((volatile unsigned short *)CAN_MBTIF1)
+#define pCAN_MBRIF1 ((volatile unsigned short *)CAN_MBRIF1)
+#define pCAN_MBIM1 ((volatile unsigned short *)CAN_MBIM1)
+#define pCAN_RFH1 ((volatile unsigned short *)CAN_RFH1)
+#define pCAN_OPSS1 ((volatile unsigned short *)CAN_OPSS1)
+
+/* For Mailboxes 16-31 */
+#define pCAN_MC2 ((volatile unsigned short *)CAN_MC2)
+#define pCAN_MD2 ((volatile unsigned short *)CAN_MD2)
+#define pCAN_TRS2 ((volatile unsigned short *)CAN_TRS2)
+#define pCAN_TRR2 ((volatile unsigned short *)CAN_TRR2)
+#define pCAN_TA2 ((volatile unsigned short *)CAN_TA2)
+#define pCAN_AA2 ((volatile unsigned short *)CAN_AA2)
+#define pCAN_RMP2 ((volatile unsigned short *)CAN_RMP2)
+#define pCAN_RML2 ((volatile unsigned short *)CAN_RML2)
+#define pCAN_MBTIF2 ((volatile unsigned short *)CAN_MBTIF2)
+#define pCAN_MBRIF2 ((volatile unsigned short *)CAN_MBRIF2)
+#define pCAN_MBIM2 ((volatile unsigned short *)CAN_MBIM2)
+#define pCAN_RFH2 ((volatile unsigned short *)CAN_RFH2)
+#define pCAN_OPSS2 ((volatile unsigned short *)CAN_OPSS2)
+
+#define pCAN_CLOCK ((volatile unsigned short *)CAN_CLOCK)
+#define pCAN_TIMING ((volatile unsigned short *)CAN_TIMING)
+#define pCAN_DEBUG ((volatile unsigned short *)CAN_DEBUG)
+#define pCAN_STATUS ((volatile unsigned short *)CAN_STATUS)
+#define pCAN_CEC ((volatile unsigned short *)CAN_CEC)
+#define pCAN_GIS ((volatile unsigned short *)CAN_GIS)
+#define pCAN_GIM ((volatile unsigned short *)CAN_GIM)
+#define pCAN_GIF ((volatile unsigned short *)CAN_GIF)
+#define pCAN_CONTROL ((volatile unsigned short *)CAN_CONTROL)
+#define pCAN_INTR ((volatile unsigned short *)CAN_INTR)
+#define pCAN_MBTD ((volatile unsigned short *)CAN_MBTD)
+#define pCAN_EWR ((volatile unsigned short *)CAN_EWR)
+#define pCAN_ESR ((volatile unsigned short *)CAN_ESR)
+#define pCAN_UCREG ((volatile unsigned short *)CAN_UCREG)
+#define pCAN_UCCNT ((volatile unsigned short *)CAN_UCCNT)
+#define pCAN_UCRC ((volatile unsigned short *)CAN_UCRC)
+#define pCAN_UCCNF ((volatile unsigned short *)CAN_UCCNF)
+
+/* Mailbox Acceptance Masks */
+#define pCAN_AM00L ((volatile unsigned short *)CAN_AM00L)
+#define pCAN_AM00H ((volatile unsigned short *)CAN_AM00H)
+#define pCAN_AM01L ((volatile unsigned short *)CAN_AM01L)
+#define pCAN_AM01H ((volatile unsigned short *)CAN_AM01H)
+#define pCAN_AM02L ((volatile unsigned short *)CAN_AM02L)
+#define pCAN_AM02H ((volatile unsigned short *)CAN_AM02H)
+#define pCAN_AM03L ((volatile unsigned short *)CAN_AM03L)
+#define pCAN_AM03H ((volatile unsigned short *)CAN_AM03H)
+#define pCAN_AM04L ((volatile unsigned short *)CAN_AM04L)
+#define pCAN_AM04H ((volatile unsigned short *)CAN_AM04H)
+#define pCAN_AM05L ((volatile unsigned short *)CAN_AM05L)
+#define pCAN_AM05H ((volatile unsigned short *)CAN_AM05H)
+#define pCAN_AM06L ((volatile unsigned short *)CAN_AM06L)
+#define pCAN_AM06H ((volatile unsigned short *)CAN_AM06H)
+#define pCAN_AM07L ((volatile unsigned short *)CAN_AM07L)
+#define pCAN_AM07H ((volatile unsigned short *)CAN_AM07H)
+#define pCAN_AM08L ((volatile unsigned short *)CAN_AM08L)
+#define pCAN_AM08H ((volatile unsigned short *)CAN_AM08H)
+#define pCAN_AM09L ((volatile unsigned short *)CAN_AM09L)
+#define pCAN_AM09H ((volatile unsigned short *)CAN_AM09H)
+#define pCAN_AM10L ((volatile unsigned short *)CAN_AM10L)
+#define pCAN_AM10H ((volatile unsigned short *)CAN_AM10H)
+#define pCAN_AM11L ((volatile unsigned short *)CAN_AM11L)
+#define pCAN_AM11H ((volatile unsigned short *)CAN_AM11H)
+#define pCAN_AM12L ((volatile unsigned short *)CAN_AM12L)
+#define pCAN_AM12H ((volatile unsigned short *)CAN_AM12H)
+#define pCAN_AM13L ((volatile unsigned short *)CAN_AM13L)
+#define pCAN_AM13H ((volatile unsigned short *)CAN_AM13H)
+#define pCAN_AM14L ((volatile unsigned short *)CAN_AM14L)
+#define pCAN_AM14H ((volatile unsigned short *)CAN_AM14H)
+#define pCAN_AM15L ((volatile unsigned short *)CAN_AM15L)
+#define pCAN_AM15H ((volatile unsigned short *)CAN_AM15H)
+
+#define pCAN_AM16L ((volatile unsigned short *)CAN_AM16L)
+#define pCAN_AM16H ((volatile unsigned short *)CAN_AM16H)
+#define pCAN_AM17L ((volatile unsigned short *)CAN_AM17L)
+#define pCAN_AM17H ((volatile unsigned short *)CAN_AM17H)
+#define pCAN_AM18L ((volatile unsigned short *)CAN_AM18L)
+#define pCAN_AM18H ((volatile unsigned short *)CAN_AM18H)
+#define pCAN_AM19L ((volatile unsigned short *)CAN_AM19L)
+#define pCAN_AM19H ((volatile unsigned short *)CAN_AM19H)
+#define pCAN_AM20L ((volatile unsigned short *)CAN_AM20L)
+#define pCAN_AM20H ((volatile unsigned short *)CAN_AM20H)
+#define pCAN_AM21L ((volatile unsigned short *)CAN_AM21L)
+#define pCAN_AM21H ((volatile unsigned short *)CAN_AM21H)
+#define pCAN_AM22L ((volatile unsigned short *)CAN_AM22L)
+#define pCAN_AM22H ((volatile unsigned short *)CAN_AM22H)
+#define pCAN_AM23L ((volatile unsigned short *)CAN_AM23L)
+#define pCAN_AM23H ((volatile unsigned short *)CAN_AM23H)
+#define pCAN_AM24L ((volatile unsigned short *)CAN_AM24L)
+#define pCAN_AM24H ((volatile unsigned short *)CAN_AM24H)
+#define pCAN_AM25L ((volatile unsigned short *)CAN_AM25L)
+#define pCAN_AM25H ((volatile unsigned short *)CAN_AM25H)
+#define pCAN_AM26L ((volatile unsigned short *)CAN_AM26L)
+#define pCAN_AM26H ((volatile unsigned short *)CAN_AM26H)
+#define pCAN_AM27L ((volatile unsigned short *)CAN_AM27L)
+#define pCAN_AM27H ((volatile unsigned short *)CAN_AM27H)
+#define pCAN_AM28L ((volatile unsigned short *)CAN_AM28L)
+#define pCAN_AM28H ((volatile unsigned short *)CAN_AM28H)
+#define pCAN_AM29L ((volatile unsigned short *)CAN_AM29L)
+#define pCAN_AM29H ((volatile unsigned short *)CAN_AM29H)
+#define pCAN_AM30L ((volatile unsigned short *)CAN_AM30L)
+#define pCAN_AM30H ((volatile unsigned short *)CAN_AM30H)
+#define pCAN_AM31L ((volatile unsigned short *)CAN_AM31L)
+#define pCAN_AM31H ((volatile unsigned short *)CAN_AM31H)
+
+/* CAN Acceptance Mask Area Macros */
+#define pCAN_AM_L(x) ((volatile unsigned short *)CAN_AM_L(x))
+#define pCAN_AM_H(x) ((volatile unsigned short *)CAN_AM_H(x))
+
+/* Mailbox Registers */
+#define pCAN_MB00_DATA0 ((volatile unsigned short *)CAN_MB00_DATA0)
+#define pCAN_MB00_DATA1 ((volatile unsigned short *)CAN_MB00_DATA1)
+#define pCAN_MB00_DATA2 ((volatile unsigned short *)CAN_MB00_DATA2)
+#define pCAN_MB00_DATA3 ((volatile unsigned short *)CAN_MB00_DATA3)
+#define pCAN_MB00_LENGTH ((volatile unsigned short *)CAN_MB00_LENGTH)
+#define pCAN_MB00_TIMESTAMP ((volatile unsigned short *)CAN_MB00_TIMESTAMP)
+#define pCAN_MB00_ID0 ((volatile unsigned short *)CAN_MB00_ID0)
+#define pCAN_MB00_ID1 ((volatile unsigned short *)CAN_MB00_ID1)
+
+#define pCAN_MB01_DATA0 ((volatile unsigned short *)CAN_MB01_DATA0)
+#define pCAN_MB01_DATA1 ((volatile unsigned short *)CAN_MB01_DATA1)
+#define pCAN_MB01_DATA2 ((volatile unsigned short *)CAN_MB01_DATA2)
+#define pCAN_MB01_DATA3 ((volatile unsigned short *)CAN_MB01_DATA3)
+#define pCAN_MB01_LENGTH ((volatile unsigned short *)CAN_MB01_LENGTH)
+#define pCAN_MB01_TIMESTAMP ((volatile unsigned short *)CAN_MB01_TIMESTAMP)
+#define pCAN_MB01_ID0 ((volatile unsigned short *)CAN_MB01_ID0)
+#define pCAN_MB01_ID1 ((volatile unsigned short *)CAN_MB01_ID1)
+
+#define pCAN_MB02_DATA0 ((volatile unsigned short *)CAN_MB02_DATA0)
+#define pCAN_MB02_DATA1 ((volatile unsigned short *)CAN_MB02_DATA1)
+#define pCAN_MB02_DATA2 ((volatile unsigned short *)CAN_MB02_DATA2)
+#define pCAN_MB02_DATA3 ((volatile unsigned short *)CAN_MB02_DATA3)
+#define pCAN_MB02_LENGTH ((volatile unsigned short *)CAN_MB02_LENGTH)
+#define pCAN_MB02_TIMESTAMP ((volatile unsigned short *)CAN_MB02_TIMESTAMP)
+#define pCAN_MB02_ID0 ((volatile unsigned short *)CAN_MB02_ID0)
+#define pCAN_MB02_ID1 ((volatile unsigned short *)CAN_MB02_ID1)
+
+#define pCAN_MB03_DATA0 ((volatile unsigned short *)CAN_MB03_DATA0)
+#define pCAN_MB03_DATA1 ((volatile unsigned short *)CAN_MB03_DATA1)
+#define pCAN_MB03_DATA2 ((volatile unsigned short *)CAN_MB03_DATA2)
+#define pCAN_MB03_DATA3 ((volatile unsigned short *)CAN_MB03_DATA3)
+#define pCAN_MB03_LENGTH ((volatile unsigned short *)CAN_MB03_LENGTH)
+#define pCAN_MB03_TIMESTAMP ((volatile unsigned short *)CAN_MB03_TIMESTAMP)
+#define pCAN_MB03_ID0 ((volatile unsigned short *)CAN_MB03_ID0)
+#define pCAN_MB03_ID1 ((volatile unsigned short *)CAN_MB03_ID1)
+
+#define pCAN_MB04_DATA0 ((volatile unsigned short *)CAN_MB04_DATA0)
+#define pCAN_MB04_DATA1 ((volatile unsigned short *)CAN_MB04_DATA1)
+#define pCAN_MB04_DATA2 ((volatile unsigned short *)CAN_MB04_DATA2)
+#define pCAN_MB04_DATA3 ((volatile unsigned short *)CAN_MB04_DATA3)
+#define pCAN_MB04_LENGTH ((volatile unsigned short *)CAN_MB04_LENGTH)
+#define pCAN_MB04_TIMESTAMP ((volatile unsigned short *)CAN_MB04_TIMESTAMP)
+#define pCAN_MB04_ID0 ((volatile unsigned short *)CAN_MB04_ID0)
+#define pCAN_MB04_ID1 ((volatile unsigned short *)CAN_MB04_ID1)
+
+#define pCAN_MB05_DATA0 ((volatile unsigned short *)CAN_MB05_DATA0)
+#define pCAN_MB05_DATA1 ((volatile unsigned short *)CAN_MB05_DATA1)
+#define pCAN_MB05_DATA2 ((volatile unsigned short *)CAN_MB05_DATA2)
+#define pCAN_MB05_DATA3 ((volatile unsigned short *)CAN_MB05_DATA3)
+#define pCAN_MB05_LENGTH ((volatile unsigned short *)CAN_MB05_LENGTH)
+#define pCAN_MB05_TIMESTAMP ((volatile unsigned short *)CAN_MB05_TIMESTAMP)
+#define pCAN_MB05_ID0 ((volatile unsigned short *)CAN_MB05_ID0)
+#define pCAN_MB05_ID1 ((volatile unsigned short *)CAN_MB05_ID1)
+
+#define pCAN_MB06_DATA0 ((volatile unsigned short *)CAN_MB06_DATA0)
+#define pCAN_MB06_DATA1 ((volatile unsigned short *)CAN_MB06_DATA1)
+#define pCAN_MB06_DATA2 ((volatile unsigned short *)CAN_MB06_DATA2)
+#define pCAN_MB06_DATA3 ((volatile unsigned short *)CAN_MB06_DATA3)
+#define pCAN_MB06_LENGTH ((volatile unsigned short *)CAN_MB06_LENGTH)
+#define pCAN_MB06_TIMESTAMP ((volatile unsigned short *)CAN_MB06_TIMESTAMP)
+#define pCAN_MB06_ID0 ((volatile unsigned short *)CAN_MB06_ID0)
+#define pCAN_MB06_ID1 ((volatile unsigned short *)CAN_MB06_ID1)
+
+#define pCAN_MB07_DATA0 ((volatile unsigned short *)CAN_MB07_DATA0)
+#define pCAN_MB07_DATA1 ((volatile unsigned short *)CAN_MB07_DATA1)
+#define pCAN_MB07_DATA2 ((volatile unsigned short *)CAN_MB07_DATA2)
+#define pCAN_MB07_DATA3 ((volatile unsigned short *)CAN_MB07_DATA3)
+#define pCAN_MB07_LENGTH ((volatile unsigned short *)CAN_MB07_LENGTH)
+#define pCAN_MB07_TIMESTAMP ((volatile unsigned short *)CAN_MB07_TIMESTAMP)
+#define pCAN_MB07_ID0 ((volatile unsigned short *)CAN_MB07_ID0)
+#define pCAN_MB07_ID1 ((volatile unsigned short *)CAN_MB07_ID1)
+
+#define pCAN_MB08_DATA0 ((volatile unsigned short *)CAN_MB08_DATA0)
+#define pCAN_MB08_DATA1 ((volatile unsigned short *)CAN_MB08_DATA1)
+#define pCAN_MB08_DATA2 ((volatile unsigned short *)CAN_MB08_DATA2)
+#define pCAN_MB08_DATA3 ((volatile unsigned short *)CAN_MB08_DATA3)
+#define pCAN_MB08_LENGTH ((volatile unsigned short *)CAN_MB08_LENGTH)
+#define pCAN_MB08_TIMESTAMP ((volatile unsigned short *)CAN_MB08_TIMESTAMP)
+#define pCAN_MB08_ID0 ((volatile unsigned short *)CAN_MB08_ID0)
+#define pCAN_MB08_ID1 ((volatile unsigned short *)CAN_MB08_ID1)
+
+#define pCAN_MB09_DATA0 ((volatile unsigned short *)CAN_MB09_DATA0)
+#define pCAN_MB09_DATA1 ((volatile unsigned short *)CAN_MB09_DATA1)
+#define pCAN_MB09_DATA2 ((volatile unsigned short *)CAN_MB09_DATA2)
+#define pCAN_MB09_DATA3 ((volatile unsigned short *)CAN_MB09_DATA3)
+#define pCAN_MB09_LENGTH ((volatile unsigned short *)CAN_MB09_LENGTH)
+#define pCAN_MB09_TIMESTAMP ((volatile unsigned short *)CAN_MB09_TIMESTAMP)
+#define pCAN_MB09_ID0 ((volatile unsigned short *)CAN_MB09_ID0)
+#define pCAN_MB09_ID1 ((volatile unsigned short *)CAN_MB09_ID1)
+
+#define pCAN_MB10_DATA0 ((volatile unsigned short *)CAN_MB10_DATA0)
+#define pCAN_MB10_DATA1 ((volatile unsigned short *)CAN_MB10_DATA1)
+#define pCAN_MB10_DATA2 ((volatile unsigned short *)CAN_MB10_DATA2)
+#define pCAN_MB10_DATA3 ((volatile unsigned short *)CAN_MB10_DATA3)
+#define pCAN_MB10_LENGTH ((volatile unsigned short *)CAN_MB10_LENGTH)
+#define pCAN_MB10_TIMESTAMP ((volatile unsigned short *)CAN_MB10_TIMESTAMP)
+#define pCAN_MB10_ID0 ((volatile unsigned short *)CAN_MB10_ID0)
+#define pCAN_MB10_ID1 ((volatile unsigned short *)CAN_MB10_ID1)
+
+#define pCAN_MB11_DATA0 ((volatile unsigned short *)CAN_MB11_DATA0)
+#define pCAN_MB11_DATA1 ((volatile unsigned short *)CAN_MB11_DATA1)
+#define pCAN_MB11_DATA2 ((volatile unsigned short *)CAN_MB11_DATA2)
+#define pCAN_MB11_DATA3 ((volatile unsigned short *)CAN_MB11_DATA3)
+#define pCAN_MB11_LENGTH ((volatile unsigned short *)CAN_MB11_LENGTH)
+#define pCAN_MB11_TIMESTAMP ((volatile unsigned short *)CAN_MB11_TIMESTAMP)
+#define pCAN_MB11_ID0 ((volatile unsigned short *)CAN_MB11_ID0)
+#define pCAN_MB11_ID1 ((volatile unsigned short *)CAN_MB11_ID1)
+
+#define pCAN_MB12_DATA0 ((volatile unsigned short *)CAN_MB12_DATA0)
+#define pCAN_MB12_DATA1 ((volatile unsigned short *)CAN_MB12_DATA1)
+#define pCAN_MB12_DATA2 ((volatile unsigned short *)CAN_MB12_DATA2)
+#define pCAN_MB12_DATA3 ((volatile unsigned short *)CAN_MB12_DATA3)
+#define pCAN_MB12_LENGTH ((volatile unsigned short *)CAN_MB12_LENGTH)
+#define pCAN_MB12_TIMESTAMP ((volatile unsigned short *)CAN_MB12_TIMESTAMP)
+#define pCAN_MB12_ID0 ((volatile unsigned short *)CAN_MB12_ID0)
+#define pCAN_MB12_ID1 ((volatile unsigned short *)CAN_MB12_ID1)
+
+#define pCAN_MB13_DATA0 ((volatile unsigned short *)CAN_MB13_DATA0)
+#define pCAN_MB13_DATA1 ((volatile unsigned short *)CAN_MB13_DATA1)
+#define pCAN_MB13_DATA2 ((volatile unsigned short *)CAN_MB13_DATA2)
+#define pCAN_MB13_DATA3 ((volatile unsigned short *)CAN_MB13_DATA3)
+#define pCAN_MB13_LENGTH ((volatile unsigned short *)CAN_MB13_LENGTH)
+#define pCAN_MB13_TIMESTAMP ((volatile unsigned short *)CAN_MB13_TIMESTAMP)
+#define pCAN_MB13_ID0 ((volatile unsigned short *)CAN_MB13_ID0)
+#define pCAN_MB13_ID1 ((volatile unsigned short *)CAN_MB13_ID1)
+
+#define pCAN_MB14_DATA0 ((volatile unsigned short *)CAN_MB14_DATA0)
+#define pCAN_MB14_DATA1 ((volatile unsigned short *)CAN_MB14_DATA1)
+#define pCAN_MB14_DATA2 ((volatile unsigned short *)CAN_MB14_DATA2)
+#define pCAN_MB14_DATA3 ((volatile unsigned short *)CAN_MB14_DATA3)
+#define pCAN_MB14_LENGTH ((volatile unsigned short *)CAN_MB14_LENGTH)
+#define pCAN_MB14_TIMESTAMP ((volatile unsigned short *)CAN_MB14_TIMESTAMP)
+#define pCAN_MB14_ID0 ((volatile unsigned short *)CAN_MB14_ID0)
+#define pCAN_MB14_ID1 ((volatile unsigned short *)CAN_MB14_ID1)
+
+#define pCAN_MB15_DATA0 ((volatile unsigned short *)CAN_MB15_DATA0)
+#define pCAN_MB15_DATA1 ((volatile unsigned short *)CAN_MB15_DATA1)
+#define pCAN_MB15_DATA2 ((volatile unsigned short *)CAN_MB15_DATA2)
+#define pCAN_MB15_DATA3 ((volatile unsigned short *)CAN_MB15_DATA3)
+#define pCAN_MB15_LENGTH ((volatile unsigned short *)CAN_MB15_LENGTH)
+#define pCAN_MB15_TIMESTAMP ((volatile unsigned short *)CAN_MB15_TIMESTAMP)
+#define pCAN_MB15_ID0 ((volatile unsigned short *)CAN_MB15_ID0)
+#define pCAN_MB15_ID1 ((volatile unsigned short *)CAN_MB15_ID1)
+
+#define pCAN_MB16_DATA0 ((volatile unsigned short *)CAN_MB16_DATA0)
+#define pCAN_MB16_DATA1 ((volatile unsigned short *)CAN_MB16_DATA1)
+#define pCAN_MB16_DATA2 ((volatile unsigned short *)CAN_MB16_DATA2)
+#define pCAN_MB16_DATA3 ((volatile unsigned short *)CAN_MB16_DATA3)
+#define pCAN_MB16_LENGTH ((volatile unsigned short *)CAN_MB16_LENGTH)
+#define pCAN_MB16_TIMESTAMP ((volatile unsigned short *)CAN_MB16_TIMESTAMP)
+#define pCAN_MB16_ID0 ((volatile unsigned short *)CAN_MB16_ID0)
+#define pCAN_MB16_ID1 ((volatile unsigned short *)CAN_MB16_ID1)
+
+#define pCAN_MB17_DATA0 ((volatile unsigned short *)CAN_MB17_DATA0)
+#define pCAN_MB17_DATA1 ((volatile unsigned short *)CAN_MB17_DATA1)
+#define pCAN_MB17_DATA2 ((volatile unsigned short *)CAN_MB17_DATA2)
+#define pCAN_MB17_DATA3 ((volatile unsigned short *)CAN_MB17_DATA3)
+#define pCAN_MB17_LENGTH ((volatile unsigned short *)CAN_MB17_LENGTH)
+#define pCAN_MB17_TIMESTAMP ((volatile unsigned short *)CAN_MB17_TIMESTAMP)
+#define pCAN_MB17_ID0 ((volatile unsigned short *)CAN_MB17_ID0)
+#define pCAN_MB17_ID1 ((volatile unsigned short *)CAN_MB17_ID1)
+
+#define pCAN_MB18_DATA0 ((volatile unsigned short *)CAN_MB18_DATA0)
+#define pCAN_MB18_DATA1 ((volatile unsigned short *)CAN_MB18_DATA1)
+#define pCAN_MB18_DATA2 ((volatile unsigned short *)CAN_MB18_DATA2)
+#define pCAN_MB18_DATA3 ((volatile unsigned short *)CAN_MB18_DATA3)
+#define pCAN_MB18_LENGTH ((volatile unsigned short *)CAN_MB18_LENGTH)
+#define pCAN_MB18_TIMESTAMP ((volatile unsigned short *)CAN_MB18_TIMESTAMP)
+#define pCAN_MB18_ID0 ((volatile unsigned short *)CAN_MB18_ID0)
+#define pCAN_MB18_ID1 ((volatile unsigned short *)CAN_MB18_ID1)
+
+#define pCAN_MB19_DATA0 ((volatile unsigned short *)CAN_MB19_DATA0)
+#define pCAN_MB19_DATA1 ((volatile unsigned short *)CAN_MB19_DATA1)
+#define pCAN_MB19_DATA2 ((volatile unsigned short *)CAN_MB19_DATA2)
+#define pCAN_MB19_DATA3 ((volatile unsigned short *)CAN_MB19_DATA3)
+#define pCAN_MB19_LENGTH ((volatile unsigned short *)CAN_MB19_LENGTH)
+#define pCAN_MB19_TIMESTAMP ((volatile unsigned short *)CAN_MB19_TIMESTAMP)
+#define pCAN_MB19_ID0 ((volatile unsigned short *)CAN_MB19_ID0)
+#define pCAN_MB19_ID1 ((volatile unsigned short *)CAN_MB19_ID1)
+
+#define pCAN_MB20_DATA0 ((volatile unsigned short *)CAN_MB20_DATA0)
+#define pCAN_MB20_DATA1 ((volatile unsigned short *)CAN_MB20_DATA1)
+#define pCAN_MB20_DATA2 ((volatile unsigned short *)CAN_MB20_DATA2)
+#define pCAN_MB20_DATA3 ((volatile unsigned short *)CAN_MB20_DATA3)
+#define pCAN_MB20_LENGTH ((volatile unsigned short *)CAN_MB20_LENGTH)
+#define pCAN_MB20_TIMESTAMP ((volatile unsigned short *)CAN_MB20_TIMESTAMP)
+#define pCAN_MB20_ID0 ((volatile unsigned short *)CAN_MB20_ID0)
+#define pCAN_MB20_ID1 ((volatile unsigned short *)CAN_MB20_ID1)
+
+#define pCAN_MB21_DATA0 ((volatile unsigned short *)CAN_MB21_DATA0)
+#define pCAN_MB21_DATA1 ((volatile unsigned short *)CAN_MB21_DATA1)
+#define pCAN_MB21_DATA2 ((volatile unsigned short *)CAN_MB21_DATA2)
+#define pCAN_MB21_DATA3 ((volatile unsigned short *)CAN_MB21_DATA3)
+#define pCAN_MB21_LENGTH ((volatile unsigned short *)CAN_MB21_LENGTH)
+#define pCAN_MB21_TIMESTAMP ((volatile unsigned short *)CAN_MB21_TIMESTAMP)
+#define pCAN_MB21_ID0 ((volatile unsigned short *)CAN_MB21_ID0)
+#define pCAN_MB21_ID1 ((volatile unsigned short *)CAN_MB21_ID1)
+
+#define pCAN_MB22_DATA0 ((volatile unsigned short *)CAN_MB22_DATA0)
+#define pCAN_MB22_DATA1 ((volatile unsigned short *)CAN_MB22_DATA1)
+#define pCAN_MB22_DATA2 ((volatile unsigned short *)CAN_MB22_DATA2)
+#define pCAN_MB22_DATA3 ((volatile unsigned short *)CAN_MB22_DATA3)
+#define pCAN_MB22_LENGTH ((volatile unsigned short *)CAN_MB22_LENGTH)
+#define pCAN_MB22_TIMESTAMP ((volatile unsigned short *)CAN_MB22_TIMESTAMP)
+#define pCAN_MB22_ID0 ((volatile unsigned short *)CAN_MB22_ID0)
+#define pCAN_MB22_ID1 ((volatile unsigned short *)CAN_MB22_ID1)
+
+#define pCAN_MB23_DATA0 ((volatile unsigned short *)CAN_MB23_DATA0)
+#define pCAN_MB23_DATA1 ((volatile unsigned short *)CAN_MB23_DATA1)
+#define pCAN_MB23_DATA2 ((volatile unsigned short *)CAN_MB23_DATA2)
+#define pCAN_MB23_DATA3 ((volatile unsigned short *)CAN_MB23_DATA3)
+#define pCAN_MB23_LENGTH ((volatile unsigned short *)CAN_MB23_LENGTH)
+#define pCAN_MB23_TIMESTAMP ((volatile unsigned short *)CAN_MB23_TIMESTAMP)
+#define pCAN_MB23_ID0 ((volatile unsigned short *)CAN_MB23_ID0)
+#define pCAN_MB23_ID1 ((volatile unsigned short *)CAN_MB23_ID1)
+
+#define pCAN_MB24_DATA0 ((volatile unsigned short *)CAN_MB24_DATA0)
+#define pCAN_MB24_DATA1 ((volatile unsigned short *)CAN_MB24_DATA1)
+#define pCAN_MB24_DATA2 ((volatile unsigned short *)CAN_MB24_DATA2)
+#define pCAN_MB24_DATA3 ((volatile unsigned short *)CAN_MB24_DATA3)
+#define pCAN_MB24_LENGTH ((volatile unsigned short *)CAN_MB24_LENGTH)
+#define pCAN_MB24_TIMESTAMP ((volatile unsigned short *)CAN_MB24_TIMESTAMP)
+#define pCAN_MB24_ID0 ((volatile unsigned short *)CAN_MB24_ID0)
+#define pCAN_MB24_ID1 ((volatile unsigned short *)CAN_MB24_ID1)
+
+#define pCAN_MB25_DATA0 ((volatile unsigned short *)CAN_MB25_DATA0)
+#define pCAN_MB25_DATA1 ((volatile unsigned short *)CAN_MB25_DATA1)
+#define pCAN_MB25_DATA2 ((volatile unsigned short *)CAN_MB25_DATA2)
+#define pCAN_MB25_DATA3 ((volatile unsigned short *)CAN_MB25_DATA3)
+#define pCAN_MB25_LENGTH ((volatile unsigned short *)CAN_MB25_LENGTH)
+#define pCAN_MB25_TIMESTAMP ((volatile unsigned short *)CAN_MB25_TIMESTAMP)
+#define pCAN_MB25_ID0 ((volatile unsigned short *)CAN_MB25_ID0)
+#define pCAN_MB25_ID1 ((volatile unsigned short *)CAN_MB25_ID1)
+
+#define pCAN_MB26_DATA0 ((volatile unsigned short *)CAN_MB26_DATA0)
+#define pCAN_MB26_DATA1 ((volatile unsigned short *)CAN_MB26_DATA1)
+#define pCAN_MB26_DATA2 ((volatile unsigned short *)CAN_MB26_DATA2)
+#define pCAN_MB26_DATA3 ((volatile unsigned short *)CAN_MB26_DATA3)
+#define pCAN_MB26_LENGTH ((volatile unsigned short *)CAN_MB26_LENGTH)
+#define pCAN_MB26_TIMESTAMP ((volatile unsigned short *)CAN_MB26_TIMESTAMP)
+#define pCAN_MB26_ID0 ((volatile unsigned short *)CAN_MB26_ID0)
+#define pCAN_MB26_ID1 ((volatile unsigned short *)CAN_MB26_ID1)
+
+#define pCAN_MB27_DATA0 ((volatile unsigned short *)CAN_MB27_DATA0)
+#define pCAN_MB27_DATA1 ((volatile unsigned short *)CAN_MB27_DATA1)
+#define pCAN_MB27_DATA2 ((volatile unsigned short *)CAN_MB27_DATA2)
+#define pCAN_MB27_DATA3 ((volatile unsigned short *)CAN_MB27_DATA3)
+#define pCAN_MB27_LENGTH ((volatile unsigned short *)CAN_MB27_LENGTH)
+#define pCAN_MB27_TIMESTAMP ((volatile unsigned short *)CAN_MB27_TIMESTAMP)
+#define pCAN_MB27_ID0 ((volatile unsigned short *)CAN_MB27_ID0)
+#define pCAN_MB27_ID1 ((volatile unsigned short *)CAN_MB27_ID1)
+
+#define pCAN_MB28_DATA0 ((volatile unsigned short *)CAN_MB28_DATA0)
+#define pCAN_MB28_DATA1 ((volatile unsigned short *)CAN_MB28_DATA1)
+#define pCAN_MB28_DATA2 ((volatile unsigned short *)CAN_MB28_DATA2)
+#define pCAN_MB28_DATA3 ((volatile unsigned short *)CAN_MB28_DATA3)
+#define pCAN_MB28_LENGTH ((volatile unsigned short *)CAN_MB28_LENGTH)
+#define pCAN_MB28_TIMESTAMP ((volatile unsigned short *)CAN_MB28_TIMESTAMP)
+#define pCAN_MB28_ID0 ((volatile unsigned short *)CAN_MB28_ID0)
+#define pCAN_MB28_ID1 ((volatile unsigned short *)CAN_MB28_ID1)
+
+#define pCAN_MB29_DATA0 ((volatile unsigned short *)CAN_MB29_DATA0)
+#define pCAN_MB29_DATA1 ((volatile unsigned short *)CAN_MB29_DATA1)
+#define pCAN_MB29_DATA2 ((volatile unsigned short *)CAN_MB29_DATA2)
+#define pCAN_MB29_DATA3 ((volatile unsigned short *)CAN_MB29_DATA3)
+#define pCAN_MB29_LENGTH ((volatile unsigned short *)CAN_MB29_LENGTH)
+#define pCAN_MB29_TIMESTAMP ((volatile unsigned short *)CAN_MB29_TIMESTAMP)
+#define pCAN_MB29_ID0 ((volatile unsigned short *)CAN_MB29_ID0)
+#define pCAN_MB29_ID1 ((volatile unsigned short *)CAN_MB29_ID1)
+
+#define pCAN_MB30_DATA0 ((volatile unsigned short *)CAN_MB30_DATA0)
+#define pCAN_MB30_DATA1 ((volatile unsigned short *)CAN_MB30_DATA1)
+#define pCAN_MB30_DATA2 ((volatile unsigned short *)CAN_MB30_DATA2)
+#define pCAN_MB30_DATA3 ((volatile unsigned short *)CAN_MB30_DATA3)
+#define pCAN_MB30_LENGTH ((volatile unsigned short *)CAN_MB30_LENGTH)
+#define pCAN_MB30_TIMESTAMP ((volatile unsigned short *)CAN_MB30_TIMESTAMP)
+#define pCAN_MB30_ID0 ((volatile unsigned short *)CAN_MB30_ID0)
+#define pCAN_MB30_ID1 ((volatile unsigned short *)CAN_MB30_ID1)
+
+#define pCAN_MB31_DATA0 ((volatile unsigned short *)CAN_MB31_DATA0)
+#define pCAN_MB31_DATA1 ((volatile unsigned short *)CAN_MB31_DATA1)
+#define pCAN_MB31_DATA2 ((volatile unsigned short *)CAN_MB31_DATA2)
+#define pCAN_MB31_DATA3 ((volatile unsigned short *)CAN_MB31_DATA3)
+#define pCAN_MB31_LENGTH ((volatile unsigned short *)CAN_MB31_LENGTH)
+#define pCAN_MB31_TIMESTAMP ((volatile unsigned short *)CAN_MB31_TIMESTAMP)
+#define pCAN_MB31_ID0 ((volatile unsigned short *)CAN_MB31_ID0)
+#define pCAN_MB31_ID1 ((volatile unsigned short *)CAN_MB31_ID1)
+
+
+/* CAN Mailbox Area Macros */
+#define pCAN_MB_ID1(x) ((volatile unsigned short *)CAN_MB_ID1(x))
+#define pCAN_MB_ID0(x) ((volatile unsigned short *)CAN_MB_ID0(x))
+#define pCAN_MB_TIMESTAMP(x) ((volatile unsigned short *)CAN_MB_TIMESTAMP(x))
+#define pCAN_MB_LENGTH(x) ((volatile unsigned short *)CAN_MB_LENGTH(x))
+#define pCAN_MB_DATA3(x) ((volatile unsigned short *)CAN_MB_DATA3(x))
+#define pCAN_MB_DATA2(x) ((volatile unsigned short *)CAN_MB_DATA2(x))
+#define pCAN_MB_DATA1(x) ((volatile unsigned short *)CAN_MB_DATA1(x))
+#define pCAN_MB_DATA0(x) ((volatile unsigned short *)CAN_MB_DATA0(x))
+
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define pCAN_CNF pCAN_DEBUG
+#define pTWI0_PRESCALE pTWI0_CONTROL
+#define pTWI0_INT_SRC pTWI0_INT_STAT
+#define pTWI0_INT_ENABLE pTWI0_INT_MASK
+#define pTWI1_PRESCALE pTWI1_CONTROL
+#define pTWI1_INT_SRC pTWI1_INT_STAT
+#define pTWI1_INT_ENABLE pTWI1_INT_MASK
+
+#endif /* _CDEF_BF538_H */
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for BF539 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF539_H
+#define _CDEF_BF539_H
+
+/* include all Core registers and bit definitions */
+#include <defBF539.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* include built-in mneumonic macros */
+#include <ccblkfn.h>
+
+#ifndef _PTR_TO_VOL_VOID_PTR
+#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
+#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
+#else
+#define _PTR_TO_VOL_VOID_PTR (volatile void **)
+#endif
+#endif
+
+/* Clock/Regulator Control */
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+
+
+/* System Interrupt Controllers */
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+#define pSIC_RVECT ((void * volatile *)SIC_RVECT)
+
+#define pSIC_IMASK0 ((volatile unsigned long *)SIC_IMASK0)
+#define pSIC_IMASK1 ((volatile unsigned long *)SIC_IMASK1)
+
+#define pSIC_ISR0 ((volatile unsigned long *)SIC_ISR0)
+#define pSIC_ISR1 ((volatile unsigned long *)SIC_ISR1)
+
+#define pSIC_IWR0 ((volatile unsigned long *)SIC_IWR0)
+#define pSIC_IWR1 ((volatile unsigned long *)SIC_IWR1)
+
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
+#define pSIC_IAR4 ((volatile unsigned long *)SIC_IAR4)
+#define pSIC_IAR5 ((volatile unsigned long *)SIC_IAR5)
+#define pSIC_IAR6 ((volatile unsigned long *)SIC_IAR6)
+
+
+/* Watchdog Timer */
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+
+/* Real Time Clock */
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_FAST ((volatile unsigned short *)RTC_FAST)
+#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
+
+
+/* UART0 Controller */
+#define pUART0_THR ((volatile unsigned short *)UART0_THR)
+#define pUART0_RBR ((volatile unsigned short *)UART0_RBR)
+#define pUART0_DLL ((volatile unsigned short *)UART0_DLL)
+#define pUART0_IER ((volatile unsigned short *)UART0_IER)
+#define pUART0_DLH ((volatile unsigned short *)UART0_DLH)
+#define pUART0_IIR ((volatile unsigned short *)UART0_IIR)
+#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
+#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
+#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
+/* #define UART0_MSR */
+#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
+#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
+
+
+/* UART1 Controller */
+#define pUART1_THR ((volatile unsigned short *)UART1_THR)
+#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
+#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
+#define pUART1_IER ((volatile unsigned short *)UART1_IER)
+#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
+#define pUART1_IIR ((volatile unsigned short *)UART1_IIR)
+#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
+#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
+#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
+#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)
+
+
+/* UART2 Controller */
+#define pUART2_THR ((volatile unsigned short *)UART2_THR)
+#define pUART2_RBR ((volatile unsigned short *)UART2_RBR)
+#define pUART2_DLL ((volatile unsigned short *)UART2_DLL)
+#define pUART2_IER ((volatile unsigned short *)UART2_IER)
+#define pUART2_DLH ((volatile unsigned short *)UART2_DLH)
+#define pUART2_IIR ((volatile unsigned short *)UART2_IIR)
+#define pUART2_LCR ((volatile unsigned short *)UART2_LCR)
+#define pUART2_MCR ((volatile unsigned short *)UART2_MCR)
+#define pUART2_LSR ((volatile unsigned short *)UART2_LSR)
+#define pUART2_SCR ((volatile unsigned short *)UART2_SCR)
+#define pUART2_GCTL ((volatile unsigned short *)UART2_GCTL)
+
+
+/* SPI0 Controller */
+#define pSPI0_CTL ((volatile unsigned short *)SPI0_CTL)
+#define pSPI0_FLG ((volatile unsigned short *)SPI0_FLG)
+#define pSPI0_STAT ((volatile unsigned short *)SPI0_STAT)
+#define pSPI0_TDBR ((volatile unsigned short *)SPI0_TDBR)
+#define pSPI0_RDBR ((volatile unsigned short *)SPI0_RDBR)
+#define pSPI0_BAUD ((volatile unsigned short *)SPI0_BAUD)
+#define pSPI0_SHADOW ((volatile unsigned short *)SPI0_SHADOW)
+
+
+/* SPI1 Controller */
+#define pSPI1_CTL ((volatile unsigned short *)SPI1_CTL)
+#define pSPI1_FLG ((volatile unsigned short *)SPI1_FLG)
+#define pSPI1_STAT ((volatile unsigned short *)SPI1_STAT)
+#define pSPI1_TDBR ((volatile unsigned short *)SPI1_TDBR)
+#define pSPI1_RDBR ((volatile unsigned short *)SPI1_RDBR)
+#define pSPI1_BAUD ((volatile unsigned short *)SPI1_BAUD)
+#define pSPI1_SHADOW ((volatile unsigned short *)SPI1_SHADOW)
+
+
+/* SPI2 Controller */
+#define pSPI2_CTL ((volatile unsigned short *)SPI2_CTL)
+#define pSPI2_FLG ((volatile unsigned short *)SPI2_FLG)
+#define pSPI2_STAT ((volatile unsigned short *)SPI2_STAT)
+#define pSPI2_TDBR ((volatile unsigned short *)SPI2_TDBR)
+#define pSPI2_RDBR ((volatile unsigned short *)SPI2_RDBR)
+#define pSPI2_BAUD ((volatile unsigned short *)SPI2_BAUD)
+#define pSPI2_SHADOW ((volatile unsigned short *)SPI2_SHADOW)
+
+
+/* TIMER 0, 1, 2 Registers */
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+
+#define pTIMER_ENABLE ((volatile unsigned short *)TIMER_ENABLE)
+#define pTIMER_DISABLE ((volatile unsigned short *)TIMER_DISABLE)
+#define pTIMER_STATUS ((volatile unsigned short *)TIMER_STATUS)
+
+
+/* Two-Wire Interface 0 */
+#define pTWI0_CLKDIV ((volatile unsigned short *)TWI0_CLKDIV)
+#define pTWI0_CONTROL ((volatile unsigned short *)TWI0_CONTROL)
+#define pTWI0_SLAVE_CTRL ((volatile unsigned short *)TWI0_SLAVE_CTRL)
+#define pTWI0_SLAVE_STAT ((volatile unsigned short *)TWI0_SLAVE_STAT)
+#define pTWI0_SLAVE_ADDR ((volatile unsigned short *)TWI0_SLAVE_ADDR)
+#define pTWI0_MASTER_CTRL ((volatile unsigned short *)TWI0_MASTER_CTRL)
+#define pTWI0_MASTER_STAT ((volatile unsigned short *)TWI0_MASTER_STAT)
+#define pTWI0_MASTER_ADDR ((volatile unsigned short *)TWI0_MASTER_ADDR)
+#define pTWI0_INT_STAT ((volatile unsigned short *)TWI0_INT_STAT)
+#define pTWI0_INT_MASK ((volatile unsigned short *)TWI0_INT_MASK)
+#define pTWI0_FIFO_CTRL ((volatile unsigned short *)TWI0_FIFO_CTRL)
+#define pTWI0_FIFO_STAT ((volatile unsigned short *)TWI0_FIFO_STAT)
+#define pTWI0_XMT_DATA8 ((volatile unsigned short *)TWI0_XMT_DATA8)
+#define pTWI0_XMT_DATA16 ((volatile unsigned short *)TWI0_XMT_DATA16)
+#define pTWI0_RCV_DATA8 ((volatile unsigned short *)TWI0_RCV_DATA8)
+#define pTWI0_RCV_DATA16 ((volatile unsigned short *)TWI0_RCV_DATA16)
+
+
+/* Two-Wire Interface 1 */
+#define pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
+#define pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
+#define pTWI1_SLAVE_CTRL ((volatile unsigned short *)TWI1_SLAVE_CTRL)
+#define pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
+#define pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
+#define pTWI1_MASTER_CTRL ((volatile unsigned short *)TWI1_MASTER_CTRL)
+#define pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
+#define pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
+#define pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
+#define pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
+#define pTWI1_FIFO_CTRL ((volatile unsigned short *)TWI1_FIFO_CTRL)
+#define pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
+#define pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
+#define pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
+#define pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
+#define pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
+
+
+/* General Purpose I/O */
+/* Flag I/O (FIO_) */
+#define pFIO_FLAG_D ((volatile unsigned short *)FIO_FLAG_D)
+#define pFIO_FLAG_C ((volatile unsigned short *)FIO_FLAG_C)
+#define pFIO_FLAG_S ((volatile unsigned short *)FIO_FLAG_S)
+#define pFIO_FLAG_T ((volatile unsigned short *)FIO_FLAG_T)
+#define pFIO_MASKA_D ((volatile unsigned short *)FIO_MASKA_D)
+#define pFIO_MASKA_C ((volatile unsigned short *)FIO_MASKA_C)
+#define pFIO_MASKA_S ((volatile unsigned short *)FIO_MASKA_S)
+#define pFIO_MASKA_T ((volatile unsigned short *)FIO_MASKA_T)
+#define pFIO_MASKB_D ((volatile unsigned short *)FIO_MASKB_D)
+#define pFIO_MASKB_C ((volatile unsigned short *)FIO_MASKB_C)
+#define pFIO_MASKB_S ((volatile unsigned short *)FIO_MASKB_S)
+#define pFIO_MASKB_T ((volatile unsigned short *)FIO_MASKB_T)
+#define pFIO_DIR ((volatile unsigned short *)FIO_DIR)
+#define pFIO_POLAR ((volatile unsigned short *)FIO_POLAR)
+#define pFIO_EDGE ((volatile unsigned short *)FIO_EDGE)
+#define pFIO_BOTH ((volatile unsigned short *)FIO_BOTH)
+#define pFIO_INEN ((volatile unsigned short *)FIO_INEN)
+
+/* GPIO Registers (Port C/D/E) */
+#define pGPIO_C_CNFG ((volatile unsigned short *)GPIO_C_CNFG)
+#define pGPIO_D_CNFG ((volatile unsigned short *)GPIO_D_CNFG)
+#define pGPIO_E_CNFG ((volatile unsigned short *)GPIO_E_CNFG)
+
+#define pGPIO_C_D ((volatile unsigned short *)GPIO_C_D)
+#define pGPIO_D_D ((volatile unsigned short *)GPIO_D_D)
+#define pGPIO_E_D ((volatile unsigned short *)GPIO_E_D)
+
+#define pGPIO_C_C ((volatile unsigned short *)GPIO_C_C)
+#define pGPIO_D_C ((volatile unsigned short *)GPIO_D_C)
+#define pGPIO_E_C ((volatile unsigned short *)GPIO_E_C)
+
+#define pGPIO_C_S ((volatile unsigned short *)GPIO_C_S)
+#define pGPIO_D_S ((volatile unsigned short *)GPIO_D_S)
+#define pGPIO_E_S ((volatile unsigned short *)GPIO_E_S)
+
+#define pGPIO_C_T ((volatile unsigned short *)GPIO_C_T)
+#define pGPIO_D_T ((volatile unsigned short *)GPIO_D_T)
+#define pGPIO_E_T ((volatile unsigned short *)GPIO_E_T)
+
+#define pGPIO_C_DIR ((volatile unsigned short *)GPIO_C_DIR)
+#define pGPIO_D_DIR ((volatile unsigned short *)GPIO_D_DIR)
+#define pGPIO_E_DIR ((volatile unsigned short *)GPIO_E_DIR)
+
+#define pGPIO_C_INEN ((volatile unsigned short *)GPIO_C_INEN)
+#define pGPIO_D_INEN ((volatile unsigned short *)GPIO_D_INEN)
+#define pGPIO_E_INEN ((volatile unsigned short *)GPIO_E_INEN)
+
+/* Deprecate old macros */
+#define pGPIO_C_DAT pGPIO_C_D
+#define pGPIO_D_DAT pGPIO_D_D
+#define pGPIO_E_DAT pGPIO_E_D
+
+#define pGPIO_C_CLR pGPIO_C_C
+#define pGPIO_D_CLR pGPIO_D_C
+#define pGPIO_E_CLR pGPIO_E_C
+
+#define pGPIO_C_SET pGPIO_C_S
+#define pGPIO_D_SET pGPIO_D_S
+#define pGPIO_E_SET pGPIO_E_S
+
+#define pGPIO_C_TGL pGPIO_C_T
+#define pGPIO_D_TGL pGPIO_D_T
+#define pGPIO_E_TGL pGPIO_E_T
+
+/* SPORT0 Controller */
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+
+/* SPORT1 Controller */
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
+
+
+/* SPORT2 Controller */
+#define pSPORT2_TCR1 ((volatile unsigned short *)SPORT2_TCR1)
+#define pSPORT2_TCR2 ((volatile unsigned short *)SPORT2_TCR2)
+#define pSPORT2_TCLKDIV ((volatile unsigned short *)SPORT2_TCLKDIV)
+#define pSPORT2_TFSDIV ((volatile unsigned short *)SPORT2_TFSDIV)
+#define pSPORT2_TX ((volatile unsigned long *)SPORT2_TX)
+#define pSPORT2_RX ((volatile unsigned long *)SPORT2_RX)
+#define pSPORT2_TX32 ((volatile unsigned long *)SPORT2_TX)
+#define pSPORT2_RX32 ((volatile unsigned long *)SPORT2_RX)
+#define pSPORT2_TX16 ((volatile unsigned short *)SPORT2_TX)
+#define pSPORT2_RX16 ((volatile unsigned short *)SPORT2_RX)
+#define pSPORT2_RCR1 ((volatile unsigned short *)SPORT2_RCR1)
+#define pSPORT2_RCR2 ((volatile unsigned short *)SPORT2_RCR2)
+#define pSPORT2_RCLKDIV ((volatile unsigned short *)SPORT2_RCLKDIV)
+#define pSPORT2_RFSDIV ((volatile unsigned short *)SPORT2_RFSDIV)
+#define pSPORT2_STAT ((volatile unsigned short *)SPORT2_STAT)
+#define pSPORT2_CHNL ((volatile unsigned short *)SPORT2_CHNL)
+#define pSPORT2_MCMC1 ((volatile unsigned short *)SPORT2_MCMC1)
+#define pSPORT2_MCMC2 ((volatile unsigned short *)SPORT2_MCMC2)
+#define pSPORT2_MTCS0 ((volatile unsigned long *)SPORT2_MTCS0)
+#define pSPORT2_MTCS1 ((volatile unsigned long *)SPORT2_MTCS1)
+#define pSPORT2_MTCS2 ((volatile unsigned long *)SPORT2_MTCS2)
+#define pSPORT2_MTCS3 ((volatile unsigned long *)SPORT2_MTCS3)
+#define pSPORT2_MRCS0 ((volatile unsigned long *)SPORT2_MRCS0)
+#define pSPORT2_MRCS1 ((volatile unsigned long *)SPORT2_MRCS1)
+#define pSPORT2_MRCS2 ((volatile unsigned long *)SPORT2_MRCS2)
+#define pSPORT2_MRCS3 ((volatile unsigned long *)SPORT2_MRCS3)
+
+
+/* SPORT3 Controller */
+#define pSPORT3_TCR1 ((volatile unsigned short *)SPORT3_TCR1)
+#define pSPORT3_TCR2 ((volatile unsigned short *)SPORT3_TCR2)
+#define pSPORT3_TCLKDIV ((volatile unsigned short *)SPORT3_TCLKDIV)
+#define pSPORT3_TFSDIV ((volatile unsigned short *)SPORT3_TFSDIV)
+#define pSPORT3_TX ((volatile unsigned long *)SPORT3_TX)
+#define pSPORT3_RX ((volatile unsigned long *)SPORT3_RX)
+#define pSPORT3_TX32 ((volatile unsigned long *)SPORT3_TX)
+#define pSPORT3_RX32 ((volatile unsigned long *)SPORT3_RX)
+#define pSPORT3_TX16 ((volatile unsigned short *)SPORT3_TX)
+#define pSPORT3_RX16 ((volatile unsigned short *)SPORT3_RX)
+#define pSPORT3_RCR1 ((volatile unsigned short *)SPORT3_RCR1)
+#define pSPORT3_RCR2 ((volatile unsigned short *)SPORT3_RCR2)
+#define pSPORT3_RCLKDIV ((volatile unsigned short *)SPORT3_RCLKDIV)
+#define pSPORT3_RFSDIV ((volatile unsigned short *)SPORT3_RFSDIV)
+#define pSPORT3_STAT ((volatile unsigned short *)SPORT3_STAT)
+#define pSPORT3_CHNL ((volatile unsigned short *)SPORT3_CHNL)
+#define pSPORT3_MCMC1 ((volatile unsigned short *)SPORT3_MCMC1)
+#define pSPORT3_MCMC2 ((volatile unsigned short *)SPORT3_MCMC2)
+#define pSPORT3_MTCS0 ((volatile unsigned long *)SPORT3_MTCS0)
+#define pSPORT3_MTCS1 ((volatile unsigned long *)SPORT3_MTCS1)
+#define pSPORT3_MTCS2 ((volatile unsigned long *)SPORT3_MTCS2)
+#define pSPORT3_MTCS3 ((volatile unsigned long *)SPORT3_MTCS3)
+#define pSPORT3_MRCS0 ((volatile unsigned long *)SPORT3_MRCS0)
+#define pSPORT3_MRCS1 ((volatile unsigned long *)SPORT3_MRCS1)
+#define pSPORT3_MRCS2 ((volatile unsigned long *)SPORT3_MRCS2)
+#define pSPORT3_MRCS3 ((volatile unsigned long *)SPORT3_MRCS3)
+
+
+/* External Bus Interface Unit */
+/* Aysnchronous Memory Controller */
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+
+/* SDRAM Controller */
+#define pEBIU_SDGCTL ((volatile unsigned long *)EBIU_SDGCTL)
+#define pEBIU_SDBCTL ((volatile unsigned short *)EBIU_SDBCTL)
+#define pEBIU_SDRRC ((volatile unsigned short *)EBIU_SDRRC)
+#define pEBIU_SDSTAT ((volatile unsigned short *)EBIU_SDSTAT)
+
+
+/* DMA Controller 0 Traffic controls */
+#define pDMAC0_TC_PER ((volatile unsigned short *)DMAC0_TC_PER)
+#define pDMAC0_TC_CNT ((volatile unsigned short *)DMAC0_TC_CNT)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define pDMA0_TCPER ((volatile unsigned short *)DMA0_TCPER)
+#define pDMA0_TCCNT ((volatile unsigned short *)DMA0_TCCNT)
+
+
+/* DMA Controller 0 */
+#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_START_ADDR)
+#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
+#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA0_CURR_ADDR)
+#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+
+#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_START_ADDR)
+#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
+#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA1_CURR_ADDR)
+#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+
+#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_START_ADDR)
+#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
+#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA2_CURR_ADDR)
+#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+
+#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_START_ADDR)
+#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
+#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA3_CURR_ADDR)
+#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+
+#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_START_ADDR)
+#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
+#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA4_CURR_ADDR)
+#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+
+#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_START_ADDR)
+#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
+#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA5_CURR_ADDR)
+#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+
+#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_START_ADDR)
+#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
+#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA6_CURR_ADDR)
+#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+
+#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_START_ADDR)
+#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
+#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR (_PTR_TO_VOL_VOID_PTR DMA7_CURR_ADDR)
+#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+
+#define pMDMA0_D1_CONFIG ((volatile unsigned short *)MDMA0_D1_CONFIG)
+#define pMDMA0_D1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA0_D1_NEXT_DESC_PTR)
+#define pMDMA0_D1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA0_D1_START_ADDR)
+#define pMDMA0_D1_X_COUNT ((volatile unsigned short *)MDMA0_D1_X_COUNT)
+#define pMDMA0_D1_Y_COUNT ((volatile unsigned short *)MDMA0_D1_Y_COUNT)
+#define pMDMA0_D1_X_MODIFY ((volatile signed short *)MDMA0_D1_X_MODIFY)
+#define pMDMA0_D1_Y_MODIFY ((volatile signed short *)MDMA0_D1_Y_MODIFY)
+#define pMDMA0_D1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA0_D1_CURR_DESC_PTR)
+#define pMDMA0_D1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA0_D1_CURR_ADDR)
+#define pMDMA0_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA0_D1_CURR_X_COUNT)
+#define pMDMA0_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA0_D1_CURR_Y_COUNT)
+#define pMDMA0_D1_IRQ_STATUS ((volatile unsigned short *)MDMA0_D1_IRQ_STATUS)
+#define pMDMA0_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA0_D1_PERIPHERAL_MAP)
+
+#define pMDMA0_S1_CONFIG ((volatile unsigned short *)MDMA0_S1_CONFIG)
+#define pMDMA0_S1_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA0_S1_NEXT_DESC_PTR)
+#define pMDMA0_S1_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA0_S1_START_ADDR)
+#define pMDMA0_S1_X_COUNT ((volatile unsigned short *)MDMA0_S1_X_COUNT)
+#define pMDMA0_S1_Y_COUNT ((volatile unsigned short *)MDMA0_S1_Y_COUNT)
+#define pMDMA0_S1_X_MODIFY ((volatile signed short *)MDMA0_S1_X_MODIFY)
+#define pMDMA0_S1_Y_MODIFY ((volatile signed short *)MDMA0_S1_Y_MODIFY)
+#define pMDMA0_S1_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA0_S1_CURR_DESC_PTR)
+#define pMDMA0_S1_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA0_S1_CURR_ADDR)
+#define pMDMA0_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA0_S1_CURR_X_COUNT)
+#define pMDMA0_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA0_S1_CURR_Y_COUNT)
+#define pMDMA0_S1_IRQ_STATUS ((volatile unsigned short *)MDMA0_S1_IRQ_STATUS)
+#define pMDMA0_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA0_S1_PERIPHERAL_MAP)
+
+#define pMDMA0_D0_CONFIG ((volatile unsigned short *)MDMA0_D0_CONFIG)
+#define pMDMA0_D0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA0_D0_NEXT_DESC_PTR)
+#define pMDMA0_D0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA0_D0_START_ADDR)
+#define pMDMA0_D0_X_COUNT ((volatile unsigned short *)MDMA0_D0_X_COUNT)
+#define pMDMA0_D0_Y_COUNT ((volatile unsigned short *)MDMA0_D0_Y_COUNT)
+#define pMDMA0_D0_X_MODIFY ((volatile signed short *)MDMA0_D0_X_MODIFY)
+#define pMDMA0_D0_Y_MODIFY ((volatile signed short *)MDMA0_D0_Y_MODIFY)
+#define pMDMA0_D0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA0_D0_CURR_DESC_PTR)
+#define pMDMA0_D0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA0_D0_CURR_ADDR)
+#define pMDMA0_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA0_D0_CURR_X_COUNT)
+#define pMDMA0_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA0_D0_CURR_Y_COUNT)
+#define pMDMA0_D0_IRQ_STATUS ((volatile unsigned short *)MDMA0_D0_IRQ_STATUS)
+#define pMDMA0_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA0_D0_PERIPHERAL_MAP)
+
+#define pMDMA0_S0_CONFIG ((volatile unsigned short *)MDMA0_S0_CONFIG)
+#define pMDMA0_S0_NEXT_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA0_S0_NEXT_DESC_PTR)
+#define pMDMA0_S0_START_ADDR (_PTR_TO_VOL_VOID_PTR MDMA0_S0_START_ADDR)
+#define pMDMA0_S0_X_COUNT ((volatile unsigned short *)MDMA0_S0_X_COUNT)
+#define pMDMA0_S0_Y_COUNT ((volatile unsigned short *)MDMA0_S0_Y_COUNT)
+#define pMDMA0_S0_X_MODIFY ((volatile signed short *)MDMA0_S0_X_MODIFY)
+#define pMDMA0_S0_Y_MODIFY ((volatile signed short *)MDMA0_S0_Y_MODIFY)
+#define pMDMA0_S0_CURR_DESC_PTR (_PTR_TO_VOL_VOID_PTR MDMA0_S0_CURR_DESC_PTR)
+#define pMDMA0_S0_CURR_ADDR (_PTR_TO_VOL_VOID_PTR MDMA0_S0_CURR_ADDR)
+#define pMDMA0_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA0_S0_CURR_X_COUNT)
+#define pMDMA0_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA0_S0_CURR_Y_COUNT)
+#define pMDMA0_S0_IRQ_STATUS ((volatile unsigned short *)MDMA0_S0_IRQ_STATUS)
+#define pMDMA0_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA0_S0_PERIPHERAL_MAP)
+
+
+/* DMA Controller 1 Traffic Control Registers */
+#define pDMAC1_TC_PER ((volatile unsigned short *)DMAC1_TC_PER)
+#define pDMAC1_TC_CNT ((volatile unsigned short *)DMAC1_TC_CNT)
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define pDMA1_TCPER pDMA1_TCPER /* Traffic Control Periods Register */
+#define pDMA1_TCCNT pDMA1_TCCNT /* Traffic Control Current Counts Register */
+
+/* DMA Controller 1 */
+#define pDMA8_NEXT_DESC_PTR ((void * volatile *)DMA8_NEXT_DESC_PTR)
+#define pDMA8_START_ADDR ((void * volatile *)DMA8_START_ADDR)
+#define pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG)
+#define pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT)
+#define pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY)
+#define pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT)
+#define pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY)
+#define pDMA8_CURR_DESC_PTR ((void * volatile *)DMA8_CURR_DESC_PTR)
+#define pDMA8_CURR_ADDR ((void * volatile *)DMA8_CURR_ADDR)
+#define pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS)
+#define pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
+#define pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT)
+#define pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT)
+
+#define pDMA9_NEXT_DESC_PTR ((void * volatile *)DMA9_NEXT_DESC_PTR)
+#define pDMA9_START_ADDR ((void * volatile *)DMA9_START_ADDR)
+#define pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG)
+#define pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT)
+#define pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY)
+#define pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT)
+#define pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY)
+#define pDMA9_CURR_DESC_PTR ((void * volatile *)DMA9_CURR_DESC_PTR)
+#define pDMA9_CURR_ADDR ((void * volatile *)DMA9_CURR_ADDR)
+#define pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS)
+#define pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
+#define pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT)
+#define pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT)
+
+#define pDMA10_NEXT_DESC_PTR ((void * volatile *)DMA10_NEXT_DESC_PTR)
+#define pDMA10_START_ADDR ((void * volatile *)DMA10_START_ADDR)
+#define pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG)
+#define pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT)
+#define pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY)
+#define pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT)
+#define pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY)
+#define pDMA10_CURR_DESC_PTR ((void * volatile *)DMA10_CURR_DESC_PTR)
+#define pDMA10_CURR_ADDR ((void * volatile *)DMA10_CURR_ADDR)
+#define pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS)
+#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
+#define pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT)
+#define pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT)
+
+#define pDMA11_NEXT_DESC_PTR ((void * volatile *)DMA11_NEXT_DESC_PTR)
+#define pDMA11_START_ADDR ((void * volatile *)DMA11_START_ADDR)
+#define pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG)
+#define pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT)
+#define pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY)
+#define pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT)
+#define pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY)
+#define pDMA11_CURR_DESC_PTR ((void * volatile *)DMA11_CURR_DESC_PTR)
+#define pDMA11_CURR_ADDR ((void * volatile *)DMA11_CURR_ADDR)
+#define pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS)
+#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
+#define pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT)
+#define pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT)
+
+#define pDMA12_NEXT_DESC_PTR ((void * volatile *)DMA12_NEXT_DESC_PTR)
+#define pDMA12_START_ADDR ((void * volatile *)DMA12_START_ADDR)
+#define pDMA12_CONFIG ((volatile unsigned short *)DMA12_CONFIG)
+#define pDMA12_X_COUNT ((volatile unsigned short *)DMA12_X_COUNT)
+#define pDMA12_X_MODIFY ((volatile signed short *)DMA12_X_MODIFY)
+#define pDMA12_Y_COUNT ((volatile unsigned short *)DMA12_Y_COUNT)
+#define pDMA12_Y_MODIFY ((volatile signed short *)DMA12_Y_MODIFY)
+#define pDMA12_CURR_DESC_PTR ((void * volatile *)DMA12_CURR_DESC_PTR)
+#define pDMA12_CURR_ADDR ((void * volatile *)DMA12_CURR_ADDR)
+#define pDMA12_IRQ_STATUS ((volatile unsigned short *)DMA12_IRQ_STATUS)
+#define pDMA12_PERIPHERAL_MAP ((volatile unsigned short *)DMA12_PERIPHERAL_MAP)
+#define pDMA12_CURR_X_COUNT ((volatile unsigned short *)DMA12_CURR_X_COUNT)
+#define pDMA12_CURR_Y_COUNT ((volatile unsigned short *)DMA12_CURR_Y_COUNT)
+
+#define pDMA13_NEXT_DESC_PTR ((void * volatile *)DMA13_NEXT_DESC_PTR)
+#define pDMA13_START_ADDR ((void * volatile *)DMA13_START_ADDR)
+#define pDMA13_CONFIG ((volatile unsigned short *)DMA13_CONFIG)
+#define pDMA13_X_COUNT ((volatile unsigned short *)DMA13_X_COUNT)
+#define pDMA13_X_MODIFY ((volatile signed short *)DMA13_X_MODIFY)
+#define pDMA13_Y_COUNT ((volatile unsigned short *)DMA13_Y_COUNT)
+#define pDMA13_Y_MODIFY ((volatile signed short *)DMA13_Y_MODIFY)
+#define pDMA13_CURR_DESC_PTR ((void * volatile *)DMA13_CURR_DESC_PTR)
+#define pDMA13_CURR_ADDR ((void * volatile *)DMA13_CURR_ADDR)
+#define pDMA13_IRQ_STATUS ((volatile unsigned short *)DMA13_IRQ_STATUS)
+#define pDMA13_PERIPHERAL_MAP ((volatile unsigned short *)DMA13_PERIPHERAL_MAP)
+#define pDMA13_CURR_X_COUNT ((volatile unsigned short *)DMA13_CURR_X_COUNT)
+#define pDMA13_CURR_Y_COUNT ((volatile unsigned short *)DMA13_CURR_Y_COUNT)
+
+#define pDMA14_NEXT_DESC_PTR ((void * volatile *)DMA14_NEXT_DESC_PTR)
+#define pDMA14_START_ADDR ((void * volatile *)DMA14_START_ADDR)
+#define pDMA14_CONFIG ((volatile unsigned short *)DMA14_CONFIG)
+#define pDMA14_X_COUNT ((volatile unsigned short *)DMA14_X_COUNT)
+#define pDMA14_X_MODIFY ((volatile signed short *)DMA14_X_MODIFY)
+#define pDMA14_Y_COUNT ((volatile unsigned short *)DMA14_Y_COUNT)
+#define pDMA14_Y_MODIFY ((volatile signed short *)DMA14_Y_MODIFY)
+#define pDMA14_CURR_DESC_PTR ((void * volatile *)DMA14_CURR_DESC_PTR)
+#define pDMA14_CURR_ADDR ((void * volatile *)DMA14_CURR_ADDR)
+#define pDMA14_IRQ_STATUS ((volatile unsigned short *)DMA14_IRQ_STATUS)
+#define pDMA14_PERIPHERAL_MAP ((volatile unsigned short *)DMA14_PERIPHERAL_MAP)
+#define pDMA14_CURR_X_COUNT ((volatile unsigned short *)DMA14_CURR_X_COUNT)
+#define pDMA14_CURR_Y_COUNT ((volatile unsigned short *)DMA14_CURR_Y_COUNT)
+
+#define pDMA15_NEXT_DESC_PTR ((void * volatile *)DMA15_NEXT_DESC_PTR)
+#define pDMA15_START_ADDR ((void * volatile *)DMA15_START_ADDR)
+#define pDMA15_CONFIG ((volatile unsigned short *)DMA15_CONFIG)
+#define pDMA15_X_COUNT ((volatile unsigned short *)DMA15_X_COUNT)
+#define pDMA15_X_MODIFY ((volatile signed short *)DMA15_X_MODIFY)
+#define pDMA15_Y_COUNT ((volatile unsigned short *)DMA15_Y_COUNT)
+#define pDMA15_Y_MODIFY ((volatile signed short *)DMA15_Y_MODIFY)
+#define pDMA15_CURR_DESC_PTR ((void * volatile *)DMA15_CURR_DESC_PTR)
+#define pDMA15_CURR_ADDR ((void * volatile *)DMA15_CURR_ADDR)
+#define pDMA15_IRQ_STATUS ((volatile unsigned short *)DMA15_IRQ_STATUS)
+#define pDMA15_PERIPHERAL_MAP ((volatile unsigned short *)DMA15_PERIPHERAL_MAP)
+#define pDMA15_CURR_X_COUNT ((volatile unsigned short *)DMA15_CURR_X_COUNT)
+#define pDMA15_CURR_Y_COUNT ((volatile unsigned short *)DMA15_CURR_Y_COUNT)
+
+#define pDMA16_NEXT_DESC_PTR ((void * volatile *)DMA16_NEXT_DESC_PTR)
+#define pDMA16_START_ADDR ((void * volatile *)DMA16_START_ADDR)
+#define pDMA16_CONFIG ((volatile unsigned short *)DMA16_CONFIG)
+#define pDMA16_X_COUNT ((volatile unsigned short *)DMA16_X_COUNT)
+#define pDMA16_X_MODIFY ((volatile signed short *)DMA16_X_MODIFY)
+#define pDMA16_Y_COUNT ((volatile unsigned short *)DMA16_Y_COUNT)
+#define pDMA16_Y_MODIFY ((volatile signed short *)DMA16_Y_MODIFY)
+#define pDMA16_CURR_DESC_PTR ((void * volatile *)DMA16_CURR_DESC_PTR)
+#define pDMA16_CURR_ADDR ((void * volatile *)DMA16_CURR_ADDR)
+#define pDMA16_IRQ_STATUS ((volatile unsigned short *)DMA16_IRQ_STATUS)
+#define pDMA16_PERIPHERAL_MAP ((volatile unsigned short *)DMA16_PERIPHERAL_MAP)
+#define pDMA16_CURR_X_COUNT ((volatile unsigned short *)DMA16_CURR_X_COUNT)
+#define pDMA16_CURR_Y_COUNT ((volatile unsigned short *)DMA16_CURR_Y_COUNT)
+
+#define pDMA17_NEXT_DESC_PTR ((void * volatile *)DMA17_NEXT_DESC_PTR)
+#define pDMA17_START_ADDR ((void * volatile *)DMA17_START_ADDR)
+#define pDMA17_CONFIG ((volatile unsigned short *)DMA17_CONFIG)
+#define pDMA17_X_COUNT ((volatile unsigned short *)DMA17_X_COUNT)
+#define pDMA17_X_MODIFY ((volatile signed short *)DMA17_X_MODIFY)
+#define pDMA17_Y_COUNT ((volatile unsigned short *)DMA17_Y_COUNT)
+#define pDMA17_Y_MODIFY ((volatile signed short *)DMA17_Y_MODIFY)
+#define pDMA17_CURR_DESC_PTR ((void * volatile *)DMA17_CURR_DESC_PTR)
+#define pDMA17_CURR_ADDR ((void * volatile *)DMA17_CURR_ADDR)
+#define pDMA17_IRQ_STATUS ((volatile unsigned short *)DMA17_IRQ_STATUS)
+#define pDMA17_PERIPHERAL_MAP ((volatile unsigned short *)DMA17_PERIPHERAL_MAP)
+#define pDMA17_CURR_X_COUNT ((volatile unsigned short *)DMA17_CURR_X_COUNT)
+#define pDMA17_CURR_Y_COUNT ((volatile unsigned short *)DMA17_CURR_Y_COUNT)
+
+#define pDMA18_NEXT_DESC_PTR ((void * volatile *)DMA18_NEXT_DESC_PTR)
+#define pDMA18_START_ADDR ((void * volatile *)DMA18_START_ADDR)
+#define pDMA18_CONFIG ((volatile unsigned short *)DMA18_CONFIG)
+#define pDMA18_X_COUNT ((volatile unsigned short *)DMA18_X_COUNT)
+#define pDMA18_X_MODIFY ((volatile signed short *)DMA18_X_MODIFY)
+#define pDMA18_Y_COUNT ((volatile unsigned short *)DMA18_Y_COUNT)
+#define pDMA18_Y_MODIFY ((volatile signed short *)DMA18_Y_MODIFY)
+#define pDMA18_CURR_DESC_PTR ((void * volatile *)DMA18_CURR_DESC_PTR)
+#define pDMA18_CURR_ADDR ((void * volatile *)DMA18_CURR_ADDR)
+#define pDMA18_IRQ_STATUS ((volatile unsigned short *)DMA18_IRQ_STATUS)
+#define pDMA18_PERIPHERAL_MAP ((volatile unsigned short *)DMA18_PERIPHERAL_MAP)
+#define pDMA18_CURR_X_COUNT ((volatile unsigned short *)DMA18_CURR_X_COUNT)
+#define pDMA18_CURR_Y_COUNT ((volatile unsigned short *)DMA18_CURR_Y_COUNT)
+
+#define pDMA19_NEXT_DESC_PTR ((void * volatile *)DMA19_NEXT_DESC_PTR)
+#define pDMA19_START_ADDR ((void * volatile *)DMA19_START_ADDR)
+#define pDMA19_CONFIG ((volatile unsigned short *)DMA19_CONFIG)
+#define pDMA19_X_COUNT ((volatile unsigned short *)DMA19_X_COUNT)
+#define pDMA19_X_MODIFY ((volatile signed short *)DMA19_X_MODIFY)
+#define pDMA19_Y_COUNT ((volatile unsigned short *)DMA19_Y_COUNT)
+#define pDMA19_Y_MODIFY ((volatile signed short *)DMA19_Y_MODIFY)
+#define pDMA19_CURR_DESC_PTR ((void * volatile *)DMA19_CURR_DESC_PTR)
+#define pDMA19_CURR_ADDR ((void * volatile *)DMA19_CURR_ADDR)
+#define pDMA19_IRQ_STATUS ((volatile unsigned short *)DMA19_IRQ_STATUS)
+#define pDMA19_PERIPHERAL_MAP ((volatile unsigned short *)DMA19_PERIPHERAL_MAP)
+#define pDMA19_CURR_X_COUNT ((volatile unsigned short *)DMA19_CURR_X_COUNT)
+#define pDMA19_CURR_Y_COUNT ((volatile unsigned short *)DMA19_CURR_Y_COUNT)
+
+#define pMDMA1_D0_NEXT_DESC_PTR ((void * volatile *)MDMA1_D0_NEXT_DESC_PTR)
+#define pMDMA1_D0_START_ADDR ((void * volatile *)MDMA1_D0_START_ADDR)
+#define pMDMA1_D0_CONFIG ((volatile unsigned short *)MDMA1_D0_CONFIG)
+#define pMDMA1_D0_X_COUNT ((volatile unsigned short *)MDMA1_D0_X_COUNT)
+#define pMDMA1_D0_X_MODIFY ((volatile signed short *)MDMA1_D0_X_MODIFY)
+#define pMDMA1_D0_Y_COUNT ((volatile unsigned short *)MDMA1_D0_Y_COUNT)
+#define pMDMA1_D0_Y_MODIFY ((volatile signed short *)MDMA1_D0_Y_MODIFY)
+#define pMDMA1_D0_CURR_DESC_PTR ((void * volatile *)MDMA1_D0_CURR_DESC_PTR)
+#define pMDMA1_D0_CURR_ADDR ((void * volatile *)MDMA1_D0_CURR_ADDR)
+#define pMDMA1_D0_IRQ_STATUS ((volatile unsigned short *)MDMA1_D0_IRQ_STATUS)
+#define pMDMA1_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP)
+#define pMDMA1_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA1_D0_CURR_X_COUNT)
+#define pMDMA1_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT)
+
+#define pMDMA1_S0_NEXT_DESC_PTR ((void * volatile *)MDMA1_S0_NEXT_DESC_PTR)
+#define pMDMA1_S0_START_ADDR ((void * volatile *)MDMA1_S0_START_ADDR)
+#define pMDMA1_S0_CONFIG ((volatile unsigned short *)MDMA1_S0_CONFIG)
+#define pMDMA1_S0_X_COUNT ((volatile unsigned short *)MDMA1_S0_X_COUNT)
+#define pMDMA1_S0_X_MODIFY ((volatile signed short *)MDMA1_S0_X_MODIFY)
+#define pMDMA1_S0_Y_COUNT ((volatile unsigned short *)MDMA1_S0_Y_COUNT)
+#define pMDMA1_S0_Y_MODIFY ((volatile signed short *)MDMA1_S0_Y_MODIFY)
+#define pMDMA1_S0_CURR_DESC_PTR ((void * volatile *)MDMA1_S0_CURR_DESC_PTR)
+#define pMDMA1_S0_CURR_ADDR ((void * volatile *)MDMA1_S0_CURR_ADDR)
+#define pMDMA1_S0_IRQ_STATUS ((volatile unsigned short *)MDMA1_S0_IRQ_STATUS)
+#define pMDMA1_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP)
+#define pMDMA1_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA1_S0_CURR_X_COUNT)
+#define pMDMA1_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT)
+
+#define pMDMA1_D1_NEXT_DESC_PTR ((void * volatile *)MDMA1_D1_NEXT_DESC_PTR)
+#define pMDMA1_D1_START_ADDR ((void * volatile *)MDMA1_D1_START_ADDR)
+#define pMDMA1_D1_CONFIG ((volatile unsigned short *)MDMA1_D1_CONFIG)
+#define pMDMA1_D1_X_COUNT ((volatile unsigned short *)MDMA1_D1_X_COUNT)
+#define pMDMA1_D1_X_MODIFY ((volatile signed short *)MDMA1_D1_X_MODIFY)
+#define pMDMA1_D1_Y_COUNT ((volatile unsigned short *)MDMA1_D1_Y_COUNT)
+#define pMDMA1_D1_Y_MODIFY ((volatile signed short *)MDMA1_D1_Y_MODIFY)
+#define pMDMA1_D1_CURR_DESC_PTR ((void * volatile *)MDMA1_D1_CURR_DESC_PTR)
+#define pMDMA1_D1_CURR_ADDR ((void * volatile *)MDMA1_D1_CURR_ADDR)
+#define pMDMA1_D1_IRQ_STATUS ((volatile unsigned short *)MDMA1_D1_IRQ_STATUS)
+#define pMDMA1_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP)
+#define pMDMA1_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA1_D1_CURR_X_COUNT)
+#define pMDMA1_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT)
+
+#define pMDMA1_S1_NEXT_DESC_PTR ((void * volatile *)MDMA1_S1_NEXT_DESC_PTR)
+#define pMDMA1_S1_START_ADDR ((void * volatile *)MDMA1_S1_START_ADDR)
+#define pMDMA1_S1_CONFIG ((volatile unsigned short *)MDMA1_S1_CONFIG)
+#define pMDMA1_S1_X_COUNT ((volatile unsigned short *)MDMA1_S1_X_COUNT)
+#define pMDMA1_S1_X_MODIFY ((volatile signed short *)MDMA1_S1_X_MODIFY)
+#define pMDMA1_S1_Y_COUNT ((volatile unsigned short *)MDMA1_S1_Y_COUNT)
+#define pMDMA1_S1_Y_MODIFY ((volatile signed short *)MDMA1_S1_Y_MODIFY)
+#define pMDMA1_S1_CURR_DESC_PTR ((void * volatile *)MDMA1_S1_CURR_DESC_PTR)
+#define pMDMA1_S1_CURR_ADDR ((void * volatile *)MDMA1_S1_CURR_ADDR)
+#define pMDMA1_S1_IRQ_STATUS ((volatile unsigned short *)MDMA1_S1_IRQ_STATUS)
+#define pMDMA1_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP)
+#define pMDMA1_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA1_S1_CURR_X_COUNT)
+#define pMDMA1_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT)
+
+
+/* Parallel Peripheral Interface (PPI) */
+#define pPPI_CONTROL ((volatile unsigned short *)PPI_CONTROL)
+#define pPPI_STATUS ((volatile unsigned short *)PPI_STATUS)
+#define pPPI_COUNT ((volatile unsigned short *)PPI_COUNT)
+#define pPPI_DELAY ((volatile unsigned short *)PPI_DELAY)
+#define pPPI_FRAME ((volatile unsigned short *)PPI_FRAME)
+
+
+/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */
+#define pMXVR_CONFIG ((volatile unsigned short *)MXVR_CONFIG)
+#define pMXVR_PLL_CTL_0 ((volatile unsigned long *)MXVR_PLL_CTL_0)
+
+#define pMXVR_STATE_0 ((volatile unsigned long *)MXVR_STATE_0)
+#define pMXVR_STATE_1 ((volatile unsigned long *)MXVR_STATE_1)
+
+#define pMXVR_INT_STAT_0 ((volatile unsigned long *)MXVR_INT_STAT_0)
+#define pMXVR_INT_STAT_1 ((volatile unsigned long *)MXVR_INT_STAT_1)
+
+#define pMXVR_INT_EN_0 ((volatile unsigned long *)MXVR_INT_EN_0)
+#define pMXVR_INT_EN_1 ((volatile unsigned long *)MXVR_INT_EN_1)
+
+#define pMXVR_POSITION ((volatile unsigned short *)MXVR_POSITION)
+#define pMXVR_MAX_POSITION ((volatile unsigned short *)MXVR_MAX_POSITION)
+
+#define pMXVR_DELAY ((volatile unsigned short *)MXVR_DELAY)
+#define pMXVR_MAX_DELAY ((volatile unsigned short *)MXVR_MAX_DELAY)
+
+#define pMXVR_LADDR ((volatile unsigned long *)MXVR_LADDR)
+#define pMXVR_GADDR ((volatile unsigned short *)MXVR_GADDR)
+#define pMXVR_AADDR ((volatile unsigned long *)MXVR_AADDR)
+
+#define pMXVR_ALLOC_0 ((volatile unsigned long *)MXVR_ALLOC_0)
+#define pMXVR_ALLOC_1 ((volatile unsigned long *)MXVR_ALLOC_1)
+#define pMXVR_ALLOC_2 ((volatile unsigned long *)MXVR_ALLOC_2)
+#define pMXVR_ALLOC_3 ((volatile unsigned long *)MXVR_ALLOC_3)
+#define pMXVR_ALLOC_4 ((volatile unsigned long *)MXVR_ALLOC_4)
+#define pMXVR_ALLOC_5 ((volatile unsigned long *)MXVR_ALLOC_5)
+#define pMXVR_ALLOC_6 ((volatile unsigned long *)MXVR_ALLOC_6)
+#define pMXVR_ALLOC_7 ((volatile unsigned long *)MXVR_ALLOC_7)
+#define pMXVR_ALLOC_8 ((volatile unsigned long *)MXVR_ALLOC_8)
+#define pMXVR_ALLOC_9 ((volatile unsigned long *)MXVR_ALLOC_9)
+#define pMXVR_ALLOC_10 ((volatile unsigned long *)MXVR_ALLOC_10)
+#define pMXVR_ALLOC_11 ((volatile unsigned long *)MXVR_ALLOC_11)
+#define pMXVR_ALLOC_12 ((volatile unsigned long *)MXVR_ALLOC_12)
+#define pMXVR_ALLOC_13 ((volatile unsigned long *)MXVR_ALLOC_13)
+#define pMXVR_ALLOC_14 ((volatile unsigned long *)MXVR_ALLOC_14)
+
+#define pMXVR_SYNC_LCHAN_0 ((volatile unsigned long *)MXVR_SYNC_LCHAN_0)
+#define pMXVR_SYNC_LCHAN_1 ((volatile unsigned long *)MXVR_SYNC_LCHAN_1)
+#define pMXVR_SYNC_LCHAN_2 ((volatile unsigned long *)MXVR_SYNC_LCHAN_2)
+#define pMXVR_SYNC_LCHAN_3 ((volatile unsigned long *)MXVR_SYNC_LCHAN_3)
+#define pMXVR_SYNC_LCHAN_4 ((volatile unsigned long *)MXVR_SYNC_LCHAN_4)
+#define pMXVR_SYNC_LCHAN_5 ((volatile unsigned long *)MXVR_SYNC_LCHAN_5)
+#define pMXVR_SYNC_LCHAN_6 ((volatile unsigned long *)MXVR_SYNC_LCHAN_6)
+#define pMXVR_SYNC_LCHAN_7 ((volatile unsigned long *)MXVR_SYNC_LCHAN_7)
+
+#define pMXVR_DMA0_CONFIG ((volatile unsigned long *)MXVR_DMA0_CONFIG)
+#define pMXVR_DMA0_START_ADDR ((void * volatile *)MXVR_DMA0_START_ADDR)
+#define pMXVR_DMA0_COUNT ((volatile unsigned short *)MXVR_DMA0_COUNT)
+#define pMXVR_DMA0_CURR_ADDR ((void * volatile *)MXVR_DMA0_CURR_ADDR)
+#define pMXVR_DMA0_CURR_COUNT ((volatile unsigned short *)MXVR_DMA0_CURR_COUNT)
+
+#define pMXVR_DMA1_CONFIG ((volatile unsigned long *)MXVR_DMA1_CONFIG)
+#define pMXVR_DMA1_START_ADDR ((void * volatile *)MXVR_DMA1_START_ADDR)
+#define pMXVR_DMA1_COUNT ((volatile unsigned short *)MXVR_DMA1_COUNT)
+#define pMXVR_DMA1_CURR_ADDR ((void * volatile *)MXVR_DMA1_CURR_ADDR)
+#define pMXVR_DMA1_CURR_COUNT ((volatile unsigned short *)MXVR_DMA1_CURR_COUNT)
+
+#define pMXVR_DMA2_CONFIG ((volatile unsigned long *)MXVR_DMA2_CONFIG)
+#define pMXVR_DMA2_START_ADDR ((void * volatile *)MXVR_DMA2_START_ADDR)
+#define pMXVR_DMA2_COUNT ((volatile unsigned short *)MXVR_DMA2_COUNT)
+#define pMXVR_DMA2_CURR_ADDR ((void * volatile *)MXVR_DMA2_CURR_ADDR)
+#define pMXVR_DMA2_CURR_COUNT ((volatile unsigned short *)MXVR_DMA2_CURR_COUNT)
+
+#define pMXVR_DMA3_CONFIG ((volatile unsigned long *)MXVR_DMA3_CONFIG)
+#define pMXVR_DMA3_START_ADDR ((void * volatile *)MXVR_DMA3_START_ADDR)
+#define pMXVR_DMA3_COUNT ((volatile unsigned short *)MXVR_DMA3_COUNT)
+#define pMXVR_DMA3_CURR_ADDR ((void * volatile *)MXVR_DMA3_CURR_ADDR)
+#define pMXVR_DMA3_CURR_COUNT ((volatile unsigned short *)MXVR_DMA3_CURR_COUNT)
+
+#define pMXVR_DMA4_CONFIG ((volatile unsigned long *)MXVR_DMA4_CONFIG)
+#define pMXVR_DMA4_START_ADDR ((void * volatile *)MXVR_DMA4_START_ADDR)
+#define pMXVR_DMA4_COUNT ((volatile unsigned short *)MXVR_DMA4_COUNT)
+#define pMXVR_DMA4_CURR_ADDR ((void * volatile *)MXVR_DMA4_CURR_ADDR)
+#define pMXVR_DMA4_CURR_COUNT ((volatile unsigned short *)MXVR_DMA4_CURR_COUNT)
+
+#define pMXVR_DMA5_CONFIG ((volatile unsigned long *)MXVR_DMA5_CONFIG)
+#define pMXVR_DMA5_START_ADDR ((void * volatile *)MXVR_DMA5_START_ADDR)
+#define pMXVR_DMA5_COUNT ((volatile unsigned short *)MXVR_DMA5_COUNT)
+#define pMXVR_DMA5_CURR_ADDR ((void * volatile *)MXVR_DMA5_CURR_ADDR)
+#define pMXVR_DMA5_CURR_COUNT ((volatile unsigned short *)MXVR_DMA5_CURR_COUNT)
+
+#define pMXVR_DMA6_CONFIG ((volatile unsigned long *)MXVR_DMA6_CONFIG)
+#define pMXVR_DMA6_START_ADDR ((void * volatile *)MXVR_DMA6_START_ADDR)
+#define pMXVR_DMA6_COUNT ((volatile unsigned short *)MXVR_DMA6_COUNT)
+#define pMXVR_DMA6_CURR_ADDR ((void * volatile *)MXVR_DMA6_CURR_ADDR)
+#define pMXVR_DMA6_CURR_COUNT ((volatile unsigned short *)MXVR_DMA6_CURR_COUNT)
+
+#define pMXVR_DMA7_CONFIG ((volatile unsigned long *)MXVR_DMA7_CONFIG)
+#define pMXVR_DMA7_START_ADDR ((void * volatile *)MXVR_DMA7_START_ADDR)
+#define pMXVR_DMA7_COUNT ((volatile unsigned short *)MXVR_DMA7_COUNT)
+#define pMXVR_DMA7_CURR_ADDR ((void * volatile *)MXVR_DMA7_CURR_ADDR)
+#define pMXVR_DMA7_CURR_COUNT ((volatile unsigned short *)MXVR_DMA7_CURR_COUNT)
+
+#define pMXVR_AP_CTL ((volatile unsigned short *)MXVR_AP_CTL)
+#define pMXVR_APRB_START_ADDR ((void * volatile *)MXVR_APRB_START_ADDR)
+#define pMXVR_APRB_CURR_ADDR ((void * volatile *)MXVR_APRB_CURR_ADDR)
+#define pMXVR_APTB_START_ADDR ((void * volatile *)MXVR_APTB_START_ADDR)
+#define pMXVR_APTB_CURR_ADDR ((void * volatile *)MXVR_APTB_CURR_ADDR)
+
+#define pMXVR_CM_CTL ((volatile unsigned long *)MXVR_CM_CTL)
+#define pMXVR_CMRB_START_ADDR ((void * volatile *)MXVR_CMRB_START_ADDR)
+#define pMXVR_CMRB_CURR_ADDR ((void * volatile *)MXVR_CMRB_CURR_ADDR)
+#define pMXVR_CMTB_START_ADDR ((void * volatile *)MXVR_CMTB_START_ADDR)
+#define pMXVR_CMTB_CURR_ADDR ((void * volatile *)MXVR_CMTB_CURR_ADDR)
+
+#define pMXVR_RRDB_START_ADDR ((void * volatile *)MXVR_RRDB_START_ADDR)
+#define pMXVR_RRDB_CURR_ADDR ((void * volatile *)MXVR_RRDB_CURR_ADDR)
+
+#define pMXVR_PAT_DATA_0 ((volatile unsigned long *)MXVR_PAT_DATA_0)
+#define pMXVR_PAT_EN_0 ((volatile unsigned long *)MXVR_PAT_EN_0)
+#define pMXVR_PAT_DATA_1 ((volatile unsigned long *)MXVR_PAT_DATA_1)
+#define pMXVR_PAT_EN_1 ((volatile unsigned long *)MXVR_PAT_EN_1)
+
+#define pMXVR_FRAME_CNT_0 ((volatile unsigned short *)MXVR_FRAME_CNT_0)
+#define pMXVR_FRAME_CNT_1 ((volatile unsigned short *)MXVR_FRAME_CNT_1)
+
+#define pMXVR_ROUTING_0 ((volatile unsigned long *)MXVR_ROUTING_0)
+#define pMXVR_ROUTING_1 ((volatile unsigned long *)MXVR_ROUTING_1)
+#define pMXVR_ROUTING_2 ((volatile unsigned long *)MXVR_ROUTING_2)
+#define pMXVR_ROUTING_3 ((volatile unsigned long *)MXVR_ROUTING_3)
+#define pMXVR_ROUTING_4 ((volatile unsigned long *)MXVR_ROUTING_4)
+#define pMXVR_ROUTING_5 ((volatile unsigned long *)MXVR_ROUTING_5)
+#define pMXVR_ROUTING_6 ((volatile unsigned long *)MXVR_ROUTING_6)
+#define pMXVR_ROUTING_7 ((volatile unsigned long *)MXVR_ROUTING_7)
+#define pMXVR_ROUTING_8 ((volatile unsigned long *)MXVR_ROUTING_8)
+#define pMXVR_ROUTING_9 ((volatile unsigned long *)MXVR_ROUTING_9)
+#define pMXVR_ROUTING_10 ((volatile unsigned long *)MXVR_ROUTING_10)
+#define pMXVR_ROUTING_11 ((volatile unsigned long *)MXVR_ROUTING_11)
+#define pMXVR_ROUTING_12 ((volatile unsigned long *)MXVR_ROUTING_12)
+#define pMXVR_ROUTING_13 ((volatile unsigned long *)MXVR_ROUTING_13)
+#define pMXVR_ROUTING_14 ((volatile unsigned long *)MXVR_ROUTING_14)
+
+#define pMXVR_PLL_CTL_1 ((volatile unsigned long *)MXVR_PLL_CTL_1)
+#define pMXVR_PLL_CTL_2 ((volatile unsigned short *)MXVR_PLL_CTL_2)
+
+#define pMXVR_BLOCK_CNT ((volatile unsigned short *)MXVR_BLOCK_CNT)
+
+
+/* CAN Controller */
+/* For Mailboxes 0-15 */
+#define pCAN_MC1 ((volatile unsigned short *)CAN_MC1)
+#define pCAN_MD1 ((volatile unsigned short *)CAN_MD1)
+#define pCAN_TRS1 ((volatile unsigned short *)CAN_TRS1)
+#define pCAN_TRR1 ((volatile unsigned short *)CAN_TRR1)
+#define pCAN_TA1 ((volatile unsigned short *)CAN_TA1)
+#define pCAN_AA1 ((volatile unsigned short *)CAN_AA1)
+#define pCAN_RMP1 ((volatile unsigned short *)CAN_RMP1)
+#define pCAN_RML1 ((volatile unsigned short *)CAN_RML1)
+#define pCAN_MBTIF1 ((volatile unsigned short *)CAN_MBTIF1)
+#define pCAN_MBRIF1 ((volatile unsigned short *)CAN_MBRIF1)
+#define pCAN_MBIM1 ((volatile unsigned short *)CAN_MBIM1)
+#define pCAN_RFH1 ((volatile unsigned short *)CAN_RFH1)
+#define pCAN_OPSS1 ((volatile unsigned short *)CAN_OPSS1)
+
+/* For Mailboxes 16-31 */
+#define pCAN_MC2 ((volatile unsigned short *)CAN_MC2)
+#define pCAN_MD2 ((volatile unsigned short *)CAN_MD2)
+#define pCAN_TRS2 ((volatile unsigned short *)CAN_TRS2)
+#define pCAN_TRR2 ((volatile unsigned short *)CAN_TRR2)
+#define pCAN_TA2 ((volatile unsigned short *)CAN_TA2)
+#define pCAN_AA2 ((volatile unsigned short *)CAN_AA2)
+#define pCAN_RMP2 ((volatile unsigned short *)CAN_RMP2)
+#define pCAN_RML2 ((volatile unsigned short *)CAN_RML2)
+#define pCAN_MBTIF2 ((volatile unsigned short *)CAN_MBTIF2)
+#define pCAN_MBRIF2 ((volatile unsigned short *)CAN_MBRIF2)
+#define pCAN_MBIM2 ((volatile unsigned short *)CAN_MBIM2)
+#define pCAN_RFH2 ((volatile unsigned short *)CAN_RFH2)
+#define pCAN_OPSS2 ((volatile unsigned short *)CAN_OPSS2)
+
+#define pCAN_CLOCK ((volatile unsigned short *)CAN_CLOCK)
+#define pCAN_TIMING ((volatile unsigned short *)CAN_TIMING)
+#define pCAN_DEBUG ((volatile unsigned short *)CAN_DEBUG)
+#define pCAN_STATUS ((volatile unsigned short *)CAN_STATUS)
+#define pCAN_CEC ((volatile unsigned short *)CAN_CEC)
+#define pCAN_GIS ((volatile unsigned short *)CAN_GIS)
+#define pCAN_GIM ((volatile unsigned short *)CAN_GIM)
+#define pCAN_GIF ((volatile unsigned short *)CAN_GIF)
+#define pCAN_CONTROL ((volatile unsigned short *)CAN_CONTROL)
+#define pCAN_INTR ((volatile unsigned short *)CAN_INTR)
+#define pCAN_MBTD ((volatile unsigned short *)CAN_MBTD)
+#define pCAN_EWR ((volatile unsigned short *)CAN_EWR)
+#define pCAN_ESR ((volatile unsigned short *)CAN_ESR)
+#define pCAN_UCREG ((volatile unsigned short *)CAN_UCREG)
+#define pCAN_UCCNT ((volatile unsigned short *)CAN_UCCNT)
+#define pCAN_UCRC ((volatile unsigned short *)CAN_UCRC)
+#define pCAN_UCCNF ((volatile unsigned short *)CAN_UCCNF)
+
+/* Mailbox Acceptance Masks */
+#define pCAN_AM00L ((volatile unsigned short *)CAN_AM00L)
+#define pCAN_AM00H ((volatile unsigned short *)CAN_AM00H)
+#define pCAN_AM01L ((volatile unsigned short *)CAN_AM01L)
+#define pCAN_AM01H ((volatile unsigned short *)CAN_AM01H)
+#define pCAN_AM02L ((volatile unsigned short *)CAN_AM02L)
+#define pCAN_AM02H ((volatile unsigned short *)CAN_AM02H)
+#define pCAN_AM03L ((volatile unsigned short *)CAN_AM03L)
+#define pCAN_AM03H ((volatile unsigned short *)CAN_AM03H)
+#define pCAN_AM04L ((volatile unsigned short *)CAN_AM04L)
+#define pCAN_AM04H ((volatile unsigned short *)CAN_AM04H)
+#define pCAN_AM05L ((volatile unsigned short *)CAN_AM05L)
+#define pCAN_AM05H ((volatile unsigned short *)CAN_AM05H)
+#define pCAN_AM06L ((volatile unsigned short *)CAN_AM06L)
+#define pCAN_AM06H ((volatile unsigned short *)CAN_AM06H)
+#define pCAN_AM07L ((volatile unsigned short *)CAN_AM07L)
+#define pCAN_AM07H ((volatile unsigned short *)CAN_AM07H)
+#define pCAN_AM08L ((volatile unsigned short *)CAN_AM08L)
+#define pCAN_AM08H ((volatile unsigned short *)CAN_AM08H)
+#define pCAN_AM09L ((volatile unsigned short *)CAN_AM09L)
+#define pCAN_AM09H ((volatile unsigned short *)CAN_AM09H)
+#define pCAN_AM10L ((volatile unsigned short *)CAN_AM10L)
+#define pCAN_AM10H ((volatile unsigned short *)CAN_AM10H)
+#define pCAN_AM11L ((volatile unsigned short *)CAN_AM11L)
+#define pCAN_AM11H ((volatile unsigned short *)CAN_AM11H)
+#define pCAN_AM12L ((volatile unsigned short *)CAN_AM12L)
+#define pCAN_AM12H ((volatile unsigned short *)CAN_AM12H)
+#define pCAN_AM13L ((volatile unsigned short *)CAN_AM13L)
+#define pCAN_AM13H ((volatile unsigned short *)CAN_AM13H)
+#define pCAN_AM14L ((volatile unsigned short *)CAN_AM14L)
+#define pCAN_AM14H ((volatile unsigned short *)CAN_AM14H)
+#define pCAN_AM15L ((volatile unsigned short *)CAN_AM15L)
+#define pCAN_AM15H ((volatile unsigned short *)CAN_AM15H)
+
+#define pCAN_AM16L ((volatile unsigned short *)CAN_AM16L)
+#define pCAN_AM16H ((volatile unsigned short *)CAN_AM16H)
+#define pCAN_AM17L ((volatile unsigned short *)CAN_AM17L)
+#define pCAN_AM17H ((volatile unsigned short *)CAN_AM17H)
+#define pCAN_AM18L ((volatile unsigned short *)CAN_AM18L)
+#define pCAN_AM18H ((volatile unsigned short *)CAN_AM18H)
+#define pCAN_AM19L ((volatile unsigned short *)CAN_AM19L)
+#define pCAN_AM19H ((volatile unsigned short *)CAN_AM19H)
+#define pCAN_AM20L ((volatile unsigned short *)CAN_AM20L)
+#define pCAN_AM20H ((volatile unsigned short *)CAN_AM20H)
+#define pCAN_AM21L ((volatile unsigned short *)CAN_AM21L)
+#define pCAN_AM21H ((volatile unsigned short *)CAN_AM21H)
+#define pCAN_AM22L ((volatile unsigned short *)CAN_AM22L)
+#define pCAN_AM22H ((volatile unsigned short *)CAN_AM22H)
+#define pCAN_AM23L ((volatile unsigned short *)CAN_AM23L)
+#define pCAN_AM23H ((volatile unsigned short *)CAN_AM23H)
+#define pCAN_AM24L ((volatile unsigned short *)CAN_AM24L)
+#define pCAN_AM24H ((volatile unsigned short *)CAN_AM24H)
+#define pCAN_AM25L ((volatile unsigned short *)CAN_AM25L)
+#define pCAN_AM25H ((volatile unsigned short *)CAN_AM25H)
+#define pCAN_AM26L ((volatile unsigned short *)CAN_AM26L)
+#define pCAN_AM26H ((volatile unsigned short *)CAN_AM26H)
+#define pCAN_AM27L ((volatile unsigned short *)CAN_AM27L)
+#define pCAN_AM27H ((volatile unsigned short *)CAN_AM27H)
+#define pCAN_AM28L ((volatile unsigned short *)CAN_AM28L)
+#define pCAN_AM28H ((volatile unsigned short *)CAN_AM28H)
+#define pCAN_AM29L ((volatile unsigned short *)CAN_AM29L)
+#define pCAN_AM29H ((volatile unsigned short *)CAN_AM29H)
+#define pCAN_AM30L ((volatile unsigned short *)CAN_AM30L)
+#define pCAN_AM30H ((volatile unsigned short *)CAN_AM30H)
+#define pCAN_AM31L ((volatile unsigned short *)CAN_AM31L)
+#define pCAN_AM31H ((volatile unsigned short *)CAN_AM31H)
+
+/* CAN Acceptance Mask Area Macros */
+#define pCAN_AM_L(x) ((volatile unsigned short *)CAN_AM_L(x))
+#define pCAN_AM_H(x) ((volatile unsigned short *)CAN_AM_H(x))
+
+/* Mailbox Registers */
+#define pCAN_MB00_DATA0 ((volatile unsigned short *)CAN_MB00_DATA0)
+#define pCAN_MB00_DATA1 ((volatile unsigned short *)CAN_MB00_DATA1)
+#define pCAN_MB00_DATA2 ((volatile unsigned short *)CAN_MB00_DATA2)
+#define pCAN_MB00_DATA3 ((volatile unsigned short *)CAN_MB00_DATA3)
+#define pCAN_MB00_LENGTH ((volatile unsigned short *)CAN_MB00_LENGTH)
+#define pCAN_MB00_TIMESTAMP ((volatile unsigned short *)CAN_MB00_TIMESTAMP)
+#define pCAN_MB00_ID0 ((volatile unsigned short *)CAN_MB00_ID0)
+#define pCAN_MB00_ID1 ((volatile unsigned short *)CAN_MB00_ID1)
+
+#define pCAN_MB01_DATA0 ((volatile unsigned short *)CAN_MB01_DATA0)
+#define pCAN_MB01_DATA1 ((volatile unsigned short *)CAN_MB01_DATA1)
+#define pCAN_MB01_DATA2 ((volatile unsigned short *)CAN_MB01_DATA2)
+#define pCAN_MB01_DATA3 ((volatile unsigned short *)CAN_MB01_DATA3)
+#define pCAN_MB01_LENGTH ((volatile unsigned short *)CAN_MB01_LENGTH)
+#define pCAN_MB01_TIMESTAMP ((volatile unsigned short *)CAN_MB01_TIMESTAMP)
+#define pCAN_MB01_ID0 ((volatile unsigned short *)CAN_MB01_ID0)
+#define pCAN_MB01_ID1 ((volatile unsigned short *)CAN_MB01_ID1)
+
+#define pCAN_MB02_DATA0 ((volatile unsigned short *)CAN_MB02_DATA0)
+#define pCAN_MB02_DATA1 ((volatile unsigned short *)CAN_MB02_DATA1)
+#define pCAN_MB02_DATA2 ((volatile unsigned short *)CAN_MB02_DATA2)
+#define pCAN_MB02_DATA3 ((volatile unsigned short *)CAN_MB02_DATA3)
+#define pCAN_MB02_LENGTH ((volatile unsigned short *)CAN_MB02_LENGTH)
+#define pCAN_MB02_TIMESTAMP ((volatile unsigned short *)CAN_MB02_TIMESTAMP)
+#define pCAN_MB02_ID0 ((volatile unsigned short *)CAN_MB02_ID0)
+#define pCAN_MB02_ID1 ((volatile unsigned short *)CAN_MB02_ID1)
+
+#define pCAN_MB03_DATA0 ((volatile unsigned short *)CAN_MB03_DATA0)
+#define pCAN_MB03_DATA1 ((volatile unsigned short *)CAN_MB03_DATA1)
+#define pCAN_MB03_DATA2 ((volatile unsigned short *)CAN_MB03_DATA2)
+#define pCAN_MB03_DATA3 ((volatile unsigned short *)CAN_MB03_DATA3)
+#define pCAN_MB03_LENGTH ((volatile unsigned short *)CAN_MB03_LENGTH)
+#define pCAN_MB03_TIMESTAMP ((volatile unsigned short *)CAN_MB03_TIMESTAMP)
+#define pCAN_MB03_ID0 ((volatile unsigned short *)CAN_MB03_ID0)
+#define pCAN_MB03_ID1 ((volatile unsigned short *)CAN_MB03_ID1)
+
+#define pCAN_MB04_DATA0 ((volatile unsigned short *)CAN_MB04_DATA0)
+#define pCAN_MB04_DATA1 ((volatile unsigned short *)CAN_MB04_DATA1)
+#define pCAN_MB04_DATA2 ((volatile unsigned short *)CAN_MB04_DATA2)
+#define pCAN_MB04_DATA3 ((volatile unsigned short *)CAN_MB04_DATA3)
+#define pCAN_MB04_LENGTH ((volatile unsigned short *)CAN_MB04_LENGTH)
+#define pCAN_MB04_TIMESTAMP ((volatile unsigned short *)CAN_MB04_TIMESTAMP)
+#define pCAN_MB04_ID0 ((volatile unsigned short *)CAN_MB04_ID0)
+#define pCAN_MB04_ID1 ((volatile unsigned short *)CAN_MB04_ID1)
+
+#define pCAN_MB05_DATA0 ((volatile unsigned short *)CAN_MB05_DATA0)
+#define pCAN_MB05_DATA1 ((volatile unsigned short *)CAN_MB05_DATA1)
+#define pCAN_MB05_DATA2 ((volatile unsigned short *)CAN_MB05_DATA2)
+#define pCAN_MB05_DATA3 ((volatile unsigned short *)CAN_MB05_DATA3)
+#define pCAN_MB05_LENGTH ((volatile unsigned short *)CAN_MB05_LENGTH)
+#define pCAN_MB05_TIMESTAMP ((volatile unsigned short *)CAN_MB05_TIMESTAMP)
+#define pCAN_MB05_ID0 ((volatile unsigned short *)CAN_MB05_ID0)
+#define pCAN_MB05_ID1 ((volatile unsigned short *)CAN_MB05_ID1)
+
+#define pCAN_MB06_DATA0 ((volatile unsigned short *)CAN_MB06_DATA0)
+#define pCAN_MB06_DATA1 ((volatile unsigned short *)CAN_MB06_DATA1)
+#define pCAN_MB06_DATA2 ((volatile unsigned short *)CAN_MB06_DATA2)
+#define pCAN_MB06_DATA3 ((volatile unsigned short *)CAN_MB06_DATA3)
+#define pCAN_MB06_LENGTH ((volatile unsigned short *)CAN_MB06_LENGTH)
+#define pCAN_MB06_TIMESTAMP ((volatile unsigned short *)CAN_MB06_TIMESTAMP)
+#define pCAN_MB06_ID0 ((volatile unsigned short *)CAN_MB06_ID0)
+#define pCAN_MB06_ID1 ((volatile unsigned short *)CAN_MB06_ID1)
+
+#define pCAN_MB07_DATA0 ((volatile unsigned short *)CAN_MB07_DATA0)
+#define pCAN_MB07_DATA1 ((volatile unsigned short *)CAN_MB07_DATA1)
+#define pCAN_MB07_DATA2 ((volatile unsigned short *)CAN_MB07_DATA2)
+#define pCAN_MB07_DATA3 ((volatile unsigned short *)CAN_MB07_DATA3)
+#define pCAN_MB07_LENGTH ((volatile unsigned short *)CAN_MB07_LENGTH)
+#define pCAN_MB07_TIMESTAMP ((volatile unsigned short *)CAN_MB07_TIMESTAMP)
+#define pCAN_MB07_ID0 ((volatile unsigned short *)CAN_MB07_ID0)
+#define pCAN_MB07_ID1 ((volatile unsigned short *)CAN_MB07_ID1)
+
+#define pCAN_MB08_DATA0 ((volatile unsigned short *)CAN_MB08_DATA0)
+#define pCAN_MB08_DATA1 ((volatile unsigned short *)CAN_MB08_DATA1)
+#define pCAN_MB08_DATA2 ((volatile unsigned short *)CAN_MB08_DATA2)
+#define pCAN_MB08_DATA3 ((volatile unsigned short *)CAN_MB08_DATA3)
+#define pCAN_MB08_LENGTH ((volatile unsigned short *)CAN_MB08_LENGTH)
+#define pCAN_MB08_TIMESTAMP ((volatile unsigned short *)CAN_MB08_TIMESTAMP)
+#define pCAN_MB08_ID0 ((volatile unsigned short *)CAN_MB08_ID0)
+#define pCAN_MB08_ID1 ((volatile unsigned short *)CAN_MB08_ID1)
+
+#define pCAN_MB09_DATA0 ((volatile unsigned short *)CAN_MB09_DATA0)
+#define pCAN_MB09_DATA1 ((volatile unsigned short *)CAN_MB09_DATA1)
+#define pCAN_MB09_DATA2 ((volatile unsigned short *)CAN_MB09_DATA2)
+#define pCAN_MB09_DATA3 ((volatile unsigned short *)CAN_MB09_DATA3)
+#define pCAN_MB09_LENGTH ((volatile unsigned short *)CAN_MB09_LENGTH)
+#define pCAN_MB09_TIMESTAMP ((volatile unsigned short *)CAN_MB09_TIMESTAMP)
+#define pCAN_MB09_ID0 ((volatile unsigned short *)CAN_MB09_ID0)
+#define pCAN_MB09_ID1 ((volatile unsigned short *)CAN_MB09_ID1)
+
+#define pCAN_MB10_DATA0 ((volatile unsigned short *)CAN_MB10_DATA0)
+#define pCAN_MB10_DATA1 ((volatile unsigned short *)CAN_MB10_DATA1)
+#define pCAN_MB10_DATA2 ((volatile unsigned short *)CAN_MB10_DATA2)
+#define pCAN_MB10_DATA3 ((volatile unsigned short *)CAN_MB10_DATA3)
+#define pCAN_MB10_LENGTH ((volatile unsigned short *)CAN_MB10_LENGTH)
+#define pCAN_MB10_TIMESTAMP ((volatile unsigned short *)CAN_MB10_TIMESTAMP)
+#define pCAN_MB10_ID0 ((volatile unsigned short *)CAN_MB10_ID0)
+#define pCAN_MB10_ID1 ((volatile unsigned short *)CAN_MB10_ID1)
+
+#define pCAN_MB11_DATA0 ((volatile unsigned short *)CAN_MB11_DATA0)
+#define pCAN_MB11_DATA1 ((volatile unsigned short *)CAN_MB11_DATA1)
+#define pCAN_MB11_DATA2 ((volatile unsigned short *)CAN_MB11_DATA2)
+#define pCAN_MB11_DATA3 ((volatile unsigned short *)CAN_MB11_DATA3)
+#define pCAN_MB11_LENGTH ((volatile unsigned short *)CAN_MB11_LENGTH)
+#define pCAN_MB11_TIMESTAMP ((volatile unsigned short *)CAN_MB11_TIMESTAMP)
+#define pCAN_MB11_ID0 ((volatile unsigned short *)CAN_MB11_ID0)
+#define pCAN_MB11_ID1 ((volatile unsigned short *)CAN_MB11_ID1)
+
+#define pCAN_MB12_DATA0 ((volatile unsigned short *)CAN_MB12_DATA0)
+#define pCAN_MB12_DATA1 ((volatile unsigned short *)CAN_MB12_DATA1)
+#define pCAN_MB12_DATA2 ((volatile unsigned short *)CAN_MB12_DATA2)
+#define pCAN_MB12_DATA3 ((volatile unsigned short *)CAN_MB12_DATA3)
+#define pCAN_MB12_LENGTH ((volatile unsigned short *)CAN_MB12_LENGTH)
+#define pCAN_MB12_TIMESTAMP ((volatile unsigned short *)CAN_MB12_TIMESTAMP)
+#define pCAN_MB12_ID0 ((volatile unsigned short *)CAN_MB12_ID0)
+#define pCAN_MB12_ID1 ((volatile unsigned short *)CAN_MB12_ID1)
+
+#define pCAN_MB13_DATA0 ((volatile unsigned short *)CAN_MB13_DATA0)
+#define pCAN_MB13_DATA1 ((volatile unsigned short *)CAN_MB13_DATA1)
+#define pCAN_MB13_DATA2 ((volatile unsigned short *)CAN_MB13_DATA2)
+#define pCAN_MB13_DATA3 ((volatile unsigned short *)CAN_MB13_DATA3)
+#define pCAN_MB13_LENGTH ((volatile unsigned short *)CAN_MB13_LENGTH)
+#define pCAN_MB13_TIMESTAMP ((volatile unsigned short *)CAN_MB13_TIMESTAMP)
+#define pCAN_MB13_ID0 ((volatile unsigned short *)CAN_MB13_ID0)
+#define pCAN_MB13_ID1 ((volatile unsigned short *)CAN_MB13_ID1)
+
+#define pCAN_MB14_DATA0 ((volatile unsigned short *)CAN_MB14_DATA0)
+#define pCAN_MB14_DATA1 ((volatile unsigned short *)CAN_MB14_DATA1)
+#define pCAN_MB14_DATA2 ((volatile unsigned short *)CAN_MB14_DATA2)
+#define pCAN_MB14_DATA3 ((volatile unsigned short *)CAN_MB14_DATA3)
+#define pCAN_MB14_LENGTH ((volatile unsigned short *)CAN_MB14_LENGTH)
+#define pCAN_MB14_TIMESTAMP ((volatile unsigned short *)CAN_MB14_TIMESTAMP)
+#define pCAN_MB14_ID0 ((volatile unsigned short *)CAN_MB14_ID0)
+#define pCAN_MB14_ID1 ((volatile unsigned short *)CAN_MB14_ID1)
+
+#define pCAN_MB15_DATA0 ((volatile unsigned short *)CAN_MB15_DATA0)
+#define pCAN_MB15_DATA1 ((volatile unsigned short *)CAN_MB15_DATA1)
+#define pCAN_MB15_DATA2 ((volatile unsigned short *)CAN_MB15_DATA2)
+#define pCAN_MB15_DATA3 ((volatile unsigned short *)CAN_MB15_DATA3)
+#define pCAN_MB15_LENGTH ((volatile unsigned short *)CAN_MB15_LENGTH)
+#define pCAN_MB15_TIMESTAMP ((volatile unsigned short *)CAN_MB15_TIMESTAMP)
+#define pCAN_MB15_ID0 ((volatile unsigned short *)CAN_MB15_ID0)
+#define pCAN_MB15_ID1 ((volatile unsigned short *)CAN_MB15_ID1)
+
+#define pCAN_MB16_DATA0 ((volatile unsigned short *)CAN_MB16_DATA0)
+#define pCAN_MB16_DATA1 ((volatile unsigned short *)CAN_MB16_DATA1)
+#define pCAN_MB16_DATA2 ((volatile unsigned short *)CAN_MB16_DATA2)
+#define pCAN_MB16_DATA3 ((volatile unsigned short *)CAN_MB16_DATA3)
+#define pCAN_MB16_LENGTH ((volatile unsigned short *)CAN_MB16_LENGTH)
+#define pCAN_MB16_TIMESTAMP ((volatile unsigned short *)CAN_MB16_TIMESTAMP)
+#define pCAN_MB16_ID0 ((volatile unsigned short *)CAN_MB16_ID0)
+#define pCAN_MB16_ID1 ((volatile unsigned short *)CAN_MB16_ID1)
+
+#define pCAN_MB17_DATA0 ((volatile unsigned short *)CAN_MB17_DATA0)
+#define pCAN_MB17_DATA1 ((volatile unsigned short *)CAN_MB17_DATA1)
+#define pCAN_MB17_DATA2 ((volatile unsigned short *)CAN_MB17_DATA2)
+#define pCAN_MB17_DATA3 ((volatile unsigned short *)CAN_MB17_DATA3)
+#define pCAN_MB17_LENGTH ((volatile unsigned short *)CAN_MB17_LENGTH)
+#define pCAN_MB17_TIMESTAMP ((volatile unsigned short *)CAN_MB17_TIMESTAMP)
+#define pCAN_MB17_ID0 ((volatile unsigned short *)CAN_MB17_ID0)
+#define pCAN_MB17_ID1 ((volatile unsigned short *)CAN_MB17_ID1)
+
+#define pCAN_MB18_DATA0 ((volatile unsigned short *)CAN_MB18_DATA0)
+#define pCAN_MB18_DATA1 ((volatile unsigned short *)CAN_MB18_DATA1)
+#define pCAN_MB18_DATA2 ((volatile unsigned short *)CAN_MB18_DATA2)
+#define pCAN_MB18_DATA3 ((volatile unsigned short *)CAN_MB18_DATA3)
+#define pCAN_MB18_LENGTH ((volatile unsigned short *)CAN_MB18_LENGTH)
+#define pCAN_MB18_TIMESTAMP ((volatile unsigned short *)CAN_MB18_TIMESTAMP)
+#define pCAN_MB18_ID0 ((volatile unsigned short *)CAN_MB18_ID0)
+#define pCAN_MB18_ID1 ((volatile unsigned short *)CAN_MB18_ID1)
+
+#define pCAN_MB19_DATA0 ((volatile unsigned short *)CAN_MB19_DATA0)
+#define pCAN_MB19_DATA1 ((volatile unsigned short *)CAN_MB19_DATA1)
+#define pCAN_MB19_DATA2 ((volatile unsigned short *)CAN_MB19_DATA2)
+#define pCAN_MB19_DATA3 ((volatile unsigned short *)CAN_MB19_DATA3)
+#define pCAN_MB19_LENGTH ((volatile unsigned short *)CAN_MB19_LENGTH)
+#define pCAN_MB19_TIMESTAMP ((volatile unsigned short *)CAN_MB19_TIMESTAMP)
+#define pCAN_MB19_ID0 ((volatile unsigned short *)CAN_MB19_ID0)
+#define pCAN_MB19_ID1 ((volatile unsigned short *)CAN_MB19_ID1)
+
+#define pCAN_MB20_DATA0 ((volatile unsigned short *)CAN_MB20_DATA0)
+#define pCAN_MB20_DATA1 ((volatile unsigned short *)CAN_MB20_DATA1)
+#define pCAN_MB20_DATA2 ((volatile unsigned short *)CAN_MB20_DATA2)
+#define pCAN_MB20_DATA3 ((volatile unsigned short *)CAN_MB20_DATA3)
+#define pCAN_MB20_LENGTH ((volatile unsigned short *)CAN_MB20_LENGTH)
+#define pCAN_MB20_TIMESTAMP ((volatile unsigned short *)CAN_MB20_TIMESTAMP)
+#define pCAN_MB20_ID0 ((volatile unsigned short *)CAN_MB20_ID0)
+#define pCAN_MB20_ID1 ((volatile unsigned short *)CAN_MB20_ID1)
+
+#define pCAN_MB21_DATA0 ((volatile unsigned short *)CAN_MB21_DATA0)
+#define pCAN_MB21_DATA1 ((volatile unsigned short *)CAN_MB21_DATA1)
+#define pCAN_MB21_DATA2 ((volatile unsigned short *)CAN_MB21_DATA2)
+#define pCAN_MB21_DATA3 ((volatile unsigned short *)CAN_MB21_DATA3)
+#define pCAN_MB21_LENGTH ((volatile unsigned short *)CAN_MB21_LENGTH)
+#define pCAN_MB21_TIMESTAMP ((volatile unsigned short *)CAN_MB21_TIMESTAMP)
+#define pCAN_MB21_ID0 ((volatile unsigned short *)CAN_MB21_ID0)
+#define pCAN_MB21_ID1 ((volatile unsigned short *)CAN_MB21_ID1)
+
+#define pCAN_MB22_DATA0 ((volatile unsigned short *)CAN_MB22_DATA0)
+#define pCAN_MB22_DATA1 ((volatile unsigned short *)CAN_MB22_DATA1)
+#define pCAN_MB22_DATA2 ((volatile unsigned short *)CAN_MB22_DATA2)
+#define pCAN_MB22_DATA3 ((volatile unsigned short *)CAN_MB22_DATA3)
+#define pCAN_MB22_LENGTH ((volatile unsigned short *)CAN_MB22_LENGTH)
+#define pCAN_MB22_TIMESTAMP ((volatile unsigned short *)CAN_MB22_TIMESTAMP)
+#define pCAN_MB22_ID0 ((volatile unsigned short *)CAN_MB22_ID0)
+#define pCAN_MB22_ID1 ((volatile unsigned short *)CAN_MB22_ID1)
+
+#define pCAN_MB23_DATA0 ((volatile unsigned short *)CAN_MB23_DATA0)
+#define pCAN_MB23_DATA1 ((volatile unsigned short *)CAN_MB23_DATA1)
+#define pCAN_MB23_DATA2 ((volatile unsigned short *)CAN_MB23_DATA2)
+#define pCAN_MB23_DATA3 ((volatile unsigned short *)CAN_MB23_DATA3)
+#define pCAN_MB23_LENGTH ((volatile unsigned short *)CAN_MB23_LENGTH)
+#define pCAN_MB23_TIMESTAMP ((volatile unsigned short *)CAN_MB23_TIMESTAMP)
+#define pCAN_MB23_ID0 ((volatile unsigned short *)CAN_MB23_ID0)
+#define pCAN_MB23_ID1 ((volatile unsigned short *)CAN_MB23_ID1)
+
+#define pCAN_MB24_DATA0 ((volatile unsigned short *)CAN_MB24_DATA0)
+#define pCAN_MB24_DATA1 ((volatile unsigned short *)CAN_MB24_DATA1)
+#define pCAN_MB24_DATA2 ((volatile unsigned short *)CAN_MB24_DATA2)
+#define pCAN_MB24_DATA3 ((volatile unsigned short *)CAN_MB24_DATA3)
+#define pCAN_MB24_LENGTH ((volatile unsigned short *)CAN_MB24_LENGTH)
+#define pCAN_MB24_TIMESTAMP ((volatile unsigned short *)CAN_MB24_TIMESTAMP)
+#define pCAN_MB24_ID0 ((volatile unsigned short *)CAN_MB24_ID0)
+#define pCAN_MB24_ID1 ((volatile unsigned short *)CAN_MB24_ID1)
+
+#define pCAN_MB25_DATA0 ((volatile unsigned short *)CAN_MB25_DATA0)
+#define pCAN_MB25_DATA1 ((volatile unsigned short *)CAN_MB25_DATA1)
+#define pCAN_MB25_DATA2 ((volatile unsigned short *)CAN_MB25_DATA2)
+#define pCAN_MB25_DATA3 ((volatile unsigned short *)CAN_MB25_DATA3)
+#define pCAN_MB25_LENGTH ((volatile unsigned short *)CAN_MB25_LENGTH)
+#define pCAN_MB25_TIMESTAMP ((volatile unsigned short *)CAN_MB25_TIMESTAMP)
+#define pCAN_MB25_ID0 ((volatile unsigned short *)CAN_MB25_ID0)
+#define pCAN_MB25_ID1 ((volatile unsigned short *)CAN_MB25_ID1)
+
+#define pCAN_MB26_DATA0 ((volatile unsigned short *)CAN_MB26_DATA0)
+#define pCAN_MB26_DATA1 ((volatile unsigned short *)CAN_MB26_DATA1)
+#define pCAN_MB26_DATA2 ((volatile unsigned short *)CAN_MB26_DATA2)
+#define pCAN_MB26_DATA3 ((volatile unsigned short *)CAN_MB26_DATA3)
+#define pCAN_MB26_LENGTH ((volatile unsigned short *)CAN_MB26_LENGTH)
+#define pCAN_MB26_TIMESTAMP ((volatile unsigned short *)CAN_MB26_TIMESTAMP)
+#define pCAN_MB26_ID0 ((volatile unsigned short *)CAN_MB26_ID0)
+#define pCAN_MB26_ID1 ((volatile unsigned short *)CAN_MB26_ID1)
+
+#define pCAN_MB27_DATA0 ((volatile unsigned short *)CAN_MB27_DATA0)
+#define pCAN_MB27_DATA1 ((volatile unsigned short *)CAN_MB27_DATA1)
+#define pCAN_MB27_DATA2 ((volatile unsigned short *)CAN_MB27_DATA2)
+#define pCAN_MB27_DATA3 ((volatile unsigned short *)CAN_MB27_DATA3)
+#define pCAN_MB27_LENGTH ((volatile unsigned short *)CAN_MB27_LENGTH)
+#define pCAN_MB27_TIMESTAMP ((volatile unsigned short *)CAN_MB27_TIMESTAMP)
+#define pCAN_MB27_ID0 ((volatile unsigned short *)CAN_MB27_ID0)
+#define pCAN_MB27_ID1 ((volatile unsigned short *)CAN_MB27_ID1)
+
+#define pCAN_MB28_DATA0 ((volatile unsigned short *)CAN_MB28_DATA0)
+#define pCAN_MB28_DATA1 ((volatile unsigned short *)CAN_MB28_DATA1)
+#define pCAN_MB28_DATA2 ((volatile unsigned short *)CAN_MB28_DATA2)
+#define pCAN_MB28_DATA3 ((volatile unsigned short *)CAN_MB28_DATA3)
+#define pCAN_MB28_LENGTH ((volatile unsigned short *)CAN_MB28_LENGTH)
+#define pCAN_MB28_TIMESTAMP ((volatile unsigned short *)CAN_MB28_TIMESTAMP)
+#define pCAN_MB28_ID0 ((volatile unsigned short *)CAN_MB28_ID0)
+#define pCAN_MB28_ID1 ((volatile unsigned short *)CAN_MB28_ID1)
+
+#define pCAN_MB29_DATA0 ((volatile unsigned short *)CAN_MB29_DATA0)
+#define pCAN_MB29_DATA1 ((volatile unsigned short *)CAN_MB29_DATA1)
+#define pCAN_MB29_DATA2 ((volatile unsigned short *)CAN_MB29_DATA2)
+#define pCAN_MB29_DATA3 ((volatile unsigned short *)CAN_MB29_DATA3)
+#define pCAN_MB29_LENGTH ((volatile unsigned short *)CAN_MB29_LENGTH)
+#define pCAN_MB29_TIMESTAMP ((volatile unsigned short *)CAN_MB29_TIMESTAMP)
+#define pCAN_MB29_ID0 ((volatile unsigned short *)CAN_MB29_ID0)
+#define pCAN_MB29_ID1 ((volatile unsigned short *)CAN_MB29_ID1)
+
+#define pCAN_MB30_DATA0 ((volatile unsigned short *)CAN_MB30_DATA0)
+#define pCAN_MB30_DATA1 ((volatile unsigned short *)CAN_MB30_DATA1)
+#define pCAN_MB30_DATA2 ((volatile unsigned short *)CAN_MB30_DATA2)
+#define pCAN_MB30_DATA3 ((volatile unsigned short *)CAN_MB30_DATA3)
+#define pCAN_MB30_LENGTH ((volatile unsigned short *)CAN_MB30_LENGTH)
+#define pCAN_MB30_TIMESTAMP ((volatile unsigned short *)CAN_MB30_TIMESTAMP)
+#define pCAN_MB30_ID0 ((volatile unsigned short *)CAN_MB30_ID0)
+#define pCAN_MB30_ID1 ((volatile unsigned short *)CAN_MB30_ID1)
+
+#define pCAN_MB31_DATA0 ((volatile unsigned short *)CAN_MB31_DATA0)
+#define pCAN_MB31_DATA1 ((volatile unsigned short *)CAN_MB31_DATA1)
+#define pCAN_MB31_DATA2 ((volatile unsigned short *)CAN_MB31_DATA2)
+#define pCAN_MB31_DATA3 ((volatile unsigned short *)CAN_MB31_DATA3)
+#define pCAN_MB31_LENGTH ((volatile unsigned short *)CAN_MB31_LENGTH)
+#define pCAN_MB31_TIMESTAMP ((volatile unsigned short *)CAN_MB31_TIMESTAMP)
+#define pCAN_MB31_ID0 ((volatile unsigned short *)CAN_MB31_ID0)
+#define pCAN_MB31_ID1 ((volatile unsigned short *)CAN_MB31_ID1)
+
+
+/* CAN Mailbox Area Macros */
+#define pCAN_MB_ID1(x) ((volatile unsigned short *)CAN_MB_ID1(x))
+#define pCAN_MB_ID0(x) ((volatile unsigned short *)CAN_MB_ID0(x))
+#define pCAN_MB_TIMESTAMP(x) ((volatile unsigned short *)CAN_MB_TIMESTAMP(x))
+#define pCAN_MB_LENGTH(x) ((volatile unsigned short *)CAN_MB_LENGTH(x))
+#define pCAN_MB_DATA3(x) ((volatile unsigned short *)CAN_MB_DATA3(x))
+#define pCAN_MB_DATA2(x) ((volatile unsigned short *)CAN_MB_DATA2(x))
+#define pCAN_MB_DATA1(x) ((volatile unsigned short *)CAN_MB_DATA1(x))
+#define pCAN_MB_DATA0(x) ((volatile unsigned short *)CAN_MB_DATA0(x))
+
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define pCAN_CNF pCAN_DEBUG
+#define pTWI0_PRESCALE pTWI0_CONTROL
+#define pTWI0_INT_SRC pTWI0_INT_STAT
+#define pTWI0_INT_ENABLE pTWI0_INT_MASK
+#define pTWI1_PRESCALE pTWI1_CONTROL
+#define pTWI1_INT_SRC pTWI1_INT_STAT
+#define pTWI1_INT_ENABLE pTWI1_INT_MASK
+
+#endif /* _CDEF_BF539_H */
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * cdefBF53x.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifndef _CDEFBF53x_H
+#define _CDEFBF53x_H
+
+#include <sys/platform.h>
+
+#endif /* _CDEFBF53x_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF541.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF541 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF541_H
+#define _CDEF_BF541_H
+
+/* include all Core registers and bit definitions */
+#include <defBF541.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/** ADSP-BF541 is a non-existent processor -- no additional #defines **/
+
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+
+#endif /* _CDEF_BF541_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF542.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF542 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF542_H
+#define _CDEF_BF542_H
+
+/* include all Core registers and bit definitions */
+#include <defBF542.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
+
+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include <cdefBF54x_base.h>
+
+/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
+
+/* ATAPI Registers */
+
+#define pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
+#define pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
+#define pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
+#define pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
+#define pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
+#define pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
+#define pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
+#define pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
+#define pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
+#define pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
+#define pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
+#define pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
+#define pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
+#define pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
+#define pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
+#define pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
+#define pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
+#define pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
+#define pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
+#define pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
+#define pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
+#define pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
+#define pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
+#define pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
+#define pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
+
+/* SDH Registers */
+
+#define pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
+#define pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
+#define pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
+#define pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
+#define pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
+#define pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
+#define pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
+#define pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
+#define pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
+#define pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
+#define pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
+#define pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
+#define pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
+#define pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
+#define pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
+#define pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
+#define pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
+#define pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
+#define pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
+#define pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
+#define pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
+#define pSDH_CFG ((volatile unsigned short *)SDH_CFG)
+#define pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
+#define pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
+#define pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
+#define pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
+#define pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
+#define pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
+#define pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
+#define pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
+#define pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
+
+/* USB Control Registers */
+
+#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
+#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
+#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
+#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
+#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
+#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
+#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
+#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
+#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
+#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
+#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
+#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
+#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
+
+/* USB Packet Control Registers */
+
+#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
+#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
+#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
+#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
+#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
+#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
+#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
+#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
+#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
+#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
+#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
+#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
+#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
+
+/* USB Endpoint FIFO Registers */
+
+#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
+#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
+#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
+#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
+#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
+#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
+#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
+#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
+
+/* USB OTG Control Registers */
+
+#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
+#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
+#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
+
+/* USB Phy Control Registers */
+
+#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
+#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
+#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
+#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
+#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
+#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
+#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
+#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
+
+/* USB Endpoint 0 Control Registers */
+
+#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
+#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
+#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
+#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
+#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
+#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
+#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
+#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
+#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
+
+/* USB Endpoint 1 Control Registers */
+
+#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
+#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
+#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
+#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
+#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
+#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
+#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
+#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
+#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
+#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
+
+/* USB Endpoint 2 Control Registers */
+
+#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
+#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
+#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
+#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
+#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
+#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
+#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
+#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
+#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
+#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
+
+/* USB Endpoint 3 Control Registers */
+
+#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
+#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
+#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
+#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
+#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
+#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
+#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
+#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
+#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
+#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
+
+/* USB Endpoint 4 Control Registers */
+
+#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
+#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
+#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
+#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
+#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
+#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
+#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
+#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
+#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
+#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
+
+/* USB Endpoint 5 Control Registers */
+
+#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
+#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
+#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
+#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
+#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
+#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
+#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
+#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
+#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
+#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
+
+/* USB Endpoint 6 Control Registers */
+
+#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
+#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
+#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
+#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
+#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
+#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
+#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
+#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
+#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
+#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
+
+/* USB Endpoint 7 Control Registers */
+
+#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
+#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
+#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
+#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
+#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
+#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
+#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
+#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
+#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
+#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
+#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
+#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
+
+/* USB Channel 0 Config Registers */
+
+#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
+#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
+#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
+#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
+#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
+
+/* USB Channel 1 Config Registers */
+
+#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
+#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
+#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
+#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
+#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
+
+/* USB Channel 2 Config Registers */
+
+#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
+#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
+#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
+#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
+#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
+
+/* USB Channel 3 Config Registers */
+
+#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
+#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
+#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
+#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
+#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
+
+/* USB Channel 4 Config Registers */
+
+#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
+#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
+#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
+#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
+#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
+
+/* USB Channel 5 Config Registers */
+
+#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
+#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
+#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
+#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
+#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
+
+/* USB Channel 6 Config Registers */
+
+#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
+#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
+#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
+#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
+#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
+
+/* USB Channel 7 Config Registers */
+
+#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
+#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
+#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
+#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
+#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
+
+/* Keypad Registers */
+
+#define pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
+#define pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
+#define pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
+#define pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
+#define pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
+#define pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
+
+#endif /* _CDEF_BF542_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF544.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF544 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF544_H
+#define _CDEF_BF544_H
+
+/* include all Core registers and bit definitions */
+#include <defBF544.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
+
+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include <cdefBF54x_base.h>
+
+/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
+
+/* Timer Registers */
+
+#define pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
+#define pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
+#define pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
+#define pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
+#define pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
+#define pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
+#define pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
+#define pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
+#define pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
+#define pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
+#define pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
+#define pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
+
+/* Timer Group of 3 */
+
+#define pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
+#define pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
+#define pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
+
+/* EPPI0 Registers */
+
+#define pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
+#define pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
+#define pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
+#define pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
+#define pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
+#define pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
+#define pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
+#define pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
+#define pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
+#define pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
+#define pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
+#define pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
+#define pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
+#define pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
+#define pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
+#define pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
+#define pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
+#define pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
+#define pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
+#define pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
+#define pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
+#define pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
+#define pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
+#define pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
+#define pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
+#define pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
+#define pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
+#define pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
+#define pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define pCAN1_MC1 ((volatile unsigned short *)CAN1_MC1)
+#define pCAN1_MD1 ((volatile unsigned short *)CAN1_MD1)
+#define pCAN1_TRS1 ((volatile unsigned short *)CAN1_TRS1)
+#define pCAN1_TRR1 ((volatile unsigned short *)CAN1_TRR1)
+#define pCAN1_TA1 ((volatile unsigned short *)CAN1_TA1)
+#define pCAN1_AA1 ((volatile unsigned short *)CAN1_AA1)
+#define pCAN1_RMP1 ((volatile unsigned short *)CAN1_RMP1)
+#define pCAN1_RML1 ((volatile unsigned short *)CAN1_RML1)
+#define pCAN1_MBTIF1 ((volatile unsigned short *)CAN1_MBTIF1)
+#define pCAN1_MBRIF1 ((volatile unsigned short *)CAN1_MBRIF1)
+#define pCAN1_MBIM1 ((volatile unsigned short *)CAN1_MBIM1)
+#define pCAN1_RFH1 ((volatile unsigned short *)CAN1_RFH1)
+#define pCAN1_OPSS1 ((volatile unsigned short *)CAN1_OPSS1)
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define pCAN1_MC2 ((volatile unsigned short *)CAN1_MC2)
+#define pCAN1_MD2 ((volatile unsigned short *)CAN1_MD2)
+#define pCAN1_TRS2 ((volatile unsigned short *)CAN1_TRS2)
+#define pCAN1_TRR2 ((volatile unsigned short *)CAN1_TRR2)
+#define pCAN1_TA2 ((volatile unsigned short *)CAN1_TA2)
+#define pCAN1_AA2 ((volatile unsigned short *)CAN1_AA2)
+#define pCAN1_RMP2 ((volatile unsigned short *)CAN1_RMP2)
+#define pCAN1_RML2 ((volatile unsigned short *)CAN1_RML2)
+#define pCAN1_MBTIF2 ((volatile unsigned short *)CAN1_MBTIF2)
+#define pCAN1_MBRIF2 ((volatile unsigned short *)CAN1_MBRIF2)
+#define pCAN1_MBIM2 ((volatile unsigned short *)CAN1_MBIM2)
+#define pCAN1_RFH2 ((volatile unsigned short *)CAN1_RFH2)
+#define pCAN1_OPSS2 ((volatile unsigned short *)CAN1_OPSS2)
+
+/* CAN Controller 1 Clock/Interrupt/Counter Registers */
+
+#define pCAN1_CLOCK ((volatile unsigned short *)CAN1_CLOCK)
+#define pCAN1_TIMING ((volatile unsigned short *)CAN1_TIMING)
+#define pCAN1_DEBUG ((volatile unsigned short *)CAN1_DEBUG)
+#define pCAN1_STATUS ((volatile unsigned short *)CAN1_STATUS)
+#define pCAN1_CEC ((volatile unsigned short *)CAN1_CEC)
+#define pCAN1_GIS ((volatile unsigned short *)CAN1_GIS)
+#define pCAN1_GIM ((volatile unsigned short *)CAN1_GIM)
+#define pCAN1_GIF ((volatile unsigned short *)CAN1_GIF)
+#define pCAN1_CONTROL ((volatile unsigned short *)CAN1_CONTROL)
+#define pCAN1_INTR ((volatile unsigned short *)CAN1_INTR)
+#define pCAN1_MBTD ((volatile unsigned short *)CAN1_MBTD)
+#define pCAN1_EWR ((volatile unsigned short *)CAN1_EWR)
+#define pCAN1_ESR ((volatile unsigned short *)CAN1_ESR)
+#define pCAN1_UCCNT ((volatile unsigned short *)CAN1_UCCNT)
+#define pCAN1_UCRC ((volatile unsigned short *)CAN1_UCRC)
+#define pCAN1_UCCNF ((volatile unsigned short *)CAN1_UCCNF)
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define pCAN1_AM00L ((volatile unsigned short *)CAN1_AM00L)
+#define pCAN1_AM00H ((volatile unsigned short *)CAN1_AM00H)
+#define pCAN1_AM01L ((volatile unsigned short *)CAN1_AM01L)
+#define pCAN1_AM01H ((volatile unsigned short *)CAN1_AM01H)
+#define pCAN1_AM02L ((volatile unsigned short *)CAN1_AM02L)
+#define pCAN1_AM02H ((volatile unsigned short *)CAN1_AM02H)
+#define pCAN1_AM03L ((volatile unsigned short *)CAN1_AM03L)
+#define pCAN1_AM03H ((volatile unsigned short *)CAN1_AM03H)
+#define pCAN1_AM04L ((volatile unsigned short *)CAN1_AM04L)
+#define pCAN1_AM04H ((volatile unsigned short *)CAN1_AM04H)
+#define pCAN1_AM05L ((volatile unsigned short *)CAN1_AM05L)
+#define pCAN1_AM05H ((volatile unsigned short *)CAN1_AM05H)
+#define pCAN1_AM06L ((volatile unsigned short *)CAN1_AM06L)
+#define pCAN1_AM06H ((volatile unsigned short *)CAN1_AM06H)
+#define pCAN1_AM07L ((volatile unsigned short *)CAN1_AM07L)
+#define pCAN1_AM07H ((volatile unsigned short *)CAN1_AM07H)
+#define pCAN1_AM08L ((volatile unsigned short *)CAN1_AM08L)
+#define pCAN1_AM08H ((volatile unsigned short *)CAN1_AM08H)
+#define pCAN1_AM09L ((volatile unsigned short *)CAN1_AM09L)
+#define pCAN1_AM09H ((volatile unsigned short *)CAN1_AM09H)
+#define pCAN1_AM10L ((volatile unsigned short *)CAN1_AM10L)
+#define pCAN1_AM10H ((volatile unsigned short *)CAN1_AM10H)
+#define pCAN1_AM11L ((volatile unsigned short *)CAN1_AM11L)
+#define pCAN1_AM11H ((volatile unsigned short *)CAN1_AM11H)
+#define pCAN1_AM12L ((volatile unsigned short *)CAN1_AM12L)
+#define pCAN1_AM12H ((volatile unsigned short *)CAN1_AM12H)
+#define pCAN1_AM13L ((volatile unsigned short *)CAN1_AM13L)
+#define pCAN1_AM13H ((volatile unsigned short *)CAN1_AM13H)
+#define pCAN1_AM14L ((volatile unsigned short *)CAN1_AM14L)
+#define pCAN1_AM14H ((volatile unsigned short *)CAN1_AM14H)
+#define pCAN1_AM15L ((volatile unsigned short *)CAN1_AM15L)
+#define pCAN1_AM15H ((volatile unsigned short *)CAN1_AM15H)
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define pCAN1_AM16L ((volatile unsigned short *)CAN1_AM16L)
+#define pCAN1_AM16H ((volatile unsigned short *)CAN1_AM16H)
+#define pCAN1_AM17L ((volatile unsigned short *)CAN1_AM17L)
+#define pCAN1_AM17H ((volatile unsigned short *)CAN1_AM17H)
+#define pCAN1_AM18L ((volatile unsigned short *)CAN1_AM18L)
+#define pCAN1_AM18H ((volatile unsigned short *)CAN1_AM18H)
+#define pCAN1_AM19L ((volatile unsigned short *)CAN1_AM19L)
+#define pCAN1_AM19H ((volatile unsigned short *)CAN1_AM19H)
+#define pCAN1_AM20L ((volatile unsigned short *)CAN1_AM20L)
+#define pCAN1_AM20H ((volatile unsigned short *)CAN1_AM20H)
+#define pCAN1_AM21L ((volatile unsigned short *)CAN1_AM21L)
+#define pCAN1_AM21H ((volatile unsigned short *)CAN1_AM21H)
+#define pCAN1_AM22L ((volatile unsigned short *)CAN1_AM22L)
+#define pCAN1_AM22H ((volatile unsigned short *)CAN1_AM22H)
+#define pCAN1_AM23L ((volatile unsigned short *)CAN1_AM23L)
+#define pCAN1_AM23H ((volatile unsigned short *)CAN1_AM23H)
+#define pCAN1_AM24L ((volatile unsigned short *)CAN1_AM24L)
+#define pCAN1_AM24H ((volatile unsigned short *)CAN1_AM24H)
+#define pCAN1_AM25L ((volatile unsigned short *)CAN1_AM25L)
+#define pCAN1_AM25H ((volatile unsigned short *)CAN1_AM25H)
+#define pCAN1_AM26L ((volatile unsigned short *)CAN1_AM26L)
+#define pCAN1_AM26H ((volatile unsigned short *)CAN1_AM26H)
+#define pCAN1_AM27L ((volatile unsigned short *)CAN1_AM27L)
+#define pCAN1_AM27H ((volatile unsigned short *)CAN1_AM27H)
+#define pCAN1_AM28L ((volatile unsigned short *)CAN1_AM28L)
+#define pCAN1_AM28H ((volatile unsigned short *)CAN1_AM28H)
+#define pCAN1_AM29L ((volatile unsigned short *)CAN1_AM29L)
+#define pCAN1_AM29H ((volatile unsigned short *)CAN1_AM29H)
+#define pCAN1_AM30L ((volatile unsigned short *)CAN1_AM30L)
+#define pCAN1_AM30H ((volatile unsigned short *)CAN1_AM30H)
+#define pCAN1_AM31L ((volatile unsigned short *)CAN1_AM31L)
+#define pCAN1_AM31H ((volatile unsigned short *)CAN1_AM31H)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define pCAN1_MB00_DATA0 ((volatile unsigned short *)CAN1_MB00_DATA0)
+#define pCAN1_MB00_DATA1 ((volatile unsigned short *)CAN1_MB00_DATA1)
+#define pCAN1_MB00_DATA2 ((volatile unsigned short *)CAN1_MB00_DATA2)
+#define pCAN1_MB00_DATA3 ((volatile unsigned short *)CAN1_MB00_DATA3)
+#define pCAN1_MB00_LENGTH ((volatile unsigned short *)CAN1_MB00_LENGTH)
+#define pCAN1_MB00_TIMESTAMP ((volatile unsigned short *)CAN1_MB00_TIMESTAMP)
+#define pCAN1_MB00_ID0 ((volatile unsigned short *)CAN1_MB00_ID0)
+#define pCAN1_MB00_ID1 ((volatile unsigned short *)CAN1_MB00_ID1)
+#define pCAN1_MB01_DATA0 ((volatile unsigned short *)CAN1_MB01_DATA0)
+#define pCAN1_MB01_DATA1 ((volatile unsigned short *)CAN1_MB01_DATA1)
+#define pCAN1_MB01_DATA2 ((volatile unsigned short *)CAN1_MB01_DATA2)
+#define pCAN1_MB01_DATA3 ((volatile unsigned short *)CAN1_MB01_DATA3)
+#define pCAN1_MB01_LENGTH ((volatile unsigned short *)CAN1_MB01_LENGTH)
+#define pCAN1_MB01_TIMESTAMP ((volatile unsigned short *)CAN1_MB01_TIMESTAMP)
+#define pCAN1_MB01_ID0 ((volatile unsigned short *)CAN1_MB01_ID0)
+#define pCAN1_MB01_ID1 ((volatile unsigned short *)CAN1_MB01_ID1)
+#define pCAN1_MB02_DATA0 ((volatile unsigned short *)CAN1_MB02_DATA0)
+#define pCAN1_MB02_DATA1 ((volatile unsigned short *)CAN1_MB02_DATA1)
+#define pCAN1_MB02_DATA2 ((volatile unsigned short *)CAN1_MB02_DATA2)
+#define pCAN1_MB02_DATA3 ((volatile unsigned short *)CAN1_MB02_DATA3)
+#define pCAN1_MB02_LENGTH ((volatile unsigned short *)CAN1_MB02_LENGTH)
+#define pCAN1_MB02_TIMESTAMP ((volatile unsigned short *)CAN1_MB02_TIMESTAMP)
+#define pCAN1_MB02_ID0 ((volatile unsigned short *)CAN1_MB02_ID0)
+#define pCAN1_MB02_ID1 ((volatile unsigned short *)CAN1_MB02_ID1)
+#define pCAN1_MB03_DATA0 ((volatile unsigned short *)CAN1_MB03_DATA0)
+#define pCAN1_MB03_DATA1 ((volatile unsigned short *)CAN1_MB03_DATA1)
+#define pCAN1_MB03_DATA2 ((volatile unsigned short *)CAN1_MB03_DATA2)
+#define pCAN1_MB03_DATA3 ((volatile unsigned short *)CAN1_MB03_DATA3)
+#define pCAN1_MB03_LENGTH ((volatile unsigned short *)CAN1_MB03_LENGTH)
+#define pCAN1_MB03_TIMESTAMP ((volatile unsigned short *)CAN1_MB03_TIMESTAMP)
+#define pCAN1_MB03_ID0 ((volatile unsigned short *)CAN1_MB03_ID0)
+#define pCAN1_MB03_ID1 ((volatile unsigned short *)CAN1_MB03_ID1)
+#define pCAN1_MB04_DATA0 ((volatile unsigned short *)CAN1_MB04_DATA0)
+#define pCAN1_MB04_DATA1 ((volatile unsigned short *)CAN1_MB04_DATA1)
+#define pCAN1_MB04_DATA2 ((volatile unsigned short *)CAN1_MB04_DATA2)
+#define pCAN1_MB04_DATA3 ((volatile unsigned short *)CAN1_MB04_DATA3)
+#define pCAN1_MB04_LENGTH ((volatile unsigned short *)CAN1_MB04_LENGTH)
+#define pCAN1_MB04_TIMESTAMP ((volatile unsigned short *)CAN1_MB04_TIMESTAMP)
+#define pCAN1_MB04_ID0 ((volatile unsigned short *)CAN1_MB04_ID0)
+#define pCAN1_MB04_ID1 ((volatile unsigned short *)CAN1_MB04_ID1)
+#define pCAN1_MB05_DATA0 ((volatile unsigned short *)CAN1_MB05_DATA0)
+#define pCAN1_MB05_DATA1 ((volatile unsigned short *)CAN1_MB05_DATA1)
+#define pCAN1_MB05_DATA2 ((volatile unsigned short *)CAN1_MB05_DATA2)
+#define pCAN1_MB05_DATA3 ((volatile unsigned short *)CAN1_MB05_DATA3)
+#define pCAN1_MB05_LENGTH ((volatile unsigned short *)CAN1_MB05_LENGTH)
+#define pCAN1_MB05_TIMESTAMP ((volatile unsigned short *)CAN1_MB05_TIMESTAMP)
+#define pCAN1_MB05_ID0 ((volatile unsigned short *)CAN1_MB05_ID0)
+#define pCAN1_MB05_ID1 ((volatile unsigned short *)CAN1_MB05_ID1)
+#define pCAN1_MB06_DATA0 ((volatile unsigned short *)CAN1_MB06_DATA0)
+#define pCAN1_MB06_DATA1 ((volatile unsigned short *)CAN1_MB06_DATA1)
+#define pCAN1_MB06_DATA2 ((volatile unsigned short *)CAN1_MB06_DATA2)
+#define pCAN1_MB06_DATA3 ((volatile unsigned short *)CAN1_MB06_DATA3)
+#define pCAN1_MB06_LENGTH ((volatile unsigned short *)CAN1_MB06_LENGTH)
+#define pCAN1_MB06_TIMESTAMP ((volatile unsigned short *)CAN1_MB06_TIMESTAMP)
+#define pCAN1_MB06_ID0 ((volatile unsigned short *)CAN1_MB06_ID0)
+#define pCAN1_MB06_ID1 ((volatile unsigned short *)CAN1_MB06_ID1)
+#define pCAN1_MB07_DATA0 ((volatile unsigned short *)CAN1_MB07_DATA0)
+#define pCAN1_MB07_DATA1 ((volatile unsigned short *)CAN1_MB07_DATA1)
+#define pCAN1_MB07_DATA2 ((volatile unsigned short *)CAN1_MB07_DATA2)
+#define pCAN1_MB07_DATA3 ((volatile unsigned short *)CAN1_MB07_DATA3)
+#define pCAN1_MB07_LENGTH ((volatile unsigned short *)CAN1_MB07_LENGTH)
+#define pCAN1_MB07_TIMESTAMP ((volatile unsigned short *)CAN1_MB07_TIMESTAMP)
+#define pCAN1_MB07_ID0 ((volatile unsigned short *)CAN1_MB07_ID0)
+#define pCAN1_MB07_ID1 ((volatile unsigned short *)CAN1_MB07_ID1)
+#define pCAN1_MB08_DATA0 ((volatile unsigned short *)CAN1_MB08_DATA0)
+#define pCAN1_MB08_DATA1 ((volatile unsigned short *)CAN1_MB08_DATA1)
+#define pCAN1_MB08_DATA2 ((volatile unsigned short *)CAN1_MB08_DATA2)
+#define pCAN1_MB08_DATA3 ((volatile unsigned short *)CAN1_MB08_DATA3)
+#define pCAN1_MB08_LENGTH ((volatile unsigned short *)CAN1_MB08_LENGTH)
+#define pCAN1_MB08_TIMESTAMP ((volatile unsigned short *)CAN1_MB08_TIMESTAMP)
+#define pCAN1_MB08_ID0 ((volatile unsigned short *)CAN1_MB08_ID0)
+#define pCAN1_MB08_ID1 ((volatile unsigned short *)CAN1_MB08_ID1)
+#define pCAN1_MB09_DATA0 ((volatile unsigned short *)CAN1_MB09_DATA0)
+#define pCAN1_MB09_DATA1 ((volatile unsigned short *)CAN1_MB09_DATA1)
+#define pCAN1_MB09_DATA2 ((volatile unsigned short *)CAN1_MB09_DATA2)
+#define pCAN1_MB09_DATA3 ((volatile unsigned short *)CAN1_MB09_DATA3)
+#define pCAN1_MB09_LENGTH ((volatile unsigned short *)CAN1_MB09_LENGTH)
+#define pCAN1_MB09_TIMESTAMP ((volatile unsigned short *)CAN1_MB09_TIMESTAMP)
+#define pCAN1_MB09_ID0 ((volatile unsigned short *)CAN1_MB09_ID0)
+#define pCAN1_MB09_ID1 ((volatile unsigned short *)CAN1_MB09_ID1)
+#define pCAN1_MB10_DATA0 ((volatile unsigned short *)CAN1_MB10_DATA0)
+#define pCAN1_MB10_DATA1 ((volatile unsigned short *)CAN1_MB10_DATA1)
+#define pCAN1_MB10_DATA2 ((volatile unsigned short *)CAN1_MB10_DATA2)
+#define pCAN1_MB10_DATA3 ((volatile unsigned short *)CAN1_MB10_DATA3)
+#define pCAN1_MB10_LENGTH ((volatile unsigned short *)CAN1_MB10_LENGTH)
+#define pCAN1_MB10_TIMESTAMP ((volatile unsigned short *)CAN1_MB10_TIMESTAMP)
+#define pCAN1_MB10_ID0 ((volatile unsigned short *)CAN1_MB10_ID0)
+#define pCAN1_MB10_ID1 ((volatile unsigned short *)CAN1_MB10_ID1)
+#define pCAN1_MB11_DATA0 ((volatile unsigned short *)CAN1_MB11_DATA0)
+#define pCAN1_MB11_DATA1 ((volatile unsigned short *)CAN1_MB11_DATA1)
+#define pCAN1_MB11_DATA2 ((volatile unsigned short *)CAN1_MB11_DATA2)
+#define pCAN1_MB11_DATA3 ((volatile unsigned short *)CAN1_MB11_DATA3)
+#define pCAN1_MB11_LENGTH ((volatile unsigned short *)CAN1_MB11_LENGTH)
+#define pCAN1_MB11_TIMESTAMP ((volatile unsigned short *)CAN1_MB11_TIMESTAMP)
+#define pCAN1_MB11_ID0 ((volatile unsigned short *)CAN1_MB11_ID0)
+#define pCAN1_MB11_ID1 ((volatile unsigned short *)CAN1_MB11_ID1)
+#define pCAN1_MB12_DATA0 ((volatile unsigned short *)CAN1_MB12_DATA0)
+#define pCAN1_MB12_DATA1 ((volatile unsigned short *)CAN1_MB12_DATA1)
+#define pCAN1_MB12_DATA2 ((volatile unsigned short *)CAN1_MB12_DATA2)
+#define pCAN1_MB12_DATA3 ((volatile unsigned short *)CAN1_MB12_DATA3)
+#define pCAN1_MB12_LENGTH ((volatile unsigned short *)CAN1_MB12_LENGTH)
+#define pCAN1_MB12_TIMESTAMP ((volatile unsigned short *)CAN1_MB12_TIMESTAMP)
+#define pCAN1_MB12_ID0 ((volatile unsigned short *)CAN1_MB12_ID0)
+#define pCAN1_MB12_ID1 ((volatile unsigned short *)CAN1_MB12_ID1)
+#define pCAN1_MB13_DATA0 ((volatile unsigned short *)CAN1_MB13_DATA0)
+#define pCAN1_MB13_DATA1 ((volatile unsigned short *)CAN1_MB13_DATA1)
+#define pCAN1_MB13_DATA2 ((volatile unsigned short *)CAN1_MB13_DATA2)
+#define pCAN1_MB13_DATA3 ((volatile unsigned short *)CAN1_MB13_DATA3)
+#define pCAN1_MB13_LENGTH ((volatile unsigned short *)CAN1_MB13_LENGTH)
+#define pCAN1_MB13_TIMESTAMP ((volatile unsigned short *)CAN1_MB13_TIMESTAMP)
+#define pCAN1_MB13_ID0 ((volatile unsigned short *)CAN1_MB13_ID0)
+#define pCAN1_MB13_ID1 ((volatile unsigned short *)CAN1_MB13_ID1)
+#define pCAN1_MB14_DATA0 ((volatile unsigned short *)CAN1_MB14_DATA0)
+#define pCAN1_MB14_DATA1 ((volatile unsigned short *)CAN1_MB14_DATA1)
+#define pCAN1_MB14_DATA2 ((volatile unsigned short *)CAN1_MB14_DATA2)
+#define pCAN1_MB14_DATA3 ((volatile unsigned short *)CAN1_MB14_DATA3)
+#define pCAN1_MB14_LENGTH ((volatile unsigned short *)CAN1_MB14_LENGTH)
+#define pCAN1_MB14_TIMESTAMP ((volatile unsigned short *)CAN1_MB14_TIMESTAMP)
+#define pCAN1_MB14_ID0 ((volatile unsigned short *)CAN1_MB14_ID0)
+#define pCAN1_MB14_ID1 ((volatile unsigned short *)CAN1_MB14_ID1)
+#define pCAN1_MB15_DATA0 ((volatile unsigned short *)CAN1_MB15_DATA0)
+#define pCAN1_MB15_DATA1 ((volatile unsigned short *)CAN1_MB15_DATA1)
+#define pCAN1_MB15_DATA2 ((volatile unsigned short *)CAN1_MB15_DATA2)
+#define pCAN1_MB15_DATA3 ((volatile unsigned short *)CAN1_MB15_DATA3)
+#define pCAN1_MB15_LENGTH ((volatile unsigned short *)CAN1_MB15_LENGTH)
+#define pCAN1_MB15_TIMESTAMP ((volatile unsigned short *)CAN1_MB15_TIMESTAMP)
+#define pCAN1_MB15_ID0 ((volatile unsigned short *)CAN1_MB15_ID0)
+#define pCAN1_MB15_ID1 ((volatile unsigned short *)CAN1_MB15_ID1)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define pCAN1_MB16_DATA0 ((volatile unsigned short *)CAN1_MB16_DATA0)
+#define pCAN1_MB16_DATA1 ((volatile unsigned short *)CAN1_MB16_DATA1)
+#define pCAN1_MB16_DATA2 ((volatile unsigned short *)CAN1_MB16_DATA2)
+#define pCAN1_MB16_DATA3 ((volatile unsigned short *)CAN1_MB16_DATA3)
+#define pCAN1_MB16_LENGTH ((volatile unsigned short *)CAN1_MB16_LENGTH)
+#define pCAN1_MB16_TIMESTAMP ((volatile unsigned short *)CAN1_MB16_TIMESTAMP)
+#define pCAN1_MB16_ID0 ((volatile unsigned short *)CAN1_MB16_ID0)
+#define pCAN1_MB16_ID1 ((volatile unsigned short *)CAN1_MB16_ID1)
+#define pCAN1_MB17_DATA0 ((volatile unsigned short *)CAN1_MB17_DATA0)
+#define pCAN1_MB17_DATA1 ((volatile unsigned short *)CAN1_MB17_DATA1)
+#define pCAN1_MB17_DATA2 ((volatile unsigned short *)CAN1_MB17_DATA2)
+#define pCAN1_MB17_DATA3 ((volatile unsigned short *)CAN1_MB17_DATA3)
+#define pCAN1_MB17_LENGTH ((volatile unsigned short *)CAN1_MB17_LENGTH)
+#define pCAN1_MB17_TIMESTAMP ((volatile unsigned short *)CAN1_MB17_TIMESTAMP)
+#define pCAN1_MB17_ID0 ((volatile unsigned short *)CAN1_MB17_ID0)
+#define pCAN1_MB17_ID1 ((volatile unsigned short *)CAN1_MB17_ID1)
+#define pCAN1_MB18_DATA0 ((volatile unsigned short *)CAN1_MB18_DATA0)
+#define pCAN1_MB18_DATA1 ((volatile unsigned short *)CAN1_MB18_DATA1)
+#define pCAN1_MB18_DATA2 ((volatile unsigned short *)CAN1_MB18_DATA2)
+#define pCAN1_MB18_DATA3 ((volatile unsigned short *)CAN1_MB18_DATA3)
+#define pCAN1_MB18_LENGTH ((volatile unsigned short *)CAN1_MB18_LENGTH)
+#define pCAN1_MB18_TIMESTAMP ((volatile unsigned short *)CAN1_MB18_TIMESTAMP)
+#define pCAN1_MB18_ID0 ((volatile unsigned short *)CAN1_MB18_ID0)
+#define pCAN1_MB18_ID1 ((volatile unsigned short *)CAN1_MB18_ID1)
+#define pCAN1_MB19_DATA0 ((volatile unsigned short *)CAN1_MB19_DATA0)
+#define pCAN1_MB19_DATA1 ((volatile unsigned short *)CAN1_MB19_DATA1)
+#define pCAN1_MB19_DATA2 ((volatile unsigned short *)CAN1_MB19_DATA2)
+#define pCAN1_MB19_DATA3 ((volatile unsigned short *)CAN1_MB19_DATA3)
+#define pCAN1_MB19_LENGTH ((volatile unsigned short *)CAN1_MB19_LENGTH)
+#define pCAN1_MB19_TIMESTAMP ((volatile unsigned short *)CAN1_MB19_TIMESTAMP)
+#define pCAN1_MB19_ID0 ((volatile unsigned short *)CAN1_MB19_ID0)
+#define pCAN1_MB19_ID1 ((volatile unsigned short *)CAN1_MB19_ID1)
+#define pCAN1_MB20_DATA0 ((volatile unsigned short *)CAN1_MB20_DATA0)
+#define pCAN1_MB20_DATA1 ((volatile unsigned short *)CAN1_MB20_DATA1)
+#define pCAN1_MB20_DATA2 ((volatile unsigned short *)CAN1_MB20_DATA2)
+#define pCAN1_MB20_DATA3 ((volatile unsigned short *)CAN1_MB20_DATA3)
+#define pCAN1_MB20_LENGTH ((volatile unsigned short *)CAN1_MB20_LENGTH)
+#define pCAN1_MB20_TIMESTAMP ((volatile unsigned short *)CAN1_MB20_TIMESTAMP)
+#define pCAN1_MB20_ID0 ((volatile unsigned short *)CAN1_MB20_ID0)
+#define pCAN1_MB20_ID1 ((volatile unsigned short *)CAN1_MB20_ID1)
+#define pCAN1_MB21_DATA0 ((volatile unsigned short *)CAN1_MB21_DATA0)
+#define pCAN1_MB21_DATA1 ((volatile unsigned short *)CAN1_MB21_DATA1)
+#define pCAN1_MB21_DATA2 ((volatile unsigned short *)CAN1_MB21_DATA2)
+#define pCAN1_MB21_DATA3 ((volatile unsigned short *)CAN1_MB21_DATA3)
+#define pCAN1_MB21_LENGTH ((volatile unsigned short *)CAN1_MB21_LENGTH)
+#define pCAN1_MB21_TIMESTAMP ((volatile unsigned short *)CAN1_MB21_TIMESTAMP)
+#define pCAN1_MB21_ID0 ((volatile unsigned short *)CAN1_MB21_ID0)
+#define pCAN1_MB21_ID1 ((volatile unsigned short *)CAN1_MB21_ID1)
+#define pCAN1_MB22_DATA0 ((volatile unsigned short *)CAN1_MB22_DATA0)
+#define pCAN1_MB22_DATA1 ((volatile unsigned short *)CAN1_MB22_DATA1)
+#define pCAN1_MB22_DATA2 ((volatile unsigned short *)CAN1_MB22_DATA2)
+#define pCAN1_MB22_DATA3 ((volatile unsigned short *)CAN1_MB22_DATA3)
+#define pCAN1_MB22_LENGTH ((volatile unsigned short *)CAN1_MB22_LENGTH)
+#define pCAN1_MB22_TIMESTAMP ((volatile unsigned short *)CAN1_MB22_TIMESTAMP)
+#define pCAN1_MB22_ID0 ((volatile unsigned short *)CAN1_MB22_ID0)
+#define pCAN1_MB22_ID1 ((volatile unsigned short *)CAN1_MB22_ID1)
+#define pCAN1_MB23_DATA0 ((volatile unsigned short *)CAN1_MB23_DATA0)
+#define pCAN1_MB23_DATA1 ((volatile unsigned short *)CAN1_MB23_DATA1)
+#define pCAN1_MB23_DATA2 ((volatile unsigned short *)CAN1_MB23_DATA2)
+#define pCAN1_MB23_DATA3 ((volatile unsigned short *)CAN1_MB23_DATA3)
+#define pCAN1_MB23_LENGTH ((volatile unsigned short *)CAN1_MB23_LENGTH)
+#define pCAN1_MB23_TIMESTAMP ((volatile unsigned short *)CAN1_MB23_TIMESTAMP)
+#define pCAN1_MB23_ID0 ((volatile unsigned short *)CAN1_MB23_ID0)
+#define pCAN1_MB23_ID1 ((volatile unsigned short *)CAN1_MB23_ID1)
+#define pCAN1_MB24_DATA0 ((volatile unsigned short *)CAN1_MB24_DATA0)
+#define pCAN1_MB24_DATA1 ((volatile unsigned short *)CAN1_MB24_DATA1)
+#define pCAN1_MB24_DATA2 ((volatile unsigned short *)CAN1_MB24_DATA2)
+#define pCAN1_MB24_DATA3 ((volatile unsigned short *)CAN1_MB24_DATA3)
+#define pCAN1_MB24_LENGTH ((volatile unsigned short *)CAN1_MB24_LENGTH)
+#define pCAN1_MB24_TIMESTAMP ((volatile unsigned short *)CAN1_MB24_TIMESTAMP)
+#define pCAN1_MB24_ID0 ((volatile unsigned short *)CAN1_MB24_ID0)
+#define pCAN1_MB24_ID1 ((volatile unsigned short *)CAN1_MB24_ID1)
+#define pCAN1_MB25_DATA0 ((volatile unsigned short *)CAN1_MB25_DATA0)
+#define pCAN1_MB25_DATA1 ((volatile unsigned short *)CAN1_MB25_DATA1)
+#define pCAN1_MB25_DATA2 ((volatile unsigned short *)CAN1_MB25_DATA2)
+#define pCAN1_MB25_DATA3 ((volatile unsigned short *)CAN1_MB25_DATA3)
+#define pCAN1_MB25_LENGTH ((volatile unsigned short *)CAN1_MB25_LENGTH)
+#define pCAN1_MB25_TIMESTAMP ((volatile unsigned short *)CAN1_MB25_TIMESTAMP)
+#define pCAN1_MB25_ID0 ((volatile unsigned short *)CAN1_MB25_ID0)
+#define pCAN1_MB25_ID1 ((volatile unsigned short *)CAN1_MB25_ID1)
+#define pCAN1_MB26_DATA0 ((volatile unsigned short *)CAN1_MB26_DATA0)
+#define pCAN1_MB26_DATA1 ((volatile unsigned short *)CAN1_MB26_DATA1)
+#define pCAN1_MB26_DATA2 ((volatile unsigned short *)CAN1_MB26_DATA2)
+#define pCAN1_MB26_DATA3 ((volatile unsigned short *)CAN1_MB26_DATA3)
+#define pCAN1_MB26_LENGTH ((volatile unsigned short *)CAN1_MB26_LENGTH)
+#define pCAN1_MB26_TIMESTAMP ((volatile unsigned short *)CAN1_MB26_TIMESTAMP)
+#define pCAN1_MB26_ID0 ((volatile unsigned short *)CAN1_MB26_ID0)
+#define pCAN1_MB26_ID1 ((volatile unsigned short *)CAN1_MB26_ID1)
+#define pCAN1_MB27_DATA0 ((volatile unsigned short *)CAN1_MB27_DATA0)
+#define pCAN1_MB27_DATA1 ((volatile unsigned short *)CAN1_MB27_DATA1)
+#define pCAN1_MB27_DATA2 ((volatile unsigned short *)CAN1_MB27_DATA2)
+#define pCAN1_MB27_DATA3 ((volatile unsigned short *)CAN1_MB27_DATA3)
+#define pCAN1_MB27_LENGTH ((volatile unsigned short *)CAN1_MB27_LENGTH)
+#define pCAN1_MB27_TIMESTAMP ((volatile unsigned short *)CAN1_MB27_TIMESTAMP)
+#define pCAN1_MB27_ID0 ((volatile unsigned short *)CAN1_MB27_ID0)
+#define pCAN1_MB27_ID1 ((volatile unsigned short *)CAN1_MB27_ID1)
+#define pCAN1_MB28_DATA0 ((volatile unsigned short *)CAN1_MB28_DATA0)
+#define pCAN1_MB28_DATA1 ((volatile unsigned short *)CAN1_MB28_DATA1)
+#define pCAN1_MB28_DATA2 ((volatile unsigned short *)CAN1_MB28_DATA2)
+#define pCAN1_MB28_DATA3 ((volatile unsigned short *)CAN1_MB28_DATA3)
+#define pCAN1_MB28_LENGTH ((volatile unsigned short *)CAN1_MB28_LENGTH)
+#define pCAN1_MB28_TIMESTAMP ((volatile unsigned short *)CAN1_MB28_TIMESTAMP)
+#define pCAN1_MB28_ID0 ((volatile unsigned short *)CAN1_MB28_ID0)
+#define pCAN1_MB28_ID1 ((volatile unsigned short *)CAN1_MB28_ID1)
+#define pCAN1_MB29_DATA0 ((volatile unsigned short *)CAN1_MB29_DATA0)
+#define pCAN1_MB29_DATA1 ((volatile unsigned short *)CAN1_MB29_DATA1)
+#define pCAN1_MB29_DATA2 ((volatile unsigned short *)CAN1_MB29_DATA2)
+#define pCAN1_MB29_DATA3 ((volatile unsigned short *)CAN1_MB29_DATA3)
+#define pCAN1_MB29_LENGTH ((volatile unsigned short *)CAN1_MB29_LENGTH)
+#define pCAN1_MB29_TIMESTAMP ((volatile unsigned short *)CAN1_MB29_TIMESTAMP)
+#define pCAN1_MB29_ID0 ((volatile unsigned short *)CAN1_MB29_ID0)
+#define pCAN1_MB29_ID1 ((volatile unsigned short *)CAN1_MB29_ID1)
+#define pCAN1_MB30_DATA0 ((volatile unsigned short *)CAN1_MB30_DATA0)
+#define pCAN1_MB30_DATA1 ((volatile unsigned short *)CAN1_MB30_DATA1)
+#define pCAN1_MB30_DATA2 ((volatile unsigned short *)CAN1_MB30_DATA2)
+#define pCAN1_MB30_DATA3 ((volatile unsigned short *)CAN1_MB30_DATA3)
+#define pCAN1_MB30_LENGTH ((volatile unsigned short *)CAN1_MB30_LENGTH)
+#define pCAN1_MB30_TIMESTAMP ((volatile unsigned short *)CAN1_MB30_TIMESTAMP)
+#define pCAN1_MB30_ID0 ((volatile unsigned short *)CAN1_MB30_ID0)
+#define pCAN1_MB30_ID1 ((volatile unsigned short *)CAN1_MB30_ID1)
+#define pCAN1_MB31_DATA0 ((volatile unsigned short *)CAN1_MB31_DATA0)
+#define pCAN1_MB31_DATA1 ((volatile unsigned short *)CAN1_MB31_DATA1)
+#define pCAN1_MB31_DATA2 ((volatile unsigned short *)CAN1_MB31_DATA2)
+#define pCAN1_MB31_DATA3 ((volatile unsigned short *)CAN1_MB31_DATA3)
+#define pCAN1_MB31_LENGTH ((volatile unsigned short *)CAN1_MB31_LENGTH)
+#define pCAN1_MB31_TIMESTAMP ((volatile unsigned short *)CAN1_MB31_TIMESTAMP)
+#define pCAN1_MB31_ID0 ((volatile unsigned short *)CAN1_MB31_ID0)
+#define pCAN1_MB31_ID1 ((volatile unsigned short *)CAN1_MB31_ID1)
+
+/* HOST Port Registers */
+
+#define pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
+#define pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
+#define pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
+#define pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
+#define pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
+#define pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
+#define pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
+#define pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
+#define pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
+#define pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
+#define pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
+#define pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
+#define pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
+#define pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
+#define pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
+#define pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
+#define pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
+#define pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
+#define pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
+#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
+#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
+
+#endif /* _CDEF_BF544_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF547.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF547 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF547_H
+#define _CDEF_BF547_H
+
+/* include all Core registers and bit definitions */
+#include <defBF547.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
+
+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include <cdefBF54x_base.h>
+
+/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
+
+/* Timer Registers */
+
+#define pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
+#define pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
+#define pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
+#define pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
+#define pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
+#define pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
+#define pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
+#define pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
+#define pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
+#define pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
+#define pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
+#define pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
+
+/* Timer Group of 3 */
+
+#define pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
+#define pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
+#define pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
+
+/* SPORT0 Registers */
+
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+/* EPPI0 Registers */
+
+#define pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
+#define pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
+#define pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
+#define pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
+#define pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
+#define pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
+#define pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
+#define pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
+#define pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
+#define pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
+#define pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
+#define pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
+#define pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
+#define pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
+
+/* UART2 Registers */
+
+#define pUART2_DLL ((volatile unsigned short *)UART2_DLL)
+#define pUART2_DLH ((volatile unsigned short *)UART2_DLH)
+#define pUART2_GCTL ((volatile unsigned short *)UART2_GCTL)
+#define pUART2_LCR ((volatile unsigned short *)UART2_LCR)
+#define pUART2_MCR ((volatile unsigned short *)UART2_MCR)
+#define pUART2_LSR ((volatile unsigned short *)UART2_LSR)
+#define pUART2_MSR ((volatile unsigned short *)UART2_MSR)
+#define pUART2_SCR ((volatile unsigned short *)UART2_SCR)
+#define pUART2_IER_SET ((volatile unsigned short *)UART2_IER_SET)
+#define pUART2_IER_CLEAR ((volatile unsigned short *)UART2_IER_CLEAR)
+#define pUART2_THR ((volatile unsigned short *)UART2_THR)
+#define pUART2_RBR ((volatile unsigned short *)UART2_RBR)
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
+#define pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
+#define pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
+#define pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
+#define pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
+#define pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
+#define pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
+#define pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
+#define pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
+#define pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
+#define pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
+#define pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
+#define pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
+#define pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
+#define pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
+#define pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
+
+/* SPI2 Registers */
+
+#define pSPI2_CTL ((volatile unsigned short *)SPI2_CTL)
+#define pSPI2_FLG ((volatile unsigned short *)SPI2_FLG)
+#define pSPI2_STAT ((volatile unsigned short *)SPI2_STAT)
+#define pSPI2_TDBR ((volatile unsigned short *)SPI2_TDBR)
+#define pSPI2_RDBR ((volatile unsigned short *)SPI2_RDBR)
+#define pSPI2_BAUD ((volatile unsigned short *)SPI2_BAUD)
+#define pSPI2_SHADOW ((volatile unsigned short *)SPI2_SHADOW)
+
+/* ATAPI Registers */
+
+#define pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
+#define pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
+#define pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
+#define pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
+#define pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
+#define pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
+#define pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
+#define pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
+#define pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
+#define pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
+#define pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
+#define pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
+#define pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
+#define pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
+#define pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
+#define pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
+#define pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
+#define pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
+#define pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
+#define pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
+#define pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
+#define pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
+#define pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
+#define pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
+#define pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
+
+/* SDH Registers */
+
+#define pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
+#define pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
+#define pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
+#define pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
+#define pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
+#define pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
+#define pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
+#define pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
+#define pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
+#define pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
+#define pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
+#define pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
+#define pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
+#define pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
+#define pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
+#define pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
+#define pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
+#define pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
+#define pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
+#define pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
+#define pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
+#define pSDH_CFG ((volatile unsigned short *)SDH_CFG)
+#define pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
+#define pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
+#define pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
+#define pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
+#define pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
+#define pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
+#define pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
+#define pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
+#define pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
+
+/* HOST Port Registers */
+
+#define pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
+#define pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
+#define pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
+
+/* USB Control Registers */
+
+#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
+#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
+#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
+#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
+#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
+#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
+#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
+#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
+#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
+#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
+#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
+#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
+#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
+
+/* USB Packet Control Registers */
+
+#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
+#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
+#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
+#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
+#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
+#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
+#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
+#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
+#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
+#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
+#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
+#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
+#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
+
+/* USB Endpoint FIFO Registers */
+
+#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
+#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
+#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
+#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
+#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
+#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
+#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
+#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
+
+/* USB OTG Control Registers */
+
+#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
+#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
+#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
+
+/* USB Phy Control Registers */
+
+#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
+#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
+#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
+#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
+#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
+#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
+#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
+#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
+
+/* USB Endpoint 0 Control Registers */
+
+#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
+#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
+#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
+#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
+#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
+#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
+#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
+#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
+#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
+
+/* USB Endpoint 1 Control Registers */
+
+#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
+#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
+#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
+#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
+#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
+#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
+#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
+#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
+#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
+#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
+
+/* USB Endpoint 2 Control Registers */
+
+#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
+#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
+#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
+#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
+#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
+#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
+#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
+#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
+#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
+#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
+
+/* USB Endpoint 3 Control Registers */
+
+#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
+#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
+#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
+#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
+#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
+#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
+#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
+#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
+#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
+#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
+
+/* USB Endpoint 4 Control Registers */
+
+#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
+#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
+#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
+#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
+#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
+#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
+#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
+#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
+#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
+#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
+
+/* USB Endpoint 5 Control Registers */
+
+#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
+#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
+#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
+#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
+#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
+#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
+#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
+#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
+#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
+#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
+
+/* USB Endpoint 6 Control Registers */
+
+#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
+#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
+#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
+#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
+#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
+#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
+#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
+#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
+#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
+#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
+
+/* USB Endpoint 7 Control Registers */
+
+#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
+#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
+#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
+#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
+#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
+#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
+#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
+#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
+#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
+#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
+#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
+#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
+
+/* USB Channel 0 Config Registers */
+
+#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
+#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
+#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
+#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
+#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
+
+/* USB Channel 1 Config Registers */
+
+#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
+#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
+#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
+#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
+#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
+
+/* USB Channel 2 Config Registers */
+
+#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
+#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
+#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
+#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
+#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
+
+/* USB Channel 3 Config Registers */
+
+#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
+#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
+#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
+#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
+#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
+
+/* USB Channel 4 Config Registers */
+
+#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
+#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
+#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
+#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
+#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
+
+/* USB Channel 5 Config Registers */
+
+#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
+#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
+#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
+#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
+#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
+
+/* USB Channel 6 Config Registers */
+
+#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
+#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
+#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
+#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
+#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
+
+/* USB Channel 7 Config Registers */
+
+#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
+#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
+#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
+#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
+#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
+
+/* Keypad Registers */
+
+#define pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
+#define pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
+#define pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
+#define pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
+#define pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
+#define pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
+#define pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
+#define pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
+#define pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
+#define pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
+#define pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
+#define pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
+#define pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
+#define pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
+#define pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
+#define pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
+#define pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
+#define pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
+#define pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
+#define pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
+#define pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
+#define pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
+#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
+#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
+
+#endif /* _CDEF_BF547_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF548.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF548 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF548_H
+#define _CDEF_BF548_H
+
+/* include all Core registers and bit definitions */
+#include <defBF548.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
+
+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include <cdefBF54x_base.h>
+
+/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
+
+/* Timer Registers */
+
+#define pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
+#define pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
+#define pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
+#define pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
+#define pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
+#define pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
+#define pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
+#define pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
+#define pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
+#define pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
+#define pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
+#define pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
+
+/* Timer Group of 3 */
+
+#define pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
+#define pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
+#define pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
+
+/* SPORT0 Registers */
+
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+/* EPPI0 Registers */
+
+#define pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
+#define pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
+#define pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
+#define pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
+#define pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
+#define pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
+#define pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
+#define pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
+#define pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
+#define pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
+#define pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
+#define pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
+#define pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
+#define pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
+
+/* UART2 Registers */
+
+#define pUART2_DLL ((volatile unsigned short *)UART2_DLL)
+#define pUART2_DLH ((volatile unsigned short *)UART2_DLH)
+#define pUART2_GCTL ((volatile unsigned short *)UART2_GCTL)
+#define pUART2_LCR ((volatile unsigned short *)UART2_LCR)
+#define pUART2_MCR ((volatile unsigned short *)UART2_MCR)
+#define pUART2_LSR ((volatile unsigned short *)UART2_LSR)
+#define pUART2_MSR ((volatile unsigned short *)UART2_MSR)
+#define pUART2_SCR ((volatile unsigned short *)UART2_SCR)
+#define pUART2_IER_SET ((volatile unsigned short *)UART2_IER_SET)
+#define pUART2_IER_CLEAR ((volatile unsigned short *)UART2_IER_CLEAR)
+#define pUART2_THR ((volatile unsigned short *)UART2_THR)
+#define pUART2_RBR ((volatile unsigned short *)UART2_RBR)
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
+#define pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
+#define pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
+#define pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
+#define pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
+#define pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
+#define pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
+#define pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
+#define pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
+#define pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
+#define pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
+#define pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
+#define pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
+#define pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
+#define pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
+#define pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
+
+/* SPI2 Registers */
+
+#define pSPI2_CTL ((volatile unsigned short *)SPI2_CTL)
+#define pSPI2_FLG ((volatile unsigned short *)SPI2_FLG)
+#define pSPI2_STAT ((volatile unsigned short *)SPI2_STAT)
+#define pSPI2_TDBR ((volatile unsigned short *)SPI2_TDBR)
+#define pSPI2_RDBR ((volatile unsigned short *)SPI2_RDBR)
+#define pSPI2_BAUD ((volatile unsigned short *)SPI2_BAUD)
+#define pSPI2_SHADOW ((volatile unsigned short *)SPI2_SHADOW)
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define pCAN1_MC1 ((volatile unsigned short *)CAN1_MC1)
+#define pCAN1_MD1 ((volatile unsigned short *)CAN1_MD1)
+#define pCAN1_TRS1 ((volatile unsigned short *)CAN1_TRS1)
+#define pCAN1_TRR1 ((volatile unsigned short *)CAN1_TRR1)
+#define pCAN1_TA1 ((volatile unsigned short *)CAN1_TA1)
+#define pCAN1_AA1 ((volatile unsigned short *)CAN1_AA1)
+#define pCAN1_RMP1 ((volatile unsigned short *)CAN1_RMP1)
+#define pCAN1_RML1 ((volatile unsigned short *)CAN1_RML1)
+#define pCAN1_MBTIF1 ((volatile unsigned short *)CAN1_MBTIF1)
+#define pCAN1_MBRIF1 ((volatile unsigned short *)CAN1_MBRIF1)
+#define pCAN1_MBIM1 ((volatile unsigned short *)CAN1_MBIM1)
+#define pCAN1_RFH1 ((volatile unsigned short *)CAN1_RFH1)
+#define pCAN1_OPSS1 ((volatile unsigned short *)CAN1_OPSS1)
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define pCAN1_MC2 ((volatile unsigned short *)CAN1_MC2)
+#define pCAN1_MD2 ((volatile unsigned short *)CAN1_MD2)
+#define pCAN1_TRS2 ((volatile unsigned short *)CAN1_TRS2)
+#define pCAN1_TRR2 ((volatile unsigned short *)CAN1_TRR2)
+#define pCAN1_TA2 ((volatile unsigned short *)CAN1_TA2)
+#define pCAN1_AA2 ((volatile unsigned short *)CAN1_AA2)
+#define pCAN1_RMP2 ((volatile unsigned short *)CAN1_RMP2)
+#define pCAN1_RML2 ((volatile unsigned short *)CAN1_RML2)
+#define pCAN1_MBTIF2 ((volatile unsigned short *)CAN1_MBTIF2)
+#define pCAN1_MBRIF2 ((volatile unsigned short *)CAN1_MBRIF2)
+#define pCAN1_MBIM2 ((volatile unsigned short *)CAN1_MBIM2)
+#define pCAN1_RFH2 ((volatile unsigned short *)CAN1_RFH2)
+#define pCAN1_OPSS2 ((volatile unsigned short *)CAN1_OPSS2)
+
+/* CAN Controller 1 Clock/Interrupt/Counter Registers */
+
+#define pCAN1_CLOCK ((volatile unsigned short *)CAN1_CLOCK)
+#define pCAN1_TIMING ((volatile unsigned short *)CAN1_TIMING)
+#define pCAN1_DEBUG ((volatile unsigned short *)CAN1_DEBUG)
+#define pCAN1_STATUS ((volatile unsigned short *)CAN1_STATUS)
+#define pCAN1_CEC ((volatile unsigned short *)CAN1_CEC)
+#define pCAN1_GIS ((volatile unsigned short *)CAN1_GIS)
+#define pCAN1_GIM ((volatile unsigned short *)CAN1_GIM)
+#define pCAN1_GIF ((volatile unsigned short *)CAN1_GIF)
+#define pCAN1_CONTROL ((volatile unsigned short *)CAN1_CONTROL)
+#define pCAN1_INTR ((volatile unsigned short *)CAN1_INTR)
+#define pCAN1_MBTD ((volatile unsigned short *)CAN1_MBTD)
+#define pCAN1_EWR ((volatile unsigned short *)CAN1_EWR)
+#define pCAN1_ESR ((volatile unsigned short *)CAN1_ESR)
+#define pCAN1_UCCNT ((volatile unsigned short *)CAN1_UCCNT)
+#define pCAN1_UCRC ((volatile unsigned short *)CAN1_UCRC)
+#define pCAN1_UCCNF ((volatile unsigned short *)CAN1_UCCNF)
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define pCAN1_AM00L ((volatile unsigned short *)CAN1_AM00L)
+#define pCAN1_AM00H ((volatile unsigned short *)CAN1_AM00H)
+#define pCAN1_AM01L ((volatile unsigned short *)CAN1_AM01L)
+#define pCAN1_AM01H ((volatile unsigned short *)CAN1_AM01H)
+#define pCAN1_AM02L ((volatile unsigned short *)CAN1_AM02L)
+#define pCAN1_AM02H ((volatile unsigned short *)CAN1_AM02H)
+#define pCAN1_AM03L ((volatile unsigned short *)CAN1_AM03L)
+#define pCAN1_AM03H ((volatile unsigned short *)CAN1_AM03H)
+#define pCAN1_AM04L ((volatile unsigned short *)CAN1_AM04L)
+#define pCAN1_AM04H ((volatile unsigned short *)CAN1_AM04H)
+#define pCAN1_AM05L ((volatile unsigned short *)CAN1_AM05L)
+#define pCAN1_AM05H ((volatile unsigned short *)CAN1_AM05H)
+#define pCAN1_AM06L ((volatile unsigned short *)CAN1_AM06L)
+#define pCAN1_AM06H ((volatile unsigned short *)CAN1_AM06H)
+#define pCAN1_AM07L ((volatile unsigned short *)CAN1_AM07L)
+#define pCAN1_AM07H ((volatile unsigned short *)CAN1_AM07H)
+#define pCAN1_AM08L ((volatile unsigned short *)CAN1_AM08L)
+#define pCAN1_AM08H ((volatile unsigned short *)CAN1_AM08H)
+#define pCAN1_AM09L ((volatile unsigned short *)CAN1_AM09L)
+#define pCAN1_AM09H ((volatile unsigned short *)CAN1_AM09H)
+#define pCAN1_AM10L ((volatile unsigned short *)CAN1_AM10L)
+#define pCAN1_AM10H ((volatile unsigned short *)CAN1_AM10H)
+#define pCAN1_AM11L ((volatile unsigned short *)CAN1_AM11L)
+#define pCAN1_AM11H ((volatile unsigned short *)CAN1_AM11H)
+#define pCAN1_AM12L ((volatile unsigned short *)CAN1_AM12L)
+#define pCAN1_AM12H ((volatile unsigned short *)CAN1_AM12H)
+#define pCAN1_AM13L ((volatile unsigned short *)CAN1_AM13L)
+#define pCAN1_AM13H ((volatile unsigned short *)CAN1_AM13H)
+#define pCAN1_AM14L ((volatile unsigned short *)CAN1_AM14L)
+#define pCAN1_AM14H ((volatile unsigned short *)CAN1_AM14H)
+#define pCAN1_AM15L ((volatile unsigned short *)CAN1_AM15L)
+#define pCAN1_AM15H ((volatile unsigned short *)CAN1_AM15H)
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define pCAN1_AM16L ((volatile unsigned short *)CAN1_AM16L)
+#define pCAN1_AM16H ((volatile unsigned short *)CAN1_AM16H)
+#define pCAN1_AM17L ((volatile unsigned short *)CAN1_AM17L)
+#define pCAN1_AM17H ((volatile unsigned short *)CAN1_AM17H)
+#define pCAN1_AM18L ((volatile unsigned short *)CAN1_AM18L)
+#define pCAN1_AM18H ((volatile unsigned short *)CAN1_AM18H)
+#define pCAN1_AM19L ((volatile unsigned short *)CAN1_AM19L)
+#define pCAN1_AM19H ((volatile unsigned short *)CAN1_AM19H)
+#define pCAN1_AM20L ((volatile unsigned short *)CAN1_AM20L)
+#define pCAN1_AM20H ((volatile unsigned short *)CAN1_AM20H)
+#define pCAN1_AM21L ((volatile unsigned short *)CAN1_AM21L)
+#define pCAN1_AM21H ((volatile unsigned short *)CAN1_AM21H)
+#define pCAN1_AM22L ((volatile unsigned short *)CAN1_AM22L)
+#define pCAN1_AM22H ((volatile unsigned short *)CAN1_AM22H)
+#define pCAN1_AM23L ((volatile unsigned short *)CAN1_AM23L)
+#define pCAN1_AM23H ((volatile unsigned short *)CAN1_AM23H)
+#define pCAN1_AM24L ((volatile unsigned short *)CAN1_AM24L)
+#define pCAN1_AM24H ((volatile unsigned short *)CAN1_AM24H)
+#define pCAN1_AM25L ((volatile unsigned short *)CAN1_AM25L)
+#define pCAN1_AM25H ((volatile unsigned short *)CAN1_AM25H)
+#define pCAN1_AM26L ((volatile unsigned short *)CAN1_AM26L)
+#define pCAN1_AM26H ((volatile unsigned short *)CAN1_AM26H)
+#define pCAN1_AM27L ((volatile unsigned short *)CAN1_AM27L)
+#define pCAN1_AM27H ((volatile unsigned short *)CAN1_AM27H)
+#define pCAN1_AM28L ((volatile unsigned short *)CAN1_AM28L)
+#define pCAN1_AM28H ((volatile unsigned short *)CAN1_AM28H)
+#define pCAN1_AM29L ((volatile unsigned short *)CAN1_AM29L)
+#define pCAN1_AM29H ((volatile unsigned short *)CAN1_AM29H)
+#define pCAN1_AM30L ((volatile unsigned short *)CAN1_AM30L)
+#define pCAN1_AM30H ((volatile unsigned short *)CAN1_AM30H)
+#define pCAN1_AM31L ((volatile unsigned short *)CAN1_AM31L)
+#define pCAN1_AM31H ((volatile unsigned short *)CAN1_AM31H)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define pCAN1_MB00_DATA0 ((volatile unsigned short *)CAN1_MB00_DATA0)
+#define pCAN1_MB00_DATA1 ((volatile unsigned short *)CAN1_MB00_DATA1)
+#define pCAN1_MB00_DATA2 ((volatile unsigned short *)CAN1_MB00_DATA2)
+#define pCAN1_MB00_DATA3 ((volatile unsigned short *)CAN1_MB00_DATA3)
+#define pCAN1_MB00_LENGTH ((volatile unsigned short *)CAN1_MB00_LENGTH)
+#define pCAN1_MB00_TIMESTAMP ((volatile unsigned short *)CAN1_MB00_TIMESTAMP)
+#define pCAN1_MB00_ID0 ((volatile unsigned short *)CAN1_MB00_ID0)
+#define pCAN1_MB00_ID1 ((volatile unsigned short *)CAN1_MB00_ID1)
+#define pCAN1_MB01_DATA0 ((volatile unsigned short *)CAN1_MB01_DATA0)
+#define pCAN1_MB01_DATA1 ((volatile unsigned short *)CAN1_MB01_DATA1)
+#define pCAN1_MB01_DATA2 ((volatile unsigned short *)CAN1_MB01_DATA2)
+#define pCAN1_MB01_DATA3 ((volatile unsigned short *)CAN1_MB01_DATA3)
+#define pCAN1_MB01_LENGTH ((volatile unsigned short *)CAN1_MB01_LENGTH)
+#define pCAN1_MB01_TIMESTAMP ((volatile unsigned short *)CAN1_MB01_TIMESTAMP)
+#define pCAN1_MB01_ID0 ((volatile unsigned short *)CAN1_MB01_ID0)
+#define pCAN1_MB01_ID1 ((volatile unsigned short *)CAN1_MB01_ID1)
+#define pCAN1_MB02_DATA0 ((volatile unsigned short *)CAN1_MB02_DATA0)
+#define pCAN1_MB02_DATA1 ((volatile unsigned short *)CAN1_MB02_DATA1)
+#define pCAN1_MB02_DATA2 ((volatile unsigned short *)CAN1_MB02_DATA2)
+#define pCAN1_MB02_DATA3 ((volatile unsigned short *)CAN1_MB02_DATA3)
+#define pCAN1_MB02_LENGTH ((volatile unsigned short *)CAN1_MB02_LENGTH)
+#define pCAN1_MB02_TIMESTAMP ((volatile unsigned short *)CAN1_MB02_TIMESTAMP)
+#define pCAN1_MB02_ID0 ((volatile unsigned short *)CAN1_MB02_ID0)
+#define pCAN1_MB02_ID1 ((volatile unsigned short *)CAN1_MB02_ID1)
+#define pCAN1_MB03_DATA0 ((volatile unsigned short *)CAN1_MB03_DATA0)
+#define pCAN1_MB03_DATA1 ((volatile unsigned short *)CAN1_MB03_DATA1)
+#define pCAN1_MB03_DATA2 ((volatile unsigned short *)CAN1_MB03_DATA2)
+#define pCAN1_MB03_DATA3 ((volatile unsigned short *)CAN1_MB03_DATA3)
+#define pCAN1_MB03_LENGTH ((volatile unsigned short *)CAN1_MB03_LENGTH)
+#define pCAN1_MB03_TIMESTAMP ((volatile unsigned short *)CAN1_MB03_TIMESTAMP)
+#define pCAN1_MB03_ID0 ((volatile unsigned short *)CAN1_MB03_ID0)
+#define pCAN1_MB03_ID1 ((volatile unsigned short *)CAN1_MB03_ID1)
+#define pCAN1_MB04_DATA0 ((volatile unsigned short *)CAN1_MB04_DATA0)
+#define pCAN1_MB04_DATA1 ((volatile unsigned short *)CAN1_MB04_DATA1)
+#define pCAN1_MB04_DATA2 ((volatile unsigned short *)CAN1_MB04_DATA2)
+#define pCAN1_MB04_DATA3 ((volatile unsigned short *)CAN1_MB04_DATA3)
+#define pCAN1_MB04_LENGTH ((volatile unsigned short *)CAN1_MB04_LENGTH)
+#define pCAN1_MB04_TIMESTAMP ((volatile unsigned short *)CAN1_MB04_TIMESTAMP)
+#define pCAN1_MB04_ID0 ((volatile unsigned short *)CAN1_MB04_ID0)
+#define pCAN1_MB04_ID1 ((volatile unsigned short *)CAN1_MB04_ID1)
+#define pCAN1_MB05_DATA0 ((volatile unsigned short *)CAN1_MB05_DATA0)
+#define pCAN1_MB05_DATA1 ((volatile unsigned short *)CAN1_MB05_DATA1)
+#define pCAN1_MB05_DATA2 ((volatile unsigned short *)CAN1_MB05_DATA2)
+#define pCAN1_MB05_DATA3 ((volatile unsigned short *)CAN1_MB05_DATA3)
+#define pCAN1_MB05_LENGTH ((volatile unsigned short *)CAN1_MB05_LENGTH)
+#define pCAN1_MB05_TIMESTAMP ((volatile unsigned short *)CAN1_MB05_TIMESTAMP)
+#define pCAN1_MB05_ID0 ((volatile unsigned short *)CAN1_MB05_ID0)
+#define pCAN1_MB05_ID1 ((volatile unsigned short *)CAN1_MB05_ID1)
+#define pCAN1_MB06_DATA0 ((volatile unsigned short *)CAN1_MB06_DATA0)
+#define pCAN1_MB06_DATA1 ((volatile unsigned short *)CAN1_MB06_DATA1)
+#define pCAN1_MB06_DATA2 ((volatile unsigned short *)CAN1_MB06_DATA2)
+#define pCAN1_MB06_DATA3 ((volatile unsigned short *)CAN1_MB06_DATA3)
+#define pCAN1_MB06_LENGTH ((volatile unsigned short *)CAN1_MB06_LENGTH)
+#define pCAN1_MB06_TIMESTAMP ((volatile unsigned short *)CAN1_MB06_TIMESTAMP)
+#define pCAN1_MB06_ID0 ((volatile unsigned short *)CAN1_MB06_ID0)
+#define pCAN1_MB06_ID1 ((volatile unsigned short *)CAN1_MB06_ID1)
+#define pCAN1_MB07_DATA0 ((volatile unsigned short *)CAN1_MB07_DATA0)
+#define pCAN1_MB07_DATA1 ((volatile unsigned short *)CAN1_MB07_DATA1)
+#define pCAN1_MB07_DATA2 ((volatile unsigned short *)CAN1_MB07_DATA2)
+#define pCAN1_MB07_DATA3 ((volatile unsigned short *)CAN1_MB07_DATA3)
+#define pCAN1_MB07_LENGTH ((volatile unsigned short *)CAN1_MB07_LENGTH)
+#define pCAN1_MB07_TIMESTAMP ((volatile unsigned short *)CAN1_MB07_TIMESTAMP)
+#define pCAN1_MB07_ID0 ((volatile unsigned short *)CAN1_MB07_ID0)
+#define pCAN1_MB07_ID1 ((volatile unsigned short *)CAN1_MB07_ID1)
+#define pCAN1_MB08_DATA0 ((volatile unsigned short *)CAN1_MB08_DATA0)
+#define pCAN1_MB08_DATA1 ((volatile unsigned short *)CAN1_MB08_DATA1)
+#define pCAN1_MB08_DATA2 ((volatile unsigned short *)CAN1_MB08_DATA2)
+#define pCAN1_MB08_DATA3 ((volatile unsigned short *)CAN1_MB08_DATA3)
+#define pCAN1_MB08_LENGTH ((volatile unsigned short *)CAN1_MB08_LENGTH)
+#define pCAN1_MB08_TIMESTAMP ((volatile unsigned short *)CAN1_MB08_TIMESTAMP)
+#define pCAN1_MB08_ID0 ((volatile unsigned short *)CAN1_MB08_ID0)
+#define pCAN1_MB08_ID1 ((volatile unsigned short *)CAN1_MB08_ID1)
+#define pCAN1_MB09_DATA0 ((volatile unsigned short *)CAN1_MB09_DATA0)
+#define pCAN1_MB09_DATA1 ((volatile unsigned short *)CAN1_MB09_DATA1)
+#define pCAN1_MB09_DATA2 ((volatile unsigned short *)CAN1_MB09_DATA2)
+#define pCAN1_MB09_DATA3 ((volatile unsigned short *)CAN1_MB09_DATA3)
+#define pCAN1_MB09_LENGTH ((volatile unsigned short *)CAN1_MB09_LENGTH)
+#define pCAN1_MB09_TIMESTAMP ((volatile unsigned short *)CAN1_MB09_TIMESTAMP)
+#define pCAN1_MB09_ID0 ((volatile unsigned short *)CAN1_MB09_ID0)
+#define pCAN1_MB09_ID1 ((volatile unsigned short *)CAN1_MB09_ID1)
+#define pCAN1_MB10_DATA0 ((volatile unsigned short *)CAN1_MB10_DATA0)
+#define pCAN1_MB10_DATA1 ((volatile unsigned short *)CAN1_MB10_DATA1)
+#define pCAN1_MB10_DATA2 ((volatile unsigned short *)CAN1_MB10_DATA2)
+#define pCAN1_MB10_DATA3 ((volatile unsigned short *)CAN1_MB10_DATA3)
+#define pCAN1_MB10_LENGTH ((volatile unsigned short *)CAN1_MB10_LENGTH)
+#define pCAN1_MB10_TIMESTAMP ((volatile unsigned short *)CAN1_MB10_TIMESTAMP)
+#define pCAN1_MB10_ID0 ((volatile unsigned short *)CAN1_MB10_ID0)
+#define pCAN1_MB10_ID1 ((volatile unsigned short *)CAN1_MB10_ID1)
+#define pCAN1_MB11_DATA0 ((volatile unsigned short *)CAN1_MB11_DATA0)
+#define pCAN1_MB11_DATA1 ((volatile unsigned short *)CAN1_MB11_DATA1)
+#define pCAN1_MB11_DATA2 ((volatile unsigned short *)CAN1_MB11_DATA2)
+#define pCAN1_MB11_DATA3 ((volatile unsigned short *)CAN1_MB11_DATA3)
+#define pCAN1_MB11_LENGTH ((volatile unsigned short *)CAN1_MB11_LENGTH)
+#define pCAN1_MB11_TIMESTAMP ((volatile unsigned short *)CAN1_MB11_TIMESTAMP)
+#define pCAN1_MB11_ID0 ((volatile unsigned short *)CAN1_MB11_ID0)
+#define pCAN1_MB11_ID1 ((volatile unsigned short *)CAN1_MB11_ID1)
+#define pCAN1_MB12_DATA0 ((volatile unsigned short *)CAN1_MB12_DATA0)
+#define pCAN1_MB12_DATA1 ((volatile unsigned short *)CAN1_MB12_DATA1)
+#define pCAN1_MB12_DATA2 ((volatile unsigned short *)CAN1_MB12_DATA2)
+#define pCAN1_MB12_DATA3 ((volatile unsigned short *)CAN1_MB12_DATA3)
+#define pCAN1_MB12_LENGTH ((volatile unsigned short *)CAN1_MB12_LENGTH)
+#define pCAN1_MB12_TIMESTAMP ((volatile unsigned short *)CAN1_MB12_TIMESTAMP)
+#define pCAN1_MB12_ID0 ((volatile unsigned short *)CAN1_MB12_ID0)
+#define pCAN1_MB12_ID1 ((volatile unsigned short *)CAN1_MB12_ID1)
+#define pCAN1_MB13_DATA0 ((volatile unsigned short *)CAN1_MB13_DATA0)
+#define pCAN1_MB13_DATA1 ((volatile unsigned short *)CAN1_MB13_DATA1)
+#define pCAN1_MB13_DATA2 ((volatile unsigned short *)CAN1_MB13_DATA2)
+#define pCAN1_MB13_DATA3 ((volatile unsigned short *)CAN1_MB13_DATA3)
+#define pCAN1_MB13_LENGTH ((volatile unsigned short *)CAN1_MB13_LENGTH)
+#define pCAN1_MB13_TIMESTAMP ((volatile unsigned short *)CAN1_MB13_TIMESTAMP)
+#define pCAN1_MB13_ID0 ((volatile unsigned short *)CAN1_MB13_ID0)
+#define pCAN1_MB13_ID1 ((volatile unsigned short *)CAN1_MB13_ID1)
+#define pCAN1_MB14_DATA0 ((volatile unsigned short *)CAN1_MB14_DATA0)
+#define pCAN1_MB14_DATA1 ((volatile unsigned short *)CAN1_MB14_DATA1)
+#define pCAN1_MB14_DATA2 ((volatile unsigned short *)CAN1_MB14_DATA2)
+#define pCAN1_MB14_DATA3 ((volatile unsigned short *)CAN1_MB14_DATA3)
+#define pCAN1_MB14_LENGTH ((volatile unsigned short *)CAN1_MB14_LENGTH)
+#define pCAN1_MB14_TIMESTAMP ((volatile unsigned short *)CAN1_MB14_TIMESTAMP)
+#define pCAN1_MB14_ID0 ((volatile unsigned short *)CAN1_MB14_ID0)
+#define pCAN1_MB14_ID1 ((volatile unsigned short *)CAN1_MB14_ID1)
+#define pCAN1_MB15_DATA0 ((volatile unsigned short *)CAN1_MB15_DATA0)
+#define pCAN1_MB15_DATA1 ((volatile unsigned short *)CAN1_MB15_DATA1)
+#define pCAN1_MB15_DATA2 ((volatile unsigned short *)CAN1_MB15_DATA2)
+#define pCAN1_MB15_DATA3 ((volatile unsigned short *)CAN1_MB15_DATA3)
+#define pCAN1_MB15_LENGTH ((volatile unsigned short *)CAN1_MB15_LENGTH)
+#define pCAN1_MB15_TIMESTAMP ((volatile unsigned short *)CAN1_MB15_TIMESTAMP)
+#define pCAN1_MB15_ID0 ((volatile unsigned short *)CAN1_MB15_ID0)
+#define pCAN1_MB15_ID1 ((volatile unsigned short *)CAN1_MB15_ID1)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define pCAN1_MB16_DATA0 ((volatile unsigned short *)CAN1_MB16_DATA0)
+#define pCAN1_MB16_DATA1 ((volatile unsigned short *)CAN1_MB16_DATA1)
+#define pCAN1_MB16_DATA2 ((volatile unsigned short *)CAN1_MB16_DATA2)
+#define pCAN1_MB16_DATA3 ((volatile unsigned short *)CAN1_MB16_DATA3)
+#define pCAN1_MB16_LENGTH ((volatile unsigned short *)CAN1_MB16_LENGTH)
+#define pCAN1_MB16_TIMESTAMP ((volatile unsigned short *)CAN1_MB16_TIMESTAMP)
+#define pCAN1_MB16_ID0 ((volatile unsigned short *)CAN1_MB16_ID0)
+#define pCAN1_MB16_ID1 ((volatile unsigned short *)CAN1_MB16_ID1)
+#define pCAN1_MB17_DATA0 ((volatile unsigned short *)CAN1_MB17_DATA0)
+#define pCAN1_MB17_DATA1 ((volatile unsigned short *)CAN1_MB17_DATA1)
+#define pCAN1_MB17_DATA2 ((volatile unsigned short *)CAN1_MB17_DATA2)
+#define pCAN1_MB17_DATA3 ((volatile unsigned short *)CAN1_MB17_DATA3)
+#define pCAN1_MB17_LENGTH ((volatile unsigned short *)CAN1_MB17_LENGTH)
+#define pCAN1_MB17_TIMESTAMP ((volatile unsigned short *)CAN1_MB17_TIMESTAMP)
+#define pCAN1_MB17_ID0 ((volatile unsigned short *)CAN1_MB17_ID0)
+#define pCAN1_MB17_ID1 ((volatile unsigned short *)CAN1_MB17_ID1)
+#define pCAN1_MB18_DATA0 ((volatile unsigned short *)CAN1_MB18_DATA0)
+#define pCAN1_MB18_DATA1 ((volatile unsigned short *)CAN1_MB18_DATA1)
+#define pCAN1_MB18_DATA2 ((volatile unsigned short *)CAN1_MB18_DATA2)
+#define pCAN1_MB18_DATA3 ((volatile unsigned short *)CAN1_MB18_DATA3)
+#define pCAN1_MB18_LENGTH ((volatile unsigned short *)CAN1_MB18_LENGTH)
+#define pCAN1_MB18_TIMESTAMP ((volatile unsigned short *)CAN1_MB18_TIMESTAMP)
+#define pCAN1_MB18_ID0 ((volatile unsigned short *)CAN1_MB18_ID0)
+#define pCAN1_MB18_ID1 ((volatile unsigned short *)CAN1_MB18_ID1)
+#define pCAN1_MB19_DATA0 ((volatile unsigned short *)CAN1_MB19_DATA0)
+#define pCAN1_MB19_DATA1 ((volatile unsigned short *)CAN1_MB19_DATA1)
+#define pCAN1_MB19_DATA2 ((volatile unsigned short *)CAN1_MB19_DATA2)
+#define pCAN1_MB19_DATA3 ((volatile unsigned short *)CAN1_MB19_DATA3)
+#define pCAN1_MB19_LENGTH ((volatile unsigned short *)CAN1_MB19_LENGTH)
+#define pCAN1_MB19_TIMESTAMP ((volatile unsigned short *)CAN1_MB19_TIMESTAMP)
+#define pCAN1_MB19_ID0 ((volatile unsigned short *)CAN1_MB19_ID0)
+#define pCAN1_MB19_ID1 ((volatile unsigned short *)CAN1_MB19_ID1)
+#define pCAN1_MB20_DATA0 ((volatile unsigned short *)CAN1_MB20_DATA0)
+#define pCAN1_MB20_DATA1 ((volatile unsigned short *)CAN1_MB20_DATA1)
+#define pCAN1_MB20_DATA2 ((volatile unsigned short *)CAN1_MB20_DATA2)
+#define pCAN1_MB20_DATA3 ((volatile unsigned short *)CAN1_MB20_DATA3)
+#define pCAN1_MB20_LENGTH ((volatile unsigned short *)CAN1_MB20_LENGTH)
+#define pCAN1_MB20_TIMESTAMP ((volatile unsigned short *)CAN1_MB20_TIMESTAMP)
+#define pCAN1_MB20_ID0 ((volatile unsigned short *)CAN1_MB20_ID0)
+#define pCAN1_MB20_ID1 ((volatile unsigned short *)CAN1_MB20_ID1)
+#define pCAN1_MB21_DATA0 ((volatile unsigned short *)CAN1_MB21_DATA0)
+#define pCAN1_MB21_DATA1 ((volatile unsigned short *)CAN1_MB21_DATA1)
+#define pCAN1_MB21_DATA2 ((volatile unsigned short *)CAN1_MB21_DATA2)
+#define pCAN1_MB21_DATA3 ((volatile unsigned short *)CAN1_MB21_DATA3)
+#define pCAN1_MB21_LENGTH ((volatile unsigned short *)CAN1_MB21_LENGTH)
+#define pCAN1_MB21_TIMESTAMP ((volatile unsigned short *)CAN1_MB21_TIMESTAMP)
+#define pCAN1_MB21_ID0 ((volatile unsigned short *)CAN1_MB21_ID0)
+#define pCAN1_MB21_ID1 ((volatile unsigned short *)CAN1_MB21_ID1)
+#define pCAN1_MB22_DATA0 ((volatile unsigned short *)CAN1_MB22_DATA0)
+#define pCAN1_MB22_DATA1 ((volatile unsigned short *)CAN1_MB22_DATA1)
+#define pCAN1_MB22_DATA2 ((volatile unsigned short *)CAN1_MB22_DATA2)
+#define pCAN1_MB22_DATA3 ((volatile unsigned short *)CAN1_MB22_DATA3)
+#define pCAN1_MB22_LENGTH ((volatile unsigned short *)CAN1_MB22_LENGTH)
+#define pCAN1_MB22_TIMESTAMP ((volatile unsigned short *)CAN1_MB22_TIMESTAMP)
+#define pCAN1_MB22_ID0 ((volatile unsigned short *)CAN1_MB22_ID0)
+#define pCAN1_MB22_ID1 ((volatile unsigned short *)CAN1_MB22_ID1)
+#define pCAN1_MB23_DATA0 ((volatile unsigned short *)CAN1_MB23_DATA0)
+#define pCAN1_MB23_DATA1 ((volatile unsigned short *)CAN1_MB23_DATA1)
+#define pCAN1_MB23_DATA2 ((volatile unsigned short *)CAN1_MB23_DATA2)
+#define pCAN1_MB23_DATA3 ((volatile unsigned short *)CAN1_MB23_DATA3)
+#define pCAN1_MB23_LENGTH ((volatile unsigned short *)CAN1_MB23_LENGTH)
+#define pCAN1_MB23_TIMESTAMP ((volatile unsigned short *)CAN1_MB23_TIMESTAMP)
+#define pCAN1_MB23_ID0 ((volatile unsigned short *)CAN1_MB23_ID0)
+#define pCAN1_MB23_ID1 ((volatile unsigned short *)CAN1_MB23_ID1)
+#define pCAN1_MB24_DATA0 ((volatile unsigned short *)CAN1_MB24_DATA0)
+#define pCAN1_MB24_DATA1 ((volatile unsigned short *)CAN1_MB24_DATA1)
+#define pCAN1_MB24_DATA2 ((volatile unsigned short *)CAN1_MB24_DATA2)
+#define pCAN1_MB24_DATA3 ((volatile unsigned short *)CAN1_MB24_DATA3)
+#define pCAN1_MB24_LENGTH ((volatile unsigned short *)CAN1_MB24_LENGTH)
+#define pCAN1_MB24_TIMESTAMP ((volatile unsigned short *)CAN1_MB24_TIMESTAMP)
+#define pCAN1_MB24_ID0 ((volatile unsigned short *)CAN1_MB24_ID0)
+#define pCAN1_MB24_ID1 ((volatile unsigned short *)CAN1_MB24_ID1)
+#define pCAN1_MB25_DATA0 ((volatile unsigned short *)CAN1_MB25_DATA0)
+#define pCAN1_MB25_DATA1 ((volatile unsigned short *)CAN1_MB25_DATA1)
+#define pCAN1_MB25_DATA2 ((volatile unsigned short *)CAN1_MB25_DATA2)
+#define pCAN1_MB25_DATA3 ((volatile unsigned short *)CAN1_MB25_DATA3)
+#define pCAN1_MB25_LENGTH ((volatile unsigned short *)CAN1_MB25_LENGTH)
+#define pCAN1_MB25_TIMESTAMP ((volatile unsigned short *)CAN1_MB25_TIMESTAMP)
+#define pCAN1_MB25_ID0 ((volatile unsigned short *)CAN1_MB25_ID0)
+#define pCAN1_MB25_ID1 ((volatile unsigned short *)CAN1_MB25_ID1)
+#define pCAN1_MB26_DATA0 ((volatile unsigned short *)CAN1_MB26_DATA0)
+#define pCAN1_MB26_DATA1 ((volatile unsigned short *)CAN1_MB26_DATA1)
+#define pCAN1_MB26_DATA2 ((volatile unsigned short *)CAN1_MB26_DATA2)
+#define pCAN1_MB26_DATA3 ((volatile unsigned short *)CAN1_MB26_DATA3)
+#define pCAN1_MB26_LENGTH ((volatile unsigned short *)CAN1_MB26_LENGTH)
+#define pCAN1_MB26_TIMESTAMP ((volatile unsigned short *)CAN1_MB26_TIMESTAMP)
+#define pCAN1_MB26_ID0 ((volatile unsigned short *)CAN1_MB26_ID0)
+#define pCAN1_MB26_ID1 ((volatile unsigned short *)CAN1_MB26_ID1)
+#define pCAN1_MB27_DATA0 ((volatile unsigned short *)CAN1_MB27_DATA0)
+#define pCAN1_MB27_DATA1 ((volatile unsigned short *)CAN1_MB27_DATA1)
+#define pCAN1_MB27_DATA2 ((volatile unsigned short *)CAN1_MB27_DATA2)
+#define pCAN1_MB27_DATA3 ((volatile unsigned short *)CAN1_MB27_DATA3)
+#define pCAN1_MB27_LENGTH ((volatile unsigned short *)CAN1_MB27_LENGTH)
+#define pCAN1_MB27_TIMESTAMP ((volatile unsigned short *)CAN1_MB27_TIMESTAMP)
+#define pCAN1_MB27_ID0 ((volatile unsigned short *)CAN1_MB27_ID0)
+#define pCAN1_MB27_ID1 ((volatile unsigned short *)CAN1_MB27_ID1)
+#define pCAN1_MB28_DATA0 ((volatile unsigned short *)CAN1_MB28_DATA0)
+#define pCAN1_MB28_DATA1 ((volatile unsigned short *)CAN1_MB28_DATA1)
+#define pCAN1_MB28_DATA2 ((volatile unsigned short *)CAN1_MB28_DATA2)
+#define pCAN1_MB28_DATA3 ((volatile unsigned short *)CAN1_MB28_DATA3)
+#define pCAN1_MB28_LENGTH ((volatile unsigned short *)CAN1_MB28_LENGTH)
+#define pCAN1_MB28_TIMESTAMP ((volatile unsigned short *)CAN1_MB28_TIMESTAMP)
+#define pCAN1_MB28_ID0 ((volatile unsigned short *)CAN1_MB28_ID0)
+#define pCAN1_MB28_ID1 ((volatile unsigned short *)CAN1_MB28_ID1)
+#define pCAN1_MB29_DATA0 ((volatile unsigned short *)CAN1_MB29_DATA0)
+#define pCAN1_MB29_DATA1 ((volatile unsigned short *)CAN1_MB29_DATA1)
+#define pCAN1_MB29_DATA2 ((volatile unsigned short *)CAN1_MB29_DATA2)
+#define pCAN1_MB29_DATA3 ((volatile unsigned short *)CAN1_MB29_DATA3)
+#define pCAN1_MB29_LENGTH ((volatile unsigned short *)CAN1_MB29_LENGTH)
+#define pCAN1_MB29_TIMESTAMP ((volatile unsigned short *)CAN1_MB29_TIMESTAMP)
+#define pCAN1_MB29_ID0 ((volatile unsigned short *)CAN1_MB29_ID0)
+#define pCAN1_MB29_ID1 ((volatile unsigned short *)CAN1_MB29_ID1)
+#define pCAN1_MB30_DATA0 ((volatile unsigned short *)CAN1_MB30_DATA0)
+#define pCAN1_MB30_DATA1 ((volatile unsigned short *)CAN1_MB30_DATA1)
+#define pCAN1_MB30_DATA2 ((volatile unsigned short *)CAN1_MB30_DATA2)
+#define pCAN1_MB30_DATA3 ((volatile unsigned short *)CAN1_MB30_DATA3)
+#define pCAN1_MB30_LENGTH ((volatile unsigned short *)CAN1_MB30_LENGTH)
+#define pCAN1_MB30_TIMESTAMP ((volatile unsigned short *)CAN1_MB30_TIMESTAMP)
+#define pCAN1_MB30_ID0 ((volatile unsigned short *)CAN1_MB30_ID0)
+#define pCAN1_MB30_ID1 ((volatile unsigned short *)CAN1_MB30_ID1)
+#define pCAN1_MB31_DATA0 ((volatile unsigned short *)CAN1_MB31_DATA0)
+#define pCAN1_MB31_DATA1 ((volatile unsigned short *)CAN1_MB31_DATA1)
+#define pCAN1_MB31_DATA2 ((volatile unsigned short *)CAN1_MB31_DATA2)
+#define pCAN1_MB31_DATA3 ((volatile unsigned short *)CAN1_MB31_DATA3)
+#define pCAN1_MB31_LENGTH ((volatile unsigned short *)CAN1_MB31_LENGTH)
+#define pCAN1_MB31_TIMESTAMP ((volatile unsigned short *)CAN1_MB31_TIMESTAMP)
+#define pCAN1_MB31_ID0 ((volatile unsigned short *)CAN1_MB31_ID0)
+#define pCAN1_MB31_ID1 ((volatile unsigned short *)CAN1_MB31_ID1)
+
+/* ATAPI Registers */
+
+#define pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
+#define pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
+#define pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
+#define pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
+#define pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
+#define pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
+#define pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
+#define pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
+#define pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
+#define pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
+#define pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
+#define pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
+#define pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
+#define pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
+#define pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
+#define pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
+#define pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
+#define pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
+#define pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
+#define pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
+#define pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
+#define pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
+#define pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
+#define pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
+#define pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
+
+/* SDH Registers */
+
+#define pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
+#define pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
+#define pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
+#define pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
+#define pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
+#define pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
+#define pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
+#define pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
+#define pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
+#define pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
+#define pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
+#define pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
+#define pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
+#define pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
+#define pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
+#define pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
+#define pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
+#define pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
+#define pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
+#define pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
+#define pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
+#define pSDH_CFG ((volatile unsigned short *)SDH_CFG)
+#define pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
+#define pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
+#define pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
+#define pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
+#define pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
+#define pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
+#define pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
+#define pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
+#define pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
+
+/* HOST Port Registers */
+
+#define pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
+#define pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
+#define pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
+
+/* USB Control Registers */
+
+#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
+#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
+#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
+#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
+#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
+#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
+#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
+#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
+#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
+#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
+#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
+#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
+#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
+
+/* USB Packet Control Registers */
+
+#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
+#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
+#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
+#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
+#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
+#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
+#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
+#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
+#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
+#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
+#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
+#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
+#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
+
+/* USB Endpoint FIFO Registers */
+
+#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
+#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
+#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
+#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
+#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
+#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
+#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
+#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
+
+/* USB OTG Control Registers */
+
+#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
+#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
+#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
+
+/* USB Phy Control Registers */
+
+#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
+#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
+#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
+#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
+#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
+#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
+#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
+#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
+
+/* USB Endpoint 0 Control Registers */
+
+#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
+#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
+#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
+#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
+#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
+#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
+#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
+#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
+#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
+
+/* USB Endpoint 1 Control Registers */
+
+#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
+#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
+#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
+#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
+#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
+#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
+#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
+#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
+#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
+#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
+
+/* USB Endpoint 2 Control Registers */
+
+#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
+#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
+#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
+#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
+#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
+#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
+#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
+#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
+#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
+#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
+
+/* USB Endpoint 3 Control Registers */
+
+#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
+#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
+#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
+#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
+#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
+#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
+#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
+#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
+#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
+#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
+
+/* USB Endpoint 4 Control Registers */
+
+#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
+#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
+#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
+#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
+#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
+#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
+#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
+#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
+#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
+#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
+
+/* USB Endpoint 5 Control Registers */
+
+#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
+#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
+#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
+#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
+#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
+#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
+#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
+#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
+#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
+#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
+
+/* USB Endpoint 6 Control Registers */
+
+#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
+#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
+#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
+#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
+#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
+#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
+#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
+#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
+#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
+#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
+
+/* USB Endpoint 7 Control Registers */
+
+#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
+#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
+#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
+#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
+#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
+#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
+#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
+#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
+#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
+#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
+#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
+#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
+
+/* USB Channel 0 Config Registers */
+
+#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
+#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
+#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
+#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
+#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
+
+/* USB Channel 1 Config Registers */
+
+#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
+#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
+#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
+#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
+#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
+
+/* USB Channel 2 Config Registers */
+
+#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
+#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
+#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
+#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
+#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
+
+/* USB Channel 3 Config Registers */
+
+#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
+#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
+#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
+#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
+#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
+
+/* USB Channel 4 Config Registers */
+
+#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
+#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
+#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
+#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
+#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
+
+/* USB Channel 5 Config Registers */
+
+#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
+#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
+#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
+#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
+#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
+
+/* USB Channel 6 Config Registers */
+
+#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
+#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
+#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
+#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
+#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
+
+/* USB Channel 7 Config Registers */
+
+#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
+#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
+#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
+#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
+#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
+
+/* Keypad Registers */
+
+#define pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
+#define pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
+#define pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
+#define pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
+#define pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
+#define pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
+#define pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
+#define pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
+#define pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
+#define pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
+#define pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
+#define pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
+#define pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
+#define pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
+#define pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
+#define pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
+#define pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
+#define pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
+#define pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
+#define pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
+#define pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
+#define pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
+#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
+#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
+
+#endif /* _CDEF_BF548_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF549.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the ADSP-BF549 peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _CDEF_BF549_H
+#define _CDEF_BF549_H
+
+/* include all Core registers and bit definitions */
+#include <defBF549.h>
+
+/* include core specific register pointer definitions */
+#include <cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
+
+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include <cdefBF54x_base.h>
+
+/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
+
+/* Timer Registers */
+
+#define pTIMER8_CONFIG ((volatile unsigned short *)TIMER8_CONFIG)
+#define pTIMER8_COUNTER ((volatile unsigned long *)TIMER8_COUNTER)
+#define pTIMER8_PERIOD ((volatile unsigned long *)TIMER8_PERIOD)
+#define pTIMER8_WIDTH ((volatile unsigned long *)TIMER8_WIDTH)
+#define pTIMER9_CONFIG ((volatile unsigned short *)TIMER9_CONFIG)
+#define pTIMER9_COUNTER ((volatile unsigned long *)TIMER9_COUNTER)
+#define pTIMER9_PERIOD ((volatile unsigned long *)TIMER9_PERIOD)
+#define pTIMER9_WIDTH ((volatile unsigned long *)TIMER9_WIDTH)
+#define pTIMER10_CONFIG ((volatile unsigned short *)TIMER10_CONFIG)
+#define pTIMER10_COUNTER ((volatile unsigned long *)TIMER10_COUNTER)
+#define pTIMER10_PERIOD ((volatile unsigned long *)TIMER10_PERIOD)
+#define pTIMER10_WIDTH ((volatile unsigned long *)TIMER10_WIDTH)
+
+/* Timer Group of 3 */
+
+#define pTIMER_ENABLE1 ((volatile unsigned short *)TIMER_ENABLE1)
+#define pTIMER_DISABLE1 ((volatile unsigned short *)TIMER_DISABLE1)
+#define pTIMER_STATUS1 ((volatile unsigned long *)TIMER_STATUS1)
+
+/* SPORT0 Registers */
+
+#define pSPORT0_TCR1 ((volatile unsigned short *)SPORT0_TCR1)
+#define pSPORT0_TCR2 ((volatile unsigned short *)SPORT0_TCR2)
+#define pSPORT0_TCLKDIV ((volatile unsigned short *)SPORT0_TCLKDIV)
+#define pSPORT0_TFSDIV ((volatile unsigned short *)SPORT0_TFSDIV)
+#define pSPORT0_TX ((volatile unsigned long *)SPORT0_TX)
+#define pSPORT0_RX ((volatile unsigned long *)SPORT0_RX)
+#define pSPORT0_RCR1 ((volatile unsigned short *)SPORT0_RCR1)
+#define pSPORT0_RCR2 ((volatile unsigned short *)SPORT0_RCR2)
+#define pSPORT0_RCLKDIV ((volatile unsigned short *)SPORT0_RCLKDIV)
+#define pSPORT0_RFSDIV ((volatile unsigned short *)SPORT0_RFSDIV)
+#define pSPORT0_STAT ((volatile unsigned short *)SPORT0_STAT)
+#define pSPORT0_CHNL ((volatile unsigned short *)SPORT0_CHNL)
+#define pSPORT0_MCMC1 ((volatile unsigned short *)SPORT0_MCMC1)
+#define pSPORT0_MCMC2 ((volatile unsigned short *)SPORT0_MCMC2)
+#define pSPORT0_MTCS0 ((volatile unsigned long *)SPORT0_MTCS0)
+#define pSPORT0_MTCS1 ((volatile unsigned long *)SPORT0_MTCS1)
+#define pSPORT0_MTCS2 ((volatile unsigned long *)SPORT0_MTCS2)
+#define pSPORT0_MTCS3 ((volatile unsigned long *)SPORT0_MTCS3)
+#define pSPORT0_MRCS0 ((volatile unsigned long *)SPORT0_MRCS0)
+#define pSPORT0_MRCS1 ((volatile unsigned long *)SPORT0_MRCS1)
+#define pSPORT0_MRCS2 ((volatile unsigned long *)SPORT0_MRCS2)
+#define pSPORT0_MRCS3 ((volatile unsigned long *)SPORT0_MRCS3)
+
+/* EPPI0 Registers */
+
+#define pEPPI0_STATUS ((volatile unsigned short *)EPPI0_STATUS)
+#define pEPPI0_HCOUNT ((volatile unsigned short *)EPPI0_HCOUNT)
+#define pEPPI0_HDELAY ((volatile unsigned short *)EPPI0_HDELAY)
+#define pEPPI0_VCOUNT ((volatile unsigned short *)EPPI0_VCOUNT)
+#define pEPPI0_VDELAY ((volatile unsigned short *)EPPI0_VDELAY)
+#define pEPPI0_FRAME ((volatile unsigned short *)EPPI0_FRAME)
+#define pEPPI0_LINE ((volatile unsigned short *)EPPI0_LINE)
+#define pEPPI0_CLKDIV ((volatile unsigned short *)EPPI0_CLKDIV)
+#define pEPPI0_CONTROL ((volatile unsigned long *)EPPI0_CONTROL)
+#define pEPPI0_FS1W_HBL ((volatile unsigned long *)EPPI0_FS1W_HBL)
+#define pEPPI0_FS1P_AVPL ((volatile unsigned long *)EPPI0_FS1P_AVPL)
+#define pEPPI0_FS2W_LVB ((volatile unsigned long *)EPPI0_FS2W_LVB)
+#define pEPPI0_FS2P_LAVF ((volatile unsigned long *)EPPI0_FS2P_LAVF)
+#define pEPPI0_CLIP ((volatile unsigned long *)EPPI0_CLIP)
+
+/* UART2 Registers */
+
+#define pUART2_DLL ((volatile unsigned short *)UART2_DLL)
+#define pUART2_DLH ((volatile unsigned short *)UART2_DLH)
+#define pUART2_GCTL ((volatile unsigned short *)UART2_GCTL)
+#define pUART2_LCR ((volatile unsigned short *)UART2_LCR)
+#define pUART2_MCR ((volatile unsigned short *)UART2_MCR)
+#define pUART2_LSR ((volatile unsigned short *)UART2_LSR)
+#define pUART2_MSR ((volatile unsigned short *)UART2_MSR)
+#define pUART2_SCR ((volatile unsigned short *)UART2_SCR)
+#define pUART2_IER_SET ((volatile unsigned short *)UART2_IER_SET)
+#define pUART2_IER_CLEAR ((volatile unsigned short *)UART2_IER_CLEAR)
+#define pUART2_THR ((volatile unsigned short *)UART2_THR)
+#define pUART2_RBR ((volatile unsigned short *)UART2_RBR)
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define pTWI1_CLKDIV ((volatile unsigned short *)TWI1_CLKDIV)
+#define pTWI1_CONTROL ((volatile unsigned short *)TWI1_CONTROL)
+#define pTWI1_SLAVE_CTL ((volatile unsigned short *)TWI1_SLAVE_CTL)
+#define pTWI1_SLAVE_STAT ((volatile unsigned short *)TWI1_SLAVE_STAT)
+#define pTWI1_SLAVE_ADDR ((volatile unsigned short *)TWI1_SLAVE_ADDR)
+#define pTWI1_MASTER_CTL ((volatile unsigned short *)TWI1_MASTER_CTL)
+#define pTWI1_MASTER_STAT ((volatile unsigned short *)TWI1_MASTER_STAT)
+#define pTWI1_MASTER_ADDR ((volatile unsigned short *)TWI1_MASTER_ADDR)
+#define pTWI1_INT_STAT ((volatile unsigned short *)TWI1_INT_STAT)
+#define pTWI1_INT_MASK ((volatile unsigned short *)TWI1_INT_MASK)
+#define pTWI1_FIFO_CTL ((volatile unsigned short *)TWI1_FIFO_CTL)
+#define pTWI1_FIFO_STAT ((volatile unsigned short *)TWI1_FIFO_STAT)
+#define pTWI1_XMT_DATA8 ((volatile unsigned short *)TWI1_XMT_DATA8)
+#define pTWI1_XMT_DATA16 ((volatile unsigned short *)TWI1_XMT_DATA16)
+#define pTWI1_RCV_DATA8 ((volatile unsigned short *)TWI1_RCV_DATA8)
+#define pTWI1_RCV_DATA16 ((volatile unsigned short *)TWI1_RCV_DATA16)
+
+/* SPI2 Registers */
+
+#define pSPI2_CTL ((volatile unsigned short *)SPI2_CTL)
+#define pSPI2_FLG ((volatile unsigned short *)SPI2_FLG)
+#define pSPI2_STAT ((volatile unsigned short *)SPI2_STAT)
+#define pSPI2_TDBR ((volatile unsigned short *)SPI2_TDBR)
+#define pSPI2_RDBR ((volatile unsigned short *)SPI2_RDBR)
+#define pSPI2_BAUD ((volatile unsigned short *)SPI2_BAUD)
+#define pSPI2_SHADOW ((volatile unsigned short *)SPI2_SHADOW)
+
+/* MXVR Registers */
+
+#define pMXVR_CONFIG ((volatile unsigned short *)MXVR_CONFIG)
+#define pMXVR_STATE_0 ((volatile unsigned long *)MXVR_STATE_0)
+#define pMXVR_STATE_1 ((volatile unsigned long *)MXVR_STATE_1)
+#define pMXVR_INT_STAT_0 ((volatile unsigned long *)MXVR_INT_STAT_0)
+#define pMXVR_INT_STAT_1 ((volatile unsigned long *)MXVR_INT_STAT_1)
+#define pMXVR_INT_EN_0 ((volatile unsigned long *)MXVR_INT_EN_0)
+#define pMXVR_INT_EN_1 ((volatile unsigned long *)MXVR_INT_EN_1)
+#define pMXVR_POSITION ((volatile unsigned short *)MXVR_POSITION)
+#define pMXVR_MAX_POSITION ((volatile unsigned short *)MXVR_MAX_POSITION)
+#define pMXVR_DELAY ((volatile unsigned short *)MXVR_DELAY)
+#define pMXVR_MAX_DELAY ((volatile unsigned short *)MXVR_MAX_DELAY)
+#define pMXVR_LADDR ((volatile unsigned long *)MXVR_LADDR)
+#define pMXVR_GADDR ((volatile unsigned short *)MXVR_GADDR)
+#define pMXVR_AADDR ((volatile unsigned long *)MXVR_AADDR)
+
+/* MXVR Allocation Table Registers */
+
+#define pMXVR_ALLOC_0 ((volatile unsigned long *)MXVR_ALLOC_0)
+#define pMXVR_ALLOC_1 ((volatile unsigned long *)MXVR_ALLOC_1)
+#define pMXVR_ALLOC_2 ((volatile unsigned long *)MXVR_ALLOC_2)
+#define pMXVR_ALLOC_3 ((volatile unsigned long *)MXVR_ALLOC_3)
+#define pMXVR_ALLOC_4 ((volatile unsigned long *)MXVR_ALLOC_4)
+#define pMXVR_ALLOC_5 ((volatile unsigned long *)MXVR_ALLOC_5)
+#define pMXVR_ALLOC_6 ((volatile unsigned long *)MXVR_ALLOC_6)
+#define pMXVR_ALLOC_7 ((volatile unsigned long *)MXVR_ALLOC_7)
+#define pMXVR_ALLOC_8 ((volatile unsigned long *)MXVR_ALLOC_8)
+#define pMXVR_ALLOC_9 ((volatile unsigned long *)MXVR_ALLOC_9)
+#define pMXVR_ALLOC_10 ((volatile unsigned long *)MXVR_ALLOC_10)
+#define pMXVR_ALLOC_11 ((volatile unsigned long *)MXVR_ALLOC_11)
+#define pMXVR_ALLOC_12 ((volatile unsigned long *)MXVR_ALLOC_12)
+#define pMXVR_ALLOC_13 ((volatile unsigned long *)MXVR_ALLOC_13)
+#define pMXVR_ALLOC_14 ((volatile unsigned long *)MXVR_ALLOC_14)
+
+/* MXVR Channel Assign Registers */
+
+#define pMXVR_SYNC_LCHAN_0 ((volatile unsigned long *)MXVR_SYNC_LCHAN_0)
+#define pMXVR_SYNC_LCHAN_1 ((volatile unsigned long *)MXVR_SYNC_LCHAN_1)
+#define pMXVR_SYNC_LCHAN_2 ((volatile unsigned long *)MXVR_SYNC_LCHAN_2)
+#define pMXVR_SYNC_LCHAN_3 ((volatile unsigned long *)MXVR_SYNC_LCHAN_3)
+#define pMXVR_SYNC_LCHAN_4 ((volatile unsigned long *)MXVR_SYNC_LCHAN_4)
+#define pMXVR_SYNC_LCHAN_5 ((volatile unsigned long *)MXVR_SYNC_LCHAN_5)
+#define pMXVR_SYNC_LCHAN_6 ((volatile unsigned long *)MXVR_SYNC_LCHAN_6)
+#define pMXVR_SYNC_LCHAN_7 ((volatile unsigned long *)MXVR_SYNC_LCHAN_7)
+
+/* MXVR DMA0 Registers */
+
+#define pMXVR_DMA0_CONFIG ((volatile unsigned long *)MXVR_DMA0_CONFIG)
+#define pMXVR_DMA0_START_ADDR ((void *volatile *)MXVR_DMA0_START_ADDR)
+#define pMXVR_DMA0_COUNT ((volatile unsigned short *)MXVR_DMA0_COUNT)
+#define pMXVR_DMA0_CURR_ADDR ((void *volatile *)MXVR_DMA0_CURR_ADDR)
+#define pMXVR_DMA0_CURR_COUNT ((volatile unsigned short *)MXVR_DMA0_CURR_COUNT)
+
+/* MXVR DMA1 Registers */
+
+#define pMXVR_DMA1_CONFIG ((volatile unsigned long *)MXVR_DMA1_CONFIG)
+#define pMXVR_DMA1_START_ADDR ((void *volatile *)MXVR_DMA1_START_ADDR)
+#define pMXVR_DMA1_COUNT ((volatile unsigned short *)MXVR_DMA1_COUNT)
+#define pMXVR_DMA1_CURR_ADDR ((void *volatile *)MXVR_DMA1_CURR_ADDR)
+#define pMXVR_DMA1_CURR_COUNT ((volatile unsigned short *)MXVR_DMA1_CURR_COUNT)
+
+/* MXVR DMA2 Registers */
+
+#define pMXVR_DMA2_CONFIG ((volatile unsigned long *)MXVR_DMA2_CONFIG)
+#define pMXVR_DMA2_START_ADDR ((void *volatile *)MXVR_DMA2_START_ADDR)
+#define pMXVR_DMA2_COUNT ((volatile unsigned short *)MXVR_DMA2_COUNT)
+#define pMXVR_DMA2_CURR_ADDR ((void *volatile *)MXVR_DMA2_CURR_ADDR)
+#define pMXVR_DMA2_CURR_COUNT ((volatile unsigned short *)MXVR_DMA2_CURR_COUNT)
+
+/* MXVR DMA3 Registers */
+
+#define pMXVR_DMA3_CONFIG ((volatile unsigned long *)MXVR_DMA3_CONFIG)
+#define pMXVR_DMA3_START_ADDR ((void *volatile *)MXVR_DMA3_START_ADDR)
+#define pMXVR_DMA3_COUNT ((volatile unsigned short *)MXVR_DMA3_COUNT)
+#define pMXVR_DMA3_CURR_ADDR ((void *volatile *)MXVR_DMA3_CURR_ADDR)
+#define pMXVR_DMA3_CURR_COUNT ((volatile unsigned short *)MXVR_DMA3_CURR_COUNT)
+
+/* MXVR DMA4 Registers */
+
+#define pMXVR_DMA4_CONFIG ((volatile unsigned long *)MXVR_DMA4_CONFIG)
+#define pMXVR_DMA4_START_ADDR ((void *volatile *)MXVR_DMA4_START_ADDR)
+#define pMXVR_DMA4_COUNT ((volatile unsigned short *)MXVR_DMA4_COUNT)
+#define pMXVR_DMA4_CURR_ADDR ((void *volatile *)MXVR_DMA4_CURR_ADDR)
+#define pMXVR_DMA4_CURR_COUNT ((volatile unsigned short *)MXVR_DMA4_CURR_COUNT)
+
+/* MXVR DMA5 Registers */
+
+#define pMXVR_DMA5_CONFIG ((volatile unsigned long *)MXVR_DMA5_CONFIG)
+#define pMXVR_DMA5_START_ADDR ((void *volatile *)MXVR_DMA5_START_ADDR)
+#define pMXVR_DMA5_COUNT ((volatile unsigned short *)MXVR_DMA5_COUNT)
+#define pMXVR_DMA5_CURR_ADDR ((void *volatile *)MXVR_DMA5_CURR_ADDR)
+#define pMXVR_DMA5_CURR_COUNT ((volatile unsigned short *)MXVR_DMA5_CURR_COUNT)
+
+/* MXVR DMA6 Registers */
+
+#define pMXVR_DMA6_CONFIG ((volatile unsigned long *)MXVR_DMA6_CONFIG)
+#define pMXVR_DMA6_START_ADDR ((void *volatile *)MXVR_DMA6_START_ADDR)
+#define pMXVR_DMA6_COUNT ((volatile unsigned short *)MXVR_DMA6_COUNT)
+#define pMXVR_DMA6_CURR_ADDR ((void *volatile *)MXVR_DMA6_CURR_ADDR)
+#define pMXVR_DMA6_CURR_COUNT ((volatile unsigned short *)MXVR_DMA6_CURR_COUNT)
+
+/* MXVR DMA7 Registers */
+
+#define pMXVR_DMA7_CONFIG ((volatile unsigned long *)MXVR_DMA7_CONFIG)
+#define pMXVR_DMA7_START_ADDR ((void *volatile *)MXVR_DMA7_START_ADDR)
+#define pMXVR_DMA7_COUNT ((volatile unsigned short *)MXVR_DMA7_COUNT)
+#define pMXVR_DMA7_CURR_ADDR ((void *volatile *)MXVR_DMA7_CURR_ADDR)
+#define pMXVR_DMA7_CURR_COUNT ((volatile unsigned short *)MXVR_DMA7_CURR_COUNT)
+
+/* MXVR Asynch Packet Registers */
+
+#define pMXVR_AP_CTL ((volatile unsigned short *)MXVR_AP_CTL)
+#define pMXVR_APRB_START_ADDR ((void *volatile *)MXVR_APRB_START_ADDR)
+#define pMXVR_APRB_CURR_ADDR ((void *volatile *)MXVR_APRB_CURR_ADDR)
+#define pMXVR_APTB_START_ADDR ((void *volatile *)MXVR_APTB_START_ADDR)
+#define pMXVR_APTB_CURR_ADDR ((void *volatile *)MXVR_APTB_CURR_ADDR)
+
+/* MXVR Control Message Registers */
+
+#define pMXVR_CM_CTL ((volatile unsigned long *)MXVR_CM_CTL)
+#define pMXVR_CMRB_START_ADDR ((void *volatile *)MXVR_CMRB_START_ADDR)
+#define pMXVR_CMRB_CURR_ADDR ((void *volatile *)MXVR_CMRB_CURR_ADDR)
+#define pMXVR_CMTB_START_ADDR ((void *volatile *)MXVR_CMTB_START_ADDR)
+#define pMXVR_CMTB_CURR_ADDR ((void *volatile *)MXVR_CMTB_CURR_ADDR)
+
+/* MXVR Remote Read Registers */
+
+#define pMXVR_RRDB_START_ADDR ((void *volatile *)MXVR_RRDB_START_ADDR)
+#define pMXVR_RRDB_CURR_ADDR ((void *volatile *)MXVR_RRDB_CURR_ADDR)
+
+/* MXVR Pattern Data Registers */
+
+#define pMXVR_PAT_DATA_0 ((volatile unsigned long *)MXVR_PAT_DATA_0)
+#define pMXVR_PAT_EN_0 ((volatile unsigned long *)MXVR_PAT_EN_0)
+#define pMXVR_PAT_DATA_1 ((volatile unsigned long *)MXVR_PAT_DATA_1)
+#define pMXVR_PAT_EN_1 ((volatile unsigned long *)MXVR_PAT_EN_1)
+
+/* MXVR Frame Counter Registers */
+
+#define pMXVR_FRAME_CNT_0 ((volatile unsigned short *)MXVR_FRAME_CNT_0)
+#define pMXVR_FRAME_CNT_1 ((volatile unsigned short *)MXVR_FRAME_CNT_1)
+
+/* MXVR Routing Table Registers */
+
+#define pMXVR_ROUTING_0 ((volatile unsigned long *)MXVR_ROUTING_0)
+#define pMXVR_ROUTING_1 ((volatile unsigned long *)MXVR_ROUTING_1)
+#define pMXVR_ROUTING_2 ((volatile unsigned long *)MXVR_ROUTING_2)
+#define pMXVR_ROUTING_3 ((volatile unsigned long *)MXVR_ROUTING_3)
+#define pMXVR_ROUTING_4 ((volatile unsigned long *)MXVR_ROUTING_4)
+#define pMXVR_ROUTING_5 ((volatile unsigned long *)MXVR_ROUTING_5)
+#define pMXVR_ROUTING_6 ((volatile unsigned long *)MXVR_ROUTING_6)
+#define pMXVR_ROUTING_7 ((volatile unsigned long *)MXVR_ROUTING_7)
+#define pMXVR_ROUTING_8 ((volatile unsigned long *)MXVR_ROUTING_8)
+#define pMXVR_ROUTING_9 ((volatile unsigned long *)MXVR_ROUTING_9)
+#define pMXVR_ROUTING_10 ((volatile unsigned long *)MXVR_ROUTING_10)
+#define pMXVR_ROUTING_11 ((volatile unsigned long *)MXVR_ROUTING_11)
+#define pMXVR_ROUTING_12 ((volatile unsigned long *)MXVR_ROUTING_12)
+#define pMXVR_ROUTING_13 ((volatile unsigned long *)MXVR_ROUTING_13)
+#define pMXVR_ROUTING_14 ((volatile unsigned long *)MXVR_ROUTING_14)
+
+/* MXVR Counter-Clock-Control Registers */
+
+#define pMXVR_BLOCK_CNT ((volatile unsigned short *)MXVR_BLOCK_CNT)
+#define pMXVR_CLK_CTL ((volatile unsigned long *)MXVR_CLK_CTL)
+#define pMXVR_CDRPLL_CTL ((volatile unsigned long *)MXVR_CDRPLL_CTL)
+#define pMXVR_FMPLL_CTL ((volatile unsigned long *)MXVR_FMPLL_CTL)
+#define pMXVR_PIN_CTL ((volatile unsigned short *)MXVR_PIN_CTL)
+#define pMXVR_SCLK_CNT ((volatile unsigned short *)MXVR_SCLK_CNT)
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define pCAN1_MC1 ((volatile unsigned short *)CAN1_MC1)
+#define pCAN1_MD1 ((volatile unsigned short *)CAN1_MD1)
+#define pCAN1_TRS1 ((volatile unsigned short *)CAN1_TRS1)
+#define pCAN1_TRR1 ((volatile unsigned short *)CAN1_TRR1)
+#define pCAN1_TA1 ((volatile unsigned short *)CAN1_TA1)
+#define pCAN1_AA1 ((volatile unsigned short *)CAN1_AA1)
+#define pCAN1_RMP1 ((volatile unsigned short *)CAN1_RMP1)
+#define pCAN1_RML1 ((volatile unsigned short *)CAN1_RML1)
+#define pCAN1_MBTIF1 ((volatile unsigned short *)CAN1_MBTIF1)
+#define pCAN1_MBRIF1 ((volatile unsigned short *)CAN1_MBRIF1)
+#define pCAN1_MBIM1 ((volatile unsigned short *)CAN1_MBIM1)
+#define pCAN1_RFH1 ((volatile unsigned short *)CAN1_RFH1)
+#define pCAN1_OPSS1 ((volatile unsigned short *)CAN1_OPSS1)
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define pCAN1_MC2 ((volatile unsigned short *)CAN1_MC2)
+#define pCAN1_MD2 ((volatile unsigned short *)CAN1_MD2)
+#define pCAN1_TRS2 ((volatile unsigned short *)CAN1_TRS2)
+#define pCAN1_TRR2 ((volatile unsigned short *)CAN1_TRR2)
+#define pCAN1_TA2 ((volatile unsigned short *)CAN1_TA2)
+#define pCAN1_AA2 ((volatile unsigned short *)CAN1_AA2)
+#define pCAN1_RMP2 ((volatile unsigned short *)CAN1_RMP2)
+#define pCAN1_RML2 ((volatile unsigned short *)CAN1_RML2)
+#define pCAN1_MBTIF2 ((volatile unsigned short *)CAN1_MBTIF2)
+#define pCAN1_MBRIF2 ((volatile unsigned short *)CAN1_MBRIF2)
+#define pCAN1_MBIM2 ((volatile unsigned short *)CAN1_MBIM2)
+#define pCAN1_RFH2 ((volatile unsigned short *)CAN1_RFH2)
+#define pCAN1_OPSS2 ((volatile unsigned short *)CAN1_OPSS2)
+
+/* CAN Controller 1 Clock/Interrupt/Counter Registers */
+
+#define pCAN1_CLOCK ((volatile unsigned short *)CAN1_CLOCK)
+#define pCAN1_TIMING ((volatile unsigned short *)CAN1_TIMING)
+#define pCAN1_DEBUG ((volatile unsigned short *)CAN1_DEBUG)
+#define pCAN1_STATUS ((volatile unsigned short *)CAN1_STATUS)
+#define pCAN1_CEC ((volatile unsigned short *)CAN1_CEC)
+#define pCAN1_GIS ((volatile unsigned short *)CAN1_GIS)
+#define pCAN1_GIM ((volatile unsigned short *)CAN1_GIM)
+#define pCAN1_GIF ((volatile unsigned short *)CAN1_GIF)
+#define pCAN1_CONTROL ((volatile unsigned short *)CAN1_CONTROL)
+#define pCAN1_INTR ((volatile unsigned short *)CAN1_INTR)
+#define pCAN1_MBTD ((volatile unsigned short *)CAN1_MBTD)
+#define pCAN1_EWR ((volatile unsigned short *)CAN1_EWR)
+#define pCAN1_ESR ((volatile unsigned short *)CAN1_ESR)
+#define pCAN1_UCCNT ((volatile unsigned short *)CAN1_UCCNT)
+#define pCAN1_UCRC ((volatile unsigned short *)CAN1_UCRC)
+#define pCAN1_UCCNF ((volatile unsigned short *)CAN1_UCCNF)
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define pCAN1_AM00L ((volatile unsigned short *)CAN1_AM00L)
+#define pCAN1_AM00H ((volatile unsigned short *)CAN1_AM00H)
+#define pCAN1_AM01L ((volatile unsigned short *)CAN1_AM01L)
+#define pCAN1_AM01H ((volatile unsigned short *)CAN1_AM01H)
+#define pCAN1_AM02L ((volatile unsigned short *)CAN1_AM02L)
+#define pCAN1_AM02H ((volatile unsigned short *)CAN1_AM02H)
+#define pCAN1_AM03L ((volatile unsigned short *)CAN1_AM03L)
+#define pCAN1_AM03H ((volatile unsigned short *)CAN1_AM03H)
+#define pCAN1_AM04L ((volatile unsigned short *)CAN1_AM04L)
+#define pCAN1_AM04H ((volatile unsigned short *)CAN1_AM04H)
+#define pCAN1_AM05L ((volatile unsigned short *)CAN1_AM05L)
+#define pCAN1_AM05H ((volatile unsigned short *)CAN1_AM05H)
+#define pCAN1_AM06L ((volatile unsigned short *)CAN1_AM06L)
+#define pCAN1_AM06H ((volatile unsigned short *)CAN1_AM06H)
+#define pCAN1_AM07L ((volatile unsigned short *)CAN1_AM07L)
+#define pCAN1_AM07H ((volatile unsigned short *)CAN1_AM07H)
+#define pCAN1_AM08L ((volatile unsigned short *)CAN1_AM08L)
+#define pCAN1_AM08H ((volatile unsigned short *)CAN1_AM08H)
+#define pCAN1_AM09L ((volatile unsigned short *)CAN1_AM09L)
+#define pCAN1_AM09H ((volatile unsigned short *)CAN1_AM09H)
+#define pCAN1_AM10L ((volatile unsigned short *)CAN1_AM10L)
+#define pCAN1_AM10H ((volatile unsigned short *)CAN1_AM10H)
+#define pCAN1_AM11L ((volatile unsigned short *)CAN1_AM11L)
+#define pCAN1_AM11H ((volatile unsigned short *)CAN1_AM11H)
+#define pCAN1_AM12L ((volatile unsigned short *)CAN1_AM12L)
+#define pCAN1_AM12H ((volatile unsigned short *)CAN1_AM12H)
+#define pCAN1_AM13L ((volatile unsigned short *)CAN1_AM13L)
+#define pCAN1_AM13H ((volatile unsigned short *)CAN1_AM13H)
+#define pCAN1_AM14L ((volatile unsigned short *)CAN1_AM14L)
+#define pCAN1_AM14H ((volatile unsigned short *)CAN1_AM14H)
+#define pCAN1_AM15L ((volatile unsigned short *)CAN1_AM15L)
+#define pCAN1_AM15H ((volatile unsigned short *)CAN1_AM15H)
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define pCAN1_AM16L ((volatile unsigned short *)CAN1_AM16L)
+#define pCAN1_AM16H ((volatile unsigned short *)CAN1_AM16H)
+#define pCAN1_AM17L ((volatile unsigned short *)CAN1_AM17L)
+#define pCAN1_AM17H ((volatile unsigned short *)CAN1_AM17H)
+#define pCAN1_AM18L ((volatile unsigned short *)CAN1_AM18L)
+#define pCAN1_AM18H ((volatile unsigned short *)CAN1_AM18H)
+#define pCAN1_AM19L ((volatile unsigned short *)CAN1_AM19L)
+#define pCAN1_AM19H ((volatile unsigned short *)CAN1_AM19H)
+#define pCAN1_AM20L ((volatile unsigned short *)CAN1_AM20L)
+#define pCAN1_AM20H ((volatile unsigned short *)CAN1_AM20H)
+#define pCAN1_AM21L ((volatile unsigned short *)CAN1_AM21L)
+#define pCAN1_AM21H ((volatile unsigned short *)CAN1_AM21H)
+#define pCAN1_AM22L ((volatile unsigned short *)CAN1_AM22L)
+#define pCAN1_AM22H ((volatile unsigned short *)CAN1_AM22H)
+#define pCAN1_AM23L ((volatile unsigned short *)CAN1_AM23L)
+#define pCAN1_AM23H ((volatile unsigned short *)CAN1_AM23H)
+#define pCAN1_AM24L ((volatile unsigned short *)CAN1_AM24L)
+#define pCAN1_AM24H ((volatile unsigned short *)CAN1_AM24H)
+#define pCAN1_AM25L ((volatile unsigned short *)CAN1_AM25L)
+#define pCAN1_AM25H ((volatile unsigned short *)CAN1_AM25H)
+#define pCAN1_AM26L ((volatile unsigned short *)CAN1_AM26L)
+#define pCAN1_AM26H ((volatile unsigned short *)CAN1_AM26H)
+#define pCAN1_AM27L ((volatile unsigned short *)CAN1_AM27L)
+#define pCAN1_AM27H ((volatile unsigned short *)CAN1_AM27H)
+#define pCAN1_AM28L ((volatile unsigned short *)CAN1_AM28L)
+#define pCAN1_AM28H ((volatile unsigned short *)CAN1_AM28H)
+#define pCAN1_AM29L ((volatile unsigned short *)CAN1_AM29L)
+#define pCAN1_AM29H ((volatile unsigned short *)CAN1_AM29H)
+#define pCAN1_AM30L ((volatile unsigned short *)CAN1_AM30L)
+#define pCAN1_AM30H ((volatile unsigned short *)CAN1_AM30H)
+#define pCAN1_AM31L ((volatile unsigned short *)CAN1_AM31L)
+#define pCAN1_AM31H ((volatile unsigned short *)CAN1_AM31H)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define pCAN1_MB00_DATA0 ((volatile unsigned short *)CAN1_MB00_DATA0)
+#define pCAN1_MB00_DATA1 ((volatile unsigned short *)CAN1_MB00_DATA1)
+#define pCAN1_MB00_DATA2 ((volatile unsigned short *)CAN1_MB00_DATA2)
+#define pCAN1_MB00_DATA3 ((volatile unsigned short *)CAN1_MB00_DATA3)
+#define pCAN1_MB00_LENGTH ((volatile unsigned short *)CAN1_MB00_LENGTH)
+#define pCAN1_MB00_TIMESTAMP ((volatile unsigned short *)CAN1_MB00_TIMESTAMP)
+#define pCAN1_MB00_ID0 ((volatile unsigned short *)CAN1_MB00_ID0)
+#define pCAN1_MB00_ID1 ((volatile unsigned short *)CAN1_MB00_ID1)
+#define pCAN1_MB01_DATA0 ((volatile unsigned short *)CAN1_MB01_DATA0)
+#define pCAN1_MB01_DATA1 ((volatile unsigned short *)CAN1_MB01_DATA1)
+#define pCAN1_MB01_DATA2 ((volatile unsigned short *)CAN1_MB01_DATA2)
+#define pCAN1_MB01_DATA3 ((volatile unsigned short *)CAN1_MB01_DATA3)
+#define pCAN1_MB01_LENGTH ((volatile unsigned short *)CAN1_MB01_LENGTH)
+#define pCAN1_MB01_TIMESTAMP ((volatile unsigned short *)CAN1_MB01_TIMESTAMP)
+#define pCAN1_MB01_ID0 ((volatile unsigned short *)CAN1_MB01_ID0)
+#define pCAN1_MB01_ID1 ((volatile unsigned short *)CAN1_MB01_ID1)
+#define pCAN1_MB02_DATA0 ((volatile unsigned short *)CAN1_MB02_DATA0)
+#define pCAN1_MB02_DATA1 ((volatile unsigned short *)CAN1_MB02_DATA1)
+#define pCAN1_MB02_DATA2 ((volatile unsigned short *)CAN1_MB02_DATA2)
+#define pCAN1_MB02_DATA3 ((volatile unsigned short *)CAN1_MB02_DATA3)
+#define pCAN1_MB02_LENGTH ((volatile unsigned short *)CAN1_MB02_LENGTH)
+#define pCAN1_MB02_TIMESTAMP ((volatile unsigned short *)CAN1_MB02_TIMESTAMP)
+#define pCAN1_MB02_ID0 ((volatile unsigned short *)CAN1_MB02_ID0)
+#define pCAN1_MB02_ID1 ((volatile unsigned short *)CAN1_MB02_ID1)
+#define pCAN1_MB03_DATA0 ((volatile unsigned short *)CAN1_MB03_DATA0)
+#define pCAN1_MB03_DATA1 ((volatile unsigned short *)CAN1_MB03_DATA1)
+#define pCAN1_MB03_DATA2 ((volatile unsigned short *)CAN1_MB03_DATA2)
+#define pCAN1_MB03_DATA3 ((volatile unsigned short *)CAN1_MB03_DATA3)
+#define pCAN1_MB03_LENGTH ((volatile unsigned short *)CAN1_MB03_LENGTH)
+#define pCAN1_MB03_TIMESTAMP ((volatile unsigned short *)CAN1_MB03_TIMESTAMP)
+#define pCAN1_MB03_ID0 ((volatile unsigned short *)CAN1_MB03_ID0)
+#define pCAN1_MB03_ID1 ((volatile unsigned short *)CAN1_MB03_ID1)
+#define pCAN1_MB04_DATA0 ((volatile unsigned short *)CAN1_MB04_DATA0)
+#define pCAN1_MB04_DATA1 ((volatile unsigned short *)CAN1_MB04_DATA1)
+#define pCAN1_MB04_DATA2 ((volatile unsigned short *)CAN1_MB04_DATA2)
+#define pCAN1_MB04_DATA3 ((volatile unsigned short *)CAN1_MB04_DATA3)
+#define pCAN1_MB04_LENGTH ((volatile unsigned short *)CAN1_MB04_LENGTH)
+#define pCAN1_MB04_TIMESTAMP ((volatile unsigned short *)CAN1_MB04_TIMESTAMP)
+#define pCAN1_MB04_ID0 ((volatile unsigned short *)CAN1_MB04_ID0)
+#define pCAN1_MB04_ID1 ((volatile unsigned short *)CAN1_MB04_ID1)
+#define pCAN1_MB05_DATA0 ((volatile unsigned short *)CAN1_MB05_DATA0)
+#define pCAN1_MB05_DATA1 ((volatile unsigned short *)CAN1_MB05_DATA1)
+#define pCAN1_MB05_DATA2 ((volatile unsigned short *)CAN1_MB05_DATA2)
+#define pCAN1_MB05_DATA3 ((volatile unsigned short *)CAN1_MB05_DATA3)
+#define pCAN1_MB05_LENGTH ((volatile unsigned short *)CAN1_MB05_LENGTH)
+#define pCAN1_MB05_TIMESTAMP ((volatile unsigned short *)CAN1_MB05_TIMESTAMP)
+#define pCAN1_MB05_ID0 ((volatile unsigned short *)CAN1_MB05_ID0)
+#define pCAN1_MB05_ID1 ((volatile unsigned short *)CAN1_MB05_ID1)
+#define pCAN1_MB06_DATA0 ((volatile unsigned short *)CAN1_MB06_DATA0)
+#define pCAN1_MB06_DATA1 ((volatile unsigned short *)CAN1_MB06_DATA1)
+#define pCAN1_MB06_DATA2 ((volatile unsigned short *)CAN1_MB06_DATA2)
+#define pCAN1_MB06_DATA3 ((volatile unsigned short *)CAN1_MB06_DATA3)
+#define pCAN1_MB06_LENGTH ((volatile unsigned short *)CAN1_MB06_LENGTH)
+#define pCAN1_MB06_TIMESTAMP ((volatile unsigned short *)CAN1_MB06_TIMESTAMP)
+#define pCAN1_MB06_ID0 ((volatile unsigned short *)CAN1_MB06_ID0)
+#define pCAN1_MB06_ID1 ((volatile unsigned short *)CAN1_MB06_ID1)
+#define pCAN1_MB07_DATA0 ((volatile unsigned short *)CAN1_MB07_DATA0)
+#define pCAN1_MB07_DATA1 ((volatile unsigned short *)CAN1_MB07_DATA1)
+#define pCAN1_MB07_DATA2 ((volatile unsigned short *)CAN1_MB07_DATA2)
+#define pCAN1_MB07_DATA3 ((volatile unsigned short *)CAN1_MB07_DATA3)
+#define pCAN1_MB07_LENGTH ((volatile unsigned short *)CAN1_MB07_LENGTH)
+#define pCAN1_MB07_TIMESTAMP ((volatile unsigned short *)CAN1_MB07_TIMESTAMP)
+#define pCAN1_MB07_ID0 ((volatile unsigned short *)CAN1_MB07_ID0)
+#define pCAN1_MB07_ID1 ((volatile unsigned short *)CAN1_MB07_ID1)
+#define pCAN1_MB08_DATA0 ((volatile unsigned short *)CAN1_MB08_DATA0)
+#define pCAN1_MB08_DATA1 ((volatile unsigned short *)CAN1_MB08_DATA1)
+#define pCAN1_MB08_DATA2 ((volatile unsigned short *)CAN1_MB08_DATA2)
+#define pCAN1_MB08_DATA3 ((volatile unsigned short *)CAN1_MB08_DATA3)
+#define pCAN1_MB08_LENGTH ((volatile unsigned short *)CAN1_MB08_LENGTH)
+#define pCAN1_MB08_TIMESTAMP ((volatile unsigned short *)CAN1_MB08_TIMESTAMP)
+#define pCAN1_MB08_ID0 ((volatile unsigned short *)CAN1_MB08_ID0)
+#define pCAN1_MB08_ID1 ((volatile unsigned short *)CAN1_MB08_ID1)
+#define pCAN1_MB09_DATA0 ((volatile unsigned short *)CAN1_MB09_DATA0)
+#define pCAN1_MB09_DATA1 ((volatile unsigned short *)CAN1_MB09_DATA1)
+#define pCAN1_MB09_DATA2 ((volatile unsigned short *)CAN1_MB09_DATA2)
+#define pCAN1_MB09_DATA3 ((volatile unsigned short *)CAN1_MB09_DATA3)
+#define pCAN1_MB09_LENGTH ((volatile unsigned short *)CAN1_MB09_LENGTH)
+#define pCAN1_MB09_TIMESTAMP ((volatile unsigned short *)CAN1_MB09_TIMESTAMP)
+#define pCAN1_MB09_ID0 ((volatile unsigned short *)CAN1_MB09_ID0)
+#define pCAN1_MB09_ID1 ((volatile unsigned short *)CAN1_MB09_ID1)
+#define pCAN1_MB10_DATA0 ((volatile unsigned short *)CAN1_MB10_DATA0)
+#define pCAN1_MB10_DATA1 ((volatile unsigned short *)CAN1_MB10_DATA1)
+#define pCAN1_MB10_DATA2 ((volatile unsigned short *)CAN1_MB10_DATA2)
+#define pCAN1_MB10_DATA3 ((volatile unsigned short *)CAN1_MB10_DATA3)
+#define pCAN1_MB10_LENGTH ((volatile unsigned short *)CAN1_MB10_LENGTH)
+#define pCAN1_MB10_TIMESTAMP ((volatile unsigned short *)CAN1_MB10_TIMESTAMP)
+#define pCAN1_MB10_ID0 ((volatile unsigned short *)CAN1_MB10_ID0)
+#define pCAN1_MB10_ID1 ((volatile unsigned short *)CAN1_MB10_ID1)
+#define pCAN1_MB11_DATA0 ((volatile unsigned short *)CAN1_MB11_DATA0)
+#define pCAN1_MB11_DATA1 ((volatile unsigned short *)CAN1_MB11_DATA1)
+#define pCAN1_MB11_DATA2 ((volatile unsigned short *)CAN1_MB11_DATA2)
+#define pCAN1_MB11_DATA3 ((volatile unsigned short *)CAN1_MB11_DATA3)
+#define pCAN1_MB11_LENGTH ((volatile unsigned short *)CAN1_MB11_LENGTH)
+#define pCAN1_MB11_TIMESTAMP ((volatile unsigned short *)CAN1_MB11_TIMESTAMP)
+#define pCAN1_MB11_ID0 ((volatile unsigned short *)CAN1_MB11_ID0)
+#define pCAN1_MB11_ID1 ((volatile unsigned short *)CAN1_MB11_ID1)
+#define pCAN1_MB12_DATA0 ((volatile unsigned short *)CAN1_MB12_DATA0)
+#define pCAN1_MB12_DATA1 ((volatile unsigned short *)CAN1_MB12_DATA1)
+#define pCAN1_MB12_DATA2 ((volatile unsigned short *)CAN1_MB12_DATA2)
+#define pCAN1_MB12_DATA3 ((volatile unsigned short *)CAN1_MB12_DATA3)
+#define pCAN1_MB12_LENGTH ((volatile unsigned short *)CAN1_MB12_LENGTH)
+#define pCAN1_MB12_TIMESTAMP ((volatile unsigned short *)CAN1_MB12_TIMESTAMP)
+#define pCAN1_MB12_ID0 ((volatile unsigned short *)CAN1_MB12_ID0)
+#define pCAN1_MB12_ID1 ((volatile unsigned short *)CAN1_MB12_ID1)
+#define pCAN1_MB13_DATA0 ((volatile unsigned short *)CAN1_MB13_DATA0)
+#define pCAN1_MB13_DATA1 ((volatile unsigned short *)CAN1_MB13_DATA1)
+#define pCAN1_MB13_DATA2 ((volatile unsigned short *)CAN1_MB13_DATA2)
+#define pCAN1_MB13_DATA3 ((volatile unsigned short *)CAN1_MB13_DATA3)
+#define pCAN1_MB13_LENGTH ((volatile unsigned short *)CAN1_MB13_LENGTH)
+#define pCAN1_MB13_TIMESTAMP ((volatile unsigned short *)CAN1_MB13_TIMESTAMP)
+#define pCAN1_MB13_ID0 ((volatile unsigned short *)CAN1_MB13_ID0)
+#define pCAN1_MB13_ID1 ((volatile unsigned short *)CAN1_MB13_ID1)
+#define pCAN1_MB14_DATA0 ((volatile unsigned short *)CAN1_MB14_DATA0)
+#define pCAN1_MB14_DATA1 ((volatile unsigned short *)CAN1_MB14_DATA1)
+#define pCAN1_MB14_DATA2 ((volatile unsigned short *)CAN1_MB14_DATA2)
+#define pCAN1_MB14_DATA3 ((volatile unsigned short *)CAN1_MB14_DATA3)
+#define pCAN1_MB14_LENGTH ((volatile unsigned short *)CAN1_MB14_LENGTH)
+#define pCAN1_MB14_TIMESTAMP ((volatile unsigned short *)CAN1_MB14_TIMESTAMP)
+#define pCAN1_MB14_ID0 ((volatile unsigned short *)CAN1_MB14_ID0)
+#define pCAN1_MB14_ID1 ((volatile unsigned short *)CAN1_MB14_ID1)
+#define pCAN1_MB15_DATA0 ((volatile unsigned short *)CAN1_MB15_DATA0)
+#define pCAN1_MB15_DATA1 ((volatile unsigned short *)CAN1_MB15_DATA1)
+#define pCAN1_MB15_DATA2 ((volatile unsigned short *)CAN1_MB15_DATA2)
+#define pCAN1_MB15_DATA3 ((volatile unsigned short *)CAN1_MB15_DATA3)
+#define pCAN1_MB15_LENGTH ((volatile unsigned short *)CAN1_MB15_LENGTH)
+#define pCAN1_MB15_TIMESTAMP ((volatile unsigned short *)CAN1_MB15_TIMESTAMP)
+#define pCAN1_MB15_ID0 ((volatile unsigned short *)CAN1_MB15_ID0)
+#define pCAN1_MB15_ID1 ((volatile unsigned short *)CAN1_MB15_ID1)
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define pCAN1_MB16_DATA0 ((volatile unsigned short *)CAN1_MB16_DATA0)
+#define pCAN1_MB16_DATA1 ((volatile unsigned short *)CAN1_MB16_DATA1)
+#define pCAN1_MB16_DATA2 ((volatile unsigned short *)CAN1_MB16_DATA2)
+#define pCAN1_MB16_DATA3 ((volatile unsigned short *)CAN1_MB16_DATA3)
+#define pCAN1_MB16_LENGTH ((volatile unsigned short *)CAN1_MB16_LENGTH)
+#define pCAN1_MB16_TIMESTAMP ((volatile unsigned short *)CAN1_MB16_TIMESTAMP)
+#define pCAN1_MB16_ID0 ((volatile unsigned short *)CAN1_MB16_ID0)
+#define pCAN1_MB16_ID1 ((volatile unsigned short *)CAN1_MB16_ID1)
+#define pCAN1_MB17_DATA0 ((volatile unsigned short *)CAN1_MB17_DATA0)
+#define pCAN1_MB17_DATA1 ((volatile unsigned short *)CAN1_MB17_DATA1)
+#define pCAN1_MB17_DATA2 ((volatile unsigned short *)CAN1_MB17_DATA2)
+#define pCAN1_MB17_DATA3 ((volatile unsigned short *)CAN1_MB17_DATA3)
+#define pCAN1_MB17_LENGTH ((volatile unsigned short *)CAN1_MB17_LENGTH)
+#define pCAN1_MB17_TIMESTAMP ((volatile unsigned short *)CAN1_MB17_TIMESTAMP)
+#define pCAN1_MB17_ID0 ((volatile unsigned short *)CAN1_MB17_ID0)
+#define pCAN1_MB17_ID1 ((volatile unsigned short *)CAN1_MB17_ID1)
+#define pCAN1_MB18_DATA0 ((volatile unsigned short *)CAN1_MB18_DATA0)
+#define pCAN1_MB18_DATA1 ((volatile unsigned short *)CAN1_MB18_DATA1)
+#define pCAN1_MB18_DATA2 ((volatile unsigned short *)CAN1_MB18_DATA2)
+#define pCAN1_MB18_DATA3 ((volatile unsigned short *)CAN1_MB18_DATA3)
+#define pCAN1_MB18_LENGTH ((volatile unsigned short *)CAN1_MB18_LENGTH)
+#define pCAN1_MB18_TIMESTAMP ((volatile unsigned short *)CAN1_MB18_TIMESTAMP)
+#define pCAN1_MB18_ID0 ((volatile unsigned short *)CAN1_MB18_ID0)
+#define pCAN1_MB18_ID1 ((volatile unsigned short *)CAN1_MB18_ID1)
+#define pCAN1_MB19_DATA0 ((volatile unsigned short *)CAN1_MB19_DATA0)
+#define pCAN1_MB19_DATA1 ((volatile unsigned short *)CAN1_MB19_DATA1)
+#define pCAN1_MB19_DATA2 ((volatile unsigned short *)CAN1_MB19_DATA2)
+#define pCAN1_MB19_DATA3 ((volatile unsigned short *)CAN1_MB19_DATA3)
+#define pCAN1_MB19_LENGTH ((volatile unsigned short *)CAN1_MB19_LENGTH)
+#define pCAN1_MB19_TIMESTAMP ((volatile unsigned short *)CAN1_MB19_TIMESTAMP)
+#define pCAN1_MB19_ID0 ((volatile unsigned short *)CAN1_MB19_ID0)
+#define pCAN1_MB19_ID1 ((volatile unsigned short *)CAN1_MB19_ID1)
+#define pCAN1_MB20_DATA0 ((volatile unsigned short *)CAN1_MB20_DATA0)
+#define pCAN1_MB20_DATA1 ((volatile unsigned short *)CAN1_MB20_DATA1)
+#define pCAN1_MB20_DATA2 ((volatile unsigned short *)CAN1_MB20_DATA2)
+#define pCAN1_MB20_DATA3 ((volatile unsigned short *)CAN1_MB20_DATA3)
+#define pCAN1_MB20_LENGTH ((volatile unsigned short *)CAN1_MB20_LENGTH)
+#define pCAN1_MB20_TIMESTAMP ((volatile unsigned short *)CAN1_MB20_TIMESTAMP)
+#define pCAN1_MB20_ID0 ((volatile unsigned short *)CAN1_MB20_ID0)
+#define pCAN1_MB20_ID1 ((volatile unsigned short *)CAN1_MB20_ID1)
+#define pCAN1_MB21_DATA0 ((volatile unsigned short *)CAN1_MB21_DATA0)
+#define pCAN1_MB21_DATA1 ((volatile unsigned short *)CAN1_MB21_DATA1)
+#define pCAN1_MB21_DATA2 ((volatile unsigned short *)CAN1_MB21_DATA2)
+#define pCAN1_MB21_DATA3 ((volatile unsigned short *)CAN1_MB21_DATA3)
+#define pCAN1_MB21_LENGTH ((volatile unsigned short *)CAN1_MB21_LENGTH)
+#define pCAN1_MB21_TIMESTAMP ((volatile unsigned short *)CAN1_MB21_TIMESTAMP)
+#define pCAN1_MB21_ID0 ((volatile unsigned short *)CAN1_MB21_ID0)
+#define pCAN1_MB21_ID1 ((volatile unsigned short *)CAN1_MB21_ID1)
+#define pCAN1_MB22_DATA0 ((volatile unsigned short *)CAN1_MB22_DATA0)
+#define pCAN1_MB22_DATA1 ((volatile unsigned short *)CAN1_MB22_DATA1)
+#define pCAN1_MB22_DATA2 ((volatile unsigned short *)CAN1_MB22_DATA2)
+#define pCAN1_MB22_DATA3 ((volatile unsigned short *)CAN1_MB22_DATA3)
+#define pCAN1_MB22_LENGTH ((volatile unsigned short *)CAN1_MB22_LENGTH)
+#define pCAN1_MB22_TIMESTAMP ((volatile unsigned short *)CAN1_MB22_TIMESTAMP)
+#define pCAN1_MB22_ID0 ((volatile unsigned short *)CAN1_MB22_ID0)
+#define pCAN1_MB22_ID1 ((volatile unsigned short *)CAN1_MB22_ID1)
+#define pCAN1_MB23_DATA0 ((volatile unsigned short *)CAN1_MB23_DATA0)
+#define pCAN1_MB23_DATA1 ((volatile unsigned short *)CAN1_MB23_DATA1)
+#define pCAN1_MB23_DATA2 ((volatile unsigned short *)CAN1_MB23_DATA2)
+#define pCAN1_MB23_DATA3 ((volatile unsigned short *)CAN1_MB23_DATA3)
+#define pCAN1_MB23_LENGTH ((volatile unsigned short *)CAN1_MB23_LENGTH)
+#define pCAN1_MB23_TIMESTAMP ((volatile unsigned short *)CAN1_MB23_TIMESTAMP)
+#define pCAN1_MB23_ID0 ((volatile unsigned short *)CAN1_MB23_ID0)
+#define pCAN1_MB23_ID1 ((volatile unsigned short *)CAN1_MB23_ID1)
+#define pCAN1_MB24_DATA0 ((volatile unsigned short *)CAN1_MB24_DATA0)
+#define pCAN1_MB24_DATA1 ((volatile unsigned short *)CAN1_MB24_DATA1)
+#define pCAN1_MB24_DATA2 ((volatile unsigned short *)CAN1_MB24_DATA2)
+#define pCAN1_MB24_DATA3 ((volatile unsigned short *)CAN1_MB24_DATA3)
+#define pCAN1_MB24_LENGTH ((volatile unsigned short *)CAN1_MB24_LENGTH)
+#define pCAN1_MB24_TIMESTAMP ((volatile unsigned short *)CAN1_MB24_TIMESTAMP)
+#define pCAN1_MB24_ID0 ((volatile unsigned short *)CAN1_MB24_ID0)
+#define pCAN1_MB24_ID1 ((volatile unsigned short *)CAN1_MB24_ID1)
+#define pCAN1_MB25_DATA0 ((volatile unsigned short *)CAN1_MB25_DATA0)
+#define pCAN1_MB25_DATA1 ((volatile unsigned short *)CAN1_MB25_DATA1)
+#define pCAN1_MB25_DATA2 ((volatile unsigned short *)CAN1_MB25_DATA2)
+#define pCAN1_MB25_DATA3 ((volatile unsigned short *)CAN1_MB25_DATA3)
+#define pCAN1_MB25_LENGTH ((volatile unsigned short *)CAN1_MB25_LENGTH)
+#define pCAN1_MB25_TIMESTAMP ((volatile unsigned short *)CAN1_MB25_TIMESTAMP)
+#define pCAN1_MB25_ID0 ((volatile unsigned short *)CAN1_MB25_ID0)
+#define pCAN1_MB25_ID1 ((volatile unsigned short *)CAN1_MB25_ID1)
+#define pCAN1_MB26_DATA0 ((volatile unsigned short *)CAN1_MB26_DATA0)
+#define pCAN1_MB26_DATA1 ((volatile unsigned short *)CAN1_MB26_DATA1)
+#define pCAN1_MB26_DATA2 ((volatile unsigned short *)CAN1_MB26_DATA2)
+#define pCAN1_MB26_DATA3 ((volatile unsigned short *)CAN1_MB26_DATA3)
+#define pCAN1_MB26_LENGTH ((volatile unsigned short *)CAN1_MB26_LENGTH)
+#define pCAN1_MB26_TIMESTAMP ((volatile unsigned short *)CAN1_MB26_TIMESTAMP)
+#define pCAN1_MB26_ID0 ((volatile unsigned short *)CAN1_MB26_ID0)
+#define pCAN1_MB26_ID1 ((volatile unsigned short *)CAN1_MB26_ID1)
+#define pCAN1_MB27_DATA0 ((volatile unsigned short *)CAN1_MB27_DATA0)
+#define pCAN1_MB27_DATA1 ((volatile unsigned short *)CAN1_MB27_DATA1)
+#define pCAN1_MB27_DATA2 ((volatile unsigned short *)CAN1_MB27_DATA2)
+#define pCAN1_MB27_DATA3 ((volatile unsigned short *)CAN1_MB27_DATA3)
+#define pCAN1_MB27_LENGTH ((volatile unsigned short *)CAN1_MB27_LENGTH)
+#define pCAN1_MB27_TIMESTAMP ((volatile unsigned short *)CAN1_MB27_TIMESTAMP)
+#define pCAN1_MB27_ID0 ((volatile unsigned short *)CAN1_MB27_ID0)
+#define pCAN1_MB27_ID1 ((volatile unsigned short *)CAN1_MB27_ID1)
+#define pCAN1_MB28_DATA0 ((volatile unsigned short *)CAN1_MB28_DATA0)
+#define pCAN1_MB28_DATA1 ((volatile unsigned short *)CAN1_MB28_DATA1)
+#define pCAN1_MB28_DATA2 ((volatile unsigned short *)CAN1_MB28_DATA2)
+#define pCAN1_MB28_DATA3 ((volatile unsigned short *)CAN1_MB28_DATA3)
+#define pCAN1_MB28_LENGTH ((volatile unsigned short *)CAN1_MB28_LENGTH)
+#define pCAN1_MB28_TIMESTAMP ((volatile unsigned short *)CAN1_MB28_TIMESTAMP)
+#define pCAN1_MB28_ID0 ((volatile unsigned short *)CAN1_MB28_ID0)
+#define pCAN1_MB28_ID1 ((volatile unsigned short *)CAN1_MB28_ID1)
+#define pCAN1_MB29_DATA0 ((volatile unsigned short *)CAN1_MB29_DATA0)
+#define pCAN1_MB29_DATA1 ((volatile unsigned short *)CAN1_MB29_DATA1)
+#define pCAN1_MB29_DATA2 ((volatile unsigned short *)CAN1_MB29_DATA2)
+#define pCAN1_MB29_DATA3 ((volatile unsigned short *)CAN1_MB29_DATA3)
+#define pCAN1_MB29_LENGTH ((volatile unsigned short *)CAN1_MB29_LENGTH)
+#define pCAN1_MB29_TIMESTAMP ((volatile unsigned short *)CAN1_MB29_TIMESTAMP)
+#define pCAN1_MB29_ID0 ((volatile unsigned short *)CAN1_MB29_ID0)
+#define pCAN1_MB29_ID1 ((volatile unsigned short *)CAN1_MB29_ID1)
+#define pCAN1_MB30_DATA0 ((volatile unsigned short *)CAN1_MB30_DATA0)
+#define pCAN1_MB30_DATA1 ((volatile unsigned short *)CAN1_MB30_DATA1)
+#define pCAN1_MB30_DATA2 ((volatile unsigned short *)CAN1_MB30_DATA2)
+#define pCAN1_MB30_DATA3 ((volatile unsigned short *)CAN1_MB30_DATA3)
+#define pCAN1_MB30_LENGTH ((volatile unsigned short *)CAN1_MB30_LENGTH)
+#define pCAN1_MB30_TIMESTAMP ((volatile unsigned short *)CAN1_MB30_TIMESTAMP)
+#define pCAN1_MB30_ID0 ((volatile unsigned short *)CAN1_MB30_ID0)
+#define pCAN1_MB30_ID1 ((volatile unsigned short *)CAN1_MB30_ID1)
+#define pCAN1_MB31_DATA0 ((volatile unsigned short *)CAN1_MB31_DATA0)
+#define pCAN1_MB31_DATA1 ((volatile unsigned short *)CAN1_MB31_DATA1)
+#define pCAN1_MB31_DATA2 ((volatile unsigned short *)CAN1_MB31_DATA2)
+#define pCAN1_MB31_DATA3 ((volatile unsigned short *)CAN1_MB31_DATA3)
+#define pCAN1_MB31_LENGTH ((volatile unsigned short *)CAN1_MB31_LENGTH)
+#define pCAN1_MB31_TIMESTAMP ((volatile unsigned short *)CAN1_MB31_TIMESTAMP)
+#define pCAN1_MB31_ID0 ((volatile unsigned short *)CAN1_MB31_ID0)
+#define pCAN1_MB31_ID1 ((volatile unsigned short *)CAN1_MB31_ID1)
+
+/* ATAPI Registers */
+
+#define pATAPI_CONTROL ((volatile unsigned short *)ATAPI_CONTROL)
+#define pATAPI_STATUS ((volatile unsigned short *)ATAPI_STATUS)
+#define pATAPI_DEV_ADDR ((volatile unsigned short *)ATAPI_DEV_ADDR)
+#define pATAPI_DEV_TXBUF ((volatile unsigned short *)ATAPI_DEV_TXBUF)
+#define pATAPI_DEV_RXBUF ((volatile unsigned short *)ATAPI_DEV_RXBUF)
+#define pATAPI_INT_MASK ((volatile unsigned short *)ATAPI_INT_MASK)
+#define pATAPI_INT_STATUS ((volatile unsigned short *)ATAPI_INT_STATUS)
+#define pATAPI_XFER_LEN ((volatile unsigned short *)ATAPI_XFER_LEN)
+#define pATAPI_LINE_STATUS ((volatile unsigned short *)ATAPI_LINE_STATUS)
+#define pATAPI_SM_STATE ((volatile unsigned short *)ATAPI_SM_STATE)
+#define pATAPI_TERMINATE ((volatile unsigned short *)ATAPI_TERMINATE)
+#define pATAPI_PIO_TFRCNT ((volatile unsigned short *)ATAPI_PIO_TFRCNT)
+#define pATAPI_DMA_TFRCNT ((volatile unsigned short *)ATAPI_DMA_TFRCNT)
+#define pATAPI_UMAIN_TFRCNT ((volatile unsigned short *)ATAPI_UMAIN_TFRCNT)
+#define pATAPI_UDMAOUT_TFRCNT ((volatile unsigned short *)ATAPI_UDMAOUT_TFRCNT)
+#define pATAPI_REG_TIM_0 ((volatile unsigned short *)ATAPI_REG_TIM_0)
+#define pATAPI_PIO_TIM_0 ((volatile unsigned short *)ATAPI_PIO_TIM_0)
+#define pATAPI_PIO_TIM_1 ((volatile unsigned short *)ATAPI_PIO_TIM_1)
+#define pATAPI_MULTI_TIM_0 ((volatile unsigned short *)ATAPI_MULTI_TIM_0)
+#define pATAPI_MULTI_TIM_1 ((volatile unsigned short *)ATAPI_MULTI_TIM_1)
+#define pATAPI_MULTI_TIM_2 ((volatile unsigned short *)ATAPI_MULTI_TIM_2)
+#define pATAPI_ULTRA_TIM_0 ((volatile unsigned short *)ATAPI_ULTRA_TIM_0)
+#define pATAPI_ULTRA_TIM_1 ((volatile unsigned short *)ATAPI_ULTRA_TIM_1)
+#define pATAPI_ULTRA_TIM_2 ((volatile unsigned short *)ATAPI_ULTRA_TIM_2)
+#define pATAPI_ULTRA_TIM_3 ((volatile unsigned short *)ATAPI_ULTRA_TIM_3)
+
+/* SDH Registers */
+
+#define pSDH_PWR_CTL ((volatile unsigned short *)SDH_PWR_CTL)
+#define pSDH_CLK_CTL ((volatile unsigned short *)SDH_CLK_CTL)
+#define pSDH_ARGUMENT ((volatile unsigned long *)SDH_ARGUMENT)
+#define pSDH_COMMAND ((volatile unsigned short *)SDH_COMMAND)
+#define pSDH_RESP_CMD ((volatile unsigned short *)SDH_RESP_CMD)
+#define pSDH_RESPONSE0 ((volatile unsigned long *)SDH_RESPONSE0)
+#define pSDH_RESPONSE1 ((volatile unsigned long *)SDH_RESPONSE1)
+#define pSDH_RESPONSE2 ((volatile unsigned long *)SDH_RESPONSE2)
+#define pSDH_RESPONSE3 ((volatile unsigned long *)SDH_RESPONSE3)
+#define pSDH_DATA_TIMER ((volatile unsigned long *)SDH_DATA_TIMER)
+#define pSDH_DATA_LGTH ((volatile unsigned short *)SDH_DATA_LGTH)
+#define pSDH_DATA_CTL ((volatile unsigned short *)SDH_DATA_CTL)
+#define pSDH_DATA_CNT ((volatile unsigned short *)SDH_DATA_CNT)
+#define pSDH_STATUS ((volatile unsigned long *)SDH_STATUS)
+#define pSDH_STATUS_CLR ((volatile unsigned short *)SDH_STATUS_CLR)
+#define pSDH_MASK0 ((volatile unsigned long *)SDH_MASK0)
+#define pSDH_MASK1 ((volatile unsigned long *)SDH_MASK1)
+#define pSDH_FIFO_CNT ((volatile unsigned short *)SDH_FIFO_CNT)
+#define pSDH_FIFO ((volatile unsigned long *)SDH_FIFO)
+#define pSDH_E_STATUS ((volatile unsigned short *)SDH_E_STATUS)
+#define pSDH_E_MASK ((volatile unsigned short *)SDH_E_MASK)
+#define pSDH_CFG ((volatile unsigned short *)SDH_CFG)
+#define pSDH_RD_WAIT_EN ((volatile unsigned short *)SDH_RD_WAIT_EN)
+#define pSDH_PID0 ((volatile unsigned short *)SDH_PID0)
+#define pSDH_PID1 ((volatile unsigned short *)SDH_PID1)
+#define pSDH_PID2 ((volatile unsigned short *)SDH_PID2)
+#define pSDH_PID3 ((volatile unsigned short *)SDH_PID3)
+#define pSDH_PID4 ((volatile unsigned short *)SDH_PID4)
+#define pSDH_PID5 ((volatile unsigned short *)SDH_PID5)
+#define pSDH_PID6 ((volatile unsigned short *)SDH_PID6)
+#define pSDH_PID7 ((volatile unsigned short *)SDH_PID7)
+
+/* HOST Port Registers */
+
+#define pHOST_CONTROL ((volatile unsigned short *)HOST_CONTROL)
+#define pHOST_STATUS ((volatile unsigned short *)HOST_STATUS)
+#define pHOST_TIMEOUT ((volatile unsigned short *)HOST_TIMEOUT)
+
+/* USB Control Registers */
+
+#define pUSB_FADDR ((volatile unsigned short *)USB_FADDR)
+#define pUSB_POWER ((volatile unsigned short *)USB_POWER)
+#define pUSB_INTRTX ((volatile unsigned short *)USB_INTRTX)
+#define pUSB_INTRRX ((volatile unsigned short *)USB_INTRRX)
+#define pUSB_INTRTXE ((volatile unsigned short *)USB_INTRTXE)
+#define pUSB_INTRRXE ((volatile unsigned short *)USB_INTRRXE)
+#define pUSB_INTRUSB ((volatile unsigned short *)USB_INTRUSB)
+#define pUSB_INTRUSBE ((volatile unsigned short *)USB_INTRUSBE)
+#define pUSB_FRAME ((volatile unsigned short *)USB_FRAME)
+#define pUSB_INDEX ((volatile unsigned short *)USB_INDEX)
+#define pUSB_TESTMODE ((volatile unsigned short *)USB_TESTMODE)
+#define pUSB_GLOBINTR ((volatile unsigned short *)USB_GLOBINTR)
+#define pUSB_GLOBAL_CTL ((volatile unsigned short *)USB_GLOBAL_CTL)
+
+/* USB Packet Control Registers */
+
+#define pUSB_TX_MAX_PACKET ((volatile unsigned short *)USB_TX_MAX_PACKET)
+#define pUSB_CSR0 ((volatile unsigned short *)USB_CSR0)
+#define pUSB_TXCSR ((volatile unsigned short *)USB_TXCSR)
+#define pUSB_RX_MAX_PACKET ((volatile unsigned short *)USB_RX_MAX_PACKET)
+#define pUSB_RXCSR ((volatile unsigned short *)USB_RXCSR)
+#define pUSB_COUNT0 ((volatile unsigned short *)USB_COUNT0)
+#define pUSB_RXCOUNT ((volatile unsigned short *)USB_RXCOUNT)
+#define pUSB_TXTYPE ((volatile unsigned short *)USB_TXTYPE)
+#define pUSB_NAKLIMIT0 ((volatile unsigned short *)USB_NAKLIMIT0)
+#define pUSB_TXINTERVAL ((volatile unsigned short *)USB_TXINTERVAL)
+#define pUSB_RXTYPE ((volatile unsigned short *)USB_RXTYPE)
+#define pUSB_RXINTERVAL ((volatile unsigned short *)USB_RXINTERVAL)
+#define pUSB_TXCOUNT ((volatile unsigned short *)USB_TXCOUNT)
+
+/* USB Endpoint FIFO Registers */
+
+#define pUSB_EP0_FIFO ((volatile unsigned short *)USB_EP0_FIFO)
+#define pUSB_EP1_FIFO ((volatile unsigned short *)USB_EP1_FIFO)
+#define pUSB_EP2_FIFO ((volatile unsigned short *)USB_EP2_FIFO)
+#define pUSB_EP3_FIFO ((volatile unsigned short *)USB_EP3_FIFO)
+#define pUSB_EP4_FIFO ((volatile unsigned short *)USB_EP4_FIFO)
+#define pUSB_EP5_FIFO ((volatile unsigned short *)USB_EP5_FIFO)
+#define pUSB_EP6_FIFO ((volatile unsigned short *)USB_EP6_FIFO)
+#define pUSB_EP7_FIFO ((volatile unsigned short *)USB_EP7_FIFO)
+
+/* USB OTG Control Registers */
+
+#define pUSB_OTG_DEV_CTL ((volatile unsigned short *)USB_OTG_DEV_CTL)
+#define pUSB_OTG_VBUS_IRQ ((volatile unsigned short *)USB_OTG_VBUS_IRQ)
+#define pUSB_OTG_VBUS_MASK ((volatile unsigned short *)USB_OTG_VBUS_MASK)
+
+/* USB Phy Control Registers */
+
+#define pUSB_LINKINFO ((volatile unsigned short *)USB_LINKINFO)
+#define pUSB_VPLEN ((volatile unsigned short *)USB_VPLEN)
+#define pUSB_HS_EOF1 ((volatile unsigned short *)USB_HS_EOF1)
+#define pUSB_FS_EOF1 ((volatile unsigned short *)USB_FS_EOF1)
+#define pUSB_LS_EOF1 ((volatile unsigned short *)USB_LS_EOF1)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define pUSB_APHY_CNTRL ((volatile unsigned short *)USB_APHY_CNTRL)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define pUSB_APHY_CALIB ((volatile unsigned short *)USB_APHY_CALIB)
+#define pUSB_APHY_CNTRL2 ((volatile unsigned short *)USB_APHY_CNTRL2)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define pUSB_PHY_TEST ((volatile unsigned short *)USB_PHY_TEST)
+#define pUSB_PLLOSC_CTRL ((volatile unsigned short *)USB_PLLOSC_CTRL)
+#define pUSB_SRP_CLKDIV ((volatile unsigned short *)USB_SRP_CLKDIV)
+
+/* USB Endpoint 0 Control Registers */
+
+#define pUSB_EP_NI0_TXMAXP ((volatile unsigned short *)USB_EP_NI0_TXMAXP)
+#define pUSB_EP_NI0_TXCSR ((volatile unsigned short *)USB_EP_NI0_TXCSR)
+#define pUSB_EP_NI0_RXMAXP ((volatile unsigned short *)USB_EP_NI0_RXMAXP)
+#define pUSB_EP_NI0_RXCSR ((volatile unsigned short *)USB_EP_NI0_RXCSR)
+#define pUSB_EP_NI0_RXCOUNT ((volatile unsigned short *)USB_EP_NI0_RXCOUNT)
+#define pUSB_EP_NI0_TXTYPE ((volatile unsigned short *)USB_EP_NI0_TXTYPE)
+#define pUSB_EP_NI0_TXINTERVAL ((volatile unsigned short *)USB_EP_NI0_TXINTERVAL)
+#define pUSB_EP_NI0_RXTYPE ((volatile unsigned short *)USB_EP_NI0_RXTYPE)
+#define pUSB_EP_NI0_RXINTERVAL ((volatile unsigned short *)USB_EP_NI0_RXINTERVAL)
+
+/* USB Endpoint 1 Control Registers */
+
+#define pUSB_EP_NI0_TXCOUNT ((volatile unsigned short *)USB_EP_NI0_TXCOUNT)
+#define pUSB_EP_NI1_TXMAXP ((volatile unsigned short *)USB_EP_NI1_TXMAXP)
+#define pUSB_EP_NI1_TXCSR ((volatile unsigned short *)USB_EP_NI1_TXCSR)
+#define pUSB_EP_NI1_RXMAXP ((volatile unsigned short *)USB_EP_NI1_RXMAXP)
+#define pUSB_EP_NI1_RXCSR ((volatile unsigned short *)USB_EP_NI1_RXCSR)
+#define pUSB_EP_NI1_RXCOUNT ((volatile unsigned short *)USB_EP_NI1_RXCOUNT)
+#define pUSB_EP_NI1_TXTYPE ((volatile unsigned short *)USB_EP_NI1_TXTYPE)
+#define pUSB_EP_NI1_TXINTERVAL ((volatile unsigned short *)USB_EP_NI1_TXINTERVAL)
+#define pUSB_EP_NI1_RXTYPE ((volatile unsigned short *)USB_EP_NI1_RXTYPE)
+#define pUSB_EP_NI1_RXINTERVAL ((volatile unsigned short *)USB_EP_NI1_RXINTERVAL)
+
+/* USB Endpoint 2 Control Registers */
+
+#define pUSB_EP_NI1_TXCOUNT ((volatile unsigned short *)USB_EP_NI1_TXCOUNT)
+#define pUSB_EP_NI2_TXMAXP ((volatile unsigned short *)USB_EP_NI2_TXMAXP)
+#define pUSB_EP_NI2_TXCSR ((volatile unsigned short *)USB_EP_NI2_TXCSR)
+#define pUSB_EP_NI2_RXMAXP ((volatile unsigned short *)USB_EP_NI2_RXMAXP)
+#define pUSB_EP_NI2_RXCSR ((volatile unsigned short *)USB_EP_NI2_RXCSR)
+#define pUSB_EP_NI2_RXCOUNT ((volatile unsigned short *)USB_EP_NI2_RXCOUNT)
+#define pUSB_EP_NI2_TXTYPE ((volatile unsigned short *)USB_EP_NI2_TXTYPE)
+#define pUSB_EP_NI2_TXINTERVAL ((volatile unsigned short *)USB_EP_NI2_TXINTERVAL)
+#define pUSB_EP_NI2_RXTYPE ((volatile unsigned short *)USB_EP_NI2_RXTYPE)
+#define pUSB_EP_NI2_RXINTERVAL ((volatile unsigned short *)USB_EP_NI2_RXINTERVAL)
+
+/* USB Endpoint 3 Control Registers */
+
+#define pUSB_EP_NI2_TXCOUNT ((volatile unsigned short *)USB_EP_NI2_TXCOUNT)
+#define pUSB_EP_NI3_TXMAXP ((volatile unsigned short *)USB_EP_NI3_TXMAXP)
+#define pUSB_EP_NI3_TXCSR ((volatile unsigned short *)USB_EP_NI3_TXCSR)
+#define pUSB_EP_NI3_RXMAXP ((volatile unsigned short *)USB_EP_NI3_RXMAXP)
+#define pUSB_EP_NI3_RXCSR ((volatile unsigned short *)USB_EP_NI3_RXCSR)
+#define pUSB_EP_NI3_RXCOUNT ((volatile unsigned short *)USB_EP_NI3_RXCOUNT)
+#define pUSB_EP_NI3_TXTYPE ((volatile unsigned short *)USB_EP_NI3_TXTYPE)
+#define pUSB_EP_NI3_TXINTERVAL ((volatile unsigned short *)USB_EP_NI3_TXINTERVAL)
+#define pUSB_EP_NI3_RXTYPE ((volatile unsigned short *)USB_EP_NI3_RXTYPE)
+#define pUSB_EP_NI3_RXINTERVAL ((volatile unsigned short *)USB_EP_NI3_RXINTERVAL)
+
+/* USB Endpoint 4 Control Registers */
+
+#define pUSB_EP_NI3_TXCOUNT ((volatile unsigned short *)USB_EP_NI3_TXCOUNT)
+#define pUSB_EP_NI4_TXMAXP ((volatile unsigned short *)USB_EP_NI4_TXMAXP)
+#define pUSB_EP_NI4_TXCSR ((volatile unsigned short *)USB_EP_NI4_TXCSR)
+#define pUSB_EP_NI4_RXMAXP ((volatile unsigned short *)USB_EP_NI4_RXMAXP)
+#define pUSB_EP_NI4_RXCSR ((volatile unsigned short *)USB_EP_NI4_RXCSR)
+#define pUSB_EP_NI4_RXCOUNT ((volatile unsigned short *)USB_EP_NI4_RXCOUNT)
+#define pUSB_EP_NI4_TXTYPE ((volatile unsigned short *)USB_EP_NI4_TXTYPE)
+#define pUSB_EP_NI4_TXINTERVAL ((volatile unsigned short *)USB_EP_NI4_TXINTERVAL)
+#define pUSB_EP_NI4_RXTYPE ((volatile unsigned short *)USB_EP_NI4_RXTYPE)
+#define pUSB_EP_NI4_RXINTERVAL ((volatile unsigned short *)USB_EP_NI4_RXINTERVAL)
+
+/* USB Endpoint 5 Control Registers */
+
+#define pUSB_EP_NI4_TXCOUNT ((volatile unsigned short *)USB_EP_NI4_TXCOUNT)
+#define pUSB_EP_NI5_TXMAXP ((volatile unsigned short *)USB_EP_NI5_TXMAXP)
+#define pUSB_EP_NI5_TXCSR ((volatile unsigned short *)USB_EP_NI5_TXCSR)
+#define pUSB_EP_NI5_RXMAXP ((volatile unsigned short *)USB_EP_NI5_RXMAXP)
+#define pUSB_EP_NI5_RXCSR ((volatile unsigned short *)USB_EP_NI5_RXCSR)
+#define pUSB_EP_NI5_RXCOUNT ((volatile unsigned short *)USB_EP_NI5_RXCOUNT)
+#define pUSB_EP_NI5_TXTYPE ((volatile unsigned short *)USB_EP_NI5_TXTYPE)
+#define pUSB_EP_NI5_TXINTERVAL ((volatile unsigned short *)USB_EP_NI5_TXINTERVAL)
+#define pUSB_EP_NI5_RXTYPE ((volatile unsigned short *)USB_EP_NI5_RXTYPE)
+#define pUSB_EP_NI5_RXINTERVAL ((volatile unsigned short *)USB_EP_NI5_RXINTERVAL)
+
+/* USB Endpoint 6 Control Registers */
+
+#define pUSB_EP_NI5_TXCOUNT ((volatile unsigned short *)USB_EP_NI5_TXCOUNT)
+#define pUSB_EP_NI6_TXMAXP ((volatile unsigned short *)USB_EP_NI6_TXMAXP)
+#define pUSB_EP_NI6_TXCSR ((volatile unsigned short *)USB_EP_NI6_TXCSR)
+#define pUSB_EP_NI6_RXMAXP ((volatile unsigned short *)USB_EP_NI6_RXMAXP)
+#define pUSB_EP_NI6_RXCSR ((volatile unsigned short *)USB_EP_NI6_RXCSR)
+#define pUSB_EP_NI6_RXCOUNT ((volatile unsigned short *)USB_EP_NI6_RXCOUNT)
+#define pUSB_EP_NI6_TXTYPE ((volatile unsigned short *)USB_EP_NI6_TXTYPE)
+#define pUSB_EP_NI6_TXINTERVAL ((volatile unsigned short *)USB_EP_NI6_TXINTERVAL)
+#define pUSB_EP_NI6_RXTYPE ((volatile unsigned short *)USB_EP_NI6_RXTYPE)
+#define pUSB_EP_NI6_RXINTERVAL ((volatile unsigned short *)USB_EP_NI6_RXINTERVAL)
+
+/* USB Endpoint 7 Control Registers */
+
+#define pUSB_EP_NI6_TXCOUNT ((volatile unsigned short *)USB_EP_NI6_TXCOUNT)
+#define pUSB_EP_NI7_TXMAXP ((volatile unsigned short *)USB_EP_NI7_TXMAXP)
+#define pUSB_EP_NI7_TXCSR ((volatile unsigned short *)USB_EP_NI7_TXCSR)
+#define pUSB_EP_NI7_RXMAXP ((volatile unsigned short *)USB_EP_NI7_RXMAXP)
+#define pUSB_EP_NI7_RXCSR ((volatile unsigned short *)USB_EP_NI7_RXCSR)
+#define pUSB_EP_NI7_RXCOUNT ((volatile unsigned short *)USB_EP_NI7_RXCOUNT)
+#define pUSB_EP_NI7_TXTYPE ((volatile unsigned short *)USB_EP_NI7_TXTYPE)
+#define pUSB_EP_NI7_TXINTERVAL ((volatile unsigned short *)USB_EP_NI7_TXINTERVAL)
+#define pUSB_EP_NI7_RXTYPE ((volatile unsigned short *)USB_EP_NI7_RXTYPE)
+#define pUSB_EP_NI7_RXINTERVAL ((volatile unsigned short *)USB_EP_NI7_RXINTERVAL)
+#define pUSB_EP_NI7_TXCOUNT ((volatile unsigned short *)USB_EP_NI7_TXCOUNT)
+#define pUSB_DMA_INTERRUPT ((volatile unsigned short *)USB_DMA_INTERRUPT)
+
+/* USB Channel 0 Config Registers */
+
+#define pUSB_DMA0CONTROL ((volatile unsigned short *)USB_DMA0CONTROL)
+#define pUSB_DMA0ADDRLOW ((volatile unsigned short *)USB_DMA0ADDRLOW)
+#define pUSB_DMA0ADDRHIGH ((volatile unsigned short *)USB_DMA0ADDRHIGH)
+#define pUSB_DMA0COUNTLOW ((volatile unsigned short *)USB_DMA0COUNTLOW)
+#define pUSB_DMA0COUNTHIGH ((volatile unsigned short *)USB_DMA0COUNTHIGH)
+
+/* USB Channel 1 Config Registers */
+
+#define pUSB_DMA1CONTROL ((volatile unsigned short *)USB_DMA1CONTROL)
+#define pUSB_DMA1ADDRLOW ((volatile unsigned short *)USB_DMA1ADDRLOW)
+#define pUSB_DMA1ADDRHIGH ((volatile unsigned short *)USB_DMA1ADDRHIGH)
+#define pUSB_DMA1COUNTLOW ((volatile unsigned short *)USB_DMA1COUNTLOW)
+#define pUSB_DMA1COUNTHIGH ((volatile unsigned short *)USB_DMA1COUNTHIGH)
+
+/* USB Channel 2 Config Registers */
+
+#define pUSB_DMA2CONTROL ((volatile unsigned short *)USB_DMA2CONTROL)
+#define pUSB_DMA2ADDRLOW ((volatile unsigned short *)USB_DMA2ADDRLOW)
+#define pUSB_DMA2ADDRHIGH ((volatile unsigned short *)USB_DMA2ADDRHIGH)
+#define pUSB_DMA2COUNTLOW ((volatile unsigned short *)USB_DMA2COUNTLOW)
+#define pUSB_DMA2COUNTHIGH ((volatile unsigned short *)USB_DMA2COUNTHIGH)
+
+/* USB Channel 3 Config Registers */
+
+#define pUSB_DMA3CONTROL ((volatile unsigned short *)USB_DMA3CONTROL)
+#define pUSB_DMA3ADDRLOW ((volatile unsigned short *)USB_DMA3ADDRLOW)
+#define pUSB_DMA3ADDRHIGH ((volatile unsigned short *)USB_DMA3ADDRHIGH)
+#define pUSB_DMA3COUNTLOW ((volatile unsigned short *)USB_DMA3COUNTLOW)
+#define pUSB_DMA3COUNTHIGH ((volatile unsigned short *)USB_DMA3COUNTHIGH)
+
+/* USB Channel 4 Config Registers */
+
+#define pUSB_DMA4CONTROL ((volatile unsigned short *)USB_DMA4CONTROL)
+#define pUSB_DMA4ADDRLOW ((volatile unsigned short *)USB_DMA4ADDRLOW)
+#define pUSB_DMA4ADDRHIGH ((volatile unsigned short *)USB_DMA4ADDRHIGH)
+#define pUSB_DMA4COUNTLOW ((volatile unsigned short *)USB_DMA4COUNTLOW)
+#define pUSB_DMA4COUNTHIGH ((volatile unsigned short *)USB_DMA4COUNTHIGH)
+
+/* USB Channel 5 Config Registers */
+
+#define pUSB_DMA5CONTROL ((volatile unsigned short *)USB_DMA5CONTROL)
+#define pUSB_DMA5ADDRLOW ((volatile unsigned short *)USB_DMA5ADDRLOW)
+#define pUSB_DMA5ADDRHIGH ((volatile unsigned short *)USB_DMA5ADDRHIGH)
+#define pUSB_DMA5COUNTLOW ((volatile unsigned short *)USB_DMA5COUNTLOW)
+#define pUSB_DMA5COUNTHIGH ((volatile unsigned short *)USB_DMA5COUNTHIGH)
+
+/* USB Channel 6 Config Registers */
+
+#define pUSB_DMA6CONTROL ((volatile unsigned short *)USB_DMA6CONTROL)
+#define pUSB_DMA6ADDRLOW ((volatile unsigned short *)USB_DMA6ADDRLOW)
+#define pUSB_DMA6ADDRHIGH ((volatile unsigned short *)USB_DMA6ADDRHIGH)
+#define pUSB_DMA6COUNTLOW ((volatile unsigned short *)USB_DMA6COUNTLOW)
+#define pUSB_DMA6COUNTHIGH ((volatile unsigned short *)USB_DMA6COUNTHIGH)
+
+/* USB Channel 7 Config Registers */
+
+#define pUSB_DMA7CONTROL ((volatile unsigned short *)USB_DMA7CONTROL)
+#define pUSB_DMA7ADDRLOW ((volatile unsigned short *)USB_DMA7ADDRLOW)
+#define pUSB_DMA7ADDRHIGH ((volatile unsigned short *)USB_DMA7ADDRHIGH)
+#define pUSB_DMA7COUNTLOW ((volatile unsigned short *)USB_DMA7COUNTLOW)
+#define pUSB_DMA7COUNTHIGH ((volatile unsigned short *)USB_DMA7COUNTHIGH)
+
+/* Keypad Registers */
+
+#define pKPAD_CTL ((volatile unsigned short *)KPAD_CTL)
+#define pKPAD_PRESCALE ((volatile unsigned short *)KPAD_PRESCALE)
+#define pKPAD_MSEL ((volatile unsigned short *)KPAD_MSEL)
+#define pKPAD_ROWCOL ((volatile unsigned short *)KPAD_ROWCOL)
+#define pKPAD_STAT ((volatile unsigned short *)KPAD_STAT)
+#define pKPAD_SOFTEVAL ((volatile unsigned short *)KPAD_SOFTEVAL)
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define pPIXC_CTL ((volatile unsigned short *)PIXC_CTL)
+#define pPIXC_PPL ((volatile unsigned short *)PIXC_PPL)
+#define pPIXC_LPF ((volatile unsigned short *)PIXC_LPF)
+#define pPIXC_AHSTART ((volatile unsigned short *)PIXC_AHSTART)
+#define pPIXC_AHEND ((volatile unsigned short *)PIXC_AHEND)
+#define pPIXC_AVSTART ((volatile unsigned short *)PIXC_AVSTART)
+#define pPIXC_AVEND ((volatile unsigned short *)PIXC_AVEND)
+#define pPIXC_ATRANSP ((volatile unsigned short *)PIXC_ATRANSP)
+#define pPIXC_BHSTART ((volatile unsigned short *)PIXC_BHSTART)
+#define pPIXC_BHEND ((volatile unsigned short *)PIXC_BHEND)
+#define pPIXC_BVSTART ((volatile unsigned short *)PIXC_BVSTART)
+#define pPIXC_BVEND ((volatile unsigned short *)PIXC_BVEND)
+#define pPIXC_BTRANSP ((volatile unsigned short *)PIXC_BTRANSP)
+#define pPIXC_INTRSTAT ((volatile unsigned short *)PIXC_INTRSTAT)
+#define pPIXC_RYCON ((volatile unsigned long *)PIXC_RYCON)
+#define pPIXC_GUCON ((volatile unsigned long *)PIXC_GUCON)
+#define pPIXC_BVCON ((volatile unsigned long *)PIXC_BVCON)
+#define pPIXC_CCBIAS ((volatile unsigned long *)PIXC_CCBIAS)
+#define pPIXC_TC ((volatile unsigned long *)PIXC_TC)
+
+#endif /* _CDEF_BF549_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** cdefBF54x_base.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the registers common to the ADSP-BF54x peripherals.
+**
+***************************************************************/
+
+#ifndef _CDEF_BF54X_H
+#define _CDEF_BF54X_H
+
+#include <defBF54x_base.h>
+
+/* ************************************************************** */
+/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
+/* ************************************************************** */
+
+/* PLL Registers */
+
+#define pPLL_CTL ((volatile unsigned short *)PLL_CTL)
+#define pPLL_DIV ((volatile unsigned short *)PLL_DIV)
+#define pVR_CTL ((volatile unsigned short *)VR_CTL)
+#define pPLL_STAT ((volatile unsigned short *)PLL_STAT)
+#define pPLL_LOCKCNT ((volatile unsigned short *)PLL_LOCKCNT)
+
+/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
+
+#define pCHIPID ((volatile unsigned long *)CHIPID)
+
+/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
+
+#define pSWRST ((volatile unsigned short *)SWRST)
+#define pSYSCR ((volatile unsigned short *)SYSCR)
+
+/* SIC Registers */
+
+#define pSIC_IMASK0 ((volatile unsigned long *)SIC_IMASK0)
+#define pSIC_IMASK1 ((volatile unsigned long *)SIC_IMASK1)
+#define pSIC_IMASK2 ((volatile unsigned long *)SIC_IMASK2)
+#define pSIC_ISR0 ((volatile unsigned long *)SIC_ISR0)
+#define pSIC_ISR1 ((volatile unsigned long *)SIC_ISR1)
+#define pSIC_ISR2 ((volatile unsigned long *)SIC_ISR2)
+#define pSIC_IWR0 ((volatile unsigned long *)SIC_IWR0)
+#define pSIC_IWR1 ((volatile unsigned long *)SIC_IWR1)
+#define pSIC_IWR2 ((volatile unsigned long *)SIC_IWR2)
+#define pSIC_IAR0 ((volatile unsigned long *)SIC_IAR0)
+#define pSIC_IAR1 ((volatile unsigned long *)SIC_IAR1)
+#define pSIC_IAR2 ((volatile unsigned long *)SIC_IAR2)
+#define pSIC_IAR3 ((volatile unsigned long *)SIC_IAR3)
+#define pSIC_IAR4 ((volatile unsigned long *)SIC_IAR4)
+#define pSIC_IAR5 ((volatile unsigned long *)SIC_IAR5)
+#define pSIC_IAR6 ((volatile unsigned long *)SIC_IAR6)
+#define pSIC_IAR7 ((volatile unsigned long *)SIC_IAR7)
+#define pSIC_IAR8 ((volatile unsigned long *)SIC_IAR8)
+#define pSIC_IAR9 ((volatile unsigned long *)SIC_IAR9)
+#define pSIC_IAR10 ((volatile unsigned long *)SIC_IAR10)
+#define pSIC_IAR11 ((volatile unsigned long *)SIC_IAR11)
+
+/* Watchdog Timer Registers */
+
+#define pWDOG_CTL ((volatile unsigned short *)WDOG_CTL)
+#define pWDOG_CNT ((volatile unsigned long *)WDOG_CNT)
+#define pWDOG_STAT ((volatile unsigned long *)WDOG_STAT)
+
+/* RTC Registers */
+
+#define pRTC_STAT ((volatile unsigned long *)RTC_STAT)
+#define pRTC_ICTL ((volatile unsigned short *)RTC_ICTL)
+#define pRTC_ISTAT ((volatile unsigned short *)RTC_ISTAT)
+#define pRTC_SWCNT ((volatile unsigned short *)RTC_SWCNT)
+#define pRTC_ALARM ((volatile unsigned long *)RTC_ALARM)
+#define pRTC_PREN ((volatile unsigned short *)RTC_PREN)
+
+/* UART0 Registers */
+
+#define pUART0_DLL ((volatile unsigned short *)UART0_DLL)
+#define pUART0_DLH ((volatile unsigned short *)UART0_DLH)
+#define pUART0_GCTL ((volatile unsigned short *)UART0_GCTL)
+#define pUART0_LCR ((volatile unsigned short *)UART0_LCR)
+#define pUART0_MCR ((volatile unsigned short *)UART0_MCR)
+#define pUART0_LSR ((volatile unsigned short *)UART0_LSR)
+#define pUART0_MSR ((volatile unsigned short *)UART0_MSR)
+#define pUART0_SCR ((volatile unsigned short *)UART0_SCR)
+#define pUART0_IER_SET ((volatile unsigned short *)UART0_IER_SET)
+#define pUART0_IER_CLEAR ((volatile unsigned short *)UART0_IER_CLEAR)
+#define pUART0_THR ((volatile unsigned short *)UART0_THR)
+#define pUART0_RBR ((volatile unsigned short *)UART0_RBR)
+
+/* SPI0 Registers */
+
+#define pSPI0_CTL ((volatile unsigned short *)SPI0_CTL)
+#define pSPI0_FLG ((volatile unsigned short *)SPI0_FLG)
+#define pSPI0_STAT ((volatile unsigned short *)SPI0_STAT)
+#define pSPI0_TDBR ((volatile unsigned short *)SPI0_TDBR)
+#define pSPI0_RDBR ((volatile unsigned short *)SPI0_RDBR)
+#define pSPI0_BAUD ((volatile unsigned short *)SPI0_BAUD)
+#define pSPI0_SHADOW ((volatile unsigned short *)SPI0_SHADOW)
+
+/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
+
+/* Two Wire Interface Registers (TWI0) */
+
+#define pTWI0_CLKDIV ((volatile unsigned short *)TWI0_CLKDIV)
+#define pTWI0_CONTROL ((volatile unsigned short *)TWI0_CONTROL)
+#define pTWI0_SLAVE_CTL ((volatile unsigned short *)TWI0_SLAVE_CTL)
+#define pTWI0_SLAVE_STAT ((volatile unsigned short *)TWI0_SLAVE_STAT)
+#define pTWI0_SLAVE_ADDR ((volatile unsigned short *)TWI0_SLAVE_ADDR)
+#define pTWI0_MASTER_CTL ((volatile unsigned short *)TWI0_MASTER_CTL)
+#define pTWI0_MASTER_STAT ((volatile unsigned short *)TWI0_MASTER_STAT)
+#define pTWI0_MASTER_ADDR ((volatile unsigned short *)TWI0_MASTER_ADDR)
+#define pTWI0_INT_STAT ((volatile unsigned short *)TWI0_INT_STAT)
+#define pTWI0_INT_MASK ((volatile unsigned short *)TWI0_INT_MASK)
+#define pTWI0_FIFO_CTL ((volatile unsigned short *)TWI0_FIFO_CTL)
+#define pTWI0_FIFO_STAT ((volatile unsigned short *)TWI0_FIFO_STAT)
+#define pTWI0_XMT_DATA8 ((volatile unsigned short *)TWI0_XMT_DATA8)
+#define pTWI0_XMT_DATA16 ((volatile unsigned short *)TWI0_XMT_DATA16)
+#define pTWI0_RCV_DATA8 ((volatile unsigned short *)TWI0_RCV_DATA8)
+#define pTWI0_RCV_DATA16 ((volatile unsigned short *)TWI0_RCV_DATA16)
+
+/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
+
+/* SPORT1 Registers */
+
+#define pSPORT1_TCR1 ((volatile unsigned short *)SPORT1_TCR1)
+#define pSPORT1_TCR2 ((volatile unsigned short *)SPORT1_TCR2)
+#define pSPORT1_TCLKDIV ((volatile unsigned short *)SPORT1_TCLKDIV)
+#define pSPORT1_TFSDIV ((volatile unsigned short *)SPORT1_TFSDIV)
+#define pSPORT1_TX ((volatile unsigned long *)SPORT1_TX)
+#define pSPORT1_RX ((volatile unsigned long *)SPORT1_RX)
+#define pSPORT1_RCR1 ((volatile unsigned short *)SPORT1_RCR1)
+#define pSPORT1_RCR2 ((volatile unsigned short *)SPORT1_RCR2)
+#define pSPORT1_RCLKDIV ((volatile unsigned short *)SPORT1_RCLKDIV)
+#define pSPORT1_RFSDIV ((volatile unsigned short *)SPORT1_RFSDIV)
+#define pSPORT1_STAT ((volatile unsigned short *)SPORT1_STAT)
+#define pSPORT1_CHNL ((volatile unsigned short *)SPORT1_CHNL)
+#define pSPORT1_MCMC1 ((volatile unsigned short *)SPORT1_MCMC1)
+#define pSPORT1_MCMC2 ((volatile unsigned short *)SPORT1_MCMC2)
+#define pSPORT1_MTCS0 ((volatile unsigned long *)SPORT1_MTCS0)
+#define pSPORT1_MTCS1 ((volatile unsigned long *)SPORT1_MTCS1)
+#define pSPORT1_MTCS2 ((volatile unsigned long *)SPORT1_MTCS2)
+#define pSPORT1_MTCS3 ((volatile unsigned long *)SPORT1_MTCS3)
+#define pSPORT1_MRCS0 ((volatile unsigned long *)SPORT1_MRCS0)
+#define pSPORT1_MRCS1 ((volatile unsigned long *)SPORT1_MRCS1)
+#define pSPORT1_MRCS2 ((volatile unsigned long *)SPORT1_MRCS2)
+#define pSPORT1_MRCS3 ((volatile unsigned long *)SPORT1_MRCS3)
+
+/* Asynchronous Memory Control Registers */
+
+#define pEBIU_AMGCTL ((volatile unsigned short *)EBIU_AMGCTL)
+#define pEBIU_AMBCTL0 ((volatile unsigned long *)EBIU_AMBCTL0)
+#define pEBIU_AMBCTL1 ((volatile unsigned long *)EBIU_AMBCTL1)
+#define pEBIU_MBSCTL ((volatile unsigned long *)EBIU_MBSCTL)
+#define pEBIU_ARBSTAT ((volatile unsigned long *)EBIU_ARBSTAT)
+#define pEBIU_MODE ((volatile unsigned long *)EBIU_MODE)
+#define pEBIU_FCTL ((volatile unsigned long *)EBIU_FCTL)
+
+/* DDR Memory Control Registers */
+
+#define pEBIU_DDRCTL0 ((volatile unsigned long *)EBIU_DDRCTL0)
+#define pEBIU_DDRCTL1 ((volatile unsigned long *)EBIU_DDRCTL1)
+#define pEBIU_DDRCTL2 ((volatile unsigned long *)EBIU_DDRCTL2)
+#define pEBIU_DDRCTL3 ((volatile unsigned long *)EBIU_DDRCTL3)
+#define pEBIU_DDRQUE ((volatile unsigned long *)EBIU_DDRQUE)
+#define pEBIU_ERRADD ((void *volatile *)EBIU_ERRADD)
+#define pEBIU_ERRMST ((volatile unsigned short *)EBIU_ERRMST)
+#define pEBIU_RSTCTL ((volatile unsigned short *)EBIU_RSTCTL)
+
+/* DDR BankRead and Write Count Registers */
+
+#define pEBIU_DDRBRC0 ((volatile unsigned long *)EBIU_DDRBRC0)
+#define pEBIU_DDRBRC1 ((volatile unsigned long *)EBIU_DDRBRC1)
+#define pEBIU_DDRBRC2 ((volatile unsigned long *)EBIU_DDRBRC2)
+#define pEBIU_DDRBRC3 ((volatile unsigned long *)EBIU_DDRBRC3)
+#define pEBIU_DDRBRC4 ((volatile unsigned long *)EBIU_DDRBRC4)
+#define pEBIU_DDRBRC5 ((volatile unsigned long *)EBIU_DDRBRC5)
+#define pEBIU_DDRBRC6 ((volatile unsigned long *)EBIU_DDRBRC6)
+#define pEBIU_DDRBRC7 ((volatile unsigned long *)EBIU_DDRBRC7)
+#define pEBIU_DDRBWC0 ((volatile unsigned long *)EBIU_DDRBWC0)
+#define pEBIU_DDRBWC1 ((volatile unsigned long *)EBIU_DDRBWC1)
+#define pEBIU_DDRBWC2 ((volatile unsigned long *)EBIU_DDRBWC2)
+#define pEBIU_DDRBWC3 ((volatile unsigned long *)EBIU_DDRBWC3)
+#define pEBIU_DDRBWC4 ((volatile unsigned long *)EBIU_DDRBWC4)
+#define pEBIU_DDRBWC5 ((volatile unsigned long *)EBIU_DDRBWC5)
+#define pEBIU_DDRBWC6 ((volatile unsigned long *)EBIU_DDRBWC6)
+#define pEBIU_DDRBWC7 ((volatile unsigned long *)EBIU_DDRBWC7)
+#define pEBIU_DDRACCT ((volatile unsigned long *)EBIU_DDRACCT)
+#define pEBIU_DDRTACT ((volatile unsigned long *)EBIU_DDRTACT)
+#define pEBIU_DDRARCT ((volatile unsigned long *)EBIU_DDRARCT)
+#define pEBIU_DDRGC0 ((volatile unsigned long *)EBIU_DDRGC0)
+#define pEBIU_DDRGC1 ((volatile unsigned long *)EBIU_DDRGC1)
+#define pEBIU_DDRGC2 ((volatile unsigned long *)EBIU_DDRGC2)
+#define pEBIU_DDRGC3 ((volatile unsigned long *)EBIU_DDRGC3)
+#define pEBIU_DDRMCEN ((volatile unsigned long *)EBIU_DDRMCEN)
+#define pEBIU_DDRMCCL ((volatile unsigned long *)EBIU_DDRMCCL)
+
+/* DMAC0 Registers */
+
+#define pDMAC0_TCPER ((volatile unsigned short *)DMAC0_TCPER)
+#define pDMAC0_TCCNT ((volatile unsigned short *)DMAC0_TCCNT)
+
+/* DMA Channel 0 Registers */
+
+#define pDMA0_NEXT_DESC_PTR ((void *volatile *)DMA0_NEXT_DESC_PTR)
+#define pDMA0_START_ADDR ((void *volatile *)DMA0_START_ADDR)
+#define pDMA0_CONFIG ((volatile unsigned short *)DMA0_CONFIG)
+#define pDMA0_X_COUNT ((volatile unsigned short *)DMA0_X_COUNT)
+#define pDMA0_X_MODIFY ((volatile signed short *)DMA0_X_MODIFY)
+#define pDMA0_Y_COUNT ((volatile unsigned short *)DMA0_Y_COUNT)
+#define pDMA0_Y_MODIFY ((volatile signed short *)DMA0_Y_MODIFY)
+#define pDMA0_CURR_DESC_PTR ((void *volatile *)DMA0_CURR_DESC_PTR)
+#define pDMA0_CURR_ADDR ((void *volatile *)DMA0_CURR_ADDR)
+#define pDMA0_IRQ_STATUS ((volatile unsigned short *)DMA0_IRQ_STATUS)
+#define pDMA0_PERIPHERAL_MAP ((volatile unsigned short *)DMA0_PERIPHERAL_MAP)
+#define pDMA0_CURR_X_COUNT ((volatile unsigned short *)DMA0_CURR_X_COUNT)
+#define pDMA0_CURR_Y_COUNT ((volatile unsigned short *)DMA0_CURR_Y_COUNT)
+
+/* DMA Channel 1 Registers */
+
+#define pDMA1_NEXT_DESC_PTR ((void *volatile *)DMA1_NEXT_DESC_PTR)
+#define pDMA1_START_ADDR ((void *volatile *)DMA1_START_ADDR)
+#define pDMA1_CONFIG ((volatile unsigned short *)DMA1_CONFIG)
+#define pDMA1_X_COUNT ((volatile unsigned short *)DMA1_X_COUNT)
+#define pDMA1_X_MODIFY ((volatile signed short *)DMA1_X_MODIFY)
+#define pDMA1_Y_COUNT ((volatile unsigned short *)DMA1_Y_COUNT)
+#define pDMA1_Y_MODIFY ((volatile signed short *)DMA1_Y_MODIFY)
+#define pDMA1_CURR_DESC_PTR ((void *volatile *)DMA1_CURR_DESC_PTR)
+#define pDMA1_CURR_ADDR ((void *volatile *)DMA1_CURR_ADDR)
+#define pDMA1_IRQ_STATUS ((volatile unsigned short *)DMA1_IRQ_STATUS)
+#define pDMA1_PERIPHERAL_MAP ((volatile unsigned short *)DMA1_PERIPHERAL_MAP)
+#define pDMA1_CURR_X_COUNT ((volatile unsigned short *)DMA1_CURR_X_COUNT)
+#define pDMA1_CURR_Y_COUNT ((volatile unsigned short *)DMA1_CURR_Y_COUNT)
+
+/* DMA Channel 2 Registers */
+
+#define pDMA2_NEXT_DESC_PTR ((void *volatile *)DMA2_NEXT_DESC_PTR)
+#define pDMA2_START_ADDR ((void *volatile *)DMA2_START_ADDR)
+#define pDMA2_CONFIG ((volatile unsigned short *)DMA2_CONFIG)
+#define pDMA2_X_COUNT ((volatile unsigned short *)DMA2_X_COUNT)
+#define pDMA2_X_MODIFY ((volatile signed short *)DMA2_X_MODIFY)
+#define pDMA2_Y_COUNT ((volatile unsigned short *)DMA2_Y_COUNT)
+#define pDMA2_Y_MODIFY ((volatile signed short *)DMA2_Y_MODIFY)
+#define pDMA2_CURR_DESC_PTR ((void *volatile *)DMA2_CURR_DESC_PTR)
+#define pDMA2_CURR_ADDR ((void *volatile *)DMA2_CURR_ADDR)
+#define pDMA2_IRQ_STATUS ((volatile unsigned short *)DMA2_IRQ_STATUS)
+#define pDMA2_PERIPHERAL_MAP ((volatile unsigned short *)DMA2_PERIPHERAL_MAP)
+#define pDMA2_CURR_X_COUNT ((volatile unsigned short *)DMA2_CURR_X_COUNT)
+#define pDMA2_CURR_Y_COUNT ((volatile unsigned short *)DMA2_CURR_Y_COUNT)
+
+/* DMA Channel 3 Registers */
+
+#define pDMA3_NEXT_DESC_PTR ((void *volatile *)DMA3_NEXT_DESC_PTR)
+#define pDMA3_START_ADDR ((void *volatile *)DMA3_START_ADDR)
+#define pDMA3_CONFIG ((volatile unsigned short *)DMA3_CONFIG)
+#define pDMA3_X_COUNT ((volatile unsigned short *)DMA3_X_COUNT)
+#define pDMA3_X_MODIFY ((volatile signed short *)DMA3_X_MODIFY)
+#define pDMA3_Y_COUNT ((volatile unsigned short *)DMA3_Y_COUNT)
+#define pDMA3_Y_MODIFY ((volatile signed short *)DMA3_Y_MODIFY)
+#define pDMA3_CURR_DESC_PTR ((void *volatile *)DMA3_CURR_DESC_PTR)
+#define pDMA3_CURR_ADDR ((void *volatile *)DMA3_CURR_ADDR)
+#define pDMA3_IRQ_STATUS ((volatile unsigned short *)DMA3_IRQ_STATUS)
+#define pDMA3_PERIPHERAL_MAP ((volatile unsigned short *)DMA3_PERIPHERAL_MAP)
+#define pDMA3_CURR_X_COUNT ((volatile unsigned short *)DMA3_CURR_X_COUNT)
+#define pDMA3_CURR_Y_COUNT ((volatile unsigned short *)DMA3_CURR_Y_COUNT)
+
+/* DMA Channel 4 Registers */
+
+#define pDMA4_NEXT_DESC_PTR ((void *volatile *)DMA4_NEXT_DESC_PTR)
+#define pDMA4_START_ADDR ((void *volatile *)DMA4_START_ADDR)
+#define pDMA4_CONFIG ((volatile unsigned short *)DMA4_CONFIG)
+#define pDMA4_X_COUNT ((volatile unsigned short *)DMA4_X_COUNT)
+#define pDMA4_X_MODIFY ((volatile signed short *)DMA4_X_MODIFY)
+#define pDMA4_Y_COUNT ((volatile unsigned short *)DMA4_Y_COUNT)
+#define pDMA4_Y_MODIFY ((volatile signed short *)DMA4_Y_MODIFY)
+#define pDMA4_CURR_DESC_PTR ((void *volatile *)DMA4_CURR_DESC_PTR)
+#define pDMA4_CURR_ADDR ((void *volatile *)DMA4_CURR_ADDR)
+#define pDMA4_IRQ_STATUS ((volatile unsigned short *)DMA4_IRQ_STATUS)
+#define pDMA4_PERIPHERAL_MAP ((volatile unsigned short *)DMA4_PERIPHERAL_MAP)
+#define pDMA4_CURR_X_COUNT ((volatile unsigned short *)DMA4_CURR_X_COUNT)
+#define pDMA4_CURR_Y_COUNT ((volatile unsigned short *)DMA4_CURR_Y_COUNT)
+
+/* DMA Channel 5 Registers */
+
+#define pDMA5_NEXT_DESC_PTR ((void *volatile *)DMA5_NEXT_DESC_PTR)
+#define pDMA5_START_ADDR ((void *volatile *)DMA5_START_ADDR)
+#define pDMA5_CONFIG ((volatile unsigned short *)DMA5_CONFIG)
+#define pDMA5_X_COUNT ((volatile unsigned short *)DMA5_X_COUNT)
+#define pDMA5_X_MODIFY ((volatile signed short *)DMA5_X_MODIFY)
+#define pDMA5_Y_COUNT ((volatile unsigned short *)DMA5_Y_COUNT)
+#define pDMA5_Y_MODIFY ((volatile signed short *)DMA5_Y_MODIFY)
+#define pDMA5_CURR_DESC_PTR ((void *volatile *)DMA5_CURR_DESC_PTR)
+#define pDMA5_CURR_ADDR ((void *volatile *)DMA5_CURR_ADDR)
+#define pDMA5_IRQ_STATUS ((volatile unsigned short *)DMA5_IRQ_STATUS)
+#define pDMA5_PERIPHERAL_MAP ((volatile unsigned short *)DMA5_PERIPHERAL_MAP)
+#define pDMA5_CURR_X_COUNT ((volatile unsigned short *)DMA5_CURR_X_COUNT)
+#define pDMA5_CURR_Y_COUNT ((volatile unsigned short *)DMA5_CURR_Y_COUNT)
+
+/* DMA Channel 6 Registers */
+
+#define pDMA6_NEXT_DESC_PTR ((void *volatile *)DMA6_NEXT_DESC_PTR)
+#define pDMA6_START_ADDR ((void *volatile *)DMA6_START_ADDR)
+#define pDMA6_CONFIG ((volatile unsigned short *)DMA6_CONFIG)
+#define pDMA6_X_COUNT ((volatile unsigned short *)DMA6_X_COUNT)
+#define pDMA6_X_MODIFY ((volatile signed short *)DMA6_X_MODIFY)
+#define pDMA6_Y_COUNT ((volatile unsigned short *)DMA6_Y_COUNT)
+#define pDMA6_Y_MODIFY ((volatile signed short *)DMA6_Y_MODIFY)
+#define pDMA6_CURR_DESC_PTR ((void *volatile *)DMA6_CURR_DESC_PTR)
+#define pDMA6_CURR_ADDR ((void *volatile *)DMA6_CURR_ADDR)
+#define pDMA6_IRQ_STATUS ((volatile unsigned short *)DMA6_IRQ_STATUS)
+#define pDMA6_PERIPHERAL_MAP ((volatile unsigned short *)DMA6_PERIPHERAL_MAP)
+#define pDMA6_CURR_X_COUNT ((volatile unsigned short *)DMA6_CURR_X_COUNT)
+#define pDMA6_CURR_Y_COUNT ((volatile unsigned short *)DMA6_CURR_Y_COUNT)
+
+/* DMA Channel 7 Registers */
+
+#define pDMA7_NEXT_DESC_PTR ((void *volatile *)DMA7_NEXT_DESC_PTR)
+#define pDMA7_START_ADDR ((void *volatile *)DMA7_START_ADDR)
+#define pDMA7_CONFIG ((volatile unsigned short *)DMA7_CONFIG)
+#define pDMA7_X_COUNT ((volatile unsigned short *)DMA7_X_COUNT)
+#define pDMA7_X_MODIFY ((volatile signed short *)DMA7_X_MODIFY)
+#define pDMA7_Y_COUNT ((volatile unsigned short *)DMA7_Y_COUNT)
+#define pDMA7_Y_MODIFY ((volatile signed short *)DMA7_Y_MODIFY)
+#define pDMA7_CURR_DESC_PTR ((void *volatile *)DMA7_CURR_DESC_PTR)
+#define pDMA7_CURR_ADDR ((void *volatile *)DMA7_CURR_ADDR)
+#define pDMA7_IRQ_STATUS ((volatile unsigned short *)DMA7_IRQ_STATUS)
+#define pDMA7_PERIPHERAL_MAP ((volatile unsigned short *)DMA7_PERIPHERAL_MAP)
+#define pDMA7_CURR_X_COUNT ((volatile unsigned short *)DMA7_CURR_X_COUNT)
+#define pDMA7_CURR_Y_COUNT ((volatile unsigned short *)DMA7_CURR_Y_COUNT)
+
+/* DMA Channel 8 Registers */
+
+#define pDMA8_NEXT_DESC_PTR ((void *volatile *)DMA8_NEXT_DESC_PTR)
+#define pDMA8_START_ADDR ((void *volatile *)DMA8_START_ADDR)
+#define pDMA8_CONFIG ((volatile unsigned short *)DMA8_CONFIG)
+#define pDMA8_X_COUNT ((volatile unsigned short *)DMA8_X_COUNT)
+#define pDMA8_X_MODIFY ((volatile signed short *)DMA8_X_MODIFY)
+#define pDMA8_Y_COUNT ((volatile unsigned short *)DMA8_Y_COUNT)
+#define pDMA8_Y_MODIFY ((volatile signed short *)DMA8_Y_MODIFY)
+#define pDMA8_CURR_DESC_PTR ((void *volatile *)DMA8_CURR_DESC_PTR)
+#define pDMA8_CURR_ADDR ((void *volatile *)DMA8_CURR_ADDR)
+#define pDMA8_IRQ_STATUS ((volatile unsigned short *)DMA8_IRQ_STATUS)
+#define pDMA8_PERIPHERAL_MAP ((volatile unsigned short *)DMA8_PERIPHERAL_MAP)
+#define pDMA8_CURR_X_COUNT ((volatile unsigned short *)DMA8_CURR_X_COUNT)
+#define pDMA8_CURR_Y_COUNT ((volatile unsigned short *)DMA8_CURR_Y_COUNT)
+
+/* DMA Channel 9 Registers */
+
+#define pDMA9_NEXT_DESC_PTR ((void *volatile *)DMA9_NEXT_DESC_PTR)
+#define pDMA9_START_ADDR ((void *volatile *)DMA9_START_ADDR)
+#define pDMA9_CONFIG ((volatile unsigned short *)DMA9_CONFIG)
+#define pDMA9_X_COUNT ((volatile unsigned short *)DMA9_X_COUNT)
+#define pDMA9_X_MODIFY ((volatile signed short *)DMA9_X_MODIFY)
+#define pDMA9_Y_COUNT ((volatile unsigned short *)DMA9_Y_COUNT)
+#define pDMA9_Y_MODIFY ((volatile signed short *)DMA9_Y_MODIFY)
+#define pDMA9_CURR_DESC_PTR ((void *volatile *)DMA9_CURR_DESC_PTR)
+#define pDMA9_CURR_ADDR ((void *volatile *)DMA9_CURR_ADDR)
+#define pDMA9_IRQ_STATUS ((volatile unsigned short *)DMA9_IRQ_STATUS)
+#define pDMA9_PERIPHERAL_MAP ((volatile unsigned short *)DMA9_PERIPHERAL_MAP)
+#define pDMA9_CURR_X_COUNT ((volatile unsigned short *)DMA9_CURR_X_COUNT)
+#define pDMA9_CURR_Y_COUNT ((volatile unsigned short *)DMA9_CURR_Y_COUNT)
+
+/* DMA Channel 10 Registers */
+
+#define pDMA10_NEXT_DESC_PTR ((void *volatile *)DMA10_NEXT_DESC_PTR)
+#define pDMA10_START_ADDR ((void *volatile *)DMA10_START_ADDR)
+#define pDMA10_CONFIG ((volatile unsigned short *)DMA10_CONFIG)
+#define pDMA10_X_COUNT ((volatile unsigned short *)DMA10_X_COUNT)
+#define pDMA10_X_MODIFY ((volatile signed short *)DMA10_X_MODIFY)
+#define pDMA10_Y_COUNT ((volatile unsigned short *)DMA10_Y_COUNT)
+#define pDMA10_Y_MODIFY ((volatile signed short *)DMA10_Y_MODIFY)
+#define pDMA10_CURR_DESC_PTR ((void *volatile *)DMA10_CURR_DESC_PTR)
+#define pDMA10_CURR_ADDR ((void *volatile *)DMA10_CURR_ADDR)
+#define pDMA10_IRQ_STATUS ((volatile unsigned short *)DMA10_IRQ_STATUS)
+#define pDMA10_PERIPHERAL_MAP ((volatile unsigned short *)DMA10_PERIPHERAL_MAP)
+#define pDMA10_CURR_X_COUNT ((volatile unsigned short *)DMA10_CURR_X_COUNT)
+#define pDMA10_CURR_Y_COUNT ((volatile unsigned short *)DMA10_CURR_Y_COUNT)
+
+/* DMA Channel 11 Registers */
+
+#define pDMA11_NEXT_DESC_PTR ((void *volatile *)DMA11_NEXT_DESC_PTR)
+#define pDMA11_START_ADDR ((void *volatile *)DMA11_START_ADDR)
+#define pDMA11_CONFIG ((volatile unsigned short *)DMA11_CONFIG)
+#define pDMA11_X_COUNT ((volatile unsigned short *)DMA11_X_COUNT)
+#define pDMA11_X_MODIFY ((volatile signed short *)DMA11_X_MODIFY)
+#define pDMA11_Y_COUNT ((volatile unsigned short *)DMA11_Y_COUNT)
+#define pDMA11_Y_MODIFY ((volatile signed short *)DMA11_Y_MODIFY)
+#define pDMA11_CURR_DESC_PTR ((void *volatile *)DMA11_CURR_DESC_PTR)
+#define pDMA11_CURR_ADDR ((void *volatile *)DMA11_CURR_ADDR)
+#define pDMA11_IRQ_STATUS ((volatile unsigned short *)DMA11_IRQ_STATUS)
+#define pDMA11_PERIPHERAL_MAP ((volatile unsigned short *)DMA11_PERIPHERAL_MAP)
+#define pDMA11_CURR_X_COUNT ((volatile unsigned short *)DMA11_CURR_X_COUNT)
+#define pDMA11_CURR_Y_COUNT ((volatile unsigned short *)DMA11_CURR_Y_COUNT)
+
+/* MDMA Stream 0 Registers */
+
+#define pMDMA_D0_NEXT_DESC_PTR ((void *volatile *)MDMA_D0_NEXT_DESC_PTR)
+#define pMDMA_D0_START_ADDR ((void *volatile *)MDMA_D0_START_ADDR)
+#define pMDMA_D0_CONFIG ((volatile unsigned short *)MDMA_D0_CONFIG)
+#define pMDMA_D0_X_COUNT ((volatile unsigned short *)MDMA_D0_X_COUNT)
+#define pMDMA_D0_X_MODIFY ((volatile signed short *)MDMA_D0_X_MODIFY)
+#define pMDMA_D0_Y_COUNT ((volatile unsigned short *)MDMA_D0_Y_COUNT)
+#define pMDMA_D0_Y_MODIFY ((volatile signed short *)MDMA_D0_Y_MODIFY)
+#define pMDMA_D0_CURR_DESC_PTR ((void *volatile *)MDMA_D0_CURR_DESC_PTR)
+#define pMDMA_D0_CURR_ADDR ((void *volatile *)MDMA_D0_CURR_ADDR)
+#define pMDMA_D0_IRQ_STATUS ((volatile unsigned short *)MDMA_D0_IRQ_STATUS)
+#define pMDMA_D0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D0_PERIPHERAL_MAP)
+#define pMDMA_D0_CURR_X_COUNT ((volatile unsigned short *)MDMA_D0_CURR_X_COUNT)
+#define pMDMA_D0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D0_CURR_Y_COUNT)
+#define pMDMA_S0_NEXT_DESC_PTR ((void *volatile *)MDMA_S0_NEXT_DESC_PTR)
+#define pMDMA_S0_START_ADDR ((void *volatile *)MDMA_S0_START_ADDR)
+#define pMDMA_S0_CONFIG ((volatile unsigned short *)MDMA_S0_CONFIG)
+#define pMDMA_S0_X_COUNT ((volatile unsigned short *)MDMA_S0_X_COUNT)
+#define pMDMA_S0_X_MODIFY ((volatile signed short *)MDMA_S0_X_MODIFY)
+#define pMDMA_S0_Y_COUNT ((volatile unsigned short *)MDMA_S0_Y_COUNT)
+#define pMDMA_S0_Y_MODIFY ((volatile signed short *)MDMA_S0_Y_MODIFY)
+#define pMDMA_S0_CURR_DESC_PTR ((void *volatile *)MDMA_S0_CURR_DESC_PTR)
+#define pMDMA_S0_CURR_ADDR ((void *volatile *)MDMA_S0_CURR_ADDR)
+#define pMDMA_S0_IRQ_STATUS ((volatile unsigned short *)MDMA_S0_IRQ_STATUS)
+#define pMDMA_S0_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S0_PERIPHERAL_MAP)
+#define pMDMA_S0_CURR_X_COUNT ((volatile unsigned short *)MDMA_S0_CURR_X_COUNT)
+#define pMDMA_S0_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S0_CURR_Y_COUNT)
+
+/* MDMA Stream 1 Registers */
+
+#define pMDMA_D1_NEXT_DESC_PTR ((void *volatile *)MDMA_D1_NEXT_DESC_PTR)
+#define pMDMA_D1_START_ADDR ((void *volatile *)MDMA_D1_START_ADDR)
+#define pMDMA_D1_CONFIG ((volatile unsigned short *)MDMA_D1_CONFIG)
+#define pMDMA_D1_X_COUNT ((volatile unsigned short *)MDMA_D1_X_COUNT)
+#define pMDMA_D1_X_MODIFY ((volatile signed short *)MDMA_D1_X_MODIFY)
+#define pMDMA_D1_Y_COUNT ((volatile unsigned short *)MDMA_D1_Y_COUNT)
+#define pMDMA_D1_Y_MODIFY ((volatile signed short *)MDMA_D1_Y_MODIFY)
+#define pMDMA_D1_CURR_DESC_PTR ((void *volatile *)MDMA_D1_CURR_DESC_PTR)
+#define pMDMA_D1_CURR_ADDR ((void *volatile *)MDMA_D1_CURR_ADDR)
+#define pMDMA_D1_IRQ_STATUS ((volatile unsigned short *)MDMA_D1_IRQ_STATUS)
+#define pMDMA_D1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D1_PERIPHERAL_MAP)
+#define pMDMA_D1_CURR_X_COUNT ((volatile unsigned short *)MDMA_D1_CURR_X_COUNT)
+#define pMDMA_D1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D1_CURR_Y_COUNT)
+#define pMDMA_S1_NEXT_DESC_PTR ((void *volatile *)MDMA_S1_NEXT_DESC_PTR)
+#define pMDMA_S1_START_ADDR ((void *volatile *)MDMA_S1_START_ADDR)
+#define pMDMA_S1_CONFIG ((volatile unsigned short *)MDMA_S1_CONFIG)
+#define pMDMA_S1_X_COUNT ((volatile unsigned short *)MDMA_S1_X_COUNT)
+#define pMDMA_S1_X_MODIFY ((volatile signed short *)MDMA_S1_X_MODIFY)
+#define pMDMA_S1_Y_COUNT ((volatile unsigned short *)MDMA_S1_Y_COUNT)
+#define pMDMA_S1_Y_MODIFY ((volatile signed short *)MDMA_S1_Y_MODIFY)
+#define pMDMA_S1_CURR_DESC_PTR ((void *volatile *)MDMA_S1_CURR_DESC_PTR)
+#define pMDMA_S1_CURR_ADDR ((void *volatile *)MDMA_S1_CURR_ADDR)
+#define pMDMA_S1_IRQ_STATUS ((volatile unsigned short *)MDMA_S1_IRQ_STATUS)
+#define pMDMA_S1_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S1_PERIPHERAL_MAP)
+#define pMDMA_S1_CURR_X_COUNT ((volatile unsigned short *)MDMA_S1_CURR_X_COUNT)
+#define pMDMA_S1_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S1_CURR_Y_COUNT)
+
+/* EPPI1 Registers */
+
+#define pEPPI1_STATUS ((volatile unsigned short *)EPPI1_STATUS)
+#define pEPPI1_HCOUNT ((volatile unsigned short *)EPPI1_HCOUNT)
+#define pEPPI1_HDELAY ((volatile unsigned short *)EPPI1_HDELAY)
+#define pEPPI1_VCOUNT ((volatile unsigned short *)EPPI1_VCOUNT)
+#define pEPPI1_VDELAY ((volatile unsigned short *)EPPI1_VDELAY)
+#define pEPPI1_FRAME ((volatile unsigned short *)EPPI1_FRAME)
+#define pEPPI1_LINE ((volatile unsigned short *)EPPI1_LINE)
+#define pEPPI1_CLKDIV ((volatile unsigned short *)EPPI1_CLKDIV)
+#define pEPPI1_CONTROL ((volatile unsigned long *)EPPI1_CONTROL)
+#define pEPPI1_FS1W_HBL ((volatile unsigned long *)EPPI1_FS1W_HBL)
+#define pEPPI1_FS1P_AVPL ((volatile unsigned long *)EPPI1_FS1P_AVPL)
+#define pEPPI1_FS2W_LVB ((volatile unsigned long *)EPPI1_FS2W_LVB)
+#define pEPPI1_FS2P_LAVF ((volatile unsigned long *)EPPI1_FS2P_LAVF)
+#define pEPPI1_CLIP ((volatile unsigned long *)EPPI1_CLIP)
+
+/* Port Interrupt 0 Registers (32-bit) */
+
+#define pPINT0_MASK_SET ((volatile unsigned long *)PINT0_MASK_SET)
+#define pPINT0_MASK_CLEAR ((volatile unsigned long *)PINT0_MASK_CLEAR)
+#define pPINT0_REQUEST ((volatile unsigned long *)PINT0_REQUEST)
+#define pPINT0_ASSIGN ((volatile unsigned long *)PINT0_ASSIGN)
+#define pPINT0_EDGE_SET ((volatile unsigned long *)PINT0_EDGE_SET)
+#define pPINT0_EDGE_CLEAR ((volatile unsigned long *)PINT0_EDGE_CLEAR)
+#define pPINT0_INVERT_SET ((volatile unsigned long *)PINT0_INVERT_SET)
+#define pPINT0_INVERT_CLEAR ((volatile unsigned long *)PINT0_INVERT_CLEAR)
+#define pPINT0_PINSTATE ((volatile unsigned long *)PINT0_PINSTATE)
+#define pPINT0_LATCH ((volatile unsigned long *)PINT0_LATCH)
+
+/* Port Interrupt 1 Registers (32-bit) */
+
+#define pPINT1_MASK_SET ((volatile unsigned long *)PINT1_MASK_SET)
+#define pPINT1_MASK_CLEAR ((volatile unsigned long *)PINT1_MASK_CLEAR)
+#define pPINT1_REQUEST ((volatile unsigned long *)PINT1_REQUEST)
+#define pPINT1_ASSIGN ((volatile unsigned long *)PINT1_ASSIGN)
+#define pPINT1_EDGE_SET ((volatile unsigned long *)PINT1_EDGE_SET)
+#define pPINT1_EDGE_CLEAR ((volatile unsigned long *)PINT1_EDGE_CLEAR)
+#define pPINT1_INVERT_SET ((volatile unsigned long *)PINT1_INVERT_SET)
+#define pPINT1_INVERT_CLEAR ((volatile unsigned long *)PINT1_INVERT_CLEAR)
+#define pPINT1_PINSTATE ((volatile unsigned long *)PINT1_PINSTATE)
+#define pPINT1_LATCH ((volatile unsigned long *)PINT1_LATCH)
+
+/* Port Interrupt 2 Registers (32-bit) */
+
+#define pPINT2_MASK_SET ((volatile unsigned long *)PINT2_MASK_SET)
+#define pPINT2_MASK_CLEAR ((volatile unsigned long *)PINT2_MASK_CLEAR)
+#define pPINT2_REQUEST ((volatile unsigned long *)PINT2_REQUEST)
+#define pPINT2_ASSIGN ((volatile unsigned long *)PINT2_ASSIGN)
+#define pPINT2_EDGE_SET ((volatile unsigned long *)PINT2_EDGE_SET)
+#define pPINT2_EDGE_CLEAR ((volatile unsigned long *)PINT2_EDGE_CLEAR)
+#define pPINT2_INVERT_SET ((volatile unsigned long *)PINT2_INVERT_SET)
+#define pPINT2_INVERT_CLEAR ((volatile unsigned long *)PINT2_INVERT_CLEAR)
+#define pPINT2_PINSTATE ((volatile unsigned long *)PINT2_PINSTATE)
+#define pPINT2_LATCH ((volatile unsigned long *)PINT2_LATCH)
+
+/* Port Interrupt 3 Registers (32-bit) */
+
+#define pPINT3_MASK_SET ((volatile unsigned long *)PINT3_MASK_SET)
+#define pPINT3_MASK_CLEAR ((volatile unsigned long *)PINT3_MASK_CLEAR)
+#define pPINT3_REQUEST ((volatile unsigned long *)PINT3_REQUEST)
+#define pPINT3_ASSIGN ((volatile unsigned long *)PINT3_ASSIGN)
+#define pPINT3_EDGE_SET ((volatile unsigned long *)PINT3_EDGE_SET)
+#define pPINT3_EDGE_CLEAR ((volatile unsigned long *)PINT3_EDGE_CLEAR)
+#define pPINT3_INVERT_SET ((volatile unsigned long *)PINT3_INVERT_SET)
+#define pPINT3_INVERT_CLEAR ((volatile unsigned long *)PINT3_INVERT_CLEAR)
+#define pPINT3_PINSTATE ((volatile unsigned long *)PINT3_PINSTATE)
+#define pPINT3_LATCH ((volatile unsigned long *)PINT3_LATCH)
+
+/* Port A Registers */
+
+#define pPORTA_FER ((volatile unsigned short *)PORTA_FER)
+#define pPORTA ((volatile unsigned short *)PORTA)
+#define pPORTA_SET ((volatile unsigned short *)PORTA_SET)
+#define pPORTA_CLEAR ((volatile unsigned short *)PORTA_CLEAR)
+#define pPORTA_DIR_SET ((volatile unsigned short *)PORTA_DIR_SET)
+#define pPORTA_DIR_CLEAR ((volatile unsigned short *)PORTA_DIR_CLEAR)
+#define pPORTA_INEN ((volatile unsigned short *)PORTA_INEN)
+#define pPORTA_MUX ((volatile unsigned long *)PORTA_MUX)
+
+/* Port B Registers */
+
+#define pPORTB_FER ((volatile unsigned short *)PORTB_FER)
+#define pPORTB ((volatile unsigned short *)PORTB)
+#define pPORTB_SET ((volatile unsigned short *)PORTB_SET)
+#define pPORTB_CLEAR ((volatile unsigned short *)PORTB_CLEAR)
+#define pPORTB_DIR_SET ((volatile unsigned short *)PORTB_DIR_SET)
+#define pPORTB_DIR_CLEAR ((volatile unsigned short *)PORTB_DIR_CLEAR)
+#define pPORTB_INEN ((volatile unsigned short *)PORTB_INEN)
+#define pPORTB_MUX ((volatile unsigned long *)PORTB_MUX)
+
+/* Port C Registers */
+
+#define pPORTC_FER ((volatile unsigned short *)PORTC_FER)
+#define pPORTC ((volatile unsigned short *)PORTC)
+#define pPORTC_SET ((volatile unsigned short *)PORTC_SET)
+#define pPORTC_CLEAR ((volatile unsigned short *)PORTC_CLEAR)
+#define pPORTC_DIR_SET ((volatile unsigned short *)PORTC_DIR_SET)
+#define pPORTC_DIR_CLEAR ((volatile unsigned short *)PORTC_DIR_CLEAR)
+#define pPORTC_INEN ((volatile unsigned short *)PORTC_INEN)
+#define pPORTC_MUX ((volatile unsigned long *)PORTC_MUX)
+
+/* Port D Registers */
+
+#define pPORTD_FER ((volatile unsigned short *)PORTD_FER)
+#define pPORTD ((volatile unsigned short *)PORTD)
+#define pPORTD_SET ((volatile unsigned short *)PORTD_SET)
+#define pPORTD_CLEAR ((volatile unsigned short *)PORTD_CLEAR)
+#define pPORTD_DIR_SET ((volatile unsigned short *)PORTD_DIR_SET)
+#define pPORTD_DIR_CLEAR ((volatile unsigned short *)PORTD_DIR_CLEAR)
+#define pPORTD_INEN ((volatile unsigned short *)PORTD_INEN)
+#define pPORTD_MUX ((volatile unsigned long *)PORTD_MUX)
+
+/* Port E Registers */
+
+#define pPORTE_FER ((volatile unsigned short *)PORTE_FER)
+#define pPORTE ((volatile unsigned short *)PORTE)
+#define pPORTE_SET ((volatile unsigned short *)PORTE_SET)
+#define pPORTE_CLEAR ((volatile unsigned short *)PORTE_CLEAR)
+#define pPORTE_DIR_SET ((volatile unsigned short *)PORTE_DIR_SET)
+#define pPORTE_DIR_CLEAR ((volatile unsigned short *)PORTE_DIR_CLEAR)
+#define pPORTE_INEN ((volatile unsigned short *)PORTE_INEN)
+#define pPORTE_MUX ((volatile unsigned long *)PORTE_MUX)
+
+/* Port F Registers */
+
+#define pPORTF_FER ((volatile unsigned short *)PORTF_FER)
+#define pPORTF ((volatile unsigned short *)PORTF)
+#define pPORTF_SET ((volatile unsigned short *)PORTF_SET)
+#define pPORTF_CLEAR ((volatile unsigned short *)PORTF_CLEAR)
+#define pPORTF_DIR_SET ((volatile unsigned short *)PORTF_DIR_SET)
+#define pPORTF_DIR_CLEAR ((volatile unsigned short *)PORTF_DIR_CLEAR)
+#define pPORTF_INEN ((volatile unsigned short *)PORTF_INEN)
+#define pPORTF_MUX ((volatile unsigned long *)PORTF_MUX)
+
+/* Port G Registers */
+
+#define pPORTG_FER ((volatile unsigned short *)PORTG_FER)
+#define pPORTG ((volatile unsigned short *)PORTG)
+#define pPORTG_SET ((volatile unsigned short *)PORTG_SET)
+#define pPORTG_CLEAR ((volatile unsigned short *)PORTG_CLEAR)
+#define pPORTG_DIR_SET ((volatile unsigned short *)PORTG_DIR_SET)
+#define pPORTG_DIR_CLEAR ((volatile unsigned short *)PORTG_DIR_CLEAR)
+#define pPORTG_INEN ((volatile unsigned short *)PORTG_INEN)
+#define pPORTG_MUX ((volatile unsigned long *)PORTG_MUX)
+
+/* Port H Registers */
+
+#define pPORTH_FER ((volatile unsigned short *)PORTH_FER)
+#define pPORTH ((volatile unsigned short *)PORTH)
+#define pPORTH_SET ((volatile unsigned short *)PORTH_SET)
+#define pPORTH_CLEAR ((volatile unsigned short *)PORTH_CLEAR)
+#define pPORTH_DIR_SET ((volatile unsigned short *)PORTH_DIR_SET)
+#define pPORTH_DIR_CLEAR ((volatile unsigned short *)PORTH_DIR_CLEAR)
+#define pPORTH_INEN ((volatile unsigned short *)PORTH_INEN)
+#define pPORTH_MUX ((volatile unsigned long *)PORTH_MUX)
+
+/* Port I Registers */
+
+#define pPORTI_FER ((volatile unsigned short *)PORTI_FER)
+#define pPORTI ((volatile unsigned short *)PORTI)
+#define pPORTI_SET ((volatile unsigned short *)PORTI_SET)
+#define pPORTI_CLEAR ((volatile unsigned short *)PORTI_CLEAR)
+#define pPORTI_DIR_SET ((volatile unsigned short *)PORTI_DIR_SET)
+#define pPORTI_DIR_CLEAR ((volatile unsigned short *)PORTI_DIR_CLEAR)
+#define pPORTI_INEN ((volatile unsigned short *)PORTI_INEN)
+#define pPORTI_MUX ((volatile unsigned long *)PORTI_MUX)
+
+/* Port J Registers */
+
+#define pPORTJ_FER ((volatile unsigned short *)PORTJ_FER)
+#define pPORTJ ((volatile unsigned short *)PORTJ)
+#define pPORTJ_SET ((volatile unsigned short *)PORTJ_SET)
+#define pPORTJ_CLEAR ((volatile unsigned short *)PORTJ_CLEAR)
+#define pPORTJ_DIR_SET ((volatile unsigned short *)PORTJ_DIR_SET)
+#define pPORTJ_DIR_CLEAR ((volatile unsigned short *)PORTJ_DIR_CLEAR)
+#define pPORTJ_INEN ((volatile unsigned short *)PORTJ_INEN)
+#define pPORTJ_MUX ((volatile unsigned long *)PORTJ_MUX)
+
+/* PWM Timer Registers */
+
+#define pTIMER0_CONFIG ((volatile unsigned short *)TIMER0_CONFIG)
+#define pTIMER0_COUNTER ((volatile unsigned long *)TIMER0_COUNTER)
+#define pTIMER0_PERIOD ((volatile unsigned long *)TIMER0_PERIOD)
+#define pTIMER0_WIDTH ((volatile unsigned long *)TIMER0_WIDTH)
+#define pTIMER1_CONFIG ((volatile unsigned short *)TIMER1_CONFIG)
+#define pTIMER1_COUNTER ((volatile unsigned long *)TIMER1_COUNTER)
+#define pTIMER1_PERIOD ((volatile unsigned long *)TIMER1_PERIOD)
+#define pTIMER1_WIDTH ((volatile unsigned long *)TIMER1_WIDTH)
+#define pTIMER2_CONFIG ((volatile unsigned short *)TIMER2_CONFIG)
+#define pTIMER2_COUNTER ((volatile unsigned long *)TIMER2_COUNTER)
+#define pTIMER2_PERIOD ((volatile unsigned long *)TIMER2_PERIOD)
+#define pTIMER2_WIDTH ((volatile unsigned long *)TIMER2_WIDTH)
+#define pTIMER3_CONFIG ((volatile unsigned short *)TIMER3_CONFIG)
+#define pTIMER3_COUNTER ((volatile unsigned long *)TIMER3_COUNTER)
+#define pTIMER3_PERIOD ((volatile unsigned long *)TIMER3_PERIOD)
+#define pTIMER3_WIDTH ((volatile unsigned long *)TIMER3_WIDTH)
+#define pTIMER4_CONFIG ((volatile unsigned short *)TIMER4_CONFIG)
+#define pTIMER4_COUNTER ((volatile unsigned long *)TIMER4_COUNTER)
+#define pTIMER4_PERIOD ((volatile unsigned long *)TIMER4_PERIOD)
+#define pTIMER4_WIDTH ((volatile unsigned long *)TIMER4_WIDTH)
+#define pTIMER5_CONFIG ((volatile unsigned short *)TIMER5_CONFIG)
+#define pTIMER5_COUNTER ((volatile unsigned long *)TIMER5_COUNTER)
+#define pTIMER5_PERIOD ((volatile unsigned long *)TIMER5_PERIOD)
+#define pTIMER5_WIDTH ((volatile unsigned long *)TIMER5_WIDTH)
+#define pTIMER6_CONFIG ((volatile unsigned short *)TIMER6_CONFIG)
+#define pTIMER6_COUNTER ((volatile unsigned long *)TIMER6_COUNTER)
+#define pTIMER6_PERIOD ((volatile unsigned long *)TIMER6_PERIOD)
+#define pTIMER6_WIDTH ((volatile unsigned long *)TIMER6_WIDTH)
+#define pTIMER7_CONFIG ((volatile unsigned short *)TIMER7_CONFIG)
+#define pTIMER7_COUNTER ((volatile unsigned long *)TIMER7_COUNTER)
+#define pTIMER7_PERIOD ((volatile unsigned long *)TIMER7_PERIOD)
+#define pTIMER7_WIDTH ((volatile unsigned long *)TIMER7_WIDTH)
+
+/* Timer Group of 8 */
+
+#define pTIMER_ENABLE0 ((volatile unsigned short *)TIMER_ENABLE0)
+#define pTIMER_DISABLE0 ((volatile unsigned short *)TIMER_DISABLE0)
+#define pTIMER_STATUS0 ((volatile unsigned long *)TIMER_STATUS0)
+
+/* DMAC1 Registers */
+
+#define pDMAC1_TCPER ((volatile unsigned short *)DMAC1_TCPER)
+#define pDMAC1_TCCNT ((volatile unsigned short *)DMAC1_TCCNT)
+
+/* DMA Channel 12 Registers */
+
+#define pDMA12_NEXT_DESC_PTR ((void *volatile *)DMA12_NEXT_DESC_PTR)
+#define pDMA12_START_ADDR ((void *volatile *)DMA12_START_ADDR)
+#define pDMA12_CONFIG ((volatile unsigned short *)DMA12_CONFIG)
+#define pDMA12_X_COUNT ((volatile unsigned short *)DMA12_X_COUNT)
+#define pDMA12_X_MODIFY ((volatile signed short *)DMA12_X_MODIFY)
+#define pDMA12_Y_COUNT ((volatile unsigned short *)DMA12_Y_COUNT)
+#define pDMA12_Y_MODIFY ((volatile signed short *)DMA12_Y_MODIFY)
+#define pDMA12_CURR_DESC_PTR ((void *volatile *)DMA12_CURR_DESC_PTR)
+#define pDMA12_CURR_ADDR ((void *volatile *)DMA12_CURR_ADDR)
+#define pDMA12_IRQ_STATUS ((volatile unsigned short *)DMA12_IRQ_STATUS)
+#define pDMA12_PERIPHERAL_MAP ((volatile unsigned short *)DMA12_PERIPHERAL_MAP)
+#define pDMA12_CURR_X_COUNT ((volatile unsigned short *)DMA12_CURR_X_COUNT)
+#define pDMA12_CURR_Y_COUNT ((volatile unsigned short *)DMA12_CURR_Y_COUNT)
+
+/* DMA Channel 13 Registers */
+
+#define pDMA13_NEXT_DESC_PTR ((void *volatile *)DMA13_NEXT_DESC_PTR)
+#define pDMA13_START_ADDR ((void *volatile *)DMA13_START_ADDR)
+#define pDMA13_CONFIG ((volatile unsigned short *)DMA13_CONFIG)
+#define pDMA13_X_COUNT ((volatile unsigned short *)DMA13_X_COUNT)
+#define pDMA13_X_MODIFY ((volatile signed short *)DMA13_X_MODIFY)
+#define pDMA13_Y_COUNT ((volatile unsigned short *)DMA13_Y_COUNT)
+#define pDMA13_Y_MODIFY ((volatile signed short *)DMA13_Y_MODIFY)
+#define pDMA13_CURR_DESC_PTR ((void *volatile *)DMA13_CURR_DESC_PTR)
+#define pDMA13_CURR_ADDR ((void *volatile *)DMA13_CURR_ADDR)
+#define pDMA13_IRQ_STATUS ((volatile unsigned short *)DMA13_IRQ_STATUS)
+#define pDMA13_PERIPHERAL_MAP ((volatile unsigned short *)DMA13_PERIPHERAL_MAP)
+#define pDMA13_CURR_X_COUNT ((volatile unsigned short *)DMA13_CURR_X_COUNT)
+#define pDMA13_CURR_Y_COUNT ((volatile unsigned short *)DMA13_CURR_Y_COUNT)
+
+/* DMA Channel 14 Registers */
+
+#define pDMA14_NEXT_DESC_PTR ((void *volatile *)DMA14_NEXT_DESC_PTR)
+#define pDMA14_START_ADDR ((void *volatile *)DMA14_START_ADDR)
+#define pDMA14_CONFIG ((volatile unsigned short *)DMA14_CONFIG)
+#define pDMA14_X_COUNT ((volatile unsigned short *)DMA14_X_COUNT)
+#define pDMA14_X_MODIFY ((volatile signed short *)DMA14_X_MODIFY)
+#define pDMA14_Y_COUNT ((volatile unsigned short *)DMA14_Y_COUNT)
+#define pDMA14_Y_MODIFY ((volatile signed short *)DMA14_Y_MODIFY)
+#define pDMA14_CURR_DESC_PTR ((void *volatile *)DMA14_CURR_DESC_PTR)
+#define pDMA14_CURR_ADDR ((void *volatile *)DMA14_CURR_ADDR)
+#define pDMA14_IRQ_STATUS ((volatile unsigned short *)DMA14_IRQ_STATUS)
+#define pDMA14_PERIPHERAL_MAP ((volatile unsigned short *)DMA14_PERIPHERAL_MAP)
+#define pDMA14_CURR_X_COUNT ((volatile unsigned short *)DMA14_CURR_X_COUNT)
+#define pDMA14_CURR_Y_COUNT ((volatile unsigned short *)DMA14_CURR_Y_COUNT)
+
+/* DMA Channel 15 Registers */
+
+#define pDMA15_NEXT_DESC_PTR ((void *volatile *)DMA15_NEXT_DESC_PTR)
+#define pDMA15_START_ADDR ((void *volatile *)DMA15_START_ADDR)
+#define pDMA15_CONFIG ((volatile unsigned short *)DMA15_CONFIG)
+#define pDMA15_X_COUNT ((volatile unsigned short *)DMA15_X_COUNT)
+#define pDMA15_X_MODIFY ((volatile signed short *)DMA15_X_MODIFY)
+#define pDMA15_Y_COUNT ((volatile unsigned short *)DMA15_Y_COUNT)
+#define pDMA15_Y_MODIFY ((volatile signed short *)DMA15_Y_MODIFY)
+#define pDMA15_CURR_DESC_PTR ((void *volatile *)DMA15_CURR_DESC_PTR)
+#define pDMA15_CURR_ADDR ((void *volatile *)DMA15_CURR_ADDR)
+#define pDMA15_IRQ_STATUS ((volatile unsigned short *)DMA15_IRQ_STATUS)
+#define pDMA15_PERIPHERAL_MAP ((volatile unsigned short *)DMA15_PERIPHERAL_MAP)
+#define pDMA15_CURR_X_COUNT ((volatile unsigned short *)DMA15_CURR_X_COUNT)
+#define pDMA15_CURR_Y_COUNT ((volatile unsigned short *)DMA15_CURR_Y_COUNT)
+
+/* DMA Channel 16 Registers */
+
+#define pDMA16_NEXT_DESC_PTR ((void *volatile *)DMA16_NEXT_DESC_PTR)
+#define pDMA16_START_ADDR ((void *volatile *)DMA16_START_ADDR)
+#define pDMA16_CONFIG ((volatile unsigned short *)DMA16_CONFIG)
+#define pDMA16_X_COUNT ((volatile unsigned short *)DMA16_X_COUNT)
+#define pDMA16_X_MODIFY ((volatile signed short *)DMA16_X_MODIFY)
+#define pDMA16_Y_COUNT ((volatile unsigned short *)DMA16_Y_COUNT)
+#define pDMA16_Y_MODIFY ((volatile signed short *)DMA16_Y_MODIFY)
+#define pDMA16_CURR_DESC_PTR ((void *volatile *)DMA16_CURR_DESC_PTR)
+#define pDMA16_CURR_ADDR ((void *volatile *)DMA16_CURR_ADDR)
+#define pDMA16_IRQ_STATUS ((volatile unsigned short *)DMA16_IRQ_STATUS)
+#define pDMA16_PERIPHERAL_MAP ((volatile unsigned short *)DMA16_PERIPHERAL_MAP)
+#define pDMA16_CURR_X_COUNT ((volatile unsigned short *)DMA16_CURR_X_COUNT)
+#define pDMA16_CURR_Y_COUNT ((volatile unsigned short *)DMA16_CURR_Y_COUNT)
+
+/* DMA Channel 17 Registers */
+
+#define pDMA17_NEXT_DESC_PTR ((void *volatile *)DMA17_NEXT_DESC_PTR)
+#define pDMA17_START_ADDR ((void *volatile *)DMA17_START_ADDR)
+#define pDMA17_CONFIG ((volatile unsigned short *)DMA17_CONFIG)
+#define pDMA17_X_COUNT ((volatile unsigned short *)DMA17_X_COUNT)
+#define pDMA17_X_MODIFY ((volatile signed short *)DMA17_X_MODIFY)
+#define pDMA17_Y_COUNT ((volatile unsigned short *)DMA17_Y_COUNT)
+#define pDMA17_Y_MODIFY ((volatile signed short *)DMA17_Y_MODIFY)
+#define pDMA17_CURR_DESC_PTR ((void *volatile *)DMA17_CURR_DESC_PTR)
+#define pDMA17_CURR_ADDR ((void *volatile *)DMA17_CURR_ADDR)
+#define pDMA17_IRQ_STATUS ((volatile unsigned short *)DMA17_IRQ_STATUS)
+#define pDMA17_PERIPHERAL_MAP ((volatile unsigned short *)DMA17_PERIPHERAL_MAP)
+#define pDMA17_CURR_X_COUNT ((volatile unsigned short *)DMA17_CURR_X_COUNT)
+#define pDMA17_CURR_Y_COUNT ((volatile unsigned short *)DMA17_CURR_Y_COUNT)
+
+/* DMA Channel 18 Registers */
+
+#define pDMA18_NEXT_DESC_PTR ((void *volatile *)DMA18_NEXT_DESC_PTR)
+#define pDMA18_START_ADDR ((void *volatile *)DMA18_START_ADDR)
+#define pDMA18_CONFIG ((volatile unsigned short *)DMA18_CONFIG)
+#define pDMA18_X_COUNT ((volatile unsigned short *)DMA18_X_COUNT)
+#define pDMA18_X_MODIFY ((volatile signed short *)DMA18_X_MODIFY)
+#define pDMA18_Y_COUNT ((volatile unsigned short *)DMA18_Y_COUNT)
+#define pDMA18_Y_MODIFY ((volatile signed short *)DMA18_Y_MODIFY)
+#define pDMA18_CURR_DESC_PTR ((void *volatile *)DMA18_CURR_DESC_PTR)
+#define pDMA18_CURR_ADDR ((void *volatile *)DMA18_CURR_ADDR)
+#define pDMA18_IRQ_STATUS ((volatile unsigned short *)DMA18_IRQ_STATUS)
+#define pDMA18_PERIPHERAL_MAP ((volatile unsigned short *)DMA18_PERIPHERAL_MAP)
+#define pDMA18_CURR_X_COUNT ((volatile unsigned short *)DMA18_CURR_X_COUNT)
+#define pDMA18_CURR_Y_COUNT ((volatile unsigned short *)DMA18_CURR_Y_COUNT)
+
+/* DMA Channel 19 Registers */
+
+#define pDMA19_NEXT_DESC_PTR ((void *volatile *)DMA19_NEXT_DESC_PTR)
+#define pDMA19_START_ADDR ((void *volatile *)DMA19_START_ADDR)
+#define pDMA19_CONFIG ((volatile unsigned short *)DMA19_CONFIG)
+#define pDMA19_X_COUNT ((volatile unsigned short *)DMA19_X_COUNT)
+#define pDMA19_X_MODIFY ((volatile signed short *)DMA19_X_MODIFY)
+#define pDMA19_Y_COUNT ((volatile unsigned short *)DMA19_Y_COUNT)
+#define pDMA19_Y_MODIFY ((volatile signed short *)DMA19_Y_MODIFY)
+#define pDMA19_CURR_DESC_PTR ((void *volatile *)DMA19_CURR_DESC_PTR)
+#define pDMA19_CURR_ADDR ((void *volatile *)DMA19_CURR_ADDR)
+#define pDMA19_IRQ_STATUS ((volatile unsigned short *)DMA19_IRQ_STATUS)
+#define pDMA19_PERIPHERAL_MAP ((volatile unsigned short *)DMA19_PERIPHERAL_MAP)
+#define pDMA19_CURR_X_COUNT ((volatile unsigned short *)DMA19_CURR_X_COUNT)
+#define pDMA19_CURR_Y_COUNT ((volatile unsigned short *)DMA19_CURR_Y_COUNT)
+
+/* DMA Channel 20 Registers */
+
+#define pDMA20_NEXT_DESC_PTR ((void *volatile *)DMA20_NEXT_DESC_PTR)
+#define pDMA20_START_ADDR ((void *volatile *)DMA20_START_ADDR)
+#define pDMA20_CONFIG ((volatile unsigned short *)DMA20_CONFIG)
+#define pDMA20_X_COUNT ((volatile unsigned short *)DMA20_X_COUNT)
+#define pDMA20_X_MODIFY ((volatile signed short *)DMA20_X_MODIFY)
+#define pDMA20_Y_COUNT ((volatile unsigned short *)DMA20_Y_COUNT)
+#define pDMA20_Y_MODIFY ((volatile signed short *)DMA20_Y_MODIFY)
+#define pDMA20_CURR_DESC_PTR ((void *volatile *)DMA20_CURR_DESC_PTR)
+#define pDMA20_CURR_ADDR ((void *volatile *)DMA20_CURR_ADDR)
+#define pDMA20_IRQ_STATUS ((volatile unsigned short *)DMA20_IRQ_STATUS)
+#define pDMA20_PERIPHERAL_MAP ((volatile unsigned short *)DMA20_PERIPHERAL_MAP)
+#define pDMA20_CURR_X_COUNT ((volatile unsigned short *)DMA20_CURR_X_COUNT)
+#define pDMA20_CURR_Y_COUNT ((volatile unsigned short *)DMA20_CURR_Y_COUNT)
+
+/* DMA Channel 21 Registers */
+
+#define pDMA21_NEXT_DESC_PTR ((void *volatile *)DMA21_NEXT_DESC_PTR)
+#define pDMA21_START_ADDR ((void *volatile *)DMA21_START_ADDR)
+#define pDMA21_CONFIG ((volatile unsigned short *)DMA21_CONFIG)
+#define pDMA21_X_COUNT ((volatile unsigned short *)DMA21_X_COUNT)
+#define pDMA21_X_MODIFY ((volatile signed short *)DMA21_X_MODIFY)
+#define pDMA21_Y_COUNT ((volatile unsigned short *)DMA21_Y_COUNT)
+#define pDMA21_Y_MODIFY ((volatile signed short *)DMA21_Y_MODIFY)
+#define pDMA21_CURR_DESC_PTR ((void *volatile *)DMA21_CURR_DESC_PTR)
+#define pDMA21_CURR_ADDR ((void *volatile *)DMA21_CURR_ADDR)
+#define pDMA21_IRQ_STATUS ((volatile unsigned short *)DMA21_IRQ_STATUS)
+#define pDMA21_PERIPHERAL_MAP ((volatile unsigned short *)DMA21_PERIPHERAL_MAP)
+#define pDMA21_CURR_X_COUNT ((volatile unsigned short *)DMA21_CURR_X_COUNT)
+#define pDMA21_CURR_Y_COUNT ((volatile unsigned short *)DMA21_CURR_Y_COUNT)
+
+/* DMA Channel 22 Registers */
+
+#define pDMA22_NEXT_DESC_PTR ((void *volatile *)DMA22_NEXT_DESC_PTR)
+#define pDMA22_START_ADDR ((void *volatile *)DMA22_START_ADDR)
+#define pDMA22_CONFIG ((volatile unsigned short *)DMA22_CONFIG)
+#define pDMA22_X_COUNT ((volatile unsigned short *)DMA22_X_COUNT)
+#define pDMA22_X_MODIFY ((volatile signed short *)DMA22_X_MODIFY)
+#define pDMA22_Y_COUNT ((volatile unsigned short *)DMA22_Y_COUNT)
+#define pDMA22_Y_MODIFY ((volatile signed short *)DMA22_Y_MODIFY)
+#define pDMA22_CURR_DESC_PTR ((void *volatile *)DMA22_CURR_DESC_PTR)
+#define pDMA22_CURR_ADDR ((void *volatile *)DMA22_CURR_ADDR)
+#define pDMA22_IRQ_STATUS ((volatile unsigned short *)DMA22_IRQ_STATUS)
+#define pDMA22_PERIPHERAL_MAP ((volatile unsigned short *)DMA22_PERIPHERAL_MAP)
+#define pDMA22_CURR_X_COUNT ((volatile unsigned short *)DMA22_CURR_X_COUNT)
+#define pDMA22_CURR_Y_COUNT ((volatile unsigned short *)DMA22_CURR_Y_COUNT)
+
+/* DMA Channel 23 Registers */
+
+#define pDMA23_NEXT_DESC_PTR ((void *volatile *)DMA23_NEXT_DESC_PTR)
+#define pDMA23_START_ADDR ((void *volatile *)DMA23_START_ADDR)
+#define pDMA23_CONFIG ((volatile unsigned short *)DMA23_CONFIG)
+#define pDMA23_X_COUNT ((volatile unsigned short *)DMA23_X_COUNT)
+#define pDMA23_X_MODIFY ((volatile signed short *)DMA23_X_MODIFY)
+#define pDMA23_Y_COUNT ((volatile unsigned short *)DMA23_Y_COUNT)
+#define pDMA23_Y_MODIFY ((volatile signed short *)DMA23_Y_MODIFY)
+#define pDMA23_CURR_DESC_PTR ((void *volatile *)DMA23_CURR_DESC_PTR)
+#define pDMA23_CURR_ADDR ((void *volatile *)DMA23_CURR_ADDR)
+#define pDMA23_IRQ_STATUS ((volatile unsigned short *)DMA23_IRQ_STATUS)
+#define pDMA23_PERIPHERAL_MAP ((volatile unsigned short *)DMA23_PERIPHERAL_MAP)
+#define pDMA23_CURR_X_COUNT ((volatile unsigned short *)DMA23_CURR_X_COUNT)
+#define pDMA23_CURR_Y_COUNT ((volatile unsigned short *)DMA23_CURR_Y_COUNT)
+
+/* MDMA Stream 2 Registers */
+
+#define pMDMA_D2_NEXT_DESC_PTR ((void *volatile *)MDMA_D2_NEXT_DESC_PTR)
+#define pMDMA_D2_START_ADDR ((void *volatile *)MDMA_D2_START_ADDR)
+#define pMDMA_D2_CONFIG ((volatile unsigned short *)MDMA_D2_CONFIG)
+#define pMDMA_D2_X_COUNT ((volatile unsigned short *)MDMA_D2_X_COUNT)
+#define pMDMA_D2_X_MODIFY ((volatile signed short *)MDMA_D2_X_MODIFY)
+#define pMDMA_D2_Y_COUNT ((volatile unsigned short *)MDMA_D2_Y_COUNT)
+#define pMDMA_D2_Y_MODIFY ((volatile signed short *)MDMA_D2_Y_MODIFY)
+#define pMDMA_D2_CURR_DESC_PTR ((void *volatile *)MDMA_D2_CURR_DESC_PTR)
+#define pMDMA_D2_CURR_ADDR ((void *volatile *)MDMA_D2_CURR_ADDR)
+#define pMDMA_D2_IRQ_STATUS ((volatile unsigned short *)MDMA_D2_IRQ_STATUS)
+#define pMDMA_D2_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D2_PERIPHERAL_MAP)
+#define pMDMA_D2_CURR_X_COUNT ((volatile unsigned short *)MDMA_D2_CURR_X_COUNT)
+#define pMDMA_D2_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D2_CURR_Y_COUNT)
+#define pMDMA_S2_NEXT_DESC_PTR ((void *volatile *)MDMA_S2_NEXT_DESC_PTR)
+#define pMDMA_S2_START_ADDR ((void *volatile *)MDMA_S2_START_ADDR)
+#define pMDMA_S2_CONFIG ((volatile unsigned short *)MDMA_S2_CONFIG)
+#define pMDMA_S2_X_COUNT ((volatile unsigned short *)MDMA_S2_X_COUNT)
+#define pMDMA_S2_X_MODIFY ((volatile signed short *)MDMA_S2_X_MODIFY)
+#define pMDMA_S2_Y_COUNT ((volatile unsigned short *)MDMA_S2_Y_COUNT)
+#define pMDMA_S2_Y_MODIFY ((volatile signed short *)MDMA_S2_Y_MODIFY)
+#define pMDMA_S2_CURR_DESC_PTR ((void *volatile *)MDMA_S2_CURR_DESC_PTR)
+#define pMDMA_S2_CURR_ADDR ((void *volatile *)MDMA_S2_CURR_ADDR)
+#define pMDMA_S2_IRQ_STATUS ((volatile unsigned short *)MDMA_S2_IRQ_STATUS)
+#define pMDMA_S2_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S2_PERIPHERAL_MAP)
+#define pMDMA_S2_CURR_X_COUNT ((volatile unsigned short *)MDMA_S2_CURR_X_COUNT)
+#define pMDMA_S2_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S2_CURR_Y_COUNT)
+
+/* MDMA Stream 3 Registers */
+
+#define pMDMA_D3_NEXT_DESC_PTR ((void *volatile *)MDMA_D3_NEXT_DESC_PTR)
+#define pMDMA_D3_START_ADDR ((void *volatile *)MDMA_D3_START_ADDR)
+#define pMDMA_D3_CONFIG ((volatile unsigned short *)MDMA_D3_CONFIG)
+#define pMDMA_D3_X_COUNT ((volatile unsigned short *)MDMA_D3_X_COUNT)
+#define pMDMA_D3_X_MODIFY ((volatile signed short *)MDMA_D3_X_MODIFY)
+#define pMDMA_D3_Y_COUNT ((volatile unsigned short *)MDMA_D3_Y_COUNT)
+#define pMDMA_D3_Y_MODIFY ((volatile signed short *)MDMA_D3_Y_MODIFY)
+#define pMDMA_D3_CURR_DESC_PTR ((void *volatile *)MDMA_D3_CURR_DESC_PTR)
+#define pMDMA_D3_CURR_ADDR ((void *volatile *)MDMA_D3_CURR_ADDR)
+#define pMDMA_D3_IRQ_STATUS ((volatile unsigned short *)MDMA_D3_IRQ_STATUS)
+#define pMDMA_D3_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_D3_PERIPHERAL_MAP)
+#define pMDMA_D3_CURR_X_COUNT ((volatile unsigned short *)MDMA_D3_CURR_X_COUNT)
+#define pMDMA_D3_CURR_Y_COUNT ((volatile unsigned short *)MDMA_D3_CURR_Y_COUNT)
+#define pMDMA_S3_NEXT_DESC_PTR ((void *volatile *)MDMA_S3_NEXT_DESC_PTR)
+#define pMDMA_S3_START_ADDR ((void *volatile *)MDMA_S3_START_ADDR)
+#define pMDMA_S3_CONFIG ((volatile unsigned short *)MDMA_S3_CONFIG)
+#define pMDMA_S3_X_COUNT ((volatile unsigned short *)MDMA_S3_X_COUNT)
+#define pMDMA_S3_X_MODIFY ((volatile signed short *)MDMA_S3_X_MODIFY)
+#define pMDMA_S3_Y_COUNT ((volatile unsigned short *)MDMA_S3_Y_COUNT)
+#define pMDMA_S3_Y_MODIFY ((volatile signed short *)MDMA_S3_Y_MODIFY)
+#define pMDMA_S3_CURR_DESC_PTR ((void *volatile *)MDMA_S3_CURR_DESC_PTR)
+#define pMDMA_S3_CURR_ADDR ((void *volatile *)MDMA_S3_CURR_ADDR)
+#define pMDMA_S3_IRQ_STATUS ((volatile unsigned short *)MDMA_S3_IRQ_STATUS)
+#define pMDMA_S3_PERIPHERAL_MAP ((volatile unsigned short *)MDMA_S3_PERIPHERAL_MAP)
+#define pMDMA_S3_CURR_X_COUNT ((volatile unsigned short *)MDMA_S3_CURR_X_COUNT)
+#define pMDMA_S3_CURR_Y_COUNT ((volatile unsigned short *)MDMA_S3_CURR_Y_COUNT)
+
+/* UART1 Registers */
+
+#define pUART1_DLL ((volatile unsigned short *)UART1_DLL)
+#define pUART1_DLH ((volatile unsigned short *)UART1_DLH)
+#define pUART1_GCTL ((volatile unsigned short *)UART1_GCTL)
+#define pUART1_LCR ((volatile unsigned short *)UART1_LCR)
+#define pUART1_MCR ((volatile unsigned short *)UART1_MCR)
+#define pUART1_LSR ((volatile unsigned short *)UART1_LSR)
+#define pUART1_MSR ((volatile unsigned short *)UART1_MSR)
+#define pUART1_SCR ((volatile unsigned short *)UART1_SCR)
+#define pUART1_IER_SET ((volatile unsigned short *)UART1_IER_SET)
+#define pUART1_IER_CLEAR ((volatile unsigned short *)UART1_IER_CLEAR)
+#define pUART1_THR ((volatile unsigned short *)UART1_THR)
+#define pUART1_RBR ((volatile unsigned short *)UART1_RBR)
+
+/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
+
+/* SPI1 Registers */
+
+#define pSPI1_CTL ((volatile unsigned short *)SPI1_CTL)
+#define pSPI1_FLG ((volatile unsigned short *)SPI1_FLG)
+#define pSPI1_STAT ((volatile unsigned short *)SPI1_STAT)
+#define pSPI1_TDBR ((volatile unsigned short *)SPI1_TDBR)
+#define pSPI1_RDBR ((volatile unsigned short *)SPI1_RDBR)
+#define pSPI1_BAUD ((volatile unsigned short *)SPI1_BAUD)
+#define pSPI1_SHADOW ((volatile unsigned short *)SPI1_SHADOW)
+
+/* SPORT2 Registers */
+
+#define pSPORT2_TCR1 ((volatile unsigned short *)SPORT2_TCR1)
+#define pSPORT2_TCR2 ((volatile unsigned short *)SPORT2_TCR2)
+#define pSPORT2_TCLKDIV ((volatile unsigned short *)SPORT2_TCLKDIV)
+#define pSPORT2_TFSDIV ((volatile unsigned short *)SPORT2_TFSDIV)
+#define pSPORT2_TX ((volatile unsigned long *)SPORT2_TX)
+#define pSPORT2_RX ((volatile unsigned long *)SPORT2_RX)
+#define pSPORT2_RCR1 ((volatile unsigned short *)SPORT2_RCR1)
+#define pSPORT2_RCR2 ((volatile unsigned short *)SPORT2_RCR2)
+#define pSPORT2_RCLKDIV ((volatile unsigned short *)SPORT2_RCLKDIV)
+#define pSPORT2_RFSDIV ((volatile unsigned short *)SPORT2_RFSDIV)
+#define pSPORT2_STAT ((volatile unsigned short *)SPORT2_STAT)
+#define pSPORT2_CHNL ((volatile unsigned short *)SPORT2_CHNL)
+#define pSPORT2_MCMC1 ((volatile unsigned short *)SPORT2_MCMC1)
+#define pSPORT2_MCMC2 ((volatile unsigned short *)SPORT2_MCMC2)
+#define pSPORT2_MTCS0 ((volatile unsigned long *)SPORT2_MTCS0)
+#define pSPORT2_MTCS1 ((volatile unsigned long *)SPORT2_MTCS1)
+#define pSPORT2_MTCS2 ((volatile unsigned long *)SPORT2_MTCS2)
+#define pSPORT2_MTCS3 ((volatile unsigned long *)SPORT2_MTCS3)
+#define pSPORT2_MRCS0 ((volatile unsigned long *)SPORT2_MRCS0)
+#define pSPORT2_MRCS1 ((volatile unsigned long *)SPORT2_MRCS1)
+#define pSPORT2_MRCS2 ((volatile unsigned long *)SPORT2_MRCS2)
+#define pSPORT2_MRCS3 ((volatile unsigned long *)SPORT2_MRCS3)
+
+/* SPORT3 Registers */
+
+#define pSPORT3_TCR1 ((volatile unsigned short *)SPORT3_TCR1)
+#define pSPORT3_TCR2 ((volatile unsigned short *)SPORT3_TCR2)
+#define pSPORT3_TCLKDIV ((volatile unsigned short *)SPORT3_TCLKDIV)
+#define pSPORT3_TFSDIV ((volatile unsigned short *)SPORT3_TFSDIV)
+#define pSPORT3_TX ((volatile unsigned long *)SPORT3_TX)
+#define pSPORT3_RX ((volatile unsigned long *)SPORT3_RX)
+#define pSPORT3_RCR1 ((volatile unsigned short *)SPORT3_RCR1)
+#define pSPORT3_RCR2 ((volatile unsigned short *)SPORT3_RCR2)
+#define pSPORT3_RCLKDIV ((volatile unsigned short *)SPORT3_RCLKDIV)
+#define pSPORT3_RFSDIV ((volatile unsigned short *)SPORT3_RFSDIV)
+#define pSPORT3_STAT ((volatile unsigned short *)SPORT3_STAT)
+#define pSPORT3_CHNL ((volatile unsigned short *)SPORT3_CHNL)
+#define pSPORT3_MCMC1 ((volatile unsigned short *)SPORT3_MCMC1)
+#define pSPORT3_MCMC2 ((volatile unsigned short *)SPORT3_MCMC2)
+#define pSPORT3_MTCS0 ((volatile unsigned long *)SPORT3_MTCS0)
+#define pSPORT3_MTCS1 ((volatile unsigned long *)SPORT3_MTCS1)
+#define pSPORT3_MTCS2 ((volatile unsigned long *)SPORT3_MTCS2)
+#define pSPORT3_MTCS3 ((volatile unsigned long *)SPORT3_MTCS3)
+#define pSPORT3_MRCS0 ((volatile unsigned long *)SPORT3_MRCS0)
+#define pSPORT3_MRCS1 ((volatile unsigned long *)SPORT3_MRCS1)
+#define pSPORT3_MRCS2 ((volatile unsigned long *)SPORT3_MRCS2)
+#define pSPORT3_MRCS3 ((volatile unsigned long *)SPORT3_MRCS3)
+
+/* EPPI2 Registers */
+
+#define pEPPI2_STATUS ((volatile unsigned short *)EPPI2_STATUS)
+#define pEPPI2_HCOUNT ((volatile unsigned short *)EPPI2_HCOUNT)
+#define pEPPI2_HDELAY ((volatile unsigned short *)EPPI2_HDELAY)
+#define pEPPI2_VCOUNT ((volatile unsigned short *)EPPI2_VCOUNT)
+#define pEPPI2_VDELAY ((volatile unsigned short *)EPPI2_VDELAY)
+#define pEPPI2_FRAME ((volatile unsigned short *)EPPI2_FRAME)
+#define pEPPI2_LINE ((volatile unsigned short *)EPPI2_LINE)
+#define pEPPI2_CLKDIV ((volatile unsigned short *)EPPI2_CLKDIV)
+#define pEPPI2_CONTROL ((volatile unsigned long *)EPPI2_CONTROL)
+#define pEPPI2_FS1W_HBL ((volatile unsigned long *)EPPI2_FS1W_HBL)
+#define pEPPI2_FS1P_AVPL ((volatile unsigned long *)EPPI2_FS1P_AVPL)
+#define pEPPI2_FS2W_LVB ((volatile unsigned long *)EPPI2_FS2W_LVB)
+#define pEPPI2_FS2P_LAVF ((volatile unsigned long *)EPPI2_FS2P_LAVF)
+#define pEPPI2_CLIP ((volatile unsigned long *)EPPI2_CLIP)
+
+/* CAN Controller 0 Config 1 Registers */
+
+#define pCAN0_MC1 ((volatile unsigned short *)CAN0_MC1)
+#define pCAN0_MD1 ((volatile unsigned short *)CAN0_MD1)
+#define pCAN0_TRS1 ((volatile unsigned short *)CAN0_TRS1)
+#define pCAN0_TRR1 ((volatile unsigned short *)CAN0_TRR1)
+#define pCAN0_TA1 ((volatile unsigned short *)CAN0_TA1)
+#define pCAN0_AA1 ((volatile unsigned short *)CAN0_AA1)
+#define pCAN0_RMP1 ((volatile unsigned short *)CAN0_RMP1)
+#define pCAN0_RML1 ((volatile unsigned short *)CAN0_RML1)
+#define pCAN0_MBTIF1 ((volatile unsigned short *)CAN0_MBTIF1)
+#define pCAN0_MBRIF1 ((volatile unsigned short *)CAN0_MBRIF1)
+#define pCAN0_MBIM1 ((volatile unsigned short *)CAN0_MBIM1)
+#define pCAN0_RFH1 ((volatile unsigned short *)CAN0_RFH1)
+#define pCAN0_OPSS1 ((volatile unsigned short *)CAN0_OPSS1)
+
+/* CAN Controller 0 Config 2 Registers */
+
+#define pCAN0_MC2 ((volatile unsigned short *)CAN0_MC2)
+#define pCAN0_MD2 ((volatile unsigned short *)CAN0_MD2)
+#define pCAN0_TRS2 ((volatile unsigned short *)CAN0_TRS2)
+#define pCAN0_TRR2 ((volatile unsigned short *)CAN0_TRR2)
+#define pCAN0_TA2 ((volatile unsigned short *)CAN0_TA2)
+#define pCAN0_AA2 ((volatile unsigned short *)CAN0_AA2)
+#define pCAN0_RMP2 ((volatile unsigned short *)CAN0_RMP2)
+#define pCAN0_RML2 ((volatile unsigned short *)CAN0_RML2)
+#define pCAN0_MBTIF2 ((volatile unsigned short *)CAN0_MBTIF2)
+#define pCAN0_MBRIF2 ((volatile unsigned short *)CAN0_MBRIF2)
+#define pCAN0_MBIM2 ((volatile unsigned short *)CAN0_MBIM2)
+#define pCAN0_RFH2 ((volatile unsigned short *)CAN0_RFH2)
+#define pCAN0_OPSS2 ((volatile unsigned short *)CAN0_OPSS2)
+
+/* CAN Controller 0 Clock/Interrupt/Counter Registers */
+
+#define pCAN0_CLOCK ((volatile unsigned short *)CAN0_CLOCK)
+#define pCAN0_TIMING ((volatile unsigned short *)CAN0_TIMING)
+#define pCAN0_DEBUG ((volatile unsigned short *)CAN0_DEBUG)
+#define pCAN0_STATUS ((volatile unsigned short *)CAN0_STATUS)
+#define pCAN0_CEC ((volatile unsigned short *)CAN0_CEC)
+#define pCAN0_GIS ((volatile unsigned short *)CAN0_GIS)
+#define pCAN0_GIM ((volatile unsigned short *)CAN0_GIM)
+#define pCAN0_GIF ((volatile unsigned short *)CAN0_GIF)
+#define pCAN0_CONTROL ((volatile unsigned short *)CAN0_CONTROL)
+#define pCAN0_INTR ((volatile unsigned short *)CAN0_INTR)
+#define pCAN0_MBTD ((volatile unsigned short *)CAN0_MBTD)
+#define pCAN0_EWR ((volatile unsigned short *)CAN0_EWR)
+#define pCAN0_ESR ((volatile unsigned short *)CAN0_ESR)
+#define pCAN0_UCCNT ((volatile unsigned short *)CAN0_UCCNT)
+#define pCAN0_UCRC ((volatile unsigned short *)CAN0_UCRC)
+#define pCAN0_UCCNF ((volatile unsigned short *)CAN0_UCCNF)
+
+/* CAN Controller 0 Acceptance Registers */
+
+#define pCAN0_AM00L ((volatile unsigned short *)CAN0_AM00L)
+#define pCAN0_AM00H ((volatile unsigned short *)CAN0_AM00H)
+#define pCAN0_AM01L ((volatile unsigned short *)CAN0_AM01L)
+#define pCAN0_AM01H ((volatile unsigned short *)CAN0_AM01H)
+#define pCAN0_AM02L ((volatile unsigned short *)CAN0_AM02L)
+#define pCAN0_AM02H ((volatile unsigned short *)CAN0_AM02H)
+#define pCAN0_AM03L ((volatile unsigned short *)CAN0_AM03L)
+#define pCAN0_AM03H ((volatile unsigned short *)CAN0_AM03H)
+#define pCAN0_AM04L ((volatile unsigned short *)CAN0_AM04L)
+#define pCAN0_AM04H ((volatile unsigned short *)CAN0_AM04H)
+#define pCAN0_AM05L ((volatile unsigned short *)CAN0_AM05L)
+#define pCAN0_AM05H ((volatile unsigned short *)CAN0_AM05H)
+#define pCAN0_AM06L ((volatile unsigned short *)CAN0_AM06L)
+#define pCAN0_AM06H ((volatile unsigned short *)CAN0_AM06H)
+#define pCAN0_AM07L ((volatile unsigned short *)CAN0_AM07L)
+#define pCAN0_AM07H ((volatile unsigned short *)CAN0_AM07H)
+#define pCAN0_AM08L ((volatile unsigned short *)CAN0_AM08L)
+#define pCAN0_AM08H ((volatile unsigned short *)CAN0_AM08H)
+#define pCAN0_AM09L ((volatile unsigned short *)CAN0_AM09L)
+#define pCAN0_AM09H ((volatile unsigned short *)CAN0_AM09H)
+#define pCAN0_AM10L ((volatile unsigned short *)CAN0_AM10L)
+#define pCAN0_AM10H ((volatile unsigned short *)CAN0_AM10H)
+#define pCAN0_AM11L ((volatile unsigned short *)CAN0_AM11L)
+#define pCAN0_AM11H ((volatile unsigned short *)CAN0_AM11H)
+#define pCAN0_AM12L ((volatile unsigned short *)CAN0_AM12L)
+#define pCAN0_AM12H ((volatile unsigned short *)CAN0_AM12H)
+#define pCAN0_AM13L ((volatile unsigned short *)CAN0_AM13L)
+#define pCAN0_AM13H ((volatile unsigned short *)CAN0_AM13H)
+#define pCAN0_AM14L ((volatile unsigned short *)CAN0_AM14L)
+#define pCAN0_AM14H ((volatile unsigned short *)CAN0_AM14H)
+#define pCAN0_AM15L ((volatile unsigned short *)CAN0_AM15L)
+#define pCAN0_AM15H ((volatile unsigned short *)CAN0_AM15H)
+
+/* CAN Controller 0 Acceptance Registers */
+
+#define pCAN0_AM16L ((volatile unsigned short *)CAN0_AM16L)
+#define pCAN0_AM16H ((volatile unsigned short *)CAN0_AM16H)
+#define pCAN0_AM17L ((volatile unsigned short *)CAN0_AM17L)
+#define pCAN0_AM17H ((volatile unsigned short *)CAN0_AM17H)
+#define pCAN0_AM18L ((volatile unsigned short *)CAN0_AM18L)
+#define pCAN0_AM18H ((volatile unsigned short *)CAN0_AM18H)
+#define pCAN0_AM19L ((volatile unsigned short *)CAN0_AM19L)
+#define pCAN0_AM19H ((volatile unsigned short *)CAN0_AM19H)
+#define pCAN0_AM20L ((volatile unsigned short *)CAN0_AM20L)
+#define pCAN0_AM20H ((volatile unsigned short *)CAN0_AM20H)
+#define pCAN0_AM21L ((volatile unsigned short *)CAN0_AM21L)
+#define pCAN0_AM21H ((volatile unsigned short *)CAN0_AM21H)
+#define pCAN0_AM22L ((volatile unsigned short *)CAN0_AM22L)
+#define pCAN0_AM22H ((volatile unsigned short *)CAN0_AM22H)
+#define pCAN0_AM23L ((volatile unsigned short *)CAN0_AM23L)
+#define pCAN0_AM23H ((volatile unsigned short *)CAN0_AM23H)
+#define pCAN0_AM24L ((volatile unsigned short *)CAN0_AM24L)
+#define pCAN0_AM24H ((volatile unsigned short *)CAN0_AM24H)
+#define pCAN0_AM25L ((volatile unsigned short *)CAN0_AM25L)
+#define pCAN0_AM25H ((volatile unsigned short *)CAN0_AM25H)
+#define pCAN0_AM26L ((volatile unsigned short *)CAN0_AM26L)
+#define pCAN0_AM26H ((volatile unsigned short *)CAN0_AM26H)
+#define pCAN0_AM27L ((volatile unsigned short *)CAN0_AM27L)
+#define pCAN0_AM27H ((volatile unsigned short *)CAN0_AM27H)
+#define pCAN0_AM28L ((volatile unsigned short *)CAN0_AM28L)
+#define pCAN0_AM28H ((volatile unsigned short *)CAN0_AM28H)
+#define pCAN0_AM29L ((volatile unsigned short *)CAN0_AM29L)
+#define pCAN0_AM29H ((volatile unsigned short *)CAN0_AM29H)
+#define pCAN0_AM30L ((volatile unsigned short *)CAN0_AM30L)
+#define pCAN0_AM30H ((volatile unsigned short *)CAN0_AM30H)
+#define pCAN0_AM31L ((volatile unsigned short *)CAN0_AM31L)
+#define pCAN0_AM31H ((volatile unsigned short *)CAN0_AM31H)
+
+/* CAN Controller 0 Mailbox Data Registers */
+
+#define pCAN0_MB00_DATA0 ((volatile unsigned short *)CAN0_MB00_DATA0)
+#define pCAN0_MB00_DATA1 ((volatile unsigned short *)CAN0_MB00_DATA1)
+#define pCAN0_MB00_DATA2 ((volatile unsigned short *)CAN0_MB00_DATA2)
+#define pCAN0_MB00_DATA3 ((volatile unsigned short *)CAN0_MB00_DATA3)
+#define pCAN0_MB00_LENGTH ((volatile unsigned short *)CAN0_MB00_LENGTH)
+#define pCAN0_MB00_TIMESTAMP ((volatile unsigned short *)CAN0_MB00_TIMESTAMP)
+#define pCAN0_MB00_ID0 ((volatile unsigned short *)CAN0_MB00_ID0)
+#define pCAN0_MB00_ID1 ((volatile unsigned short *)CAN0_MB00_ID1)
+#define pCAN0_MB01_DATA0 ((volatile unsigned short *)CAN0_MB01_DATA0)
+#define pCAN0_MB01_DATA1 ((volatile unsigned short *)CAN0_MB01_DATA1)
+#define pCAN0_MB01_DATA2 ((volatile unsigned short *)CAN0_MB01_DATA2)
+#define pCAN0_MB01_DATA3 ((volatile unsigned short *)CAN0_MB01_DATA3)
+#define pCAN0_MB01_LENGTH ((volatile unsigned short *)CAN0_MB01_LENGTH)
+#define pCAN0_MB01_TIMESTAMP ((volatile unsigned short *)CAN0_MB01_TIMESTAMP)
+#define pCAN0_MB01_ID0 ((volatile unsigned short *)CAN0_MB01_ID0)
+#define pCAN0_MB01_ID1 ((volatile unsigned short *)CAN0_MB01_ID1)
+#define pCAN0_MB02_DATA0 ((volatile unsigned short *)CAN0_MB02_DATA0)
+#define pCAN0_MB02_DATA1 ((volatile unsigned short *)CAN0_MB02_DATA1)
+#define pCAN0_MB02_DATA2 ((volatile unsigned short *)CAN0_MB02_DATA2)
+#define pCAN0_MB02_DATA3 ((volatile unsigned short *)CAN0_MB02_DATA3)
+#define pCAN0_MB02_LENGTH ((volatile unsigned short *)CAN0_MB02_LENGTH)
+#define pCAN0_MB02_TIMESTAMP ((volatile unsigned short *)CAN0_MB02_TIMESTAMP)
+#define pCAN0_MB02_ID0 ((volatile unsigned short *)CAN0_MB02_ID0)
+#define pCAN0_MB02_ID1 ((volatile unsigned short *)CAN0_MB02_ID1)
+#define pCAN0_MB03_DATA0 ((volatile unsigned short *)CAN0_MB03_DATA0)
+#define pCAN0_MB03_DATA1 ((volatile unsigned short *)CAN0_MB03_DATA1)
+#define pCAN0_MB03_DATA2 ((volatile unsigned short *)CAN0_MB03_DATA2)
+#define pCAN0_MB03_DATA3 ((volatile unsigned short *)CAN0_MB03_DATA3)
+#define pCAN0_MB03_LENGTH ((volatile unsigned short *)CAN0_MB03_LENGTH)
+#define pCAN0_MB03_TIMESTAMP ((volatile unsigned short *)CAN0_MB03_TIMESTAMP)
+#define pCAN0_MB03_ID0 ((volatile unsigned short *)CAN0_MB03_ID0)
+#define pCAN0_MB03_ID1 ((volatile unsigned short *)CAN0_MB03_ID1)
+#define pCAN0_MB04_DATA0 ((volatile unsigned short *)CAN0_MB04_DATA0)
+#define pCAN0_MB04_DATA1 ((volatile unsigned short *)CAN0_MB04_DATA1)
+#define pCAN0_MB04_DATA2 ((volatile unsigned short *)CAN0_MB04_DATA2)
+#define pCAN0_MB04_DATA3 ((volatile unsigned short *)CAN0_MB04_DATA3)
+#define pCAN0_MB04_LENGTH ((volatile unsigned short *)CAN0_MB04_LENGTH)
+#define pCAN0_MB04_TIMESTAMP ((volatile unsigned short *)CAN0_MB04_TIMESTAMP)
+#define pCAN0_MB04_ID0 ((volatile unsigned short *)CAN0_MB04_ID0)
+#define pCAN0_MB04_ID1 ((volatile unsigned short *)CAN0_MB04_ID1)
+#define pCAN0_MB05_DATA0 ((volatile unsigned short *)CAN0_MB05_DATA0)
+#define pCAN0_MB05_DATA1 ((volatile unsigned short *)CAN0_MB05_DATA1)
+#define pCAN0_MB05_DATA2 ((volatile unsigned short *)CAN0_MB05_DATA2)
+#define pCAN0_MB05_DATA3 ((volatile unsigned short *)CAN0_MB05_DATA3)
+#define pCAN0_MB05_LENGTH ((volatile unsigned short *)CAN0_MB05_LENGTH)
+#define pCAN0_MB05_TIMESTAMP ((volatile unsigned short *)CAN0_MB05_TIMESTAMP)
+#define pCAN0_MB05_ID0 ((volatile unsigned short *)CAN0_MB05_ID0)
+#define pCAN0_MB05_ID1 ((volatile unsigned short *)CAN0_MB05_ID1)
+#define pCAN0_MB06_DATA0 ((volatile unsigned short *)CAN0_MB06_DATA0)
+#define pCAN0_MB06_DATA1 ((volatile unsigned short *)CAN0_MB06_DATA1)
+#define pCAN0_MB06_DATA2 ((volatile unsigned short *)CAN0_MB06_DATA2)
+#define pCAN0_MB06_DATA3 ((volatile unsigned short *)CAN0_MB06_DATA3)
+#define pCAN0_MB06_LENGTH ((volatile unsigned short *)CAN0_MB06_LENGTH)
+#define pCAN0_MB06_TIMESTAMP ((volatile unsigned short *)CAN0_MB06_TIMESTAMP)
+#define pCAN0_MB06_ID0 ((volatile unsigned short *)CAN0_MB06_ID0)
+#define pCAN0_MB06_ID1 ((volatile unsigned short *)CAN0_MB06_ID1)
+#define pCAN0_MB07_DATA0 ((volatile unsigned short *)CAN0_MB07_DATA0)
+#define pCAN0_MB07_DATA1 ((volatile unsigned short *)CAN0_MB07_DATA1)
+#define pCAN0_MB07_DATA2 ((volatile unsigned short *)CAN0_MB07_DATA2)
+#define pCAN0_MB07_DATA3 ((volatile unsigned short *)CAN0_MB07_DATA3)
+#define pCAN0_MB07_LENGTH ((volatile unsigned short *)CAN0_MB07_LENGTH)
+#define pCAN0_MB07_TIMESTAMP ((volatile unsigned short *)CAN0_MB07_TIMESTAMP)
+#define pCAN0_MB07_ID0 ((volatile unsigned short *)CAN0_MB07_ID0)
+#define pCAN0_MB07_ID1 ((volatile unsigned short *)CAN0_MB07_ID1)
+#define pCAN0_MB08_DATA0 ((volatile unsigned short *)CAN0_MB08_DATA0)
+#define pCAN0_MB08_DATA1 ((volatile unsigned short *)CAN0_MB08_DATA1)
+#define pCAN0_MB08_DATA2 ((volatile unsigned short *)CAN0_MB08_DATA2)
+#define pCAN0_MB08_DATA3 ((volatile unsigned short *)CAN0_MB08_DATA3)
+#define pCAN0_MB08_LENGTH ((volatile unsigned short *)CAN0_MB08_LENGTH)
+#define pCAN0_MB08_TIMESTAMP ((volatile unsigned short *)CAN0_MB08_TIMESTAMP)
+#define pCAN0_MB08_ID0 ((volatile unsigned short *)CAN0_MB08_ID0)
+#define pCAN0_MB08_ID1 ((volatile unsigned short *)CAN0_MB08_ID1)
+#define pCAN0_MB09_DATA0 ((volatile unsigned short *)CAN0_MB09_DATA0)
+#define pCAN0_MB09_DATA1 ((volatile unsigned short *)CAN0_MB09_DATA1)
+#define pCAN0_MB09_DATA2 ((volatile unsigned short *)CAN0_MB09_DATA2)
+#define pCAN0_MB09_DATA3 ((volatile unsigned short *)CAN0_MB09_DATA3)
+#define pCAN0_MB09_LENGTH ((volatile unsigned short *)CAN0_MB09_LENGTH)
+#define pCAN0_MB09_TIMESTAMP ((volatile unsigned short *)CAN0_MB09_TIMESTAMP)
+#define pCAN0_MB09_ID0 ((volatile unsigned short *)CAN0_MB09_ID0)
+#define pCAN0_MB09_ID1 ((volatile unsigned short *)CAN0_MB09_ID1)
+#define pCAN0_MB10_DATA0 ((volatile unsigned short *)CAN0_MB10_DATA0)
+#define pCAN0_MB10_DATA1 ((volatile unsigned short *)CAN0_MB10_DATA1)
+#define pCAN0_MB10_DATA2 ((volatile unsigned short *)CAN0_MB10_DATA2)
+#define pCAN0_MB10_DATA3 ((volatile unsigned short *)CAN0_MB10_DATA3)
+#define pCAN0_MB10_LENGTH ((volatile unsigned short *)CAN0_MB10_LENGTH)
+#define pCAN0_MB10_TIMESTAMP ((volatile unsigned short *)CAN0_MB10_TIMESTAMP)
+#define pCAN0_MB10_ID0 ((volatile unsigned short *)CAN0_MB10_ID0)
+#define pCAN0_MB10_ID1 ((volatile unsigned short *)CAN0_MB10_ID1)
+#define pCAN0_MB11_DATA0 ((volatile unsigned short *)CAN0_MB11_DATA0)
+#define pCAN0_MB11_DATA1 ((volatile unsigned short *)CAN0_MB11_DATA1)
+#define pCAN0_MB11_DATA2 ((volatile unsigned short *)CAN0_MB11_DATA2)
+#define pCAN0_MB11_DATA3 ((volatile unsigned short *)CAN0_MB11_DATA3)
+#define pCAN0_MB11_LENGTH ((volatile unsigned short *)CAN0_MB11_LENGTH)
+#define pCAN0_MB11_TIMESTAMP ((volatile unsigned short *)CAN0_MB11_TIMESTAMP)
+#define pCAN0_MB11_ID0 ((volatile unsigned short *)CAN0_MB11_ID0)
+#define pCAN0_MB11_ID1 ((volatile unsigned short *)CAN0_MB11_ID1)
+#define pCAN0_MB12_DATA0 ((volatile unsigned short *)CAN0_MB12_DATA0)
+#define pCAN0_MB12_DATA1 ((volatile unsigned short *)CAN0_MB12_DATA1)
+#define pCAN0_MB12_DATA2 ((volatile unsigned short *)CAN0_MB12_DATA2)
+#define pCAN0_MB12_DATA3 ((volatile unsigned short *)CAN0_MB12_DATA3)
+#define pCAN0_MB12_LENGTH ((volatile unsigned short *)CAN0_MB12_LENGTH)
+#define pCAN0_MB12_TIMESTAMP ((volatile unsigned short *)CAN0_MB12_TIMESTAMP)
+#define pCAN0_MB12_ID0 ((volatile unsigned short *)CAN0_MB12_ID0)
+#define pCAN0_MB12_ID1 ((volatile unsigned short *)CAN0_MB12_ID1)
+#define pCAN0_MB13_DATA0 ((volatile unsigned short *)CAN0_MB13_DATA0)
+#define pCAN0_MB13_DATA1 ((volatile unsigned short *)CAN0_MB13_DATA1)
+#define pCAN0_MB13_DATA2 ((volatile unsigned short *)CAN0_MB13_DATA2)
+#define pCAN0_MB13_DATA3 ((volatile unsigned short *)CAN0_MB13_DATA3)
+#define pCAN0_MB13_LENGTH ((volatile unsigned short *)CAN0_MB13_LENGTH)
+#define pCAN0_MB13_TIMESTAMP ((volatile unsigned short *)CAN0_MB13_TIMESTAMP)
+#define pCAN0_MB13_ID0 ((volatile unsigned short *)CAN0_MB13_ID0)
+#define pCAN0_MB13_ID1 ((volatile unsigned short *)CAN0_MB13_ID1)
+#define pCAN0_MB14_DATA0 ((volatile unsigned short *)CAN0_MB14_DATA0)
+#define pCAN0_MB14_DATA1 ((volatile unsigned short *)CAN0_MB14_DATA1)
+#define pCAN0_MB14_DATA2 ((volatile unsigned short *)CAN0_MB14_DATA2)
+#define pCAN0_MB14_DATA3 ((volatile unsigned short *)CAN0_MB14_DATA3)
+#define pCAN0_MB14_LENGTH ((volatile unsigned short *)CAN0_MB14_LENGTH)
+#define pCAN0_MB14_TIMESTAMP ((volatile unsigned short *)CAN0_MB14_TIMESTAMP)
+#define pCAN0_MB14_ID0 ((volatile unsigned short *)CAN0_MB14_ID0)
+#define pCAN0_MB14_ID1 ((volatile unsigned short *)CAN0_MB14_ID1)
+#define pCAN0_MB15_DATA0 ((volatile unsigned short *)CAN0_MB15_DATA0)
+#define pCAN0_MB15_DATA1 ((volatile unsigned short *)CAN0_MB15_DATA1)
+#define pCAN0_MB15_DATA2 ((volatile unsigned short *)CAN0_MB15_DATA2)
+#define pCAN0_MB15_DATA3 ((volatile unsigned short *)CAN0_MB15_DATA3)
+#define pCAN0_MB15_LENGTH ((volatile unsigned short *)CAN0_MB15_LENGTH)
+#define pCAN0_MB15_TIMESTAMP ((volatile unsigned short *)CAN0_MB15_TIMESTAMP)
+#define pCAN0_MB15_ID0 ((volatile unsigned short *)CAN0_MB15_ID0)
+#define pCAN0_MB15_ID1 ((volatile unsigned short *)CAN0_MB15_ID1)
+
+/* CAN Controller 0 Mailbox Data Registers */
+
+#define pCAN0_MB16_DATA0 ((volatile unsigned short *)CAN0_MB16_DATA0)
+#define pCAN0_MB16_DATA1 ((volatile unsigned short *)CAN0_MB16_DATA1)
+#define pCAN0_MB16_DATA2 ((volatile unsigned short *)CAN0_MB16_DATA2)
+#define pCAN0_MB16_DATA3 ((volatile unsigned short *)CAN0_MB16_DATA3)
+#define pCAN0_MB16_LENGTH ((volatile unsigned short *)CAN0_MB16_LENGTH)
+#define pCAN0_MB16_TIMESTAMP ((volatile unsigned short *)CAN0_MB16_TIMESTAMP)
+#define pCAN0_MB16_ID0 ((volatile unsigned short *)CAN0_MB16_ID0)
+#define pCAN0_MB16_ID1 ((volatile unsigned short *)CAN0_MB16_ID1)
+#define pCAN0_MB17_DATA0 ((volatile unsigned short *)CAN0_MB17_DATA0)
+#define pCAN0_MB17_DATA1 ((volatile unsigned short *)CAN0_MB17_DATA1)
+#define pCAN0_MB17_DATA2 ((volatile unsigned short *)CAN0_MB17_DATA2)
+#define pCAN0_MB17_DATA3 ((volatile unsigned short *)CAN0_MB17_DATA3)
+#define pCAN0_MB17_LENGTH ((volatile unsigned short *)CAN0_MB17_LENGTH)
+#define pCAN0_MB17_TIMESTAMP ((volatile unsigned short *)CAN0_MB17_TIMESTAMP)
+#define pCAN0_MB17_ID0 ((volatile unsigned short *)CAN0_MB17_ID0)
+#define pCAN0_MB17_ID1 ((volatile unsigned short *)CAN0_MB17_ID1)
+#define pCAN0_MB18_DATA0 ((volatile unsigned short *)CAN0_MB18_DATA0)
+#define pCAN0_MB18_DATA1 ((volatile unsigned short *)CAN0_MB18_DATA1)
+#define pCAN0_MB18_DATA2 ((volatile unsigned short *)CAN0_MB18_DATA2)
+#define pCAN0_MB18_DATA3 ((volatile unsigned short *)CAN0_MB18_DATA3)
+#define pCAN0_MB18_LENGTH ((volatile unsigned short *)CAN0_MB18_LENGTH)
+#define pCAN0_MB18_TIMESTAMP ((volatile unsigned short *)CAN0_MB18_TIMESTAMP)
+#define pCAN0_MB18_ID0 ((volatile unsigned short *)CAN0_MB18_ID0)
+#define pCAN0_MB18_ID1 ((volatile unsigned short *)CAN0_MB18_ID1)
+#define pCAN0_MB19_DATA0 ((volatile unsigned short *)CAN0_MB19_DATA0)
+#define pCAN0_MB19_DATA1 ((volatile unsigned short *)CAN0_MB19_DATA1)
+#define pCAN0_MB19_DATA2 ((volatile unsigned short *)CAN0_MB19_DATA2)
+#define pCAN0_MB19_DATA3 ((volatile unsigned short *)CAN0_MB19_DATA3)
+#define pCAN0_MB19_LENGTH ((volatile unsigned short *)CAN0_MB19_LENGTH)
+#define pCAN0_MB19_TIMESTAMP ((volatile unsigned short *)CAN0_MB19_TIMESTAMP)
+#define pCAN0_MB19_ID0 ((volatile unsigned short *)CAN0_MB19_ID0)
+#define pCAN0_MB19_ID1 ((volatile unsigned short *)CAN0_MB19_ID1)
+#define pCAN0_MB20_DATA0 ((volatile unsigned short *)CAN0_MB20_DATA0)
+#define pCAN0_MB20_DATA1 ((volatile unsigned short *)CAN0_MB20_DATA1)
+#define pCAN0_MB20_DATA2 ((volatile unsigned short *)CAN0_MB20_DATA2)
+#define pCAN0_MB20_DATA3 ((volatile unsigned short *)CAN0_MB20_DATA3)
+#define pCAN0_MB20_LENGTH ((volatile unsigned short *)CAN0_MB20_LENGTH)
+#define pCAN0_MB20_TIMESTAMP ((volatile unsigned short *)CAN0_MB20_TIMESTAMP)
+#define pCAN0_MB20_ID0 ((volatile unsigned short *)CAN0_MB20_ID0)
+#define pCAN0_MB20_ID1 ((volatile unsigned short *)CAN0_MB20_ID1)
+#define pCAN0_MB21_DATA0 ((volatile unsigned short *)CAN0_MB21_DATA0)
+#define pCAN0_MB21_DATA1 ((volatile unsigned short *)CAN0_MB21_DATA1)
+#define pCAN0_MB21_DATA2 ((volatile unsigned short *)CAN0_MB21_DATA2)
+#define pCAN0_MB21_DATA3 ((volatile unsigned short *)CAN0_MB21_DATA3)
+#define pCAN0_MB21_LENGTH ((volatile unsigned short *)CAN0_MB21_LENGTH)
+#define pCAN0_MB21_TIMESTAMP ((volatile unsigned short *)CAN0_MB21_TIMESTAMP)
+#define pCAN0_MB21_ID0 ((volatile unsigned short *)CAN0_MB21_ID0)
+#define pCAN0_MB21_ID1 ((volatile unsigned short *)CAN0_MB21_ID1)
+#define pCAN0_MB22_DATA0 ((volatile unsigned short *)CAN0_MB22_DATA0)
+#define pCAN0_MB22_DATA1 ((volatile unsigned short *)CAN0_MB22_DATA1)
+#define pCAN0_MB22_DATA2 ((volatile unsigned short *)CAN0_MB22_DATA2)
+#define pCAN0_MB22_DATA3 ((volatile unsigned short *)CAN0_MB22_DATA3)
+#define pCAN0_MB22_LENGTH ((volatile unsigned short *)CAN0_MB22_LENGTH)
+#define pCAN0_MB22_TIMESTAMP ((volatile unsigned short *)CAN0_MB22_TIMESTAMP)
+#define pCAN0_MB22_ID0 ((volatile unsigned short *)CAN0_MB22_ID0)
+#define pCAN0_MB22_ID1 ((volatile unsigned short *)CAN0_MB22_ID1)
+#define pCAN0_MB23_DATA0 ((volatile unsigned short *)CAN0_MB23_DATA0)
+#define pCAN0_MB23_DATA1 ((volatile unsigned short *)CAN0_MB23_DATA1)
+#define pCAN0_MB23_DATA2 ((volatile unsigned short *)CAN0_MB23_DATA2)
+#define pCAN0_MB23_DATA3 ((volatile unsigned short *)CAN0_MB23_DATA3)
+#define pCAN0_MB23_LENGTH ((volatile unsigned short *)CAN0_MB23_LENGTH)
+#define pCAN0_MB23_TIMESTAMP ((volatile unsigned short *)CAN0_MB23_TIMESTAMP)
+#define pCAN0_MB23_ID0 ((volatile unsigned short *)CAN0_MB23_ID0)
+#define pCAN0_MB23_ID1 ((volatile unsigned short *)CAN0_MB23_ID1)
+#define pCAN0_MB24_DATA0 ((volatile unsigned short *)CAN0_MB24_DATA0)
+#define pCAN0_MB24_DATA1 ((volatile unsigned short *)CAN0_MB24_DATA1)
+#define pCAN0_MB24_DATA2 ((volatile unsigned short *)CAN0_MB24_DATA2)
+#define pCAN0_MB24_DATA3 ((volatile unsigned short *)CAN0_MB24_DATA3)
+#define pCAN0_MB24_LENGTH ((volatile unsigned short *)CAN0_MB24_LENGTH)
+#define pCAN0_MB24_TIMESTAMP ((volatile unsigned short *)CAN0_MB24_TIMESTAMP)
+#define pCAN0_MB24_ID0 ((volatile unsigned short *)CAN0_MB24_ID0)
+#define pCAN0_MB24_ID1 ((volatile unsigned short *)CAN0_MB24_ID1)
+#define pCAN0_MB25_DATA0 ((volatile unsigned short *)CAN0_MB25_DATA0)
+#define pCAN0_MB25_DATA1 ((volatile unsigned short *)CAN0_MB25_DATA1)
+#define pCAN0_MB25_DATA2 ((volatile unsigned short *)CAN0_MB25_DATA2)
+#define pCAN0_MB25_DATA3 ((volatile unsigned short *)CAN0_MB25_DATA3)
+#define pCAN0_MB25_LENGTH ((volatile unsigned short *)CAN0_MB25_LENGTH)
+#define pCAN0_MB25_TIMESTAMP ((volatile unsigned short *)CAN0_MB25_TIMESTAMP)
+#define pCAN0_MB25_ID0 ((volatile unsigned short *)CAN0_MB25_ID0)
+#define pCAN0_MB25_ID1 ((volatile unsigned short *)CAN0_MB25_ID1)
+#define pCAN0_MB26_DATA0 ((volatile unsigned short *)CAN0_MB26_DATA0)
+#define pCAN0_MB26_DATA1 ((volatile unsigned short *)CAN0_MB26_DATA1)
+#define pCAN0_MB26_DATA2 ((volatile unsigned short *)CAN0_MB26_DATA2)
+#define pCAN0_MB26_DATA3 ((volatile unsigned short *)CAN0_MB26_DATA3)
+#define pCAN0_MB26_LENGTH ((volatile unsigned short *)CAN0_MB26_LENGTH)
+#define pCAN0_MB26_TIMESTAMP ((volatile unsigned short *)CAN0_MB26_TIMESTAMP)
+#define pCAN0_MB26_ID0 ((volatile unsigned short *)CAN0_MB26_ID0)
+#define pCAN0_MB26_ID1 ((volatile unsigned short *)CAN0_MB26_ID1)
+#define pCAN0_MB27_DATA0 ((volatile unsigned short *)CAN0_MB27_DATA0)
+#define pCAN0_MB27_DATA1 ((volatile unsigned short *)CAN0_MB27_DATA1)
+#define pCAN0_MB27_DATA2 ((volatile unsigned short *)CAN0_MB27_DATA2)
+#define pCAN0_MB27_DATA3 ((volatile unsigned short *)CAN0_MB27_DATA3)
+#define pCAN0_MB27_LENGTH ((volatile unsigned short *)CAN0_MB27_LENGTH)
+#define pCAN0_MB27_TIMESTAMP ((volatile unsigned short *)CAN0_MB27_TIMESTAMP)
+#define pCAN0_MB27_ID0 ((volatile unsigned short *)CAN0_MB27_ID0)
+#define pCAN0_MB27_ID1 ((volatile unsigned short *)CAN0_MB27_ID1)
+#define pCAN0_MB28_DATA0 ((volatile unsigned short *)CAN0_MB28_DATA0)
+#define pCAN0_MB28_DATA1 ((volatile unsigned short *)CAN0_MB28_DATA1)
+#define pCAN0_MB28_DATA2 ((volatile unsigned short *)CAN0_MB28_DATA2)
+#define pCAN0_MB28_DATA3 ((volatile unsigned short *)CAN0_MB28_DATA3)
+#define pCAN0_MB28_LENGTH ((volatile unsigned short *)CAN0_MB28_LENGTH)
+#define pCAN0_MB28_TIMESTAMP ((volatile unsigned short *)CAN0_MB28_TIMESTAMP)
+#define pCAN0_MB28_ID0 ((volatile unsigned short *)CAN0_MB28_ID0)
+#define pCAN0_MB28_ID1 ((volatile unsigned short *)CAN0_MB28_ID1)
+#define pCAN0_MB29_DATA0 ((volatile unsigned short *)CAN0_MB29_DATA0)
+#define pCAN0_MB29_DATA1 ((volatile unsigned short *)CAN0_MB29_DATA1)
+#define pCAN0_MB29_DATA2 ((volatile unsigned short *)CAN0_MB29_DATA2)
+#define pCAN0_MB29_DATA3 ((volatile unsigned short *)CAN0_MB29_DATA3)
+#define pCAN0_MB29_LENGTH ((volatile unsigned short *)CAN0_MB29_LENGTH)
+#define pCAN0_MB29_TIMESTAMP ((volatile unsigned short *)CAN0_MB29_TIMESTAMP)
+#define pCAN0_MB29_ID0 ((volatile unsigned short *)CAN0_MB29_ID0)
+#define pCAN0_MB29_ID1 ((volatile unsigned short *)CAN0_MB29_ID1)
+#define pCAN0_MB30_DATA0 ((volatile unsigned short *)CAN0_MB30_DATA0)
+#define pCAN0_MB30_DATA1 ((volatile unsigned short *)CAN0_MB30_DATA1)
+#define pCAN0_MB30_DATA2 ((volatile unsigned short *)CAN0_MB30_DATA2)
+#define pCAN0_MB30_DATA3 ((volatile unsigned short *)CAN0_MB30_DATA3)
+#define pCAN0_MB30_LENGTH ((volatile unsigned short *)CAN0_MB30_LENGTH)
+#define pCAN0_MB30_TIMESTAMP ((volatile unsigned short *)CAN0_MB30_TIMESTAMP)
+#define pCAN0_MB30_ID0 ((volatile unsigned short *)CAN0_MB30_ID0)
+#define pCAN0_MB30_ID1 ((volatile unsigned short *)CAN0_MB30_ID1)
+#define pCAN0_MB31_DATA0 ((volatile unsigned short *)CAN0_MB31_DATA0)
+#define pCAN0_MB31_DATA1 ((volatile unsigned short *)CAN0_MB31_DATA1)
+#define pCAN0_MB31_DATA2 ((volatile unsigned short *)CAN0_MB31_DATA2)
+#define pCAN0_MB31_DATA3 ((volatile unsigned short *)CAN0_MB31_DATA3)
+#define pCAN0_MB31_LENGTH ((volatile unsigned short *)CAN0_MB31_LENGTH)
+#define pCAN0_MB31_TIMESTAMP ((volatile unsigned short *)CAN0_MB31_TIMESTAMP)
+#define pCAN0_MB31_ID0 ((volatile unsigned short *)CAN0_MB31_ID0)
+#define pCAN0_MB31_ID1 ((volatile unsigned short *)CAN0_MB31_ID1)
+
+/* UART3 Registers */
+
+#define pUART3_DLL ((volatile unsigned short *)UART3_DLL)
+#define pUART3_DLH ((volatile unsigned short *)UART3_DLH)
+#define pUART3_GCTL ((volatile unsigned short *)UART3_GCTL)
+#define pUART3_LCR ((volatile unsigned short *)UART3_LCR)
+#define pUART3_MCR ((volatile unsigned short *)UART3_MCR)
+#define pUART3_LSR ((volatile unsigned short *)UART3_LSR)
+#define pUART3_MSR ((volatile unsigned short *)UART3_MSR)
+#define pUART3_SCR ((volatile unsigned short *)UART3_SCR)
+#define pUART3_IER_SET ((volatile unsigned short *)UART3_IER_SET)
+#define pUART3_IER_CLEAR ((volatile unsigned short *)UART3_IER_CLEAR)
+#define pUART3_THR ((volatile unsigned short *)UART3_THR)
+#define pUART3_RBR ((volatile unsigned short *)UART3_RBR)
+
+/* NFC Registers */
+
+#define pNFC_CTL ((volatile unsigned short *)NFC_CTL)
+#define pNFC_STAT ((volatile unsigned short *)NFC_STAT)
+#define pNFC_IRQSTAT ((volatile unsigned short *)NFC_IRQSTAT)
+#define pNFC_IRQMASK ((volatile unsigned short *)NFC_IRQMASK)
+#define pNFC_ECC0 ((volatile unsigned short *)NFC_ECC0)
+#define pNFC_ECC1 ((volatile unsigned short *)NFC_ECC1)
+#define pNFC_ECC2 ((volatile unsigned short *)NFC_ECC2)
+#define pNFC_ECC3 ((volatile unsigned short *)NFC_ECC3)
+#define pNFC_COUNT ((volatile unsigned short *)NFC_COUNT)
+#define pNFC_RST ((volatile unsigned short *)NFC_RST)
+#define pNFC_PGCTL ((volatile unsigned short *)NFC_PGCTL)
+#define pNFC_READ ((volatile unsigned short *)NFC_READ)
+#define pNFC_ADDR ((volatile unsigned short *)NFC_ADDR)
+#define pNFC_CMD ((volatile unsigned short *)NFC_CMD)
+#define pNFC_DATA_WR ((volatile unsigned short *)NFC_DATA_WR)
+#define pNFC_DATA_RD ((volatile unsigned short *)NFC_DATA_RD)
+
+/* Counter Registers */
+
+#define pCNT_CONFIG ((volatile unsigned short *)CNT_CONFIG)
+#define pCNT_IMASK ((volatile unsigned short *)CNT_IMASK)
+#define pCNT_STATUS ((volatile unsigned short *)CNT_STATUS)
+#define pCNT_COMMAND ((volatile unsigned short *)CNT_COMMAND)
+#define pCNT_DEBOUNCE ((volatile unsigned short *)CNT_DEBOUNCE)
+#define pCNT_COUNTER ((volatile unsigned long *)CNT_COUNTER)
+#define pCNT_MAX ((volatile unsigned long *)CNT_MAX)
+#define pCNT_MIN ((volatile unsigned long *)CNT_MIN)
+
+/* OTP/FUSE Registers */
+
+#define pOTP_CONTROL ((volatile unsigned short *)OTP_CONTROL)
+#define pOTP_BEN ((volatile unsigned short *)OTP_BEN)
+#define pOTP_STATUS ((volatile unsigned short *)OTP_STATUS)
+#define pOTP_TIMING ((volatile unsigned long *)OTP_TIMING)
+
+/* Security Registers */
+
+#define pSECURE_SYSSWT ((volatile unsigned long *)SECURE_SYSSWT)
+#define pSECURE_CONTROL ((volatile unsigned short *)SECURE_CONTROL)
+#define pSECURE_STATUS ((volatile unsigned short *)SECURE_STATUS)
+
+/* DMA Peripheral Mux Register */
+
+#define pDMAC1_PERIMUX ((volatile unsigned short *)DMAC1_PERIMUX)
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define pOTP_DATA0 ((volatile unsigned long *)OTP_DATA0)
+#define pOTP_DATA1 ((volatile unsigned long *)OTP_DATA1)
+#define pOTP_DATA2 ((volatile unsigned long *)OTP_DATA2)
+#define pOTP_DATA3 ((volatile unsigned long *)OTP_DATA3)
+
+/* Handshake MDMA 0 Registers */
+
+#define pHMDMA0_CONTROL ((volatile unsigned short *)HMDMA0_CONTROL)
+#define pHMDMA0_ECINIT ((volatile unsigned short *)HMDMA0_ECINIT)
+#define pHMDMA0_BCINIT ((volatile unsigned short *)HMDMA0_BCINIT)
+#define pHMDMA0_ECURGENT ((volatile unsigned short *)HMDMA0_ECURGENT)
+#define pHMDMA0_ECOVERFLOW ((volatile unsigned short *)HMDMA0_ECOVERFLOW)
+#define pHMDMA0_ECOUNT ((volatile unsigned short *)HMDMA0_ECOUNT)
+#define pHMDMA0_BCOUNT ((volatile unsigned short *)HMDMA0_BCOUNT)
+
+/* Handshake MDMA 1 Registers */
+
+#define pHMDMA1_CONTROL ((volatile unsigned short *)HMDMA1_CONTROL)
+#define pHMDMA1_ECINIT ((volatile unsigned short *)HMDMA1_ECINIT)
+#define pHMDMA1_BCINIT ((volatile unsigned short *)HMDMA1_BCINIT)
+#define pHMDMA1_ECURGENT ((volatile unsigned short *)HMDMA1_ECURGENT)
+#define pHMDMA1_ECOVERFLOW ((volatile unsigned short *)HMDMA1_ECOVERFLOW)
+#define pHMDMA1_ECOUNT ((volatile unsigned short *)HMDMA1_ECOUNT)
+#define pHMDMA1_BCOUNT ((volatile unsigned short *)HMDMA1_BCOUNT)
+
+/* legacy definitions */
+#define pEBIU_AMCBCTL0 pEBIU_AMBCTL0
+#define pEBIU_AMCBCTL1 pEBIU_AMBCTL1
+#define pPINT0_IRQ pPINT0_REQUEST
+#define pPINT1_IRQ pPINT1_REQUEST
+#define pPINT2_IRQ pPINT2_REQUEST
+#define pPINT3_IRQ pPINT3_REQUEST
+
+#endif /* _CDEF_BF54X_H */
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * cdefBF561.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
+
+#ifndef _CDEF_BF561_H
+#define _CDEF_BF561_H
+
+#if !defined(__ADSPBF561__)
+#warning cdefBF561.h should only be included for BF561 chip.
+#endif
+/* include all Core registers and bit definitions */
+#include <defBF561.h>
+#include <cdef_LPBlackfin.h>
+
+/*********************************************************************************** */
+/* System MMR Register Map */
+/*********************************************************************************** */
+
+#ifndef _PTR_TO_VOL_VOID_PTR
+#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
+#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
+#else
+#define _PTR_TO_VOL_VOID_PTR (volatile void **)
+#endif
+#endif
+
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define pPLL_CTL (volatile unsigned short *)PLL_CTL
+#define pPLL_DIV (volatile unsigned short *)PLL_DIV
+#define pVR_CTL (volatile unsigned short *)VR_CTL
+#define pPLL_STAT (volatile unsigned short *)PLL_STAT
+#define pPLL_LOCKCNT (volatile unsigned short *)PLL_LOCKCNT
+#define pCHIPID ((volatile unsigned long*)CHIPID)
+
+/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
+#define pSICA_SWRST (volatile unsigned short *)SICA_SWRST
+#define pSICA_SYSCR (volatile unsigned short *)SICA_SYSCR
+#define pSICA_RVECT (volatile unsigned short *)SICA_RVECT
+#define pSICA_IMASK (volatile unsigned long *)SICA_IMASK
+#define pSICA_IMASK0 (volatile unsigned long *)SICA_IMASK0
+#define pSICA_IMASK1 (volatile unsigned long *)SICA_IMASK1
+#define pSICA_IAR0 (volatile unsigned long *)SICA_IAR0
+#define pSICA_IAR1 (volatile unsigned long *)SICA_IAR1
+#define pSICA_IAR2 (volatile unsigned long *)SICA_IAR2
+#define pSICA_IAR3 (volatile unsigned long *)SICA_IAR3
+#define pSICA_IAR4 (volatile unsigned long *)SICA_IAR4
+#define pSICA_IAR5 (volatile unsigned long *)SICA_IAR5
+#define pSICA_IAR6 (volatile unsigned long *)SICA_IAR6
+#define pSICA_IAR7 (volatile unsigned long *)SICA_IAR7
+#define pSICA_ISR0 (volatile unsigned long *)SICA_ISR0
+#define pSICA_ISR1 (volatile unsigned long *)SICA_ISR1
+#define pSICA_IWR0 (volatile unsigned long *)SICA_IWR0
+#define pSICA_IWR1 (volatile unsigned long *)SICA_IWR1
+
+/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
+#define pSICB_SWRST (volatile unsigned short *)SICB_SWRST
+#define pSICB_SYSCR (volatile unsigned short *)SICB_SYSCR
+#define pSICB_RVECT (volatile unsigned short *)SICB_RVECT
+#define pSICB_IMASK0 (volatile unsigned long *)SICB_IMASK0
+#define pSICB_IMASK1 (volatile unsigned long *)SICB_IMASK1
+#define pSICB_IAR0 (volatile unsigned long *)SICB_IAR0
+#define pSICB_IAR1 (volatile unsigned long *)SICB_IAR1
+#define pSICB_IAR2 (volatile unsigned long *)SICB_IAR2
+#define pSICB_IAR3 (volatile unsigned long *)SICB_IAR3
+#define pSICB_IAR4 (volatile unsigned long *)SICB_IAR4
+#define pSICB_IAR5 (volatile unsigned long *)SICB_IAR5
+#define pSICB_IAR6 (volatile unsigned long *)SICB_IAR6
+#define pSICB_IAR7 (volatile unsigned long *)SICB_IAR7
+#define pSICB_ISR0 (volatile unsigned long *)SICB_ISR0
+#define pSICB_ISR1 (volatile unsigned long *)SICB_ISR1
+#define pSICB_IWR0 (volatile unsigned long *)SICB_IWR0
+#define pSICB_IWR1 (volatile unsigned long *)SICB_IWR1
+/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
+#define pWDOGA_CTL (volatile unsigned short *)WDOGA_CTL
+#define pWDOGA_CNT (volatile unsigned long *)WDOGA_CNT
+#define pWDOGA_STAT (volatile unsigned long *)WDOGA_STAT
+
+/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
+#define pWDOGB_CTL (volatile unsigned short *)WDOGB_CTL
+#define pWDOGB_CNT (volatile unsigned long *)WDOGB_CNT
+#define pWDOGB_STAT (volatile unsigned long *)WDOGB_STAT
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define pUART_THR (volatile unsigned short *)UART_THR
+#define pUART_RBR (volatile unsigned short *)UART_RBR
+#define pUART_DLL (volatile unsigned short *)UART_DLL
+#define pUART_IER (volatile unsigned short *)UART_IER
+#define pUART_DLH (volatile unsigned short *)UART_DLH
+#define pUART_IIR (volatile unsigned short *)UART_IIR
+#define pUART_LCR (volatile unsigned short *)UART_LCR
+#define pUART_MCR (volatile unsigned short *)UART_MCR
+#define pUART_LSR (volatile unsigned short *)UART_LSR
+#define pUART_MSR (volatile unsigned short *)UART_MSR
+#define pUART_SCR (volatile unsigned short *)UART_SCR
+#define pUART_GCTL (volatile unsigned short *)UART_GCTL
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define pSPI_CTL (volatile unsigned short *)SPI_CTL
+#define pSPI_FLG (volatile unsigned short *)SPI_FLG
+#define pSPI_STAT (volatile unsigned short *)SPI_STAT
+#define pSPI_TDBR (volatile unsigned short *)SPI_TDBR
+#define pSPI_RDBR (volatile unsigned short *)SPI_RDBR
+#define pSPI_BAUD (volatile unsigned short *)SPI_BAUD
+#define pSPI_SHADOW (volatile unsigned short *)SPI_SHADOW
+
+/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
+#define pTIMER0_CONFIG (volatile unsigned short *)TIMER0_CONFIG
+#define pTIMER0_COUNTER (volatile unsigned long *)TIMER0_COUNTER
+#define pTIMER0_PERIOD (volatile unsigned long *)TIMER0_PERIOD
+#define pTIMER0_WIDTH (volatile unsigned long *)TIMER0_WIDTH
+#define pTIMER1_CONFIG (volatile unsigned short *)TIMER1_CONFIG
+#define pTIMER1_COUNTER (volatile unsigned long *)TIMER1_COUNTER
+#define pTIMER1_PERIOD (volatile unsigned long *)TIMER1_PERIOD
+#define pTIMER1_WIDTH (volatile unsigned long *)TIMER1_WIDTH
+#define pTIMER2_CONFIG (volatile unsigned short *)TIMER2_CONFIG
+#define pTIMER2_COUNTER (volatile unsigned long *)TIMER2_COUNTER
+#define pTIMER2_PERIOD (volatile unsigned long *)TIMER2_PERIOD
+#define pTIMER2_WIDTH (volatile unsigned long *)TIMER2_WIDTH
+#define pTIMER3_CONFIG (volatile unsigned short *)TIMER3_CONFIG
+#define pTIMER3_COUNTER (volatile unsigned long *)TIMER3_COUNTER
+#define pTIMER3_PERIOD (volatile unsigned long *)TIMER3_PERIOD
+#define pTIMER3_WIDTH (volatile unsigned long *)TIMER3_WIDTH
+#define pTIMER4_CONFIG (volatile unsigned short *)TIMER4_CONFIG
+#define pTIMER4_COUNTER (volatile unsigned long *)TIMER4_COUNTER
+#define pTIMER4_PERIOD (volatile unsigned long *)TIMER4_PERIOD
+#define pTIMER4_WIDTH (volatile unsigned long *)TIMER4_WIDTH
+#define pTIMER5_CONFIG (volatile unsigned short *)TIMER5_CONFIG
+#define pTIMER5_COUNTER (volatile unsigned long *)TIMER5_COUNTER
+#define pTIMER5_PERIOD (volatile unsigned long *)TIMER5_PERIOD
+#define pTIMER5_WIDTH (volatile unsigned long *)TIMER5_WIDTH
+#define pTIMER6_CONFIG (volatile unsigned short *)TIMER6_CONFIG
+#define pTIMER6_COUNTER (volatile unsigned long *)TIMER6_COUNTER
+#define pTIMER6_PERIOD (volatile unsigned long *)TIMER6_PERIOD
+#define pTIMER6_WIDTH (volatile unsigned long *)TIMER6_WIDTH
+#define pTIMER7_CONFIG (volatile unsigned short *)TIMER7_CONFIG
+#define pTIMER7_COUNTER (volatile unsigned long *)TIMER7_COUNTER
+#define pTIMER7_PERIOD (volatile unsigned long *)TIMER7_PERIOD
+#define pTIMER7_WIDTH (volatile unsigned long *)TIMER7_WIDTH
+
+/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
+#define pTMRS8_ENABLE (volatile unsigned short *)TMRS8_ENABLE
+#define pTMRS8_DISABLE (volatile unsigned short *)TMRS8_DISABLE
+#define pTMRS8_STATUS (volatile unsigned long *)TMRS8_STATUS
+#define pTIMER8_CONFIG (volatile unsigned short *)TIMER8_CONFIG
+#define pTIMER8_COUNTER (volatile unsigned long *)TIMER8_COUNTER
+#define pTIMER8_PERIOD (volatile unsigned long *)TIMER8_PERIOD
+#define pTIMER8_WIDTH (volatile unsigned long *)TIMER8_WIDTH
+#define pTIMER9_CONFIG (volatile unsigned short *)TIMER9_CONFIG
+#define pTIMER9_COUNTER (volatile unsigned long *)TIMER9_COUNTER
+#define pTIMER9_PERIOD (volatile unsigned long *)TIMER9_PERIOD
+#define pTIMER9_WIDTH (volatile unsigned long *)TIMER9_WIDTH
+#define pTIMER10_CONFIG (volatile unsigned short *)TIMER10_CONFIG
+#define pTIMER10_COUNTER (volatile unsigned long *)TIMER10_COUNTER
+#define pTIMER10_PERIOD (volatile unsigned long *)TIMER10_PERIOD
+#define pTIMER10_WIDTH (volatile unsigned long *)TIMER10_WIDTH
+#define pTIMER11_CONFIG (volatile unsigned short *)TIMER11_CONFIG
+#define pTIMER11_COUNTER (volatile unsigned long *)TIMER11_COUNTER
+#define pTIMER11_PERIOD (volatile unsigned long *)TIMER11_PERIOD
+#define pTIMER11_WIDTH (volatile unsigned long *)TIMER11_WIDTH
+#define pTMRS4_ENABLE (volatile unsigned short *)TMRS4_ENABLE
+#define pTMRS4_DISABLE (volatile unsigned short *)TMRS4_DISABLE
+#define pTMRS4_STATUS (volatile unsigned long *)TMRS4_STATUS
+
+/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
+#define pFIO0_FLAG_D (volatile unsigned short *)FIO0_FLAG_D
+#define pFIO0_FLAG_C (volatile unsigned short *)FIO0_FLAG_C
+#define pFIO0_FLAG_S (volatile unsigned short *)FIO0_FLAG_S
+#define pFIO0_FLAG_T (volatile unsigned short *)FIO0_FLAG_T
+#define pFIO0_MASKA_D (volatile unsigned short *)FIO0_MASKA_D
+#define pFIO0_MASKA_C (volatile unsigned short *)FIO0_MASKA_C
+#define pFIO0_MASKA_S (volatile unsigned short *)FIO0_MASKA_S
+#define pFIO0_MASKA_T (volatile unsigned short *)FIO0_MASKA_T
+#define pFIO0_MASKB_D (volatile unsigned short *)FIO0_MASKB_D
+#define pFIO0_MASKB_C (volatile unsigned short *)FIO0_MASKB_C
+#define pFIO0_MASKB_S (volatile unsigned short *)FIO0_MASKB_S
+#define pFIO0_MASKB_T (volatile unsigned short *)FIO0_MASKB_T
+#define pFIO0_DIR (volatile unsigned short *)FIO0_DIR
+#define pFIO0_POLAR (volatile unsigned short *)FIO0_POLAR
+#define pFIO0_EDGE (volatile unsigned short *)FIO0_EDGE
+#define pFIO0_BOTH (volatile unsigned short *)FIO0_BOTH
+#define pFIO0_INEN (volatile unsigned short *)FIO0_INEN
+/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
+#define pFIO1_FLAG_D (volatile unsigned short *)FIO1_FLAG_D
+#define pFIO1_FLAG_C (volatile unsigned short *)FIO1_FLAG_C
+#define pFIO1_FLAG_S (volatile unsigned short *)FIO1_FLAG_S
+#define pFIO1_FLAG_T (volatile unsigned short *)FIO1_FLAG_T
+#define pFIO1_MASKA_D (volatile unsigned short *)FIO1_MASKA_D
+#define pFIO1_MASKA_C (volatile unsigned short *)FIO1_MASKA_C
+#define pFIO1_MASKA_S (volatile unsigned short *)FIO1_MASKA_S
+#define pFIO1_MASKA_T (volatile unsigned short *)FIO1_MASKA_T
+#define pFIO1_MASKB_D (volatile unsigned short *)FIO1_MASKB_D
+#define pFIO1_MASKB_C (volatile unsigned short *)FIO1_MASKB_C
+#define pFIO1_MASKB_S (volatile unsigned short *)FIO1_MASKB_S
+#define pFIO1_MASKB_T (volatile unsigned short *)FIO1_MASKB_T
+#define pFIO1_DIR (volatile unsigned short *)FIO1_DIR
+#define pFIO1_POLAR (volatile unsigned short *)FIO1_POLAR
+#define pFIO1_EDGE (volatile unsigned short *)FIO1_EDGE
+#define pFIO1_BOTH (volatile unsigned short *)FIO1_BOTH
+#define pFIO1_INEN (volatile unsigned short *)FIO1_INEN
+/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
+#define pFIO2_FLAG_D (volatile unsigned short *)FIO2_FLAG_D
+#define pFIO2_FLAG_C (volatile unsigned short *)FIO2_FLAG_C
+#define pFIO2_FLAG_S (volatile unsigned short *)FIO2_FLAG_S
+#define pFIO2_FLAG_T (volatile unsigned short *)FIO2_FLAG_T
+#define pFIO2_MASKA_D (volatile unsigned short *)FIO2_MASKA_D
+#define pFIO2_MASKA_C (volatile unsigned short *)FIO2_MASKA_C
+#define pFIO2_MASKA_S (volatile unsigned short *)FIO2_MASKA_S
+#define pFIO2_MASKA_T (volatile unsigned short *)FIO2_MASKA_T
+#define pFIO2_MASKB_D (volatile unsigned short *)FIO2_MASKB_D
+#define pFIO2_MASKB_C (volatile unsigned short *)FIO2_MASKB_C
+#define pFIO2_MASKB_S (volatile unsigned short *)FIO2_MASKB_S
+#define pFIO2_MASKB_T (volatile unsigned short *)FIO2_MASKB_T
+#define pFIO2_DIR (volatile unsigned short *)FIO2_DIR
+#define pFIO2_POLAR (volatile unsigned short *)FIO2_POLAR
+#define pFIO2_EDGE (volatile unsigned short *)FIO2_EDGE
+#define pFIO2_BOTH (volatile unsigned short *)FIO2_BOTH
+#define pFIO2_INEN (volatile unsigned short *)FIO2_INEN
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define pSPORT0_TCR1 (volatile unsigned short *)SPORT0_TCR1
+#define pSPORT0_TCR2 (volatile unsigned short *)SPORT0_TCR2
+#define pSPORT0_TCLKDIV (volatile unsigned short *)SPORT0_TCLKDIV
+#define pSPORT0_TFSDIV (volatile unsigned short *)SPORT0_TFSDIV
+#define pSPORT0_TX (volatile unsigned long *)SPORT0_TX
+#define pSPORT0_RX (volatile unsigned long *)SPORT0_RX
+#define pSPORT0_TX32 ((volatile long *)SPORT0_TX)
+#define pSPORT0_RX32 ((volatile long *)SPORT0_RX)
+#define pSPORT0_TX16 ((volatile unsigned short *)SPORT0_TX)
+#define pSPORT0_RX16 ((volatile unsigned short *)SPORT0_RX)
+#define pSPORT0_RCR1 (volatile unsigned short *)SPORT0_RCR1
+#define pSPORT0_RCR2 (volatile unsigned short *)SPORT0_RCR2
+#define pSPORT0_RCLKDIV (volatile unsigned short *)SPORT0_RCLKDIV
+#define pSPORT0_RFSDIV (volatile unsigned short *)SPORT0_RFSDIV
+#define pSPORT0_STAT (volatile unsigned short *)SPORT0_STAT
+#define pSPORT0_CHNL (volatile unsigned short *)SPORT0_CHNL
+#define pSPORT0_MCMC1 (volatile unsigned short *)SPORT0_MCMC1
+#define pSPORT0_MCMC2 (volatile unsigned short *)SPORT0_MCMC2
+#define pSPORT0_MTCS0 (volatile unsigned long *)SPORT0_MTCS0
+#define pSPORT0_MTCS1 (volatile unsigned long *)SPORT0_MTCS1
+#define pSPORT0_MTCS2 (volatile unsigned long *)SPORT0_MTCS2
+#define pSPORT0_MTCS3 (volatile unsigned long *)SPORT0_MTCS3
+#define pSPORT0_MRCS0 (volatile unsigned long *)SPORT0_MRCS0
+#define pSPORT0_MRCS1 (volatile unsigned long *)SPORT0_MRCS1
+#define pSPORT0_MRCS2 (volatile unsigned long *)SPORT0_MRCS2
+#define pSPORT0_MRCS3 (volatile unsigned long *)SPORT0_MRCS3
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define pSPORT1_TCR1 (volatile unsigned short *)SPORT1_TCR1
+#define pSPORT1_TCR2 (volatile unsigned short *)SPORT1_TCR2
+#define pSPORT1_TCLKDIV (volatile unsigned short *)SPORT1_TCLKDIV
+#define pSPORT1_TFSDIV (volatile unsigned short *)SPORT1_TFSDIV
+#define pSPORT1_TX (volatile unsigned long *)SPORT1_TX
+#define pSPORT1_RX (volatile unsigned long *)SPORT1_RX
+#define pSPORT1_TX32 ((volatile long *)SPORT1_TX)
+#define pSPORT1_RX32 ((volatile long *)SPORT1_RX)
+#define pSPORT1_TX16 ((volatile unsigned short *)SPORT1_TX)
+#define pSPORT1_RX16 ((volatile unsigned short *)SPORT1_RX)
+#define pSPORT1_RCR1 (volatile unsigned short *)SPORT1_RCR1
+#define pSPORT1_RCR2 (volatile unsigned short *)SPORT1_RCR2
+#define pSPORT1_RCLKDIV (volatile unsigned short *)SPORT1_RCLKDIV
+#define pSPORT1_RFSDIV (volatile unsigned short *)SPORT1_RFSDIV
+#define pSPORT1_STAT (volatile unsigned short *)SPORT1_STAT
+#define pSPORT1_CHNL (volatile unsigned short *)SPORT1_CHNL
+#define pSPORT1_MCMC1 (volatile unsigned short *)SPORT1_MCMC1
+#define pSPORT1_MCMC2 (volatile unsigned short *)SPORT1_MCMC2
+#define pSPORT1_MTCS0 (volatile unsigned long *)SPORT1_MTCS0
+#define pSPORT1_MTCS1 (volatile unsigned long *)SPORT1_MTCS1
+#define pSPORT1_MTCS2 (volatile unsigned long *)SPORT1_MTCS2
+#define pSPORT1_MTCS3 (volatile unsigned long *)SPORT1_MTCS3
+#define pSPORT1_MRCS0 (volatile unsigned long *)SPORT1_MRCS0
+#define pSPORT1_MRCS1 (volatile unsigned long *)SPORT1_MRCS1
+#define pSPORT1_MRCS2 (volatile unsigned long *)SPORT1_MRCS2
+#define pSPORT1_MRCS3 (volatile unsigned long *)SPORT1_MRCS3
+/* Asynchronous Memory Controller - External Bus Interface Unit */
+#define pEBIU_AMGCTL (volatile unsigned short *)EBIU_AMGCTL
+#define pEBIU_AMBCTL0 (volatile unsigned long *)EBIU_AMBCTL0
+#define pEBIU_AMBCTL1 (volatile unsigned long *)EBIU_AMBCTL1
+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define pEBIU_SDGCTL (volatile unsigned long *)EBIU_SDGCTL
+#define pEBIU_SDBCTL (volatile unsigned long *)EBIU_SDBCTL
+#define pEBIU_SDRRC (volatile unsigned short *)EBIU_SDRRC
+#define pEBIU_SDSTAT (volatile unsigned short *)EBIU_SDSTAT
+/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
+#define pPPI0_CONTROL (volatile unsigned short *)PPI0_CONTROL
+#define pPPI0_STATUS (volatile unsigned short *)PPI0_STATUS
+#define pPPI0_COUNT (volatile unsigned short *)PPI0_COUNT
+#define pPPI0_DELAY (volatile unsigned short *)PPI0_DELAY
+#define pPPI0_FRAME (volatile unsigned short *)PPI0_FRAME
+/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
+#define pPPI1_CONTROL (volatile unsigned short *)PPI1_CONTROL
+#define pPPI1_STATUS (volatile unsigned short *)PPI1_STATUS
+#define pPPI1_COUNT (volatile unsigned short *)PPI1_COUNT
+#define pPPI1_DELAY (volatile unsigned short *)PPI1_DELAY
+#define pPPI1_FRAME (volatile unsigned short *)PPI1_FRAME
+/*DMA traffic control registers */
+#define pDMA1_TC_PER (volatile unsigned short *)DMA1_TC_PER
+#define pDMA1_TC_CNT (volatile unsigned short *)DMA1_TC_CNT
+#define pDMA2_TC_PER (volatile unsigned short *)DMA2_TC_PER
+#define pDMA2_TC_CNT (volatile unsigned short *)DMA2_TC_CNT
+/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
+#define pDMA1_0_CONFIG (volatile unsigned short *)DMA1_0_CONFIG
+#define pDMA1_0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_0_NEXT_DESC_PTR
+#define pDMA1_0_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_0_START_ADDR
+#define pDMA1_0_X_COUNT (volatile unsigned short *)DMA1_0_X_COUNT
+#define pDMA1_0_Y_COUNT (volatile unsigned short *)DMA1_0_Y_COUNT
+#define pDMA1_0_X_MODIFY (volatile signed short *)DMA1_0_X_MODIFY
+#define pDMA1_0_Y_MODIFY (volatile signed short *)DMA1_0_Y_MODIFY
+#define pDMA1_0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_0_CURR_DESC_PTR
+#define pDMA1_0_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_0_CURR_ADDR
+#define pDMA1_0_CURR_X_COUNT (volatile unsigned short *)DMA1_0_CURR_X_COUNT
+#define pDMA1_0_CURR_Y_COUNT (volatile unsigned short *)DMA1_0_CURR_Y_COUNT
+#define pDMA1_0_IRQ_STATUS (volatile unsigned short *)DMA1_0_IRQ_STATUS
+#define pDMA1_0_PERIPHERAL_MAP (volatile unsigned short *)DMA1_0_PERIPHERAL_MAP
+#define pDMA1_1_CONFIG (volatile unsigned short *)DMA1_1_CONFIG
+#define pDMA1_1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_1_NEXT_DESC_PTR
+#define pDMA1_1_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_1_START_ADDR
+#define pDMA1_1_X_COUNT (volatile unsigned short *)DMA1_1_X_COUNT
+#define pDMA1_1_Y_COUNT (volatile unsigned short *)DMA1_1_Y_COUNT
+#define pDMA1_1_X_MODIFY (volatile signed short *)DMA1_1_X_MODIFY
+#define pDMA1_1_Y_MODIFY (volatile signed short *)DMA1_1_Y_MODIFY
+#define pDMA1_1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_1_CURR_DESC_PTR
+#define pDMA1_1_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_1_CURR_ADDR
+#define pDMA1_1_CURR_X_COUNT (volatile unsigned short *)DMA1_1_CURR_X_COUNT
+#define pDMA1_1_CURR_Y_COUNT (volatile unsigned short *)DMA1_1_CURR_Y_COUNT
+#define pDMA1_1_IRQ_STATUS (volatile unsigned short *)DMA1_1_IRQ_STATUS
+#define pDMA1_1_PERIPHERAL_MAP (volatile unsigned short *)DMA1_1_PERIPHERAL_MAP
+#define pDMA1_2_CONFIG (volatile unsigned short *)DMA1_2_CONFIG
+#define pDMA1_2_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_2_NEXT_DESC_PTR
+#define pDMA1_2_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_2_START_ADDR
+#define pDMA1_2_X_COUNT (volatile unsigned short *)DMA1_2_X_COUNT
+#define pDMA1_2_Y_COUNT (volatile unsigned short *)DMA1_2_Y_COUNT
+#define pDMA1_2_X_MODIFY (volatile signed short *)DMA1_2_X_MODIFY
+#define pDMA1_2_Y_MODIFY (volatile signed short *)DMA1_2_Y_MODIFY
+#define pDMA1_2_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_2_CURR_DESC_PTR
+#define pDMA1_2_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_2_CURR_ADDR
+#define pDMA1_2_CURR_X_COUNT (volatile unsigned short *)DMA1_2_CURR_X_COUNT
+#define pDMA1_2_CURR_Y_COUNT (volatile unsigned short *)DMA1_2_CURR_Y_COUNT
+#define pDMA1_2_IRQ_STATUS (volatile unsigned short *)DMA1_2_IRQ_STATUS
+#define pDMA1_2_PERIPHERAL_MAP (volatile unsigned short *)DMA1_2_PERIPHERAL_MAP
+#define pDMA1_3_CONFIG (volatile unsigned short *)DMA1_3_CONFIG
+#define pDMA1_3_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_3_NEXT_DESC_PTR
+#define pDMA1_3_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_3_START_ADDR
+#define pDMA1_3_X_COUNT (volatile unsigned short *)DMA1_3_X_COUNT
+#define pDMA1_3_Y_COUNT (volatile unsigned short *)DMA1_3_Y_COUNT
+#define pDMA1_3_X_MODIFY (volatile signed short *)DMA1_3_X_MODIFY
+#define pDMA1_3_Y_MODIFY (volatile signed short *)DMA1_3_Y_MODIFY
+#define pDMA1_3_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_3_CURR_DESC_PTR
+#define pDMA1_3_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_3_CURR_ADDR
+#define pDMA1_3_CURR_X_COUNT (volatile unsigned short *)DMA1_3_CURR_X_COUNT
+#define pDMA1_3_CURR_Y_COUNT (volatile unsigned short *)DMA1_3_CURR_Y_COUNT
+#define pDMA1_3_IRQ_STATUS (volatile unsigned short *)DMA1_3_IRQ_STATUS
+#define pDMA1_3_PERIPHERAL_MAP (volatile unsigned short *)DMA1_3_PERIPHERAL_MAP
+#define pDMA1_4_CONFIG (volatile unsigned short *)DMA1_4_CONFIG
+#define pDMA1_4_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_4_NEXT_DESC_PTR
+#define pDMA1_4_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_4_START_ADDR
+#define pDMA1_4_X_COUNT (volatile unsigned short *)DMA1_4_X_COUNT
+#define pDMA1_4_Y_COUNT (volatile unsigned short *)DMA1_4_Y_COUNT
+#define pDMA1_4_X_MODIFY (volatile signed short *)DMA1_4_X_MODIFY
+#define pDMA1_4_Y_MODIFY (volatile signed short *)DMA1_4_Y_MODIFY
+#define pDMA1_4_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_4_CURR_DESC_PTR
+#define pDMA1_4_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_4_CURR_ADDR
+#define pDMA1_4_CURR_X_COUNT (volatile unsigned short *)DMA1_4_CURR_X_COUNT
+#define pDMA1_4_CURR_Y_COUNT (volatile unsigned short *)DMA1_4_CURR_Y_COUNT
+#define pDMA1_4_IRQ_STATUS (volatile unsigned short *)DMA1_4_IRQ_STATUS
+#define pDMA1_4_PERIPHERAL_MAP (volatile unsigned short *)DMA1_4_PERIPHERAL_MAP
+#define pDMA1_5_CONFIG (volatile unsigned short *)DMA1_5_CONFIG
+#define pDMA1_5_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_5_NEXT_DESC_PTR
+#define pDMA1_5_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_5_START_ADDR
+#define pDMA1_5_X_COUNT (volatile unsigned short *)DMA1_5_X_COUNT
+#define pDMA1_5_Y_COUNT (volatile unsigned short *)DMA1_5_Y_COUNT
+#define pDMA1_5_X_MODIFY (volatile signed short *)DMA1_5_X_MODIFY
+#define pDMA1_5_Y_MODIFY (volatile signed short *)DMA1_5_Y_MODIFY
+#define pDMA1_5_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_5_CURR_DESC_PTR
+#define pDMA1_5_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_5_CURR_ADDR
+#define pDMA1_5_CURR_X_COUNT (volatile unsigned short *)DMA1_5_CURR_X_COUNT
+#define pDMA1_5_CURR_Y_COUNT (volatile unsigned short *)DMA1_5_CURR_Y_COUNT
+#define pDMA1_5_IRQ_STATUS (volatile unsigned short *)DMA1_5_IRQ_STATUS
+#define pDMA1_5_PERIPHERAL_MAP (volatile unsigned short *)DMA1_5_PERIPHERAL_MAP
+#define pDMA1_6_CONFIG (volatile unsigned short *)DMA1_6_CONFIG
+#define pDMA1_6_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_6_NEXT_DESC_PTR
+#define pDMA1_6_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_6_START_ADDR
+#define pDMA1_6_X_COUNT (volatile unsigned short *)DMA1_6_X_COUNT
+#define pDMA1_6_Y_COUNT (volatile unsigned short *)DMA1_6_Y_COUNT
+#define pDMA1_6_X_MODIFY (volatile signed short *)DMA1_6_X_MODIFY
+#define pDMA1_6_Y_MODIFY (volatile signed short *)DMA1_6_Y_MODIFY
+#define pDMA1_6_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_6_CURR_DESC_PTR
+#define pDMA1_6_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_6_CURR_ADDR
+#define pDMA1_6_CURR_X_COUNT (volatile unsigned short *)DMA1_6_CURR_X_COUNT
+#define pDMA1_6_CURR_Y_COUNT (volatile unsigned short *)DMA1_6_CURR_Y_COUNT
+#define pDMA1_6_IRQ_STATUS (volatile unsigned short *)DMA1_6_IRQ_STATUS
+#define pDMA1_6_PERIPHERAL_MAP (volatile unsigned short *)DMA1_6_PERIPHERAL_MAP
+#define pDMA1_7_CONFIG (volatile unsigned short *)DMA1_7_CONFIG
+#define pDMA1_7_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_7_NEXT_DESC_PTR
+#define pDMA1_7_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_7_START_ADDR
+#define pDMA1_7_X_COUNT (volatile unsigned short *)DMA1_7_X_COUNT
+#define pDMA1_7_Y_COUNT (volatile unsigned short *)DMA1_7_Y_COUNT
+#define pDMA1_7_X_MODIFY (volatile signed short *)DMA1_7_X_MODIFY
+#define pDMA1_7_Y_MODIFY (volatile signed short *)DMA1_7_Y_MODIFY
+#define pDMA1_7_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_7_CURR_DESC_PTR
+#define pDMA1_7_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_7_CURR_ADDR
+#define pDMA1_7_CURR_X_COUNT (volatile unsigned short *)DMA1_7_CURR_X_COUNT
+#define pDMA1_7_CURR_Y_COUNT (volatile unsigned short *)DMA1_7_CURR_Y_COUNT
+#define pDMA1_7_IRQ_STATUS (volatile unsigned short *)DMA1_7_IRQ_STATUS
+#define pDMA1_7_PERIPHERAL_MAP (volatile unsigned short *)DMA1_7_PERIPHERAL_MAP
+#define pDMA1_8_CONFIG (volatile unsigned short *)DMA1_8_CONFIG
+#define pDMA1_8_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_8_NEXT_DESC_PTR
+#define pDMA1_8_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_8_START_ADDR
+#define pDMA1_8_X_COUNT (volatile unsigned short *)DMA1_8_X_COUNT
+#define pDMA1_8_Y_COUNT (volatile unsigned short *)DMA1_8_Y_COUNT
+#define pDMA1_8_X_MODIFY (volatile signed short *)DMA1_8_X_MODIFY
+#define pDMA1_8_Y_MODIFY (volatile signed short *)DMA1_8_Y_MODIFY
+#define pDMA1_8_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_8_CURR_DESC_PTR
+#define pDMA1_8_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_8_CURR_ADDR
+#define pDMA1_8_CURR_X_COUNT (volatile unsigned short *)DMA1_8_CURR_X_COUNT
+#define pDMA1_8_CURR_Y_COUNT (volatile unsigned short *)DMA1_8_CURR_Y_COUNT
+#define pDMA1_8_IRQ_STATUS (volatile unsigned short *)DMA1_8_IRQ_STATUS
+#define pDMA1_8_PERIPHERAL_MAP (volatile unsigned short *)DMA1_8_PERIPHERAL_MAP
+#define pDMA1_9_CONFIG (volatile unsigned short *)DMA1_9_CONFIG
+#define pDMA1_9_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_9_NEXT_DESC_PTR
+#define pDMA1_9_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_9_START_ADDR
+#define pDMA1_9_X_COUNT (volatile unsigned short *)DMA1_9_X_COUNT
+#define pDMA1_9_Y_COUNT (volatile unsigned short *)DMA1_9_Y_COUNT
+#define pDMA1_9_X_MODIFY (volatile signed short *)DMA1_9_X_MODIFY
+#define pDMA1_9_Y_MODIFY (volatile signed short *)DMA1_9_Y_MODIFY
+#define pDMA1_9_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_9_CURR_DESC_PTR
+#define pDMA1_9_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_9_CURR_ADDR
+#define pDMA1_9_CURR_X_COUNT (volatile unsigned short *)DMA1_9_CURR_X_COUNT
+#define pDMA1_9_CURR_Y_COUNT (volatile unsigned short *)DMA1_9_CURR_Y_COUNT
+#define pDMA1_9_IRQ_STATUS (volatile unsigned short *)DMA1_9_IRQ_STATUS
+#define pDMA1_9_PERIPHERAL_MAP (volatile unsigned short *)DMA1_9_PERIPHERAL_MAP
+#define pDMA1_10_CONFIG (volatile unsigned short *)DMA1_10_CONFIG
+#define pDMA1_10_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_10_NEXT_DESC_PTR
+#define pDMA1_10_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_10_START_ADDR
+#define pDMA1_10_X_COUNT (volatile unsigned short *)DMA1_10_X_COUNT
+#define pDMA1_10_Y_COUNT (volatile unsigned short *)DMA1_10_Y_COUNT
+#define pDMA1_10_X_MODIFY (volatile signed short *)DMA1_10_X_MODIFY
+#define pDMA1_10_Y_MODIFY (volatile signed short *)DMA1_10_Y_MODIFY
+#define pDMA1_10_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_10_CURR_DESC_PTR
+#define pDMA1_10_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_10_CURR_ADDR
+#define pDMA1_10_CURR_X_COUNT (volatile unsigned short *)DMA1_10_CURR_X_COUNT
+#define pDMA1_10_CURR_Y_COUNT (volatile unsigned short *)DMA1_10_CURR_Y_COUNT
+#define pDMA1_10_IRQ_STATUS (volatile unsigned short *)DMA1_10_IRQ_STATUS
+#define pDMA1_10_PERIPHERAL_MAP (volatile unsigned short *)DMA1_10_PERIPHERAL_MAP
+#define pDMA1_11_CONFIG (volatile unsigned short *)DMA1_11_CONFIG
+#define pDMA1_11_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_11_NEXT_DESC_PTR
+#define pDMA1_11_START_ADDR _PTR_TO_VOL_VOID_PTR DMA1_11_START_ADDR
+#define pDMA1_11_X_COUNT (volatile unsigned short *)DMA1_11_X_COUNT
+#define pDMA1_11_Y_COUNT (volatile unsigned short *)DMA1_11_Y_COUNT
+#define pDMA1_11_X_MODIFY (volatile signed short *)DMA1_11_X_MODIFY
+#define pDMA1_11_Y_MODIFY (volatile signed short *)DMA1_11_Y_MODIFY
+#define pDMA1_11_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA1_11_CURR_DESC_PTR
+#define pDMA1_11_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA1_11_CURR_ADDR
+#define pDMA1_11_CURR_X_COUNT (volatile unsigned short *)DMA1_11_CURR_X_COUNT
+#define pDMA1_11_CURR_Y_COUNT (volatile unsigned short *)DMA1_11_CURR_Y_COUNT
+#define pDMA1_11_IRQ_STATUS (volatile unsigned short *)DMA1_11_IRQ_STATUS
+#define pDMA1_11_PERIPHERAL_MAP (volatile unsigned short *)DMA1_11_PERIPHERAL_MAP
+/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
+#define pMDMA1_D0_CONFIG (volatile unsigned short *)MDMA1_D0_CONFIG
+#define pMDMA1_D0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D0_NEXT_DESC_PTR
+#define pMDMA1_D0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D0_START_ADDR
+#define pMDMA1_D0_X_COUNT (volatile unsigned short *)MDMA1_D0_X_COUNT
+#define pMDMA1_D0_Y_COUNT (volatile unsigned short *)MDMA1_D0_Y_COUNT
+#define pMDMA1_D0_X_MODIFY (volatile signed short *)MDMA1_D0_X_MODIFY
+#define pMDMA1_D0_Y_MODIFY (volatile signed short *)MDMA1_D0_Y_MODIFY
+#define pMDMA1_D0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D0_CURR_DESC_PTR
+#define pMDMA1_D0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D0_CURR_ADDR
+#define pMDMA1_D0_CURR_X_COUNT (volatile unsigned short *)MDMA1_D0_CURR_X_COUNT
+#define pMDMA1_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D0_CURR_Y_COUNT
+#define pMDMA1_D0_IRQ_STATUS (volatile unsigned short *)MDMA1_D0_IRQ_STATUS
+#define pMDMA1_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D0_PERIPHERAL_MAP
+#define pMDMA1_S0_CONFIG (volatile unsigned short *)MDMA1_S0_CONFIG
+#define pMDMA1_S0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S0_NEXT_DESC_PTR
+#define pMDMA1_S0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S0_START_ADDR
+#define pMDMA1_S0_X_COUNT (volatile unsigned short *)MDMA1_S0_X_COUNT
+#define pMDMA1_S0_Y_COUNT (volatile unsigned short *)MDMA1_S0_Y_COUNT
+#define pMDMA1_S0_X_MODIFY (volatile signed short *)MDMA1_S0_X_MODIFY
+#define pMDMA1_S0_Y_MODIFY (volatile signed short *)MDMA1_S0_Y_MODIFY
+#define pMDMA1_S0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S0_CURR_DESC_PTR
+#define pMDMA1_S0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S0_CURR_ADDR
+#define pMDMA1_S0_CURR_X_COUNT (volatile unsigned short *)MDMA1_S0_CURR_X_COUNT
+#define pMDMA1_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S0_CURR_Y_COUNT
+#define pMDMA1_S0_IRQ_STATUS (volatile unsigned short *)MDMA1_S0_IRQ_STATUS
+#define pMDMA1_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S0_PERIPHERAL_MAP
+#define pMDMA1_D1_CONFIG (volatile unsigned short *)MDMA1_D1_CONFIG
+#define pMDMA1_D1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D1_NEXT_DESC_PTR
+#define pMDMA1_D1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D1_START_ADDR
+#define pMDMA1_D1_X_COUNT (volatile unsigned short *)MDMA1_D1_X_COUNT
+#define pMDMA1_D1_Y_COUNT (volatile unsigned short *)MDMA1_D1_Y_COUNT
+#define pMDMA1_D1_X_MODIFY (volatile signed short *)MDMA1_D1_X_MODIFY
+#define pMDMA1_D1_Y_MODIFY (volatile signed short *)MDMA1_D1_Y_MODIFY
+#define pMDMA1_D1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_D1_CURR_DESC_PTR
+#define pMDMA1_D1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_D1_CURR_ADDR
+#define pMDMA1_D1_CURR_X_COUNT (volatile unsigned short *)MDMA1_D1_CURR_X_COUNT
+#define pMDMA1_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_D1_CURR_Y_COUNT
+#define pMDMA1_D1_IRQ_STATUS (volatile unsigned short *)MDMA1_D1_IRQ_STATUS
+#define pMDMA1_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_D1_PERIPHERAL_MAP
+#define pMDMA1_S1_CONFIG (volatile unsigned short *)MDMA1_S1_CONFIG
+#define pMDMA1_S1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S1_NEXT_DESC_PTR
+#define pMDMA1_S1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S1_START_ADDR
+#define pMDMA1_S1_X_COUNT (volatile unsigned short *)MDMA1_S1_X_COUNT
+#define pMDMA1_S1_Y_COUNT (volatile unsigned short *)MDMA1_S1_Y_COUNT
+#define pMDMA1_S1_X_MODIFY (volatile signed short *)MDMA1_S1_X_MODIFY
+#define pMDMA1_S1_Y_MODIFY (volatile signed short *)MDMA1_S1_Y_MODIFY
+#define pMDMA1_S1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA1_S1_CURR_DESC_PTR
+#define pMDMA1_S1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA1_S1_CURR_ADDR
+#define pMDMA1_S1_CURR_X_COUNT (volatile unsigned short *)MDMA1_S1_CURR_X_COUNT
+#define pMDMA1_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA1_S1_CURR_Y_COUNT
+#define pMDMA1_S1_IRQ_STATUS (volatile unsigned short *)MDMA1_S1_IRQ_STATUS
+#define pMDMA1_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA1_S1_PERIPHERAL_MAP
+/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
+#define pDMA2_0_CONFIG (volatile unsigned short *)DMA2_0_CONFIG
+#define pDMA2_0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_0_NEXT_DESC_PTR
+#define pDMA2_0_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_0_START_ADDR
+#define pDMA2_0_X_COUNT (volatile unsigned short *)DMA2_0_X_COUNT
+#define pDMA2_0_Y_COUNT (volatile unsigned short *)DMA2_0_Y_COUNT
+#define pDMA2_0_X_MODIFY (volatile signed short *)DMA2_0_X_MODIFY
+#define pDMA2_0_Y_MODIFY (volatile signed short *)DMA2_0_Y_MODIFY
+#define pDMA2_0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_0_CURR_DESC_PTR
+#define pDMA2_0_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_0_CURR_ADDR
+#define pDMA2_0_CURR_X_COUNT (volatile unsigned short *)DMA2_0_CURR_X_COUNT
+#define pDMA2_0_CURR_Y_COUNT (volatile unsigned short *)DMA2_0_CURR_Y_COUNT
+#define pDMA2_0_IRQ_STATUS (volatile unsigned short *)DMA2_0_IRQ_STATUS
+#define pDMA2_0_PERIPHERAL_MAP (volatile unsigned short *)DMA2_0_PERIPHERAL_MAP
+#define pDMA2_1_CONFIG (volatile unsigned short *)DMA2_1_CONFIG
+#define pDMA2_1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_1_NEXT_DESC_PTR
+#define pDMA2_1_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_1_START_ADDR
+#define pDMA2_1_X_COUNT (volatile unsigned short *)DMA2_1_X_COUNT
+#define pDMA2_1_Y_COUNT (volatile unsigned short *)DMA2_1_Y_COUNT
+#define pDMA2_1_X_MODIFY (volatile signed short *)DMA2_1_X_MODIFY
+#define pDMA2_1_Y_MODIFY (volatile signed short *)DMA2_1_Y_MODIFY
+#define pDMA2_1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_1_CURR_DESC_PTR
+#define pDMA2_1_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_1_CURR_ADDR
+#define pDMA2_1_CURR_X_COUNT (volatile unsigned short *)DMA2_1_CURR_X_COUNT
+#define pDMA2_1_CURR_Y_COUNT (volatile unsigned short *)DMA2_1_CURR_Y_COUNT
+#define pDMA2_1_IRQ_STATUS (volatile unsigned short *)DMA2_1_IRQ_STATUS
+#define pDMA2_1_PERIPHERAL_MAP (volatile unsigned short *)DMA2_1_PERIPHERAL_MAP
+#define pDMA2_2_CONFIG (volatile unsigned short *)DMA2_2_CONFIG
+#define pDMA2_2_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_2_NEXT_DESC_PTR
+#define pDMA2_2_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_2_START_ADDR
+#define pDMA2_2_X_COUNT (volatile unsigned short *)DMA2_2_X_COUNT
+#define pDMA2_2_Y_COUNT (volatile unsigned short *)DMA2_2_Y_COUNT
+#define pDMA2_2_X_MODIFY (volatile signed short *)DMA2_2_X_MODIFY
+#define pDMA2_2_Y_MODIFY (volatile signed short *)DMA2_2_Y_MODIFY
+#define pDMA2_2_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_2_CURR_DESC_PTR
+#define pDMA2_2_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_2_CURR_ADDR
+#define pDMA2_2_CURR_X_COUNT (volatile unsigned short *)DMA2_2_CURR_X_COUNT
+#define pDMA2_2_CURR_Y_COUNT (volatile unsigned short *)DMA2_2_CURR_Y_COUNT
+#define pDMA2_2_IRQ_STATUS (volatile unsigned short *)DMA2_2_IRQ_STATUS
+#define pDMA2_2_PERIPHERAL_MAP (volatile unsigned short *)DMA2_2_PERIPHERAL_MAP
+#define pDMA2_3_CONFIG (volatile unsigned short *)DMA2_3_CONFIG
+#define pDMA2_3_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_3_NEXT_DESC_PTR
+#define pDMA2_3_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_3_START_ADDR
+#define pDMA2_3_X_COUNT (volatile unsigned short *)DMA2_3_X_COUNT
+#define pDMA2_3_Y_COUNT (volatile unsigned short *)DMA2_3_Y_COUNT
+#define pDMA2_3_X_MODIFY (volatile signed short *)DMA2_3_X_MODIFY
+#define pDMA2_3_Y_MODIFY (volatile signed short *)DMA2_3_Y_MODIFY
+#define pDMA2_3_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_3_CURR_DESC_PTR
+#define pDMA2_3_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_3_CURR_ADDR
+#define pDMA2_3_CURR_X_COUNT (volatile unsigned short *)DMA2_3_CURR_X_COUNT
+#define pDMA2_3_CURR_Y_COUNT (volatile unsigned short *)DMA2_3_CURR_Y_COUNT
+#define pDMA2_3_IRQ_STATUS (volatile unsigned short *)DMA2_3_IRQ_STATUS
+#define pDMA2_3_PERIPHERAL_MAP (volatile unsigned short *)DMA2_3_PERIPHERAL_MAP
+#define pDMA2_4_CONFIG (volatile unsigned short *)DMA2_4_CONFIG
+#define pDMA2_4_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_4_NEXT_DESC_PTR
+#define pDMA2_4_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_4_START_ADDR
+#define pDMA2_4_X_COUNT (volatile unsigned short *)DMA2_4_X_COUNT
+#define pDMA2_4_Y_COUNT (volatile unsigned short *)DMA2_4_Y_COUNT
+#define pDMA2_4_X_MODIFY (volatile signed short *)DMA2_4_X_MODIFY
+#define pDMA2_4_Y_MODIFY (volatile signed short *)DMA2_4_Y_MODIFY
+#define pDMA2_4_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_4_CURR_DESC_PTR
+#define pDMA2_4_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_4_CURR_ADDR
+#define pDMA2_4_CURR_X_COUNT (volatile unsigned short *)DMA2_4_CURR_X_COUNT
+#define pDMA2_4_CURR_Y_COUNT (volatile unsigned short *)DMA2_4_CURR_Y_COUNT
+#define pDMA2_4_IRQ_STATUS (volatile unsigned short *)DMA2_4_IRQ_STATUS
+#define pDMA2_4_PERIPHERAL_MAP (volatile unsigned short *)DMA2_4_PERIPHERAL_MAP
+#define pDMA2_5_CONFIG (volatile unsigned short *)DMA2_5_CONFIG
+#define pDMA2_5_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_5_NEXT_DESC_PTR
+#define pDMA2_5_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_5_START_ADDR
+#define pDMA2_5_X_COUNT (volatile unsigned short *)DMA2_5_X_COUNT
+#define pDMA2_5_Y_COUNT (volatile unsigned short *)DMA2_5_Y_COUNT
+#define pDMA2_5_X_MODIFY (volatile signed short *)DMA2_5_X_MODIFY
+#define pDMA2_5_Y_MODIFY (volatile signed short *)DMA2_5_Y_MODIFY
+#define pDMA2_5_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_5_CURR_DESC_PTR
+#define pDMA2_5_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_5_CURR_ADDR
+#define pDMA2_5_CURR_X_COUNT (volatile unsigned short *)DMA2_5_CURR_X_COUNT
+#define pDMA2_5_CURR_Y_COUNT (volatile unsigned short *)DMA2_5_CURR_Y_COUNT
+#define pDMA2_5_IRQ_STATUS (volatile unsigned short *)DMA2_5_IRQ_STATUS
+#define pDMA2_5_PERIPHERAL_MAP (volatile unsigned short *)DMA2_5_PERIPHERAL_MAP
+#define pDMA2_6_CONFIG (volatile unsigned short *)DMA2_6_CONFIG
+#define pDMA2_6_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_6_NEXT_DESC_PTR
+#define pDMA2_6_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_6_START_ADDR
+#define pDMA2_6_X_COUNT (volatile unsigned short *)DMA2_6_X_COUNT
+#define pDMA2_6_Y_COUNT (volatile unsigned short *)DMA2_6_Y_COUNT
+#define pDMA2_6_X_MODIFY (volatile signed short *)DMA2_6_X_MODIFY
+#define pDMA2_6_Y_MODIFY (volatile signed short *)DMA2_6_Y_MODIFY
+#define pDMA2_6_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_6_CURR_DESC_PTR
+#define pDMA2_6_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_6_CURR_ADDR
+#define pDMA2_6_CURR_X_COUNT (volatile unsigned short *)DMA2_6_CURR_X_COUNT
+#define pDMA2_6_CURR_Y_COUNT (volatile unsigned short *)DMA2_6_CURR_Y_COUNT
+#define pDMA2_6_IRQ_STATUS (volatile unsigned short *)DMA2_6_IRQ_STATUS
+#define pDMA2_6_PERIPHERAL_MAP (volatile unsigned short *)DMA2_6_PERIPHERAL_MAP
+#define pDMA2_7_CONFIG (volatile unsigned short *)DMA2_7_CONFIG
+#define pDMA2_7_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_7_NEXT_DESC_PTR
+#define pDMA2_7_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_7_START_ADDR
+#define pDMA2_7_X_COUNT (volatile unsigned short *)DMA2_7_X_COUNT
+#define pDMA2_7_Y_COUNT (volatile unsigned short *)DMA2_7_Y_COUNT
+#define pDMA2_7_X_MODIFY (volatile signed short *)DMA2_7_X_MODIFY
+#define pDMA2_7_Y_MODIFY (volatile signed short *)DMA2_7_Y_MODIFY
+#define pDMA2_7_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_7_CURR_DESC_PTR
+#define pDMA2_7_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_7_CURR_ADDR
+#define pDMA2_7_CURR_X_COUNT (volatile unsigned short *)DMA2_7_CURR_X_COUNT
+#define pDMA2_7_CURR_Y_COUNT (volatile unsigned short *)DMA2_7_CURR_Y_COUNT
+#define pDMA2_7_IRQ_STATUS (volatile unsigned short *)DMA2_7_IRQ_STATUS
+#define pDMA2_7_PERIPHERAL_MAP (volatile unsigned short *)DMA2_7_PERIPHERAL_MAP
+#define pDMA2_8_CONFIG (volatile unsigned short *)DMA2_8_CONFIG
+#define pDMA2_8_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_8_NEXT_DESC_PTR
+#define pDMA2_8_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_8_START_ADDR
+#define pDMA2_8_X_COUNT (volatile unsigned short *)DMA2_8_X_COUNT
+#define pDMA2_8_Y_COUNT (volatile unsigned short *)DMA2_8_Y_COUNT
+#define pDMA2_8_X_MODIFY (volatile signed short *)DMA2_8_X_MODIFY
+#define pDMA2_8_Y_MODIFY (volatile signed short *)DMA2_8_Y_MODIFY
+#define pDMA2_8_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_8_CURR_DESC_PTR
+#define pDMA2_8_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_8_CURR_ADDR
+#define pDMA2_8_CURR_X_COUNT (volatile unsigned short *)DMA2_8_CURR_X_COUNT
+#define pDMA2_8_CURR_Y_COUNT (volatile unsigned short *)DMA2_8_CURR_Y_COUNT
+#define pDMA2_8_IRQ_STATUS (volatile unsigned short *)DMA2_8_IRQ_STATUS
+#define pDMA2_8_PERIPHERAL_MAP (volatile unsigned short *)DMA2_8_PERIPHERAL_MAP
+#define pDMA2_9_CONFIG (volatile unsigned short *)DMA2_9_CONFIG
+#define pDMA2_9_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_9_NEXT_DESC_PTR
+#define pDMA2_9_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_9_START_ADDR
+#define pDMA2_9_X_COUNT (volatile unsigned short *)DMA2_9_X_COUNT
+#define pDMA2_9_Y_COUNT (volatile unsigned short *)DMA2_9_Y_COUNT
+#define pDMA2_9_X_MODIFY (volatile signed short *)DMA2_9_X_MODIFY
+#define pDMA2_9_Y_MODIFY (volatile signed short *)DMA2_9_Y_MODIFY
+#define pDMA2_9_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_9_CURR_DESC_PTR
+#define pDMA2_9_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_9_CURR_ADDR
+#define pDMA2_9_CURR_X_COUNT (volatile unsigned short *)DMA2_9_CURR_X_COUNT
+#define pDMA2_9_CURR_Y_COUNT (volatile unsigned short *)DMA2_9_CURR_Y_COUNT
+#define pDMA2_9_IRQ_STATUS (volatile unsigned short *)DMA2_9_IRQ_STATUS
+#define pDMA2_9_PERIPHERAL_MAP (volatile unsigned short *)DMA2_9_PERIPHERAL_MAP
+#define pDMA2_10_CONFIG (volatile unsigned short *)DMA2_10_CONFIG
+#define pDMA2_10_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_10_NEXT_DESC_PTR
+#define pDMA2_10_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_10_START_ADDR
+#define pDMA2_10_X_COUNT (volatile unsigned short *)DMA2_10_X_COUNT
+#define pDMA2_10_Y_COUNT (volatile unsigned short *)DMA2_10_Y_COUNT
+#define pDMA2_10_X_MODIFY (volatile signed short *)DMA2_10_X_MODIFY
+#define pDMA2_10_Y_MODIFY (volatile signed short *)DMA2_10_Y_MODIFY
+#define pDMA2_10_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_10_CURR_DESC_PTR
+#define pDMA2_10_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_10_CURR_ADDR
+#define pDMA2_10_CURR_X_COUNT (volatile unsigned short *)DMA2_10_CURR_X_COUNT
+#define pDMA2_10_CURR_Y_COUNT (volatile unsigned short *)DMA2_10_CURR_Y_COUNT
+#define pDMA2_10_IRQ_STATUS (volatile unsigned short *)DMA2_10_IRQ_STATUS
+#define pDMA2_10_PERIPHERAL_MAP (volatile unsigned short *)DMA2_10_PERIPHERAL_MAP
+#define pDMA2_11_CONFIG (volatile unsigned short *)DMA2_11_CONFIG
+#define pDMA2_11_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_11_NEXT_DESC_PTR
+#define pDMA2_11_START_ADDR _PTR_TO_VOL_VOID_PTR DMA2_11_START_ADDR
+#define pDMA2_11_X_COUNT (volatile unsigned short *)DMA2_11_X_COUNT
+#define pDMA2_11_Y_COUNT (volatile unsigned short *)DMA2_11_Y_COUNT
+#define pDMA2_11_X_MODIFY (volatile signed short *)DMA2_11_X_MODIFY
+#define pDMA2_11_Y_MODIFY (volatile signed short *)DMA2_11_Y_MODIFY
+#define pDMA2_11_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR DMA2_11_CURR_DESC_PTR
+#define pDMA2_11_CURR_ADDR _PTR_TO_VOL_VOID_PTR DMA2_11_CURR_ADDR
+#define pDMA2_11_CURR_X_COUNT (volatile unsigned short *)DMA2_11_CURR_X_COUNT
+#define pDMA2_11_CURR_Y_COUNT (volatile unsigned short *)DMA2_11_CURR_Y_COUNT
+#define pDMA2_11_IRQ_STATUS (volatile unsigned short *)DMA2_11_IRQ_STATUS
+#define pDMA2_11_PERIPHERAL_MAP (volatile unsigned short *)DMA2_11_PERIPHERAL_MAP
+/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
+#define pMDMA2_D0_CONFIG (volatile unsigned short *)MDMA2_D0_CONFIG
+#define pMDMA2_D0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D0_NEXT_DESC_PTR
+#define pMDMA2_D0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D0_START_ADDR
+#define pMDMA2_D0_X_COUNT (volatile unsigned short *)MDMA2_D0_X_COUNT
+#define pMDMA2_D0_Y_COUNT (volatile unsigned short *)MDMA2_D0_Y_COUNT
+#define pMDMA2_D0_X_MODIFY (volatile signed short *)MDMA2_D0_X_MODIFY
+#define pMDMA2_D0_Y_MODIFY (volatile signed short *)MDMA2_D0_Y_MODIFY
+#define pMDMA2_D0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D0_CURR_DESC_PTR
+#define pMDMA2_D0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D0_CURR_ADDR
+#define pMDMA2_D0_CURR_X_COUNT (volatile unsigned short *)MDMA2_D0_CURR_X_COUNT
+#define pMDMA2_D0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D0_CURR_Y_COUNT
+#define pMDMA2_D0_IRQ_STATUS (volatile unsigned short *)MDMA2_D0_IRQ_STATUS
+#define pMDMA2_D0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D0_PERIPHERAL_MAP
+#define pMDMA2_S0_CONFIG (volatile unsigned short *)MDMA2_S0_CONFIG
+#define pMDMA2_S0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S0_NEXT_DESC_PTR
+#define pMDMA2_S0_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S0_START_ADDR
+#define pMDMA2_S0_X_COUNT (volatile unsigned short *)MDMA2_S0_X_COUNT
+#define pMDMA2_S0_Y_COUNT (volatile unsigned short *)MDMA2_S0_Y_COUNT
+#define pMDMA2_S0_X_MODIFY (volatile signed short *)MDMA2_S0_X_MODIFY
+#define pMDMA2_S0_Y_MODIFY (volatile signed short *)MDMA2_S0_Y_MODIFY
+#define pMDMA2_S0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S0_CURR_DESC_PTR
+#define pMDMA2_S0_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S0_CURR_ADDR
+#define pMDMA2_S0_CURR_X_COUNT (volatile unsigned short *)MDMA2_S0_CURR_X_COUNT
+#define pMDMA2_S0_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S0_CURR_Y_COUNT
+#define pMDMA2_S0_IRQ_STATUS (volatile unsigned short *)MDMA2_S0_IRQ_STATUS
+#define pMDMA2_S0_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S0_PERIPHERAL_MAP
+#define pMDMA2_D1_CONFIG (volatile unsigned short *)MDMA2_D1_CONFIG
+#define pMDMA2_D1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D1_NEXT_DESC_PTR
+#define pMDMA2_D1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D1_START_ADDR
+#define pMDMA2_D1_X_COUNT (volatile unsigned short *)MDMA2_D1_X_COUNT
+#define pMDMA2_D1_Y_COUNT (volatile unsigned short *)MDMA2_D1_Y_COUNT
+#define pMDMA2_D1_X_MODIFY (volatile signed short *)MDMA2_D1_X_MODIFY
+#define pMDMA2_D1_Y_MODIFY (volatile signed short *)MDMA2_D1_Y_MODIFY
+#define pMDMA2_D1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_D1_CURR_DESC_PTR
+#define pMDMA2_D1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_D1_CURR_ADDR
+#define pMDMA2_D1_CURR_X_COUNT (volatile unsigned short *)MDMA2_D1_CURR_X_COUNT
+#define pMDMA2_D1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_D1_CURR_Y_COUNT
+#define pMDMA2_D1_IRQ_STATUS (volatile unsigned short *)MDMA2_D1_IRQ_STATUS
+#define pMDMA2_D1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_D1_PERIPHERAL_MAP
+#define pMDMA2_S1_CONFIG (volatile unsigned short *)MDMA2_S1_CONFIG
+#define pMDMA2_S1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S1_NEXT_DESC_PTR
+#define pMDMA2_S1_START_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S1_START_ADDR
+#define pMDMA2_S1_X_COUNT (volatile unsigned short *)MDMA2_S1_X_COUNT
+#define pMDMA2_S1_Y_COUNT (volatile unsigned short *)MDMA2_S1_Y_COUNT
+#define pMDMA2_S1_X_MODIFY (volatile signed short *)MDMA2_S1_X_MODIFY
+#define pMDMA2_S1_Y_MODIFY (volatile signed short *)MDMA2_S1_Y_MODIFY
+#define pMDMA2_S1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR MDMA2_S1_CURR_DESC_PTR
+#define pMDMA2_S1_CURR_ADDR _PTR_TO_VOL_VOID_PTR MDMA2_S1_CURR_ADDR
+#define pMDMA2_S1_CURR_X_COUNT (volatile unsigned short *)MDMA2_S1_CURR_X_COUNT
+#define pMDMA2_S1_CURR_Y_COUNT (volatile unsigned short *)MDMA2_S1_CURR_Y_COUNT
+#define pMDMA2_S1_IRQ_STATUS (volatile unsigned short *)MDMA2_S1_IRQ_STATUS
+#define pMDMA2_S1_PERIPHERAL_MAP (volatile unsigned short *)MDMA2_S1_PERIPHERAL_MAP
+/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
+#define pIMDMA_D0_CONFIG (volatile unsigned short *)IMDMA_D0_CONFIG
+#define pIMDMA_D0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D0_NEXT_DESC_PTR
+#define pIMDMA_D0_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D0_START_ADDR
+#define pIMDMA_D0_X_COUNT (volatile unsigned short *)IMDMA_D0_X_COUNT
+#define pIMDMA_D0_Y_COUNT (volatile unsigned short *)IMDMA_D0_Y_COUNT
+#define pIMDMA_D0_X_MODIFY (volatile signed short *)IMDMA_D0_X_MODIFY
+#define pIMDMA_D0_Y_MODIFY (volatile signed short *)IMDMA_D0_Y_MODIFY
+#define pIMDMA_D0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D0_CURR_DESC_PTR
+#define pIMDMA_D0_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D0_CURR_ADDR
+#define pIMDMA_D0_CURR_X_COUNT (volatile unsigned short *)IMDMA_D0_CURR_X_COUNT
+#define pIMDMA_D0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D0_CURR_Y_COUNT
+#define pIMDMA_D0_IRQ_STATUS (volatile unsigned short *)IMDMA_D0_IRQ_STATUS
+#define pIMDMA_S0_CONFIG (volatile unsigned short *)IMDMA_S0_CONFIG
+#define pIMDMA_S0_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S0_NEXT_DESC_PTR
+#define pIMDMA_S0_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S0_START_ADDR
+#define pIMDMA_S0_X_COUNT (volatile unsigned short *)IMDMA_S0_X_COUNT
+#define pIMDMA_S0_Y_COUNT (volatile unsigned short *)IMDMA_S0_Y_COUNT
+#define pIMDMA_S0_X_MODIFY (volatile signed short *)IMDMA_S0_X_MODIFY
+#define pIMDMA_S0_Y_MODIFY (volatile signed short *)IMDMA_S0_Y_MODIFY
+#define pIMDMA_S0_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S0_CURR_DESC_PTR
+#define pIMDMA_S0_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S0_CURR_ADDR
+#define pIMDMA_S0_CURR_X_COUNT (volatile unsigned short *)IMDMA_S0_CURR_X_COUNT
+#define pIMDMA_S0_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S0_CURR_Y_COUNT
+#define pIMDMA_S0_IRQ_STATUS (volatile unsigned short *)IMDMA_S0_IRQ_STATUS
+#define pIMDMA_D1_CONFIG (volatile unsigned short *)IMDMA_D1_CONFIG
+#define pIMDMA_D1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D1_NEXT_DESC_PTR
+#define pIMDMA_D1_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D1_START_ADDR
+#define pIMDMA_D1_X_COUNT (volatile unsigned short *)IMDMA_D1_X_COUNT
+#define pIMDMA_D1_Y_COUNT (volatile unsigned short *)IMDMA_D1_Y_COUNT
+#define pIMDMA_D1_X_MODIFY (volatile signed short *)IMDMA_D1_X_MODIFY
+#define pIMDMA_D1_Y_MODIFY (volatile signed short *)IMDMA_D1_Y_MODIFY
+#define pIMDMA_D1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_D1_CURR_DESC_PTR
+#define pIMDMA_D1_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_D1_CURR_ADDR
+#define pIMDMA_D1_CURR_X_COUNT (volatile unsigned short *)IMDMA_D1_CURR_X_COUNT
+#define pIMDMA_D1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_D1_CURR_Y_COUNT
+#define pIMDMA_D1_IRQ_STATUS (volatile unsigned short *)IMDMA_D1_IRQ_STATUS
+#define pIMDMA_S1_CONFIG (volatile unsigned short *)IMDMA_S1_CONFIG
+#define pIMDMA_S1_NEXT_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S1_NEXT_DESC_PTR
+#define pIMDMA_S1_START_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S1_START_ADDR
+#define pIMDMA_S1_X_COUNT (volatile unsigned short *)IMDMA_S1_X_COUNT
+#define pIMDMA_S1_Y_COUNT (volatile unsigned short *)IMDMA_S1_Y_COUNT
+#define pIMDMA_S1_X_MODIFY (volatile signed short *)IMDMA_S1_X_MODIFY
+#define pIMDMA_S1_Y_MODIFY (volatile signed short *)IMDMA_S1_Y_MODIFY
+#define pIMDMA_S1_CURR_DESC_PTR _PTR_TO_VOL_VOID_PTR IMDMA_S1_CURR_DESC_PTR
+#define pIMDMA_S1_CURR_ADDR _PTR_TO_VOL_VOID_PTR IMDMA_S1_CURR_ADDR
+#define pIMDMA_S1_CURR_X_COUNT (volatile unsigned short *)IMDMA_S1_CURR_X_COUNT
+#define pIMDMA_S1_CURR_Y_COUNT (volatile unsigned short *)IMDMA_S1_CURR_Y_COUNT
+#define pIMDMA_S1_IRQ_STATUS (volatile unsigned short *)IMDMA_S1_IRQ_STATUS
+
+#endif /* _CDEF_BF561_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * cdef_LPBlackfin.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifndef _CDEF_LPBLACKFIN_H
+#define _CDEF_LPBLACKFIN_H
+
+#if !defined(__ADSPLPBLACKFIN__)
+#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
+#endif
+#include <def_LPBlackfin.h>
+
+#ifndef _PTR_TO_VOL_VOID_PTR
+#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
+#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
+#else
+#define _PTR_TO_VOL_VOID_PTR (volatile void **)
+#endif
+#endif
+
+/* Cache & SRAM Memory */
+#define pSRAM_BASE_ADDRESS (_PTR_TO_VOL_VOID_PTR SRAM_BASE_ADDRESS)
+#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
+#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
+#define pDCPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR DCPLB_FAULT_ADDR)
+#define pDCPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR0)
+#define pDCPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR1)
+#define pDCPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR2)
+#define pDCPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR3)
+#define pDCPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR4)
+#define pDCPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR5)
+#define pDCPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR6)
+#define pDCPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR7)
+#define pDCPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR8)
+#define pDCPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR9)
+#define pDCPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR10)
+#define pDCPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR11)
+#define pDCPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR12)
+#define pDCPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR13)
+#define pDCPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR14)
+#define pDCPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR15)
+#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
+#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
+#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
+#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
+#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
+#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
+#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
+#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
+#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
+#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
+#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
+#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
+#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
+#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
+#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
+#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
+#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
+#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
+#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
+#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
+#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
+#define pICPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR ICPLB_FAULT_ADDR)
+#define pICPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR0)
+#define pICPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR1)
+#define pICPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR2)
+#define pICPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR3)
+#define pICPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR4)
+#define pICPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR5)
+#define pICPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR6)
+#define pICPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR7)
+#define pICPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR8)
+#define pICPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR9)
+#define pICPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR10)
+#define pICPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR11)
+#define pICPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR12)
+#define pICPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR13)
+#define pICPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR14)
+#define pICPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR15)
+#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
+#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
+#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
+#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
+#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
+#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
+#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
+#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
+#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
+#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
+#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
+#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
+#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
+#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
+#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
+#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
+#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
+#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
+#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
+
+/* Event/Interrupt Registers */
+#define pEVT0 (_PTR_TO_VOL_VOID_PTR EVT0)
+#define pEVT1 (_PTR_TO_VOL_VOID_PTR EVT1)
+#define pEVT2 (_PTR_TO_VOL_VOID_PTR EVT2)
+#define pEVT3 (_PTR_TO_VOL_VOID_PTR EVT3)
+#define pEVT4 (_PTR_TO_VOL_VOID_PTR EVT4)
+#define pEVT5 (_PTR_TO_VOL_VOID_PTR EVT5)
+#define pEVT6 (_PTR_TO_VOL_VOID_PTR EVT6)
+#define pEVT7 (_PTR_TO_VOL_VOID_PTR EVT7)
+#define pEVT8 (_PTR_TO_VOL_VOID_PTR EVT8)
+#define pEVT9 (_PTR_TO_VOL_VOID_PTR EVT9)
+#define pEVT10 (_PTR_TO_VOL_VOID_PTR EVT10)
+#define pEVT11 (_PTR_TO_VOL_VOID_PTR EVT11)
+#define pEVT12 (_PTR_TO_VOL_VOID_PTR EVT12)
+#define pEVT13 (_PTR_TO_VOL_VOID_PTR EVT13)
+#define pEVT14 (_PTR_TO_VOL_VOID_PTR EVT14)
+#define pEVT15 (_PTR_TO_VOL_VOID_PTR EVT15)
+#define pIMASK ((volatile unsigned long *)IMASK)
+#define pIPEND ((volatile unsigned long *)IPEND)
+#define pILAT ((volatile unsigned long *)ILAT)
+
+/* Core Timer Registers */
+#define pTCNTL ((volatile unsigned long *)TCNTL)
+#define pTPERIOD ((volatile unsigned long *)TPERIOD)
+#define pTSCALE ((volatile unsigned long *)TSCALE)
+#define pTCOUNT ((volatile unsigned long *)TCOUNT)
+
+/* Debug/MP/Emulation Registers */
+#define pDSPID ((volatile unsigned long *)DSPID)
+#define pDBGCTL ((volatile unsigned long *)DBGCTL)
+#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
+#define pEMUDAT ((volatile unsigned long *)EMUDAT)
+
+/* Trace Buffer Registers */
+#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
+#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
+#define pTBUF (_PTR_TO_VOL_VOID_PTR TBUF)
+
+/* Watch Point Control Registers */
+#define pWPIACTL ((volatile unsigned long *)WPIACTL)
+#define pWPIA0 (_PTR_TO_VOL_VOID_PTR WPIA0)
+#define pWPIA1 (_PTR_TO_VOL_VOID_PTR WPIA1)
+#define pWPIA2 (_PTR_TO_VOL_VOID_PTR WPIA2)
+#define pWPIA3 (_PTR_TO_VOL_VOID_PTR WPIA3)
+#define pWPIA4 (_PTR_TO_VOL_VOID_PTR WPIA4)
+#define pWPIA5 (_PTR_TO_VOL_VOID_PTR WPIA5)
+#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
+#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
+#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
+#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
+#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
+#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
+#define pWPDACTL ((volatile unsigned long *)WPDACTL)
+#define pWPDA0 (_PTR_TO_VOL_VOID_PTR WPDA0)
+#define pWPDA1 (_PTR_TO_VOL_VOID_PTR WPDA1)
+#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
+#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
+#define pWPSTAT ((volatile unsigned long *)WPSTAT)
+
+/* Performance Monitor Registers */
+#define pPFCTL ((volatile unsigned long *)PFCTL)
+#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
+#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
+
+#endif /* _CDEF_LPBLACKFIN_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * cdefblackfin.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifndef _CDEF_BLACKFIN_H
+#define _CDEF_BLACKFIN_H
+
+#if defined(__ADSPLPBLACKFIN__)
+#warning cdefblackfin.h should only be included for 535 compatible chips.
+#endif
+#include <defblackfin.h>
+
+#ifndef _PTR_TO_VOL_VOID_PTR
+#ifndef _USE_LEGACY_CDEF_BEHAVIOUR
+#define _PTR_TO_VOL_VOID_PTR (void * volatile *)
+#else
+#define _PTR_TO_VOL_VOID_PTR (volatile void **)
+#endif
+#endif
+
+/* Cache & SRAM Memory */
+#define pSRAM_BASE_ADDRESS (_PTR_TO_VOL_VOID_PTR SRAM_BASE_ADDRESS)
+#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
+#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
+#define pDCPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR DCPLB_FAULT_ADDR)
+#define pDCPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR0)
+#define pDCPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR1)
+#define pDCPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR2)
+#define pDCPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR3)
+#define pDCPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR4)
+#define pDCPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR5)
+#define pDCPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR6)
+#define pDCPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR7)
+#define pDCPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR8)
+#define pDCPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR9)
+#define pDCPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR10)
+#define pDCPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR11)
+#define pDCPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR12)
+#define pDCPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR13)
+#define pDCPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR14)
+#define pDCPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR DCPLB_ADDR15)
+#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
+#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
+#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
+#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
+#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
+#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
+#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
+#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
+#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
+#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
+#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
+#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
+#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
+#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
+#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
+#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
+#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
+#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
+#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
+#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
+#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
+#define pICPLB_FAULT_ADDR (_PTR_TO_VOL_VOID_PTR ICPLB_FAULT_ADDR)
+#define pICPLB_ADDR0 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR0)
+#define pICPLB_ADDR1 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR1)
+#define pICPLB_ADDR2 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR2)
+#define pICPLB_ADDR3 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR3)
+#define pICPLB_ADDR4 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR4)
+#define pICPLB_ADDR5 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR5)
+#define pICPLB_ADDR6 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR6)
+#define pICPLB_ADDR7 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR7)
+#define pICPLB_ADDR8 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR8)
+#define pICPLB_ADDR9 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR9)
+#define pICPLB_ADDR10 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR10)
+#define pICPLB_ADDR11 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR11)
+#define pICPLB_ADDR12 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR12)
+#define pICPLB_ADDR13 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR13)
+#define pICPLB_ADDR14 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR14)
+#define pICPLB_ADDR15 (_PTR_TO_VOL_VOID_PTR ICPLB_ADDR15)
+#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
+#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
+#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
+#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
+#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
+#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
+#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
+#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
+#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
+#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
+#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
+#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
+#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
+#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
+#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
+#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
+#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
+#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
+#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
+
+/* Event/Interrupt Registers */
+#define pEVT0 (_PTR_TO_VOL_VOID_PTR EVT0)
+#define pEVT1 (_PTR_TO_VOL_VOID_PTR EVT1)
+#define pEVT2 (_PTR_TO_VOL_VOID_PTR EVT2)
+#define pEVT3 (_PTR_TO_VOL_VOID_PTR EVT3)
+#define pEVT4 (_PTR_TO_VOL_VOID_PTR EVT4)
+#define pEVT5 (_PTR_TO_VOL_VOID_PTR EVT5)
+#define pEVT6 (_PTR_TO_VOL_VOID_PTR EVT6)
+#define pEVT7 (_PTR_TO_VOL_VOID_PTR EVT7)
+#define pEVT8 (_PTR_TO_VOL_VOID_PTR EVT8)
+#define pEVT9 (_PTR_TO_VOL_VOID_PTR EVT9)
+#define pEVT10 (_PTR_TO_VOL_VOID_PTR EVT10)
+#define pEVT11 (_PTR_TO_VOL_VOID_PTR EVT11)
+#define pEVT12 (_PTR_TO_VOL_VOID_PTR EVT12)
+#define pEVT13 (_PTR_TO_VOL_VOID_PTR EVT13)
+#define pEVT14 (_PTR_TO_VOL_VOID_PTR EVT14)
+#define pEVT15 (_PTR_TO_VOL_VOID_PTR EVT15)
+#define pIMASK ((volatile unsigned short *)IMASK)
+#define pIPEND ((volatile unsigned short *)IPEND)
+#define pILAT ((volatile unsigned short *)ILAT)
+
+/* Core Timer Registers */
+#define pTCNTL ((volatile unsigned long *)TCNTL)
+#define pTPERIOD ((volatile unsigned long *)TPERIOD)
+#define pTSCALE ((volatile unsigned long *)TSCALE)
+#define pTCOUNT ((volatile unsigned long *)TCOUNT)
+
+/* Debug/MP/Emulation Registers */
+#define pDSPID ((volatile unsigned long *)DSPID)
+#define pDBGCTL ((volatile unsigned long *)DBGCTL)
+#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
+#define pEMUDAT ((volatile unsigned long *)EMUDAT)
+
+/* Trace Buffer Registers */
+#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
+#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
+#define pTBUF (_PTR_TO_VOL_VOID_PTR TBUF)
+
+/* Watch Point Control Registers */
+#define pWPIACTL ((volatile unsigned long *)WPIACTL)
+#define pWPIA0 (_PTR_TO_VOL_VOID_PTR WPIA0)
+#define pWPIA1 (_PTR_TO_VOL_VOID_PTR WPIA1)
+#define pWPIA2 (_PTR_TO_VOL_VOID_PTR WPIA2)
+#define pWPIA3 (_PTR_TO_VOL_VOID_PTR WPIA3)
+#define pWPIA4 (_PTR_TO_VOL_VOID_PTR WPIA4)
+#define pWPIA5 (_PTR_TO_VOL_VOID_PTR WPIA5)
+#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
+#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
+#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
+#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
+#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
+#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
+#define pWPDACTL ((volatile unsigned long *)WPDACTL)
+#define pWPDA0 (_PTR_TO_VOL_VOID_PTR WPDA0)
+#define pWPDA1 (_PTR_TO_VOL_VOID_PTR WPDA1)
+#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
+#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
+#define pWPSTAT ((volatile unsigned long *)WPSTAT)
+
+/* Performance Monitor Registers */
+#define pPFCTL ((volatile unsigned long *)PFCTL)
+#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
+#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
+
+#endif /* _CDEF_BLACKFIN_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * cplb.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/* Defines necessary for cplb initialisation routines. */
+
+#ifndef _CPLB_H
+#define _CPLB_H
+
+#include <sys/platform.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
+#endif /* _MISRA_RULES */
+
+#define CPLB_ENABLE_ICACHE_P 0
+#define CPLB_ENABLE_DCACHE_P 1
+#define CPLB_ENABLE_DCACHE2_P 2
+#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
+#define CPLB_ENABLE_ICPLBS_P 4
+#define CPLB_ENABLE_DCPLBS_P 5
+#define CPLB_SET_DCBS_P 6
+#define CPLB_INVALIDATE_B_P 23
+
+/* ___cplb_ctrl bitmasks */
+#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
+#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
+#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
+#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
+#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
+#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
+#define CPLB_ENABLE_ANY_CPLBS \
+ ( CPLB_ENABLE_CPLBS | CPLB_ENABLE_ICPLBS | CPLB_ENABLE_DCPLBS )
+#define CPLB_SET_DCBS (1<<CPLB_SET_DCBS_P)
+
+/* Bitmasks for dcache_invalidate routine parameters */
+#define CPLB_INVALIDATE_A 0
+#define CPLB_INVALIDATE_B (1<<CPLB_INVALIDATE_B_P)
+
+/* _cplb_mgr return values */
+#define CPLB_RELOADED 0x0000
+#define CPLB_NO_UNLOCKED 0x0001
+#define CPLB_NO_ADDR_MATCH 0x0002
+#define CPLB_PROT_VIOL 0x0003
+#define CPLB_NO_ACTION 0x0004
+
+/* CPLB configurations */
+#define CPLB_DEF_CACHE_WT ( CPLB_L1_CHBL | CPLB_WT )
+#define CPLB_DEF_CACHE_WB ( CPLB_L1_CHBL )
+#define CPLB_CACHE_ENABLED ( CPLB_L1_CHBL | CPLB_DIRTY )
+
+#define CPLB_DEF_CACHE ( CPLB_L1_CHBL | CPLB_WT )
+#define CPLB_ALL_ACCESS ( CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR )
+
+#define CPLB_I_PAGE_MGMT ( CPLB_LOCK | CPLB_VALID )
+#define CPLB_D_PAGE_MGMT ( CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID )
+#define CPLB_DNOCACHE ( CPLB_ALL_ACCESS | CPLB_VALID )
+#define CPLB_DDOCACHE ( CPLB_DNOCACHE | CPLB_DEF_CACHE )
+#define CPLB_INOCACHE ( CPLB_USER_RD | CPLB_VALID )
+#define CPLB_IDOCACHE ( CPLB_INOCACHE | CPLB_L1_CHBL )
+
+#define CPLB_DDOCACHE_WT ( CPLB_DNOCACHE | CPLB_DEF_CACHE_WT )
+#define CPLB_DDOCACHE_WB ( CPLB_DNOCACHE | CPLB_DEF_CACHE_WB )
+
+/* Event type parameter for replacement manager _cplb_mgr */
+#define CPLB_EVT_ICPLB_MISS 0
+#define CPLB_EVT_DCPLB_MISS 1
+#define CPLB_EVT_DCPLB_WRITE 2
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _CPLB_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#pragma once
+#ifndef __NO_BUILTIN
+#pragma system_header /* cplbtab.h */
+#endif
+/************************************************************************
+ *
+ * cplbtab.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/* Define structures for the CPLB tables. */
+
+#ifndef _CPLBTAB_H
+#define _CPLBTAB_H
+
+#include <cplb.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_6_3)
+#pragma diag(suppress:misra_rule_8_12)
+#endif /* _MISRA_RULES */
+
+typedef struct {
+ unsigned long addr;
+ unsigned long flags;
+} cplb_entry;
+
+extern cplb_entry dcplbs_table[];
+extern cplb_entry icplbs_table[];
+extern int __cplb_ctrl;
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+void cplb_init(int _enable_cpls_caches);
+int cplb_mgr(int _is_data_miss, int _enable_cache);
+void cplb_hdr(void);
+void cache_invalidate(int _caches);
+void icache_invalidate(void);
+void dcache_invalidate(int _caches);
+void dcache_invalidate_both(void);
+void flush_data_cache(void);
+void flush_data_buffer(void *_start, void *_end, int _invalidate);
+void disable_data_cache(void);
+void enable_data_cache(int _cplb_ctrl);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _CPLBTAB_H */
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF522_H
+#define _DEF_BF522_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
+
+/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <defBF52x_base.h>
+
+#endif /* _DEF_BF522_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF525_H
+#define _DEF_BF525_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
+
+/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <defBF52x_base.h>
+
+/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
+
+/* USB Control Registers */
+
+#define USB_FADDR 0xffc03800 /* Function address register */
+#define USB_POWER 0xffc03804 /* Power management register */
+#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
+#define USB_FRAME 0xffc03820 /* USB frame number */
+#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
+
+#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
+
+#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+
+/* USB Endpoint 1 Control Registers */
+
+#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+
+/* USB Endpoint 2 Control Registers */
+
+#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+
+/* USB Endpoint 3 Control Registers */
+
+#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+
+/* USB Endpoint 4 Control Registers */
+
+#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+
+/* USB Endpoint 5 Control Registers */
+
+#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+
+/* USB Endpoint 6 Control Registers */
+
+#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+
+/* USB Endpoint 7 Control Registers */
+
+#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+
+#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
+#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
+#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
+#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
+#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
+#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
+#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
+#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
+#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS 0x7f /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
+#define nENABLE_SUSPENDM 0x0
+#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
+#define nSUSPEND_MODE 0x0
+#define RESUME_MODE 0x4 /* DMA Mode */
+#define nRESUME_MODE 0x0
+#define RESET 0x8 /* Reset indicator */
+#define nRESET 0x0
+#define HS_MODE 0x10 /* High Speed mode indicator */
+#define nHS_MODE 0x0
+#define HS_ENABLE 0x20 /* high Speed Enable */
+#define nHS_ENABLE 0x0
+#define SOFT_CONN 0x40 /* Soft connect */
+#define nSOFT_CONN 0x0
+#define ISO_UPDATE 0x80 /* Isochronous update */
+#define nISO_UPDATE 0x0
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
+#define nEP0_TX 0x0
+#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
+#define nEP1_TX 0x0
+#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
+#define nEP2_TX 0x0
+#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
+#define nEP3_TX 0x0
+#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
+#define nEP4_TX 0x0
+#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
+#define nEP5_TX 0x0
+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
+#define nEP6_TX 0x0
+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
+#define nEP7_TX 0x0
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
+#define nEP1_RX 0x0
+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
+#define nEP2_RX 0x0
+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
+#define nEP3_RX 0x0
+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
+#define nEP4_RX 0x0
+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
+#define nEP5_RX 0x0
+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
+#define nEP6_RX 0x0
+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
+#define nEP7_RX 0x0
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
+#define nEP0_TX_E 0x0
+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
+#define nEP1_TX_E 0x0
+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
+#define nEP2_TX_E 0x0
+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
+#define nEP3_TX_E 0x0
+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
+#define nEP4_TX_E 0x0
+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
+#define nEP5_TX_E 0x0
+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
+#define nEP6_TX_E 0x0
+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
+#define nEP7_TX_E 0x0
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
+#define nEP1_RX_E 0x0
+#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
+#define nEP2_RX_E 0x0
+#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
+#define nEP3_RX_E 0x0
+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
+#define nEP4_RX_E 0x0
+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
+#define nEP5_RX_E 0x0
+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
+#define nEP6_RX_E 0x0
+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
+#define nEP7_RX_E 0x0
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B 0x1 /* Suspend indicator */
+#define nSUSPEND_B 0x0
+#define RESUME_B 0x2 /* Resume indicator */
+#define nRESUME_B 0x0
+#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
+#define nRESET_OR_BABLE_B 0x0
+#define SOF_B 0x8 /* Start of frame */
+#define nSOF_B 0x0
+#define CONN_B 0x10 /* Connection indicator */
+#define nCONN_B 0x0
+#define DISCON_B 0x20 /* Disconnect indicator */
+#define nDISCON_B 0x0
+#define SESSION_REQ_B 0x40 /* Session Request */
+#define nSESSION_REQ_B 0x0
+#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
+#define nVBUS_ERROR_B 0x0
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
+#define nSUSPEND_BE 0x0
+#define RESUME_BE 0x2 /* Resume indicator int enable */
+#define nRESUME_BE 0x0
+#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
+#define nRESET_OR_BABLE_BE 0x0
+#define SOF_BE 0x8 /* Start of frame int enable */
+#define nSOF_BE 0x0
+#define CONN_BE 0x10 /* Connection indicator int enable */
+#define nCONN_BE 0x0
+#define DISCON_BE 0x20 /* Disconnect indicator int enable */
+#define nDISCON_BE 0x0
+#define SESSION_REQ_BE 0x40 /* Session Request int enable */
+#define nSESSION_REQ_BE 0x0
+#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
+#define nVBUS_ERROR_BE 0x0
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER 0x7ff /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT 0xf /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA 0x1 /* enables USB module */
+#define nGLOBAL_ENA 0x0
+#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
+#define nEP1_TX_ENA 0x0
+#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
+#define nEP2_TX_ENA 0x0
+#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
+#define nEP3_TX_ENA 0x0
+#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
+#define nEP4_TX_ENA 0x0
+#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
+#define nEP5_TX_ENA 0x0
+#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
+#define nEP6_TX_ENA 0x0
+#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
+#define nEP7_TX_ENA 0x0
+#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
+#define nEP1_RX_ENA 0x0
+#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
+#define nEP2_RX_ENA 0x0
+#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
+#define nEP3_RX_ENA 0x0
+#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
+#define nEP4_RX_ENA 0x0
+#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
+#define nEP5_RX_ENA 0x0
+#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
+#define nEP6_RX_ENA 0x0
+#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
+#define nEP7_RX_ENA 0x0
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION 0x1 /* session indicator */
+#define nSESSION 0x0
+#define HOST_REQ 0x2 /* Host negotiation request */
+#define nHOST_REQ 0x0
+#define HOST_MODE 0x4 /* indicates USBDRC is a host */
+#define nHOST_MODE 0x0
+#define VBUS0 0x8 /* Vbus level indicator[0] */
+#define nVBUS0 0x0
+#define VBUS1 0x10 /* Vbus level indicator[1] */
+#define nVBUS1 0x0
+#define LSDEV 0x20 /* Low-speed indicator */
+#define nLSDEV 0x0
+#define FSDEV 0x40 /* Full or High-speed indicator */
+#define nFSDEV 0x0
+#define B_DEVICE 0x80 /* A' or 'B' device indicator */
+#define nB_DEVICE 0x0
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
+#define nDRIVE_VBUS_ON 0x0
+#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
+#define nDRIVE_VBUS_OFF 0x0
+#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
+#define nCHRG_VBUS_START 0x0
+#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
+#define nCHRG_VBUS_END 0x0
+#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
+#define nDISCHRG_VBUS_START 0x0
+#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
+#define nDISCHRG_VBUS_END 0x0
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
+#define nDRIVE_VBUS_ON_ENA 0x0
+#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
+#define nDRIVE_VBUS_OFF_ENA 0x0
+#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
+#define nCHRG_VBUS_START_ENA 0x0
+#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
+#define nCHRG_VBUS_END_ENA 0x0
+#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
+#define nDISCHRG_VBUS_START_ENA 0x0
+#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
+#define nDISCHRG_VBUS_END_ENA 0x0
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY 0x1 /* data packet receive indicator */
+#define nRXPKTRDY 0x0
+#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
+#define nTXPKTRDY 0x0
+#define STALL_SENT 0x4 /* STALL handshake sent */
+#define nSTALL_SENT 0x0
+#define DATAEND 0x8 /* Data end indicator */
+#define nDATAEND 0x0
+#define SETUPEND 0x10 /* Setup end */
+#define nSETUPEND 0x0
+#define SENDSTALL 0x20 /* Send STALL handshake */
+#define nSENDSTALL 0x0
+#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
+#define nSERVICED_RXPKTRDY 0x0
+#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
+#define nSERVICED_SETUPEND 0x0
+#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
+#define nFLUSHFIFO 0x0
+#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
+#define nSTALL_RECEIVED_H 0x0
+#define SETUPPKT_H 0x8 /* send Setup token host mode */
+#define nSETUPPKT_H 0x0
+#define ERROR_H 0x10 /* timeout error indicator host mode */
+#define nERROR_H 0x0
+#define REQPKT_H 0x20 /* Request an IN transaction host mode */
+#define nREQPKT_H 0x0
+#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
+#define nSTATUSPKT_H 0x0
+#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
+#define nNAK_TIMEOUT_H 0x0
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
+#define nTXPKTRDY_T 0x0
+#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
+#define nFIFO_NOT_EMPTY_T 0x0
+#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
+#define nUNDERRUN_T 0x0
+#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
+#define nFLUSHFIFO_T 0x0
+#define STALL_SEND_T 0x10 /* issue a Stall handshake */
+#define nSTALL_SEND_T 0x0
+#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
+#define nSTALL_SENT_T 0x0
+#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_T 0x0
+#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
+#define nINCOMPTX_T 0x0
+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_T 0x0
+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
+#define nFORCE_DATATOGGLE_T 0x0
+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_T 0x0
+#define ISO_T 0x4000 /* enable Isochronous transfers */
+#define nISO_T 0x0
+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOSET_T 0x0
+#define ERROR_TH 0x4 /* error condition host mode */
+#define nERROR_TH 0x0
+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_TH 0x0
+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
+#define nNAK_TIMEOUT_TH 0x0
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
+#define nRXPKTRDY_R 0x0
+#define FIFO_FULL_R 0x2 /* FIFO not empty */
+#define nFIFO_FULL_R 0x0
+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
+#define nOVERRUN_R 0x0
+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
+#define nDATAERROR_R 0x0
+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
+#define nFLUSHFIFO_R 0x0
+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
+#define nSTALL_SEND_R 0x0
+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
+#define nSTALL_SENT_R 0x0
+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_R 0x0
+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
+#define nINCOMPRX_R 0x0
+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_R 0x0
+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
+#define nDISNYET_R 0x0
+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_R 0x0
+#define ISO_R 0x4000 /* enable Isochronous transfers */
+#define nISO_R 0x0
+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOCLEAR_R 0x0
+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
+#define nERROR_RH 0x0
+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
+#define nREQPKT_RH 0x0
+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_RH 0x0
+#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
+#define nINCOMPRX_RH 0x0
+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
+#define nDMAREQMODE_RH 0x0
+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
+#define nAUTOREQ_RH 0x0
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T 0xf /* EP number */
+#define PROTOCOL_T 0xc /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R 0xf /* EP number */
+#define PROTOCOL_R 0xc /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
+#define nDMA0_INT 0x0
+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
+#define nDMA1_INT 0x0
+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
+#define nDMA2_INT 0x0
+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
+#define nDMA3_INT 0x0
+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
+#define nDMA4_INT 0x0
+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
+#define nDMA5_INT 0x0
+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
+#define nDMA6_INT 0x0
+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
+#define nDMA7_INT 0x0
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA 0x1 /* DMA enable */
+#define nDMA_ENA 0x0
+#define DIRECTION 0x2 /* direction of DMA transfer */
+#define nDIRECTION 0x0
+#define MODE 0x4 /* DMA Bus error */
+#define nMODE 0x0
+#define INT_ENA 0x8 /* Interrupt enable */
+#define nINT_ENA 0x0
+#define EPNUM 0xf0 /* EP number */
+#define BUSERROR 0x100 /* DMA Bus error */
+#define nBUSERROR 0x0
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+#endif /* _DEF_BF525_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF527_H
+#define _DEF_BF527_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
+
+/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
+#include <defBF52x_base.h>
+
+/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
+/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
+
+#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+
+#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+
+#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
+
+#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
+#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
+#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
+#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
+
+/* Listing for IEEE-Supported Count Registers */
+
+#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
+#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
+#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
+#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
+#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
+#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
+#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
+#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
+#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
+#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
+#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
+#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
+#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
+#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
+#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
+#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
+#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
+#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
+#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
+#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
+#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
+#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
+#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
+#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
+#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
+#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
+#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
+#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
+#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
+#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
+#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
+#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
+#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
+#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
+#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
+#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer: All macros are intended to make C and Assembly code more readable.
+** Use these macros carefully, as any that do left shifts for field
+** depositing will result in the lower order bits being destroyed. Any
+** macro that shifts left to properly position the bit-field should be
+** used as part of an OR to initialize a register and NOT as a dynamic
+** modifier UNLESS the lower order bits are saved and ORed back in when
+** the macro is used.
+*************************************************************************************/
+
+/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
+
+/* EMAC_OPMODE Masks */
+
+#define RE 0x00000001 /* Receiver Enable */
+#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
+#define HU 0x00000010 /* Hash Filter Unicast Address */
+#define HM 0x00000020 /* Hash Filter Multicast Address */
+#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
+#define PR 0x00000080 /* Promiscuous Mode Enable */
+#define IFE 0x00000100 /* Inverse Filtering Enable */
+#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
+#define PBF 0x00000400 /* Pass Bad Frames Enable */
+#define PSF 0x00000800 /* Pass Short Frames Enable */
+#define RAF 0x00001000 /* Receive-All Mode */
+#define TE 0x00010000 /* Transmitter Enable */
+#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
+#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
+#define DC 0x00080000 /* Deferral Check */
+#define BOLMT 0x00300000 /* Back-Off Limit */
+#define BOLMT_10 0x00000000 /* 10-bit range */
+#define BOLMT_8 0x00100000 /* 8-bit range */
+#define BOLMT_4 0x00200000 /* 4-bit range */
+#define BOLMT_1 0x00300000 /* 1-bit range */
+#define DRTY 0x00400000 /* Disable TX Retry On Collision */
+#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
+#define RMII 0x01000000 /* RMII/MII* Mode */
+#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
+#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
+#define LB 0x08000000 /* Internal Loopback Enable */
+#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
+
+/* EMAC_STAADD Masks */
+
+#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
+#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
+#define STADISPRE 0x00000004 /* Disable Preamble Generation */
+#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
+#define REGAD 0x000007C0 /* STA Register Address */
+#define PHYAD 0x0000F800 /* PHY Device Address */
+
+#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
+
+/* EMAC_STADAT Mask */
+
+#define STADATA 0x0000FFFF /* Station Management Data */
+
+/* EMAC_FLC Masks */
+
+#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
+#define FLCE 0x00000002 /* Flow Control Enable */
+#define PCF 0x00000004 /* Pass Control Frames */
+#define BKPRSEN 0x00000008 /* Enable Backpressure */
+#define FLCPAUSE 0xFFFF0000 /* Pause Time */
+
+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
+
+/* EMAC_WKUP_CTL Masks */
+
+#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
+#define MPKE 0x00000002 /* Magic Packet Enable */
+#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
+#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
+#define MPKS 0x00000020 /* Magic Packet Received Status */
+#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
+
+/* EMAC_WKUP_FFCMD Masks */
+
+#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
+#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
+#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
+#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
+#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
+#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
+#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
+#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
+
+/* EMAC_WKUP_FFOFF Masks */
+
+#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
+#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
+#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
+#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
+
+#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+/* Set ALL Offsets */
+#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+
+#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
+#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
+
+#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+
+#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
+#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
+
+#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+
+/* EMAC_SYSCTL Masks */
+
+#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
+#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
+#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
+#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
+
+#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
+
+/* EMAC_SYSTAT Masks */
+
+#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
+#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
+#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
+#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
+#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
+#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
+#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
+#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+
+#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
+#define RX_COMP 0x00001000 /* RX Frame Complete */
+#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
+#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
+#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
+#define RX_CRC 0x00010000 /* RX Frame CRC Error */
+#define RX_LEN 0x00020000 /* RX Frame Length Error */
+#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
+#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
+#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
+#define RX_PHY 0x00200000 /* RX Frame PHY Error */
+#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
+#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
+#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
+#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
+#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
+#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
+#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
+#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
+#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
+#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
+
+/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
+
+#define TX_COMP 0x00000001 /* TX Frame Complete */
+#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
+#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
+#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
+#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
+#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
+#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
+#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
+#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
+#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
+#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
+#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
+#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
+#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
+#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
+
+/* EMAC_MMC_CTL Masks */
+#define RSTC 0x00000001 /* Reset All Counters */
+#define CROLL 0x00000002 /* Counter Roll-Over Enable */
+#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
+#define MMCE 0x00000008 /* Enable MMC Counter Operation */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
+#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
+#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
+#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
+#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
+#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
+#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
+#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
+#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
+#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
+#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
+#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
+#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
+#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
+#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
+#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
+#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
+#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
+#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
+#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
+#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
+#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
+#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
+#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
+
+#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
+#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
+#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
+#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
+#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
+#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
+#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
+#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
+#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
+#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
+#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
+#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
+#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
+#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
+#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
+#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
+#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
+#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
+#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
+#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
+#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
+#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
+#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
+
+/* USB Control Registers */
+
+#define USB_FADDR 0xffc03800 /* Function address register */
+#define USB_POWER 0xffc03804 /* Power management register */
+#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
+#define USB_FRAME 0xffc03820 /* USB frame number */
+#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
+
+#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
+
+#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+
+/* USB Endpoint 1 Control Registers */
+
+#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+
+/* USB Endpoint 2 Control Registers */
+
+#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+
+/* USB Endpoint 3 Control Registers */
+
+#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+
+/* USB Endpoint 4 Control Registers */
+
+#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+
+/* USB Endpoint 5 Control Registers */
+
+#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
+
+/* USB Endpoint 6 Control Registers */
+
+#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+
+/* USB Endpoint 7 Control Registers */
+
+#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+
+#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
+#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
+#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
+#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
+#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
+#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
+#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
+#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
+#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS 0x7f /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
+#define nENABLE_SUSPENDM 0x0
+#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
+#define nSUSPEND_MODE 0x0
+#define RESUME_MODE 0x4 /* DMA Mode */
+#define nRESUME_MODE 0x0
+#define RESET 0x8 /* Reset indicator */
+#define nRESET 0x0
+#define HS_MODE 0x10 /* High Speed mode indicator */
+#define nHS_MODE 0x0
+#define HS_ENABLE 0x20 /* high Speed Enable */
+#define nHS_ENABLE 0x0
+#define SOFT_CONN 0x40 /* Soft connect */
+#define nSOFT_CONN 0x0
+#define ISO_UPDATE 0x80 /* Isochronous update */
+#define nISO_UPDATE 0x0
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
+#define nEP0_TX 0x0
+#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
+#define nEP1_TX 0x0
+#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
+#define nEP2_TX 0x0
+#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
+#define nEP3_TX 0x0
+#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
+#define nEP4_TX 0x0
+#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
+#define nEP5_TX 0x0
+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
+#define nEP6_TX 0x0
+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
+#define nEP7_TX 0x0
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
+#define nEP1_RX 0x0
+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
+#define nEP2_RX 0x0
+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
+#define nEP3_RX 0x0
+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
+#define nEP4_RX 0x0
+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
+#define nEP5_RX 0x0
+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
+#define nEP6_RX 0x0
+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
+#define nEP7_RX 0x0
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
+#define nEP0_TX_E 0x0
+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
+#define nEP1_TX_E 0x0
+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
+#define nEP2_TX_E 0x0
+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
+#define nEP3_TX_E 0x0
+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
+#define nEP4_TX_E 0x0
+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
+#define nEP5_TX_E 0x0
+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
+#define nEP6_TX_E 0x0
+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
+#define nEP7_TX_E 0x0
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
+#define nEP1_RX_E 0x0
+#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
+#define nEP2_RX_E 0x0
+#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
+#define nEP3_RX_E 0x0
+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
+#define nEP4_RX_E 0x0
+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
+#define nEP5_RX_E 0x0
+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
+#define nEP6_RX_E 0x0
+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
+#define nEP7_RX_E 0x0
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B 0x1 /* Suspend indicator */
+#define nSUSPEND_B 0x0
+#define RESUME_B 0x2 /* Resume indicator */
+#define nRESUME_B 0x0
+#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
+#define nRESET_OR_BABLE_B 0x0
+#define SOF_B 0x8 /* Start of frame */
+#define nSOF_B 0x0
+#define CONN_B 0x10 /* Connection indicator */
+#define nCONN_B 0x0
+#define DISCON_B 0x20 /* Disconnect indicator */
+#define nDISCON_B 0x0
+#define SESSION_REQ_B 0x40 /* Session Request */
+#define nSESSION_REQ_B 0x0
+#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
+#define nVBUS_ERROR_B 0x0
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
+#define nSUSPEND_BE 0x0
+#define RESUME_BE 0x2 /* Resume indicator int enable */
+#define nRESUME_BE 0x0
+#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
+#define nRESET_OR_BABLE_BE 0x0
+#define SOF_BE 0x8 /* Start of frame int enable */
+#define nSOF_BE 0x0
+#define CONN_BE 0x10 /* Connection indicator int enable */
+#define nCONN_BE 0x0
+#define DISCON_BE 0x20 /* Disconnect indicator int enable */
+#define nDISCON_BE 0x0
+#define SESSION_REQ_BE 0x40 /* Session Request int enable */
+#define nSESSION_REQ_BE 0x0
+#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
+#define nVBUS_ERROR_BE 0x0
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER 0x7ff /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT 0xf /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA 0x1 /* enables USB module */
+#define nGLOBAL_ENA 0x0
+#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
+#define nEP1_TX_ENA 0x0
+#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
+#define nEP2_TX_ENA 0x0
+#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
+#define nEP3_TX_ENA 0x0
+#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
+#define nEP4_TX_ENA 0x0
+#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
+#define nEP5_TX_ENA 0x0
+#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
+#define nEP6_TX_ENA 0x0
+#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
+#define nEP7_TX_ENA 0x0
+#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
+#define nEP1_RX_ENA 0x0
+#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
+#define nEP2_RX_ENA 0x0
+#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
+#define nEP3_RX_ENA 0x0
+#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
+#define nEP4_RX_ENA 0x0
+#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
+#define nEP5_RX_ENA 0x0
+#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
+#define nEP6_RX_ENA 0x0
+#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
+#define nEP7_RX_ENA 0x0
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION 0x1 /* session indicator */
+#define nSESSION 0x0
+#define HOST_REQ 0x2 /* Host negotiation request */
+#define nHOST_REQ 0x0
+#define HOST_MODE 0x4 /* indicates USBDRC is a host */
+#define nHOST_MODE 0x0
+#define VBUS0 0x8 /* Vbus level indicator[0] */
+#define nVBUS0 0x0
+#define VBUS1 0x10 /* Vbus level indicator[1] */
+#define nVBUS1 0x0
+#define LSDEV 0x20 /* Low-speed indicator */
+#define nLSDEV 0x0
+#define FSDEV 0x40 /* Full or High-speed indicator */
+#define nFSDEV 0x0
+#define B_DEVICE 0x80 /* A' or 'B' device indicator */
+#define nB_DEVICE 0x0
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
+#define nDRIVE_VBUS_ON 0x0
+#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
+#define nDRIVE_VBUS_OFF 0x0
+#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
+#define nCHRG_VBUS_START 0x0
+#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
+#define nCHRG_VBUS_END 0x0
+#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
+#define nDISCHRG_VBUS_START 0x0
+#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
+#define nDISCHRG_VBUS_END 0x0
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
+#define nDRIVE_VBUS_ON_ENA 0x0
+#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
+#define nDRIVE_VBUS_OFF_ENA 0x0
+#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
+#define nCHRG_VBUS_START_ENA 0x0
+#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
+#define nCHRG_VBUS_END_ENA 0x0
+#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
+#define nDISCHRG_VBUS_START_ENA 0x0
+#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
+#define nDISCHRG_VBUS_END_ENA 0x0
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY 0x1 /* data packet receive indicator */
+#define nRXPKTRDY 0x0
+#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
+#define nTXPKTRDY 0x0
+#define STALL_SENT 0x4 /* STALL handshake sent */
+#define nSTALL_SENT 0x0
+#define DATAEND 0x8 /* Data end indicator */
+#define nDATAEND 0x0
+#define SETUPEND 0x10 /* Setup end */
+#define nSETUPEND 0x0
+#define SENDSTALL 0x20 /* Send STALL handshake */
+#define nSENDSTALL 0x0
+#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
+#define nSERVICED_RXPKTRDY 0x0
+#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
+#define nSERVICED_SETUPEND 0x0
+#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
+#define nFLUSHFIFO 0x0
+#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
+#define nSTALL_RECEIVED_H 0x0
+#define SETUPPKT_H 0x8 /* send Setup token host mode */
+#define nSETUPPKT_H 0x0
+#define ERROR_H 0x10 /* timeout error indicator host mode */
+#define nERROR_H 0x0
+#define REQPKT_H 0x20 /* Request an IN transaction host mode */
+#define nREQPKT_H 0x0
+#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
+#define nSTATUSPKT_H 0x0
+#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
+#define nNAK_TIMEOUT_H 0x0
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
+#define nTXPKTRDY_T 0x0
+#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
+#define nFIFO_NOT_EMPTY_T 0x0
+#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
+#define nUNDERRUN_T 0x0
+#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
+#define nFLUSHFIFO_T 0x0
+#define STALL_SEND_T 0x10 /* issue a Stall handshake */
+#define nSTALL_SEND_T 0x0
+#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
+#define nSTALL_SENT_T 0x0
+#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_T 0x0
+#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
+#define nINCOMPTX_T 0x0
+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_T 0x0
+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
+#define nFORCE_DATATOGGLE_T 0x0
+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_T 0x0
+#define ISO_T 0x4000 /* enable Isochronous transfers */
+#define nISO_T 0x0
+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOSET_T 0x0
+#define ERROR_TH 0x4 /* error condition host mode */
+#define nERROR_TH 0x0
+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_TH 0x0
+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
+#define nNAK_TIMEOUT_TH 0x0
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
+#define nRXPKTRDY_R 0x0
+#define FIFO_FULL_R 0x2 /* FIFO not empty */
+#define nFIFO_FULL_R 0x0
+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
+#define nOVERRUN_R 0x0
+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
+#define nDATAERROR_R 0x0
+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
+#define nFLUSHFIFO_R 0x0
+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
+#define nSTALL_SEND_R 0x0
+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
+#define nSTALL_SENT_R 0x0
+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_R 0x0
+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
+#define nINCOMPRX_R 0x0
+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_R 0x0
+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
+#define nDISNYET_R 0x0
+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_R 0x0
+#define ISO_R 0x4000 /* enable Isochronous transfers */
+#define nISO_R 0x0
+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOCLEAR_R 0x0
+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
+#define nERROR_RH 0x0
+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
+#define nREQPKT_RH 0x0
+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_RH 0x0
+#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
+#define nINCOMPRX_RH 0x0
+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
+#define nDMAREQMODE_RH 0x0
+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
+#define nAUTOREQ_RH 0x0
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T 0xf /* EP number */
+#define PROTOCOL_T 0xc /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R 0xf /* EP number */
+#define PROTOCOL_R 0xc /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
+#define nDMA0_INT 0x0
+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
+#define nDMA1_INT 0x0
+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
+#define nDMA2_INT 0x0
+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
+#define nDMA3_INT 0x0
+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
+#define nDMA4_INT 0x0
+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
+#define nDMA5_INT 0x0
+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
+#define nDMA6_INT 0x0
+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
+#define nDMA7_INT 0x0
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA 0x1 /* DMA enable */
+#define nDMA_ENA 0x0
+#define DIRECTION 0x2 /* direction of DMA transfer */
+#define nDIRECTION 0x0
+#define MODE 0x4 /* DMA Bus error */
+#define nMODE 0x0
+#define INT_ENA 0x8 /* Interrupt enable */
+#define nINT_ENA 0x0
+#define EPNUM 0xf0 /* EP number */
+#define BUSERROR 0x100 /* DMA Bus error */
+#define nBUSERROR 0x0
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+#endif /* _DEF_BF527_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF52x_base.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the registers common to the ADSP-BF52x peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _DEF_BF52X_H
+#define _DEF_BF52X_H
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+
+/* ************************************************************** */
+/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
+/* ************************************************************** */
+
+/* ==== begin from defBF534.h ==== */
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL 0xFFC00000 /* PLL Control Register */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT 0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID 0xFFC00014 /* Device ID Register */
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST 0xFFC00100 /* Software Reset Register */
+#define SYSCR 0xFFC00104 /* System Configuration Register */
+#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
+
+#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SIC_IMASK SIC_IMASK0
+
+#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
+
+#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SIC_ISR SIC_ISR0
+
+#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
+/* legacy register name (below) provided for backwards code compatibility */
+#define SIC_IWR SIC_IWR0
+
+/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
+#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
+#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
+#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
+#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
+#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
+#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
+#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
+
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT 0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
+#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART0_THR 0xFFC00400 /* Transmit Holding register */
+#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
+#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
+#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define UART0_LCR 0xFFC0040C /* Line Control Register */
+#define UART0_MCR 0xFFC00410 /* Modem Control Register */
+#define UART0_LSR 0xFFC00414 /* Line Status Register */
+#define UART0_MSR 0xFFC00418 /* Modem Status Register */
+#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
+#define UART0_GCTL 0xFFC00424 /* Global Control Register */
+
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL 0xFFC00500 /* SPI Control Register */
+#define SPI_FLG 0xFFC00504 /* SPI Flag register */
+#define SPI_STAT 0xFFC00508 /* SPI Status register */
+#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
+#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
+#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
+
+
+/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
+
+#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
+
+#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
+
+#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
+
+#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
+
+#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
+
+#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
+
+#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
+#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
+#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
+#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
+#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
+#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
+#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
+#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
+#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
+#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
+#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
+#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
+#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
+#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
+#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
+#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
+#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
+#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
+
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
+
+
+/* DMA Traffic Control Registers */
+#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
+#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+
+#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+
+#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+
+#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+
+#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+
+#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+
+#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+
+#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+
+#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+
+#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+
+#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+
+#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
+
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
+
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
+
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
+
+
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
+#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
+#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
+#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
+#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
+#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
+#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
+#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
+#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
+#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
+#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
+#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
+#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
+#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
+#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
+#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
+#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
+#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
+#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
+#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
+#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
+#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
+#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
+#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
+#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
+#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
+#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
+#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
+#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
+#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
+#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
+#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
+#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
+#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
+#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
+#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
+#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
+#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
+#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
+#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
+#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
+#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
+#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
+
+
+/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
+#define UART1_THR 0xFFC02000 /* Transmit Holding register */
+#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
+#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
+#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
+#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
+#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
+#define UART1_LCR 0xFFC0200C /* Line Control Register */
+#define UART1_MCR 0xFFC02010 /* Modem Control Register */
+#define UART1_LSR 0xFFC02014 /* Line Status Register */
+#define UART1_MSR 0xFFC02018 /* Modem Status Register */
+#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
+#define UART1_GCTL 0xFFC02024 /* Global Control Register */
+
+
+/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
+
+/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
+#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
+#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
+#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
+
+
+/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
+#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
+
+#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
+
+/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
+#define PORTF_MUX 0xFFC03210 /* Port F mux control */
+#define PORTG_MUX 0xFFC03214 /* Port G mux control */
+#define PORTH_MUX 0xFFC03218 /* Port H mux control */
+#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
+#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
+#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
+#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
+#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
+#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
+#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
+#define NONGPIO_DRIVE 0xFFC03280 /* Drive strength control for non-GPIO pins */
+#define NONGPIO_SLEW 0xFFC03284 /* Slew control for non-GPIO pins */
+#define NONGPIO_HYSTERESIS 0xFFC03288 /* Schmitt trigger control for non-GPIO pins */
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer: All macros are intended to make C and Assembly code more readable.
+** Use these macros carefully, as any that do left shifts for field
+** depositing will result in the lower order bits being destroyed. Any
+** macro that shifts left to properly position the bit-field should be
+** used as part of an OR to initialize a register and NOT as a dynamic
+** modifier UNLESS the lower order bits are saved and ORed back in when
+** the macro is used.
+*************************************************************************************/
+/*
+** ********************* PLL AND RESET MASKS ****************************************/
+/* PLL_CTL Masks */
+#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF 0x0002 /* PLL Not Powered */
+#define STOPCK 0x0008 /* Core Clock Off */
+#define PDWN 0x0020 /* Enter Deep Sleep Mode */
+#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
+#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
+#define BYPASS 0x0100 /* Bypass the PLL */
+#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
+/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
+#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+
+/* PLL_DIV Masks */
+#define SSEL 0x000F /* System Select */
+#define CSEL 0x0030 /* Core Select */
+#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
+#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
+#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
+#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
+/* PLL_DIV Macros */
+#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+
+/* VR_CTL Masks */
+#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
+
+#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
+#define VLEV_085 0x0040 /* VLEV = 0.85 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_090 0x0050 /* VLEV = 0.90 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_095 0x0060 /* VLEV = 0.95 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_100 0x0070 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_105 0x0080 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_110 0x0090 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_115 0x00A0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_120 0x00B0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
+
+#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
+#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
+#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
+#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
+#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
+#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
+#define FULL_ON 0x0002 /* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
+#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
+
+/* SWRST Masks */
+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks */
+#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
+#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+
+/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */
+#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
+
+#define IRQ_DMA_ERR0 0x00000002 /* Error Interrupt (DMA error 0 interrupt (generic)) */
+#define IRQ_DMAR0 0x00000004 /* DMAR0 Block (DMAR0 block interrupt) */
+#define IRQ_DMAR1 0x00000008 /* DMAR1 Block (DMAR1 block interrupt) */
+#define IRQ_DMAR0_ERR 0x00000010 /* Error Interrupt (DMAR0 overflow error interrupt) */
+#define IRQ_DMAR1_ERR 0x00000020 /* Error Interrupt (DMAR1 overflow error interrupt) */
+#define IRQ_PPI_ERR 0x00000040 /* Error Interrupt (PPI error interrupt) */
+#define IRQ_MAC_ERR 0x00000080 /* Error Interrupt (MAC status interrupt) */
+#define IRQ_SPORT0_ERR 0x00000100 /* Error Interrupt (SPORT0 status interrupt) */
+#define IRQ_SPORT1_ERR 0x00000200 /* Error Interrupt (SPORT1 status interrupt) */
+#define IRQ_UART0_ERR 0x00001000 /* Error Interrupt (UART0 status interrupt) */
+#define IRQ_UART1_ERR 0x00002000 /* Error Interrupt (UART1 status interrupt) */
+#define IRQ_RTC 0x00004000 /* Real Time Clock Interrupt */
+#define IRQ_DMA0 0x00008000 /* DMA channel 0 (PPI/NFC) Interrupt */
+#define IRQ_DMA3 0x00010000 /* DMA Channel 3 (SPORT0 RX) Interrupt */
+#define IRQ_DMA4 0x00020000 /* DMA Channel 4 (SPORT0 TX) Interrupt */
+#define IRQ_DMA5 0x00040000 /* DMA Channel 5 (SPORT1 RX) Interrupt */
+#define IRQ_DMA6 0x00080000 /* DMA Channel 6 (SPORT1 TX) Interrupt */
+#define IRQ_TWI 0x00100000 /* TWI Interrupt */
+#define IRQ_DMA7 0x00200000 /* DMA Channel 7 (SPI) Interrupt */
+#define IRQ_DMA8 0x00400000 /* DMA Channel 8 (UART0 RX) Interrupt */
+#define IRQ_DMA9 0x00800000 /* DMA Channel 9 (UART0 TX) Interrupt */
+#define IRQ_DMA10 0x01000000 /* DMA Channel 10 (UART1 RX) Interrupt */
+#define IRQ_DMA11 0x02000000 /* DMA Channel 11 (UART1 TX) Interrupt */
+#define IRQ_OTP 0x04000000 /* OTP Interrupt */
+#define IRQ_CNT 0x08000000 /* GP Counter Interrupt */
+#define IRQ_DMA1 0x10000000 /* DMA Channel 1 (EthernetRX/HOSTDP) Interrupt */
+#define IRQ_PFA_PORTH 0x20000000 /* PF Port H Interrupt A */
+#define IRQ_DMA2 0x40000000 /* DMA Channel 2 (Ethernet TX/NFC) Interrupt */
+#define IRQ_PFB_PORTH 0x80000000 /* PF Port H Interrupt B */
+
+/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
+
+#define IRQ_TIMER0 0x00000001 /* Timer 0 Interrupt */
+#define IRQ_TIMER1 0x00000002 /* Timer 1 Interrupt */
+#define IRQ_TIMER2 0x00000004 /* Timer 2 Interrupt */
+#define IRQ_TIMER3 0x00000008 /* Timer 3 Interrupt */
+#define IRQ_TIMER4 0x00000010 /* Timer 4 Interrupt */
+#define IRQ_TIMER5 0x00000020 /* Timer 5 Interrupt */
+#define IRQ_TIMER6 0x00000040 /* Timer 6 Interrupt */
+#define IRQ_TIMER7 0x00000080 /* Timer 7 Interrupt */
+#define IRQ_PFA_PORTG 0x00000100 /* PF Port G Interrupt A */
+#define IRQ_PFB_PORTG 0x00000200 /* PF Port G Interrupt B */
+#define IRQ_DMA12 0x00000400 /* DMA Channels 12 (MDMA0 Destination) TX Interrupt */
+#define IRQ_DMA13 0x00000400 /* DMA Channels 13 (MDMA0 Source) RX Interrupt */
+#define IRQ_DMA14 0x00000800 /* DMA Channels 14 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA15 0x00000800 /* DMA Channels 15 (MDMA1 Source) RX Interrupt */
+#define IRQ_WDOG 0x00001000 /* Software Watchdog Timer Interrupt */
+#define IRQ_PFA_PORTF 0x00002000 /* PF Port F Interrupt A */
+#define IRQ_PFB_PORTF 0x00004000 /* PF Port F Interrupt B */
+#define IRQ_SPI_ERR 0x00008000 /* Error Interrupt (SPI status interrupt) */
+#define IRQ_NAND_ERR 0x00010000 /* NAND error interrupt */
+#define IRQ_HOSTDP_STATUS 0x00020000 /* HOSTDP status interrupt */
+#define IRQ_HOSTRD_DONE 0x00040000 /* Host Read Done interrupt */
+#define IRQ_USB_EINT 0x00080000 /* USB EINT interrupt */
+#define IRQ_USB_INT0 0x00100000 /* USB INT0 interrupt */
+#define IRQ_USB_INT1 0x00200000 /* USB INT1 interrupt */
+#define IRQ_USB_INT2 0x00400000 /* USB INT1 interrupt */
+#define IRQ_USB_DMAINT 0x00800000 /* USB DMAINT interrupt */
+
+
+/* SIC_IAR0 Macros */
+#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Macros */
+#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #13 assigned IVG #x */
+
+/* SIC_IAR2 Macros */
+#define P14_IVG(x) (((x)&0xF)-7) /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #15 assigned IVG #x */
+#define P16_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #21 assigned IVG #x */
+
+/* SIC_IAR3 Macros */
+#define P22_IVG(x) (((x)&0xF)-7) /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #23 assigned IVG #x */
+#define P24_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #29 assigned IVG #x */
+
+/* SIC_IAR4 Macros */
+#define P30_IVG(x) (((x)&0xF)-7) /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #31 assigned IVG #x */
+#define P32_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #32 assigned IVG #x */
+#define P33_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #33 assigned IVG #x */
+#define P34_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #34 assigned IVG #x */
+#define P35_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #35 assigned IVG #x */
+#define P36_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #36 assigned IVG #x */
+#define P37_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #37 assigned IVG #x */
+
+/* SIC_IAR5 Macros */
+#define P38_IVG(x) (((x)&0xF)-7) /* Peripheral #38assigned IVG #x */
+#define P39_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #39assigned IVG #x */
+#define P40_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #40 assigned IVG #x */
+#define P41_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #41 assigned IVG #x */
+#define P42_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #42 assigned IVG #x */
+#define P43_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #43 assigned IVG #x */
+#define P44_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #44 assigned IVG #x */
+#define P45_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #45 assigned IVG #x */
+
+/* SIC_IAR6 Macros */
+#define P46_IVG(x) (((x)&0xF)-7) /* Peripheral #46 assigned IVG #x */
+#define P47_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #47 assigned IVG #x */
+#define P48_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #48 assigned IVG #x */
+#define P49_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #49 assigned IVG #x */
+#define P50_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #50 assigned IVG #x */
+#define P51_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #51 assigned IVG #x */
+#define P52_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #52 assigned IVG #x */
+#define P53_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #53 assigned IVG #x */
+
+/* SIC_IAR7 Macros */
+#define P54_IVG(x) (((x)&0xF)-7) /* Peripheral #54 assigned IVG #x */
+#define P55_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #55 assigned IVG #x */
+#define P56_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #56 assigned IVG #x */
+#define P57_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #57 assigned IVG #x */
+#define P58_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #58 assigned IVG #x */
+#define P59_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #59 assigned IVG #x */
+#define P60_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #60 assigned IVG #x */
+#define P61_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #61 assigned IVG #x */
+
+/* SIC_IMASK0 Masks */
+#define SIC_UNMASK0_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK0_ALL 0xFFFFF3FF /* Mask all peripheral interrupts */
+#define SIC_MASK0(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK0(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IMASK1 Masks */
+#define SIC_UNMASK1_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK1_ALL 0xFFFFFF /* Mask all peripheral interrupts */
+#define SIC_MASK1(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK1(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+
+
+/* SIC_IWR0 Masks */
+#define IWR0_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR0_ENABLE_ALL 0xFFFFF3FF /* Wakeup Enable all peripherals */
+#define IWR0_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
+#define IWR0_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+
+/* SIC_IWR1 Masks */
+#define IWR1_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR1_ENABLE_ALL 0xFFFFFF /* Wakeup Enable all peripherals */
+#define IWR1_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
+#define IWR1_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+
+#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#define WDEV_RESET 0x0000 /* generate reset event on roll over */
+#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
+#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
+#define WDEV_NONE 0x0006 /* no event on roll over */
+#define WDEN 0x0FF0 /* enable watchdog */
+#define WDDIS 0x0AD0 /* disable watchdog */
+#define WDRO 0x8000 /* watchdog rolled over latch */
+
+/* depreciated WDOG_CTL Register Masks for legacy code */
+
+
+#define ICTL WDEV
+#define ENABLE_RESET WDEV_RESET
+#define WDOG_RESET WDEV_RESET
+#define ENABLE_NMI WDEV_NMI
+#define WDOG_NMI WDEV_NMI
+#define ENABLE_GPI WDEV_GPI
+#define WDOG_GPI WDEV_GPI
+#define DISABLE_EVT WDEV_NONE
+#define WDOG_NONE WDEV_NONE
+
+#define TMR_EN WDEN
+#define TMR_DIS WDDIS
+#define TRO WDRO
+#define ICTL_P0 0x01
+ #define ICTL_P1 0x02
+#define TRO_P 0x0F
+
+
+
+/* *************** REAL TIME CLOCK MASKS **************************/
+/* RTC_STAT and RTC_ALARM Masks */
+#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
+#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
+#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
+#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
+
+/* RTC_ALARM Macro z=day y=hr x=min w=sec */
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+
+/* RTC_ICTL and RTC_ISTAT Masks */
+#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
+#define ALARM 0x0002 /* Alarm Interrupt Enable */
+#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
+#define MINUTE 0x0008 /* Minutes Interrupt Enable */
+#define HOUR 0x0010 /* Hours Interrupt Enable */
+#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
+#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WRITE_PENDING 0x4000 /* Write Pending Status */
+#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
+
+/* RTC_FAST / RTC_PREN Mask */
+#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
+
+
+/* ************** UART CONTROLLER MASKS *************************/
+/* UARTx_LCR Masks */
+#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#define STB 0x04 /* Stop Bits */
+#define PEN 0x08 /* Parity Enable */
+#define EPS 0x10 /* Even Parity Select */
+#define STP 0x20 /* Stick Parity */
+#define SB 0x40 /* Set Break */
+#define DLAB 0x80 /* Divisor Latch Access */
+
+/* UARTx_MCR Mask */
+#define LOOP_ENA 0x10 /* Loopback Mode Enable */
+#define LOOP_ENA_P 0x04
+
+/* UARTx_LSR Masks */
+#define DR 0x01 /* Data Ready */
+#define OE 0x02 /* Overrun Error */
+#define PE 0x04 /* Parity Error */
+#define FE 0x08 /* Framing Error */
+#define BI 0x10 /* Break Interrupt */
+#define THRE 0x20 /* THR Empty */
+#define TEMT 0x40 /* TSR and UART_THR Empty */
+
+/* UARTx_IER Masks */
+#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
+#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI 0x04 /* Enable RX Status Interrupt */
+
+/* UARTx_IIR Masks */
+#define NINT 0x01 /* Pending Interrupt */
+#define STATUS 0x06 /* Highest Priority Pending Interrupt */
+
+/* UARTx_GCTL Masks */
+#define UCEN 0x01 /* Enable UARTx Clocks */
+#define IREN 0x02 /* Enable IrDA Mode */
+#define TPOLC 0x04 /* IrDA TX Polarity Change */
+#define RPOLC 0x08 /* IrDA RX Polarity Change */
+#define FPE 0x10 /* Force Parity Error On Transmit */
+#define FFE 0x20 /* Force Framing Error On Transmit */
+
+
+/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
+/* SPI_CTL Masks */
+#define TIMOD 0x0003 /* Transfer Initiate Mode */
+#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
+#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
+#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
+#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
+#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
+#define PSSE 0x0010 /* Slave-Select Input Enable */
+#define EMISO 0x0020 /* Enable MISO As Output */
+#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
+#define LSBF 0x0200 /* LSB First */
+#define CPHA 0x0400 /* Clock Phase */
+#define CPOL 0x0800 /* Clock Polarity */
+#define MSTR 0x1000 /* Master/Slave* */
+#define WOM 0x2000 /* Write Open Drain Master */
+#define SPE 0x4000 /* SPI Enable */
+
+/* SPI_FLG Masks */
+#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
+#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
+#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
+#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
+#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
+#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
+#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
+#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
+#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
+#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
+#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
+#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
+#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
+#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
+
+/* SPI_STAT Masks */
+#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
+#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
+#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
+#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
+#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
+#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
+#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
+
+
+/* **************** GENERAL PURPOSE TIMER MASKS **********************/
+/* TIMER_ENABLE Masks */
+#define TIMEN0 0x0001 /* Enable Timer 0 */
+#define TIMEN1 0x0002 /* Enable Timer 1 */
+#define TIMEN2 0x0004 /* Enable Timer 2 */
+#define TIMEN3 0x0008 /* Enable Timer 3 */
+#define TIMEN4 0x0010 /* Enable Timer 4 */
+#define TIMEN5 0x0020 /* Enable Timer 5 */
+#define TIMEN6 0x0040 /* Enable Timer 6 */
+#define TIMEN7 0x0080 /* Enable Timer 7 */
+
+/* TIMER_DISABLE Masks */
+#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
+#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
+#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
+#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
+#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
+#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
+#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
+#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
+
+/* TIMER_STATUS Masks */
+#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
+#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
+#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
+#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
+#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
+#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
+#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
+#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
+#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
+#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
+#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
+#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
+#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
+#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
+#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
+#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
+#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
+#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
+#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
+#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
+#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
+#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
+#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
+#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks */
+#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
+#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
+#define EXT_CLK 0x0003 /* External Clock Mode */
+#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
+#define PERIOD_CNT 0x0008 /* Period Count */
+#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
+#define TIN_SEL 0x0020 /* Timer Input Select */
+#define OUT_DIS 0x0040 /* Output Pad Disable */
+#define CLK_SEL 0x0080 /* Timer Clock Select */
+#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
+#define EMU_RUN 0x0200 /* Emulation Behavior Select */
+#define ERR_TYP 0xC000 /* Error Type */
+
+
+/* ****************** GPIO PORTS F, G, H MASKS ***********************/
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
+/* Port F Masks */
+#define PF0 0x0001
+#define PF1 0x0002
+#define PF2 0x0004
+#define PF3 0x0008
+#define PF4 0x0010
+#define PF5 0x0020
+#define PF6 0x0040
+#define PF7 0x0080
+#define PF8 0x0100
+#define PF9 0x0200
+#define PF10 0x0400
+#define PF11 0x0800
+#define PF12 0x1000
+#define PF13 0x2000
+#define PF14 0x4000
+#define PF15 0x8000
+
+/* Port G Masks */
+#define PG0 0x0001
+#define PG1 0x0002
+#define PG2 0x0004
+#define PG3 0x0008
+#define PG4 0x0010
+#define PG5 0x0020
+#define PG6 0x0040
+#define PG7 0x0080
+#define PG8 0x0100
+#define PG9 0x0200
+#define PG10 0x0400
+#define PG11 0x0800
+#define PG12 0x1000
+#define PG13 0x2000
+#define PG14 0x4000
+#define PG15 0x8000
+
+/* Port H Masks */
+#define PH0 0x0001
+#define PH1 0x0002
+#define PH2 0x0004
+#define PH3 0x0008
+#define PH4 0x0010
+#define PH5 0x0020
+#define PH6 0x0040
+#define PH7 0x0080
+#define PH8 0x0100
+#define PH9 0x0200
+#define PH10 0x0400
+#define PH11 0x0800
+#define PH12 0x1000
+#define PH13 0x2000
+#define PH14 0x4000
+#define PH15 0x8000
+
+
+/* ******************* SERIAL PORT MASKS **************************************/
+/* SPORTx_TCR1 Masks */
+#define TSPEN 0x0001 /* Transmit Enable */
+#define ITCLK 0x0002 /* Internal Transmit Clock Select */
+#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define TLSBIT 0x0010 /* Transmit Bit Order */
+#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
+#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
+#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
+#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
+#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
+#define TCKFE 0x4000 /* Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks and Macro */
+#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#define TXSE 0x0100 /* TX Secondary Enable */
+#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
+#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN 0x0001 /* Receive Enable */
+#define IRCLK 0x0002 /* Internal Receive Clock Select */
+#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define RLSBIT 0x0010 /* Receive Bit Order */
+#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
+#define RFSR 0x0400 /* Receive Frame Sync Required Select */
+#define LRFS 0x1000 /* Low Receive Frame Sync Select */
+#define LARFS 0x2000 /* Late Receive Frame Sync Select */
+#define RCKFE 0x4000 /* Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
+#define RXSE 0x0100 /* RX Secondary Enable */
+#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
+#define RRFST 0x0400 /* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
+#define RUVF 0x0002 /* Sticky Receive Underflow Status */
+#define ROVF 0x0004 /* Sticky Receive Overflow Status */
+#define TXF 0x0008 /* Transmit FIFO Full Status */
+#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
+#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
+#define TXHRE 0x0040 /* Transmit Hold Register Empty */
+
+/* SPORTx_MCMC1 Macros */
+#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
+
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+
+/* SPORTx_MCMC2 Masks */
+#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
+#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
+#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
+#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
+#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
+#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
+#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
+#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
+#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
+#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
+#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
+#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
+#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
+#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
+#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
+#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
+#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
+#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
+#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
+#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
+
+
+/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
+/* EBIU_AMGCTL Masks */
+#define AMCKEN 0x0001 /* Enable CLKOUT */
+#define AMBEN_NONE 0x0000 /* All Banks Disabled */
+#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
+#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
+#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
+#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
+#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
+#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
+#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
+#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
+#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
+#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
+#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
+#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
+#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
+#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
+#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
+#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
+#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
+#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
+#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
+#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
+#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
+#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
+#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
+#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
+#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
+#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
+#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
+#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
+#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
+#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
+#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
+#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
+#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
+#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
+#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
+#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
+#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
+#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
+
+#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
+#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
+#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
+#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
+#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
+#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
+#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
+#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
+#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
+#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
+#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
+#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
+#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
+#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
+#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
+#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
+#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
+#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
+#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
+#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
+#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
+#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
+#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
+#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
+#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
+#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
+#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
+#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
+#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
+#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
+#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
+#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
+#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
+#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
+#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
+#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
+#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
+#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
+#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
+#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
+#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
+#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
+#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
+#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
+#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
+#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
+#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
+#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
+#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
+#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
+#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
+#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
+#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
+#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
+#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
+#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
+#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
+#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
+#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
+#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
+#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
+#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
+#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
+#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
+#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
+#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
+#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
+#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
+#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
+#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
+#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
+
+#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
+#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
+#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
+#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
+#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
+#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
+#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
+#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
+#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
+#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
+#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
+#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
+#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
+#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
+#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
+#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
+#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
+#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
+#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
+#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
+#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
+#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
+#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
+#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
+#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
+#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
+#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
+#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
+#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
+#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
+#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
+#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
+#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
+#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
+#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
+#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
+
+
+/* ********************** SDRAM CONTROLLER MASKS **********************************************/
+/* EBIU_SDGCTL Masks */
+#define SCTLE 0x00000001 /* Enable SDRAM Signals */
+#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
+#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
+#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
+#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
+#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
+#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
+#define EBUFE 0x02000000 /* Enable External Buffering Timing */
+#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
+#define EMREN 0x10000000 /* Extended Mode Register Enable */
+#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
+#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE 0x0001 /* Enable SDRAM External Bank */
+#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
+#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
+#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
+#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
+#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
+#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
+#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
+#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
+#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
+#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI 0x0001 /* SDRAM Controller Idle */
+#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
+#define SDPUA 0x0004 /* SDRAM Power-Up Active */
+#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
+#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
+#define BGSTAT 0x0020 /* Bus Grant Status */
+
+
+/* ************************** DMA CONTROLLER MASKS ********************************/
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN 0x0001 /* DMA Channel Enable */
+#define WNR 0x0002 /* Channel Direction (W/R*) */
+#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
+#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
+#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
+#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
+#define SYNC 0x0020 /* DMA Buffer Clear */
+#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
+#define DI_EN 0x0080 /* Data Interrupt Enable */
+#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
+#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
+#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
+#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
+#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
+#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
+#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
+#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
+#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
+#define FLOW_STOP 0x0000 /* Stop Mode */
+#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
+#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
+#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
+#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
+#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
+#define PMAP_PPI 0x0000 /* PPI Port DMA */
+#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
+#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
+#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
+#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
+#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
+#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
+#define PMAP_SPI 0x7000 /* SPI Port DMA */
+#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
+#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
+#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
+#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
+#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
+#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
+#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
+
+
+/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
+/* PPI_CONTROL Masks */
+#define PORT_EN 0x0001 /* PPI Port Enable */
+#define PORT_DIR 0x0002 /* PPI Port Direction */
+#define XFR_TYPE 0x000C /* PPI Transfer Type */
+#define PORT_CFG 0x0030 /* PPI Port Configuration */
+#define FLD_SEL 0x0040 /* PPI Active Field Select */
+#define PACK_EN 0x0080 /* PPI Packing Mode */
+/* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
+#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
+#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
+#define DLEN_8 0x0000 /* Data Length = 8 Bits */
+#define DLEN_10 0x0800 /* Data Length = 10 Bits */
+#define DLEN_11 0x1000 /* Data Length = 11 Bits */
+#define DLEN_12 0x1800 /* Data Length = 12 Bits */
+#define DLEN_13 0x2000 /* Data Length = 13 Bits */
+#define DLEN_14 0x2800 /* Data Length = 14 Bits */
+#define DLEN_15 0x3000 /* Data Length = 15 Bits */
+#define DLEN_16 0x3800 /* Data Length = 16 Bits */
+#define POLC 0x4000 /* PPI Clock Polarity */
+#define POLS 0x8000 /* PPI Frame Sync Polarity */
+
+/* PPI_STATUS Masks */
+#define LT_ERR_OVR 0x0100 /* Line Track Overflow Error */
+#define LT_ERR_UNDR 0x0200 /* Line Track Underflow Error */
+#define FLD 0x0400 /* Field Indicator */
+#define FT_ERR 0x0800 /* Frame Track Error */
+#define OVR 0x1000 /* FIFO Overflow Error */
+#define UNDR 0x2000 /* FIFO Underrun Error */
+#define ERR_DET 0x4000 /* Error Detected Indicator */
+#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
+
+
+/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+
+/* TWI_PRESCALE Masks */
+#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
+#define TWI_ENA 0x0080 /* TWI Enable */
+#define SCCB 0x0200 /* SCCB Compatibility Enable */
+
+/* TWI_SLAVE_CTRL Masks */
+#define SEN 0x0001 /* Slave Enable */
+#define SADD_LEN 0x0002 /* Slave Address Length */
+#define STDVAL 0x0004 /* Slave Transmit Data Valid */
+#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN 0x0010 /* General Call Adrress Matching Enabled */
+
+/* TWI_SLAVE_STAT Masks */
+#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL 0x0002 /* General Call Indicator */
+
+/* TWI_MASTER_CTRL Masks */
+#define MEN 0x0001 /* Master Mode Enable */
+#define MADD_LEN 0x0002 /* Master Address Length */
+#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
+#define FAST 0x0008 /* Use Fast Mode Timing Specs */
+#define STOP 0x0010 /* Issue Stop Condition */
+#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
+#define DCNT 0x3FC0 /* Data Bytes To Transfer */
+#define SDAOVR 0x4000 /* Serial Data Override */
+#define SCLOVR 0x8000 /* Serial Clock Override */
+
+/* TWI_MASTER_STAT Masks */
+#define MPROG 0x0001 /* Master Transfer In Progress */
+#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
+#define ANAK 0x0004 /* Address Not Acknowledged */
+#define DNAK 0x0008 /* Data Not Acknowledged */
+#define BUFRDERR 0x0010 /* Buffer Read Error */
+#define BUFWRERR 0x0020 /* Buffer Write Error */
+#define SDASEN 0x0040 /* Serial Data Sense */
+#define SCLSEN 0x0080 /* Serial Clock Sense */
+#define BUSBUSY 0x0100 /* Bus Busy Indicator */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
+#define SINIT 0x0001 /* Slave Transfer Initiated */
+#define SCOMP 0x0002 /* Slave Transfer Complete */
+#define SERR 0x0004 /* Slave Transfer Error */
+#define SOVF 0x0008 /* Slave Overflow */
+#define MCOMP 0x0010 /* Master Transfer Complete */
+#define MERR 0x0020 /* Master Transfer Error */
+#define XMTSERV 0x0040 /* Transmit FIFO Service */
+#define RCVSERV 0x0080 /* Receive FIFO Service */
+
+/* TWI_FIFO_CTRL Masks */
+#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
+#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
+#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
+#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
+
+/* TWI_FIFO_STAT Masks */
+#define XMTSTAT 0x0003 /* Transmit FIFO Status */
+#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
+#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
+#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
+
+#define RCVSTAT 0x000C /* Receive FIFO Status */
+#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
+#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
+#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
+
+
+/* Omit CAN masks from defBF534.h */
+
+/* ******************* PIN CONTROL REGISTER MASKS ************************/
+/* PORT_MUX Masks */
+#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
+#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
+#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
+
+#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
+#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
+#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
+#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
+
+#define PFDE 0x0008 /* Port F DMA Request Enable */
+#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
+#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
+
+#define PFTE 0x0010 /* Port F Timer Enable */
+#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
+#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
+
+#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
+#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
+#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
+
+#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
+#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
+#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
+
+#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
+#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
+#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
+
+#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
+#define PFFE_TIMER 0x0000 /* Enable TMR2 */
+#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
+
+#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
+#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
+#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
+
+#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
+#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
+#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
+
+#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
+#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
+#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
+
+
+/* ****************** HANDSHAKE DMA (HMDMA) MASKS *********************/
+/* HMDMAx_CTL Masks */
+#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
+#define REP 0x0002 /* HMDMA Request Polarity */
+#define UTE 0x0004 /* Urgency Threshold Enable */
+#define OIE 0x0010 /* Overflow Interrupt Enable */
+#define BDIE 0x0020 /* Block Done Interrupt Enable */
+#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
+#define DRQ 0x0300 /* HMDMA Request Type */
+#define DRQ_NONE 0x0000 /* No Request */
+#define DRQ_SINGLE 0x0100 /* Channels Request Single */
+#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
+#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
+#define RBC 0x1000 /* Reload BCNT With IBCNT */
+#define PS 0x2000 /* HMDMA Pin Status */
+#define OI 0x4000 /* Overflow Interrupt Generated */
+#define BDI 0x8000 /* Block Done Interrupt Generated */
+
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define PGDE_UART PFDE_UART
+#define PGDE_DMA PFDE_DMA
+#define CKELOW SCKELOW
+
+/* ==== end from defBF534.h ==== */
+
+/* HOST Port Registers */
+
+#define HOST_CONTROL 0xffc03400 /* HOSTDP Control Register */
+#define HOST_STATUS 0xffc03404 /* HOSTDP Status Register */
+#define HOST_TIMEOUT 0xffc03408 /* HOSTDP Acknowledge Mode Timeout Register */
+
+/* Counter Registers */
+
+#define CNT_CONFIG 0xffc03500 /* Configuration Register */
+#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
+#define CNT_STATUS 0xffc03508 /* Status Register */
+#define CNT_COMMAND 0xffc0350c /* Command Register */
+#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
+#define CNT_COUNTER 0xffc03514 /* Counter Register */
+#define CNT_MAX 0xffc03518 /* Maximal Count Register */
+#define CNT_MIN 0xffc0351c /* Minimal Count Register */
+
+/* OTP/FUSE Registers */
+
+#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
+#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
+#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
+
+/* Security Registers */
+
+#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
+#define SECURE_CONTROL 0xffc03624 /* Secure Control */
+#define SECURE_STATUS 0xffc03628 /* Secure Status */
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+
+/* NFC Registers */
+
+#define NFC_CTL 0xffc03700 /* NAND Control Register */
+#define NFC_STAT 0xffc03704 /* NAND Status Register */
+#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
+#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
+#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
+#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
+#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
+#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
+#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
+#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
+#define NFC_READ 0xffc0372c /* NAND Read Data Register */
+#define NFC_ADDR 0xffc03740 /* NAND Address Register */
+#define NFC_CMD 0xffc03744 /* NAND Command Register */
+#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
+#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
+
+/* ********************************************************** */
+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
+/* and MULTI BIT READ MACROS */
+/* ********************************************************** */
+
+/* Bit masks for HOST_CONTROL */
+
+#define HOSTDP_EN 0x1 /* HOSTDP Enable */
+#define nHOSTDP_EN 0x0
+#define HOSTDP_END 0x2 /* Host Endianess */
+#define nHOSTDP_END 0x0
+#define HOSTDP_DATA_SIZE 0x4 /* Data Size */
+#define nHOSTDP_DATA_SIZE 0x0
+#define HOSTDP_RST 0x8 /* HOSTDP Reset */
+#define nHOSTDP_RST 0x0
+#define HRDY_OVR 0x20 /* HRDY Override */
+#define nHRDY_OVR 0x0
+#define INT_MODE 0x40 /* Interrupt Mode */
+#define nINT_MODE 0x0
+#define BT_EN 0x80 /* Bus Timeout Enable */
+#define nBT_EN 0x0
+#define EHW 0x100 /* Enable Host Write */
+#define nEHW 0x0
+#define EHR 0x200 /* Enable Host Read */
+#define nEHR 0x0
+#define BDR 0x400 /* Burst DMA Requests */
+#define nBDR 0x0
+
+/* Bit masks for HOST_STATUS */
+
+#define DMA_RDY 0x1 /* DMA Ready */
+#define nDMA_RDY 0x0
+#define FIFOFULL 0x2 /* FIFO Full */
+#define nFIFOFULL 0x0
+#define FIFOEMPTY 0x4 /* FIFO Empty */
+#define nFIFOEMPTY 0x0
+#define DMA_CMPLT 0x8 /* DMA Complete */
+#define nDMA_CMPLT 0x0
+#define HSHK 0x10 /* Host Handshake */
+#define nHSHK 0x0
+#define HOSTDP_TOUT 0x20 /* HOSTDP Timeout */
+#define nHOSTDP_TOUT 0x0
+#define HIRQ 0x40 /* Host Interrupt Request */
+#define nHIRQ 0x0
+#define ALLOW_CNFG 0x80 /* Allow New Configuration */
+#define nALLOW_CNFG 0x0
+#define DMA_DIR 0x100 /* DMA Direction */
+#define nDMA_DIR 0x0
+#define BTE 0x200 /* Bus Timeout Enabled */
+#define nBTE 0x0
+#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
+#define nHOSTRD_DONE 0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
+
+/* Bit masks for CNT_CONFIG */
+
+#define CNTE 0x1 /* Counter Enable */
+#define nCNTE 0x0
+#define DEBE 0x2 /* Debounce Enable */
+#define nDEBE 0x0
+#define CDGINV 0x10 /* CDG Pin Polarity Invert */
+#define nCDGINV 0x0
+#define CUDINV 0x20 /* CUD Pin Polarity Invert */
+#define nCUDINV 0x0
+#define CZMINV 0x40 /* CZM Pin Polarity Invert */
+#define nCZMINV 0x0
+#define CNTMODE 0x700 /* Counter Operating Mode */
+#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
+#define nZMZC 0x0
+#define BNDMODE 0x3000 /* Boundary register Mode */
+#define INPDIS 0x8000 /* CUG and CDG Input Disable */
+#define nINPDIS 0x0
+
+/* Bit masks for CNT_IMASK */
+
+#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
+#define nICIE 0x0
+#define UCIE 0x2 /* Up count Interrupt Enable */
+#define nUCIE 0x0
+#define DCIE 0x4 /* Down count Interrupt Enable */
+#define nDCIE 0x0
+#define MINCIE 0x8 /* Min Count Interrupt Enable */
+#define nMINCIE 0x0
+#define MAXCIE 0x10 /* Max Count Interrupt Enable */
+#define nMAXCIE 0x0
+#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
+#define nCOV31IE 0x0
+#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
+#define nCOV15IE 0x0
+#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
+#define nCZEROIE 0x0
+#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
+#define nCZMIE 0x0
+#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
+#define nCZMEIE 0x0
+#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
+#define nCZMZIE 0x0
+
+/* Bit masks for CNT_STATUS */
+
+#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
+#define nICII 0x0
+#define UCII 0x2 /* Up count Interrupt Identifier */
+#define nUCII 0x0
+#define DCII 0x4 /* Down count Interrupt Identifier */
+#define nDCII 0x0
+#define MINCII 0x8 /* Min Count Interrupt Identifier */
+#define nMINCII 0x0
+#define MAXCII 0x10 /* Max Count Interrupt Identifier */
+#define nMAXCII 0x0
+#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
+#define nCOV31II 0x0
+#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
+#define nCOV15II 0x0
+#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
+#define nCZEROII 0x0
+#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
+#define nCZMII 0x0
+#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
+#define nCZMEII 0x0
+#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
+#define nCZMZII 0x0
+
+/* Bit masks for CNT_COMMAND */
+
+#define W1LCNT 0xf /* Load Counter Register */
+#define W1LMIN 0xf0 /* Load Min Register */
+#define W1LMAX 0xf00 /* Load Max Register */
+#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
+#define nW1ZMONCE 0x0
+
+/* Bit masks for CNT_DEBOUNCE */
+
+#define DPRESCALE 0xf /* Load Counter Register */
+
+/* Bit masks for OTP_CONTROL */
+
+#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
+#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
+#define nFIEN 0x0
+#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
+#define nFTESTDEC 0x0
+#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
+#define nFWRTEST 0x0
+#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
+#define nFRDEN 0x0
+#define FWREN 0x8000 /* OTP/Fuse Write Enable */
+#define nFWREN 0x0
+
+/* Bit masks for OTP_BEN */
+
+#define FBEN 0xffff /* OTP/Fuse Byte Enable */
+
+/* Bit masks for OTP_STATUS */
+
+#define FCOMP 0x1 /* OTP/Fuse Access Complete */
+#define nFCOMP 0x0
+#define FERROR 0x2 /* OTP/Fuse Access Error */
+#define nFERROR 0x0
+#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
+#define nMMRGLOAD 0x0
+#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
+#define nMMRGLOCK 0x0
+#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
+#define nFPGMEN 0x0
+
+/* Bit masks for OTP_TIMING */
+
+#define USECDIV 0xff /* Micro Second Divider */
+#define READACC 0x7f00 /* Read Access Time */
+#define CPUMPRL 0x38000 /* Charge Pump Release Time */
+#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
+#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
+#define PGMTIME 0xff000000 /* Program Time */
+
+/* Bit masks for SECURE_SYSSWT */
+
+#define EMUDABL 0x1 /* Emulation Disable. */
+#define nEMUDABL 0x0
+#define RSTDABL 0x2 /* Reset Disable */
+#define nRSTDABL 0x0
+#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
+#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
+#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
+#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
+#define nDMA0OVR 0x0
+#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
+#define nDMA1OVR 0x0
+#define EMUOVR 0x4000 /* Emulation Override */
+#define nEMUOVR 0x0
+#define OTPSEN 0x8000 /* OTP Secrets Enable. */
+#define nOTPSEN 0x0
+#define L2DABL 0x70000 /* L2 Memory Disable. */
+
+/* Bit masks for SECURE_CONTROL */
+
+#define SECURE0 0x1 /* SECURE 0 */
+#define nSECURE0 0x0
+#define SECURE1 0x2 /* SECURE 1 */
+#define nSECURE1 0x0
+#define SECURE2 0x4 /* SECURE 2 */
+#define nSECURE2 0x0
+#define SECURE3 0x8 /* SECURE 3 */
+#define nSECURE3 0x0
+
+/* Bit masks for SECURE_STATUS */
+
+#define SECMODE 0x3 /* Secured Mode Control State */
+#define NMI 0x4 /* Non Maskable Interrupt */
+#define nNMI 0x0
+#define AFVALID 0x8 /* Authentication Firmware Valid */
+#define nAFVALID 0x0
+#define AFEXIT 0x10 /* Authentication Firmware Exit */
+#define nAFEXIT 0x0
+#define SECSTAT 0xe0 /* Secure Status */
+
+/* Bit masks for NFC_CTL */
+
+#define WR_DLY 0xf /* Write Strobe Delay */
+#define RD_DLY 0xf0 /* Read Strobe Delay */
+#define PG_SIZE 0x200 /* Page Size */
+#define nPG_SIZE 0x0
+
+/* Bit masks for NFC_STAT */
+
+#define NBUSY 0x1 /* Not Busy */
+#define nNBUSY 0x0
+#define WB_FULL 0x2 /* Write Buffer Full */
+#define nWB_FULL 0x0
+#define PG_WR_STAT 0x4 /* Page Write Pending */
+#define nPG_WR_STAT 0x0
+#define PG_RD_STAT 0x8 /* Page Read Pending */
+#define nPG_RD_STAT 0x0
+#define WB_EMPTY 0x10 /* Write Buffer Empty */
+#define nWB_EMPTY 0x0
+
+/* Bit masks for NFC_IRQSTAT */
+
+#define NBUSYIRQ 0x1 /* Not Busy IRQ */
+#define nNBUSYIRQ 0x0
+#define WB_OVF 0x2 /* Write Buffer Overflow */
+#define nWB_OVF 0x0
+#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
+#define nWB_EDGE 0x0
+#define RD_RDY 0x8 /* Read Data Ready */
+#define nRD_RDY 0x0
+#define WR_DONE 0x10 /* Page Write Done */
+#define nWR_DONE 0x0
+
+/* Bit masks for NFC_IRQMASK */
+
+#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
+#define nMASK_BUSYIRQ 0x0
+#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
+#define nMASK_WBOVF 0x0
+#define MASK_WBEDGE 0x4 /* Mask Write Buffer Edge Detect */
+#define nMASK_WBEDGE 0x0
+#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
+#define nMASK_RDRDY 0x0
+#define MASK_WRDONE 0x10 /* Mask Write Done */
+#define nMASK_WRDONE 0x0
+
+/* Bit masks for NFC_RST */
+
+#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
+#define nECC_RST 0x0
+
+/* Bit masks for NFC_PGCTL */
+
+#define PG_RD_START 0x1 /* Page Read Start */
+#define nPG_RD_START 0x0
+#define PG_WR_START 0x2 /* Page Write Start */
+#define nPG_WR_START 0x0
+
+/* Bit masks for NFC_ECC0 */
+
+#define ECC0 0x7ff /* Parity Calculation Result0 */
+
+/* Bit masks for NFC_ECC1 */
+
+#define ECC1 0x7ff /* Parity Calculation Result1 */
+
+/* Bit masks for NFC_ECC2 */
+
+#define ECC2 0x7ff /* Parity Calculation Result2 */
+
+/* Bit masks for NFC_ECC3 */
+
+#define ECC3 0x7ff /* Parity Calculation Result3 */
+
+/* Bit masks for NFC_COUNT */
+
+#define ECCCNT 0x3ff /* Transfer Count */
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF52X_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * defBF531.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifndef _DEFBF531_H
+#define _DEFBF531_H
+
+#include <defBF532.h>
+
+#endif /* _DEFBF531_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * defBF532.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
+
+#ifndef _DEF_BF532_H
+#define _DEF_BF532_H
+
+#if !defined(__ADSPLPBLACKFIN__)
+#warning defBF532.h should only be included for 532 compatible chips
+#endif
+/* include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+/*********************************************************************************** */
+/* System MMR Register Map */
+/*********************************************************************************** */
+/*// Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
+
+#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
+#define CHIPID 0xFFC00014 /* Chip ID Register */
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
+#define SYSCR 0xFFC00104 /* System Configuration registe */
+#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
+
+
+/*// Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+
+
+/*// Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT 0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
+#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
+
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART_THR 0xFFC00400 /* Transmit Holding register */
+#define UART_RBR 0xFFC00400 /* Receive Buffer register */
+#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
+#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define UART_LCR 0xFFC0040C /* Line Control Register */
+#define UART_MCR 0xFFC00410 /* Modem Control Register */
+#define UART_LSR 0xFFC00414 /* Line Status Register */
+/*#define UART_MSR 0xFFC00418 // Modem Status Register //(UNUSED in ADSP-BF532) */
+#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
+#define UART_GCTL 0xFFC00424 /* Global Control Register */
+
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL 0xFFC00500 /* SPI Control Register */
+#define SPI_FLG 0xFFC00504 /* SPI Flag register */
+#define SPI_STAT 0xFFC00508 /* SPI Status register */
+#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
+#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
+#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
+
+
+/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
+
+#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
+
+#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
+#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
+#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
+
+
+/*// General Purpose IO (0xFFC00700 - 0xFFC007FF) */
+#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
+#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
+#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
+#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
+#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
+#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
+#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
+#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
+#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
+#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
+#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
+#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
+#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
+#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
+#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
+#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
+#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
+
+
+/*// SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+
+/*// SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+/* Asynchronous Memory Controller */
+#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller */
+#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
+
+
+/* DMA Traffic controls */
+#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
+#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+
+#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+
+#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+
+#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+
+#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+
+#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+
+#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+
+#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+
+#define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */
+#define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */
+
+#define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */
+#define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */
+
+#define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */
+#define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */
+
+#define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */
+#define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */
+
+
+/*// Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
+
+/*********************************************************************************** */
+/* System MMR Register Bits */
+/******************************************************************************* */
+
+/* ********************* PLL AND RESET MASKS ************************ */
+/*// PLL_CTL Masks */
+#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
+#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF 0x0002 /* Shut off PLL clocks */
+#define STOPCK_OFF 0x0008 /* Core clock off */
+#define STOPCK 0x0008 /* Core Clock Off */
+#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
+
+#if !defined(__ADSPBF538__)
+/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
+# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
+# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
+#endif
+
+#define BYPASS 0x0100 /* Bypass the PLL */
+/* PLL_CTL Macros */
+#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+
+/* PLL_DIV Masks */
+#define SSEL 0x000F /* System Select */
+#define CSEL 0x0030 /* Core Select */
+
+#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
+
+#define CCLK_DIV1 0x0000 /* CCLK = VCO / 1 */
+#define CCLK_DIV2 0x0010 /* CCLK = VCO / 2 */
+#define CCLK_DIV4 0x0020 /* CCLK = VCO / 4 */
+#define CCLK_DIV8 0x0030 /* CCLK = VCO / 8 */
+/* PLL_DIV Macros */
+#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
+#define FULL_ON 0x0002 /* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
+#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
+
+/* VR_CTL Masks */
+#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
+#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
+#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
+
+#define GAIN 0x000C /* Voltage Level Gain */
+#define GAIN_5 0x0000 /* GAIN = 5 */
+#define GAIN_10 0x0004 /* GAIN = 10 */
+#define GAIN_20 0x0008 /* GAIN = 20 */
+#define GAIN_50 0x000C /* GAIN = 50 */
+
+#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
+#define VLEV_085 0x0060 /* VLEV = 0.85 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_090 0x0070 /* VLEV = 0.90 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_095 0x0080 /* VLEV = 0.95 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
+
+#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
+#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
+
+/* SWRST Mask */
+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks */
+#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
+#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+
+
+/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
+
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
+#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
+#define DMA_ERR_IRQ 0x00000002 /* DMA Controller Error Interrupt Request */
+#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
+#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
+#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
+#define SPI_ERR_IRQ 0x00000020 /* SPI Error Interrupt Request */
+#define UART_ERR_IRQ 0x00000040 /* UART Error Interrupt Request */
+#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
+#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
+#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
+#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
+#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
+#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
+#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
+#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
+#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
+#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
+#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
+#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
+#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
+#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
+#define MDMA0_IRQ 0x00200000 /* MemDMA Stream 0 Interrupt Request */
+#define MDMA1_IRQ 0x00400000 /* MemDMA Stream 1 Interrupt Request */
+#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
+
+
+/* SIC_IAR0 Macros */
+#define P0_IVG(x) (((x)-7)&0xF) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Macros */
+#define P8_IVG(x) (((x)-7)&0xF) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #15 assigned IVG #x */
+
+/* SIC_IAR2 Macros */
+#define P16_IVG(x) (((x)-7)&0xF) /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #23 assigned IVG #x */
+
+/* SIC_IARx Macros */
+#define PX_IVG_CLR(x) (0xFFFFFFFF ^ (0xF << (((x)%8)*4))) /* Clear IVG Select for Peripheral #x */
+/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
+#define PX_IVG(x,y) ((((y)-7)&0xF) << (((x)%8)*4)) /* Set IVG Select to #y for Peripheral #x */
+/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
+
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+
+#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#define WDEV_RESET 0x0000 /* generate reset event on roll over */
+#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
+#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
+#define WDEV_NONE 0x0006 /* no event on roll over */
+#define WDEN 0x0FF0 /* enable watchdog */
+#define WDDIS 0x0AD0 /* disable watchdog */
+#define WDRO 0x8000 /* watchdog rolled over latch */
+
+/* depreciated WDOG_CTL Register Masks for legacy code */
+#define ICTL WDEV
+#define ENABLE_RESET WDEV_RESET
+#define WDOG_RESET WDEV_RESET
+#define ENABLE_NMI WDEV_NMI
+#define WDOG_NMI WDEV_NMI
+#define ENABLE_GPI WDEV_GPI
+#define WDOG_GPI WDEV_GPI
+#define DISABLE_EVT WDEV_NONE
+#define WDOG_NONE WDEV_NONE
+
+#define TMR_EN WDEN
+#define WDOG_DISABLE WDDIS
+#define TRO WDRO
+
+#define ICTL_P0 0x01
+#define ICTL_P1 0x02
+#define TRO_P 0x0F
+
+
+/* *************** REAL TIME CLOCK MASKS **************************/
+/* RTC_STAT and RTC_ALARM register */
+#define RTSEC 0x0000003F /* Real-Time Clock Seconds */
+#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */
+#define RTHR 0x0001F000 /* Real-Time Clock Hours */
+#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */
+
+/* RTC_ICTL register */
+#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
+#define AIE 0x0002 /* Alarm Interrupt Enable */
+#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
+#define MIE 0x0008 /* Minutes Interrupt Enable */
+#define HIE 0x0010 /* Hours Interrupt Enable */
+#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
+#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WCIE 0x8000 /* Write Complete Interrupt Enable */
+
+/* RTC_ISTAT register */
+#define SWEF 0x0001 /* Stopwatch Event Flag */
+#define AEF 0x0002 /* Alarm Event Flag */
+#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
+#define MEF 0x0008 /* Minutes Event Flag */
+#define HEF 0x0010 /* Hours Event Flag */
+#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
+#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
+#define WPS 0x4000 /* Write Pending Status (RO) */
+#define WCOM 0x8000 /* Write Complete */
+
+/*// RTC_FAST Mask (RTC_PREN Mask) */
+#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
+#define PREN 0x00000001
+ /* ** Must be set after power-up for proper operation of RTC */
+
+/* RTC_ALARM Macro z=day y=hr x=min w=sec */
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+
+/* Deprecated RTC_STAT and RTC_ALARM Masks */
+#define RTC_SEC RTSEC /* Real-Time Clock Seconds */
+#define RTC_MIN RTMIN /* Real-Time Clock Minutes */
+#define RTC_HR RTHR /* Real-Time Clock Hours */
+#define RTC_DAY RTDAY /* Real-Time Clock Days */
+
+/* Deprecated RTC_ICTL/RTC_ISTAT Masks */
+#define STOPWATCH SWIE /* Stopwatch Interrupt Enable */
+#define ALARM AIE /* Alarm Interrupt Enable */
+#define SECOND SIE /* Seconds (1 Hz) Interrupt Enable */
+#define MINUTE MIE /* Minutes Interrupt Enable */
+#define HOUR HIE /* Hours Interrupt Enable */
+#define DAY DIE /* 24 Hours (Days) Interrupt Enable */
+#define DAY_ALARM DAIE /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WRITE_COMPLETE WCIE /* Write Complete Interrupt Enable */
+
+
+/* ***************************** UART CONTROLLER MASKS ********************** */
+/* UART_LCR Register */
+
+#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#define STB 0x04 /* Stop Bits */
+#define PEN 0x08 /* Parity Enable */
+#define EPS 0x10 /* Even Parity Select */
+#define STP 0x20 /* Stick Parity */
+#define SB 0x40 /* Set Break */
+#define DLAB 0x80 /* Divisor Latch Access */
+
+#define DLAB_P 0x07
+#define SB_P 0x06
+#define STP_P 0x05
+#define EPS_P 0x04
+#define PEN_P 0x03
+#define STB_P 0x02
+#define WLS_P1 0x01
+#define WLS_P0 0x00
+
+/* UART_MCR Register */
+#define LOOP_ENA 0x10 /* Loopback Mode Enable */
+#define LOOP_ENA_P 0x04
+/* Deprecated UARTx_MCR Mask */
+
+/* UART_LSR Register */
+#define DR 0x01 /* Data Ready */
+#define OE 0x02 /* Overrun Error */
+#define PE 0x04 /* Parity Error */
+#define FE 0x08 /* Framing Error */
+#define BI 0x10 /* Break Interrupt */
+#define THRE 0x20 /* THR Empty */
+#define TEMT 0x40 /* TSR and UART_THR Empty */
+
+#define TEMP_P 0x06
+#define THRE_P 0x05
+#define BI_P 0x04
+#define FE_P 0x03
+#define PE_P 0x02
+#define OE_P 0x01
+#define DR_P 0x00
+
+/* UART_IER Register */
+#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
+#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI 0x04 /* Enable RX Status Interrupt */
+
+#define ELSI_P 0x02
+#define ETBEI_P 0x01
+#define ERBFI_P 0x00
+
+/* UART_IIR Register */
+#define STATUS(x) (((x) << 1) & 0x06)
+#define NINT 0x01
+#define STATUS_P1 0x02
+#define STATUS_P0 0x01
+#define NINT_P 0x00
+
+/* UART_GCTL Register */
+#define UCEN 0x01 /* Enable UARTx Clocks */
+#define IREN 0x02 /* Enable IrDA Mode */
+#define TPOLC 0x04 /* IrDA TX Polarity Change */
+#define RPOLC 0x08 /* IrDA RX Polarity Change */
+#define FPE 0x10 /* Force Parity Error On Transmit */
+#define FFE 0x20 /* Force Framing Error On Transmit */
+
+#define FFE_P 0x05
+#define FPE_P 0x04
+#define RPOLC_P 0x03
+#define TPOLC_P 0x02
+#define IREN_P 0x01
+#define UCEN_P 0x00
+
+
+/* ********** SERIAL PORT MASKS ********************** */
+/* SPORTx_TCR1 Masks */
+#define TSPEN 0x0001 /* TX enable */
+#define ITCLK 0x0002 /* Internal TX Clock Select */
+#define TDTYPE 0x000C /* TX Data Formatting Select */
+#define DTYPE_NORM 0x0000 /* Data Format Normal */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define TLSBIT 0x0010 /* TX Bit Order */
+#define ITFS 0x0200 /* Internal TX Frame Sync Select */
+#define TFSR 0x0400 /* TX Frame Sync Required Select */
+#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
+#define LTFS 0x1000 /* Low TX Frame Sync Select */
+#define LATFS 0x2000 /* Late TX Frame Sync Select */
+#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
+/* SPORTx_RCR1 Deprecated Masks */
+#define TULAW DTYPE_ULAW /* Compand Using u-Law */
+#define TALAW DTYPE_ALAW /* Compand Using A-Law */
+
+/* SPORTx_TCR2 Masks */
+#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__)
+# define SLEN 0x001F
+#else
+# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#endif
+#define TXSE 0x0100 /*TX Secondary Enable */
+#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
+#define TRFST 0x0400 /*TX Right-First Data Order */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN 0x0001 /* RX enable */
+#define IRCLK 0x0002 /* Internal RX Clock Select */
+#define RDTYPE 0x000C /* RX Data Formatting Select */
+#define DTYPE_NORM 0x0000 /* no companding */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define RLSBIT 0x0010 /* RX Bit Order */
+#define IRFS 0x0200 /* Internal RX Frame Sync Select */
+#define RFSR 0x0400 /* RX Frame Sync Required Select */
+#define LRFS 0x1000 /* Low RX Frame Sync Select */
+#define LARFS 0x2000 /* Late RX Frame Sync Select */
+#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
+/* SPORTx_RCR1 Deprecated Masks */
+#define RULAW DTYPE_ULAW /* Compand Using u-Law */
+#define RALAW DTYPE_ALAW /* Compand Using A-Law */
+
+/* SPORTx_RCR2 Masks */
+/* SLEN defined above */
+#define RXSE 0x0100 /*RX Secondary Enable */
+#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
+#define RRFST 0x0400 /*Right-First Data Order */
+
+/*SPORTx_STAT Masks */
+#define RXNE 0x0001 /*RX FIFO Not Empty Status */
+#define RUVF 0x0002 /*RX Underflow Status */
+#define ROVF 0x0004 /*RX Overflow Status */
+#define TXF 0x0008 /*TX FIFO Full Status */
+#define TUVF 0x0010 /*TX Underflow Status */
+#define TOVF 0x0020 /*TX Overflow Status */
+#define TXHRE 0x0040 /*TX Hold Register Empty */
+
+/*SPORTx_MCMC1 Masks */
+#define WSIZE 0x0000F000 /*Multichannel Window Size Field */
+#define WOFF 0x000003FF /*Multichannel Window Offset Field */
+/* SPORTx_MCMC1 Macros */
+#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
+/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+
+/*SPORTx_MCMC2 Masks */
+#define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
+#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE 0x0004 /*Multichannel DMA Transmit Packing */
+#define MCDRXPE 0x0008 /*Multichannel DMA Receive Packing */
+#define MCMEN 0x0010 /*Multichannel Frame Mode Enable */
+#define FSDR 0x0080 /*Multichannel Frame Sync to Data Relationship */
+#define MFD 0xF000 /*Multichannel Frame Delay */
+#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
+#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
+#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
+#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
+#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
+#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
+#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
+#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
+#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
+#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
+#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
+#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
+#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
+#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
+#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
+#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
+
+
+/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
+/*// PPI_CONTROL Masks */
+#define PORT_EN 0x0001 /* PPI Port Enable */
+#define PORT_DIR 0x0002 /* PPI Port Direction */
+#define XFR_TYPE 0x000C /* PPI Transfer Type */
+#define PORT_CFG 0x0030 /* PPI Port Configuration */
+#define FLD_SEL 0x0040 /* PPI Active Field Select */
+#define PACK_EN 0x0080 /* PPI Packing Mode */
+/* previous versions of defBF532.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
+#define ALT_TIMING 0x0100 /* Enable Alternate PPI Timing (0.5 Silicon And Beyond) */
+#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
+#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
+#define DLENGTH 0x3800 /* PPI Data Length */
+#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
+#define DLEN_10 0x0800 /* Data Length = 10 Bits */
+#define DLEN_11 0x1000 /* Data Length = 11 Bits */
+#define DLEN_12 0x1800 /* Data Length = 12 Bits */
+#define DLEN_13 0x2000 /* Data Length = 13 Bits */
+#define DLEN_14 0x2800 /* Data Length = 14 Bits */
+#define DLEN_15 0x3000 /* Data Length = 15 Bits */
+#define DLEN_16 0x3800 /* Data Length = 16 Bits */
+#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
+#define POL 0xC000 /* PPI Signal Polarities */
+#define POLC 0x4000 /* PPI Clock Polarity */
+#define POLS 0x8000 /* PPI Frame Sync Polarity */
+
+
+/*// PPI_STATUS Masks */
+#define FLD 0x0400 /* Field Indicator */
+#define FT_ERR 0x0800 /* Frame Track Error */
+#define OVR 0x1000 /* FIFO Overflow Error */
+#define UNDR 0x2000 /* FIFO Underrun Error */
+#define ERR_DET 0x4000 /* Error Detected Indicator */
+#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
+
+
+/* ********** DMA CONTROLLER MASKS ***********************/
+/*//DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN 0x0001 /* Channel Enable */
+#define WNR 0x0002 /* Channel Direction (W/R*) */
+#define WDSIZE_8 0x0000 /* Word Size 8 bits */
+#define WDSIZE_16 0x0004 /* Word Size 16 bits */
+#define WDSIZE_32 0x0008 /* Word Size 32 bits */
+#define DMA2D 0x0010 /* 2D/1D* Mode */
+#define RESTART 0x0020 /* Restart */
+#define DI_SEL 0x0040 /* Data Interrupt Select */
+#define DI_EN 0x0080 /* Data Interrupt Enable */
+#define NDSIZE 0x0900 /* Next Descriptor Size */
+#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
+#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
+#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
+#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
+#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
+#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
+#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
+#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
+#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
+#define FLOW 0x7000 /* Flow Control */
+#define FLOW_STOP 0x0000 /* Stop Mode */
+#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
+#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
+#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
+#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
+
+#define DMAEN_P 0x0 /* Channel Enable */
+#define WNR_P 0x1 /* Channel Direction (W/R*) */
+#define DMA2D_P 0x4 /* 2D/1D* Mode */
+#define RESTART_P 0x5 /* Restart */
+#define DI_SEL_P 0x6 /* Data Interrupt Select */
+#define DI_EN_P 0x7 /* Data Interrupt Enable */
+
+/*//DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE 0x0001 /* DMA Done Indicator */
+#define DMA_ERR 0x0002 /* DMA Error Indicator */
+#define DFETCH 0x0004 /* Descriptor Fetch Indicator */
+#define DMA_RUN 0x0008 /* DMA Running Indicator */
+
+#define DMA_DONE_P 0x0 /* DMA Done Indicator */
+#define DMA_ERR_P 0x1 /* DMA Error Indicator */
+#define DFETCH_P 0x2 /* Descriptor Fetch Indicator */
+#define DMA_RUN_P 0x3 /* DMA Running Indicator */
+
+/*//DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+
+#define CTYPE 0x0040 /* DMA Channel Type Indicator */
+#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
+#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
+#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
+#define PCAPWR 0x0400 /* DMA Write Operation Indicator */
+#define PCAPRD 0x0800 /* DMA Read Operation Indicator */
+#define PMAP 0xF000 /* DMA Peripheral Map Field */
+
+#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
+#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
+#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
+#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
+#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
+#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
+#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
+#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
+
+
+/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
+/* PWM Timer bit definitions */
+/* TIMER_ENABLE Register */
+#define TIMEN0 0x0001 /* Enable Timer 0 */
+#define TIMEN1 0x0002 /* Enable Timer 1 */
+#define TIMEN2 0x0004 /* Enable Timer 2 */
+
+#define TIMEN0_P 0x00
+#define TIMEN1_P 0x01
+#define TIMEN2_P 0x02
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0 0x0001 /* Disable Timer 0 */
+#define TIMDIS1 0x0002 /* Disable Timer 1 */
+#define TIMDIS2 0x0004 /* Disable Timer 2 */
+
+#define TIMDIS0_P 0x00
+#define TIMDIS1_P 0x01
+#define TIMDIS2_P 0x02
+
+/* TIMER_STATUS Register */
+#define TIMIL0 0x0001 /* Timer 0 Interrupt */
+#define TIMIL1 0x0002 /* Timer 1 Interrupt */
+#define TIMIL2 0x0004 /* Timer 2 Interrupt */
+#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
+#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
+#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
+#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
+#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
+#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
+
+#define TIMIL0_P 0x00
+#define TIMIL1_P 0x01
+#define TIMIL2_P 0x02
+#define TOVF_ERR0_P 0x04
+#define TOVF_ERR1_P 0x05
+#define TOVF_ERR2_P 0x06
+#define TRUN0_P 0x0C
+#define TRUN1_P 0x0D
+#define TRUN2_P 0x0E
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR0_P TOVF_ERR0_P
+#define TOVL_ERR1_P TOVF_ERR1_P
+#define TOVL_ERR2_P TOVF_ERR2_P
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT 0x0001
+#define WDTH_CAP 0x0002
+#define EXT_CLK 0x0003
+#define PULSE_HI 0x0004
+#define PERIOD_CNT 0x0008
+#define IRQ_ENA 0x0010
+#define TIN_SEL 0x0020
+#define OUT_DIS 0x0040
+#define CLK_SEL 0x0080
+#define TOGGLE_HI 0x0100
+#define EMU_RUN 0x0200
+#define ERR_TYP(x) (((x) & 0x03) << 14)
+
+#define TMODE_P0 0x00
+#define TMODE_P1 0x01
+#define PULSE_HI_P 0x02
+#define PERIOD_CNT_P 0x03
+#define IRQ_ENA_P 0x04
+#define TIN_SEL_P 0x05
+#define OUT_DIS_P 0x06
+#define CLK_SEL_P 0x07
+#define TOGGLE_HI_P 0x08
+#define EMU_RUN_P 0x09
+#define ERR_TYP_P0 0x0E
+#define ERR_TYP_P1 0x0F
+
+
+/*/ ****************** GENERAL-PURPOSE I/O ********************* */
+/* Port F (Previously Flag I/O_ Masks */
+#define PF0 0x0001
+#define PF1 0x0002
+#define PF2 0x0004
+#define PF3 0x0008
+#define PF4 0x0010
+#define PF5 0x0020
+#define PF6 0x0040
+#define PF7 0x0080
+#define PF8 0x0100
+#define PF9 0x0200
+#define PF10 0x0400
+#define PF11 0x0800
+#define PF12 0x1000
+#define PF13 0x2000
+#define PF14 0x4000
+#define PF15 0x8000
+
+/* PORT F BIT POSITIONS */
+#define PF0_P 0x0
+#define PF1_P 0x1
+#define PF2_P 0x2
+#define PF3_P 0x3
+#define PF4_P 0x4
+#define PF5_P 0x5
+#define PF6_P 0x6
+#define PF7_P 0x7
+#define PF8_P 0x8
+#define PF9_P 0x9
+#define PF10_P 0xA
+#define PF11_P 0xB
+#define PF12_P 0xC
+#define PF13_P 0xD
+#define PF14_P 0xE
+#define PF15_P 0xF
+
+
+/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
+/* SPI_CTL Masks */
+#define TIMOD 0x0003 /* Transfer Initiate Mode */
+#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
+#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
+#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
+#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
+#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
+#define PSSE 0x0010 /* Slave-Select Input Enable */
+#define EMISO 0x0020 /* Enable MISO As Output */
+#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
+#define LSBF 0x0200 /* LSB First */
+#define CPHA 0x0400 /* Clock Phase */
+#define CPOL 0x0800 /* Clock Polarity */
+#define MSTR 0x1000 /* Master/Slave* */
+#define WOM 0x2000 /* Write Open Drain Master */
+#define SPE 0x4000 /* SPI Enable */
+
+/* SPI_FLG Masks */
+#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_FLG Bit Positions */
+#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_STAT Masks */
+#define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */
+#define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */
+#define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
+#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
+#define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */
+#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
+#define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */
+
+/* SPIx_FLG Masks */
+#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
+#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
+#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
+#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
+#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
+#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
+#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
+
+
+/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
+/* EBIU_AMGCTL Masks */
+#define AMCKEN 0x0001 /* Enable CLKOUT */
+#define AMBEN_NONE 0x0000 /* All Banks Disabled */
+#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
+
+/* EBIU_AMGCTL Bit Positions */
+#define AMCKEN_P 0x0000 /* Enable CLKOUT */
+#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
+#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
+
+/* ********************** SDRAM CONTROLLER MASKS *************************** */
+/* EBIU_SDGCTL Masks */
+#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
+#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
+#define PFE 0x00000010 /* Enable SDRAM prefetch */
+#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
+#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD 0x00200000 /*Power-up start delay */
+#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
+#define EBUFE 0x02000000 /* Enable external buffering timing */
+#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
+#define EMREN 0x10000000 /* Extended mode register enable */
+#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
+#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE 0x00000001 /* Enable SDRAM external bank */
+#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
+#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
+#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
+#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
+#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI 0x00000001 /* SDRAM controller is idle */
+#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
+#define SDPUA 0x00000004 /* SDRAM power up active */
+#define SDRS 0x00000008 /* SDRAM is in reset state */
+#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
+#define BGSTAT 0x00000020 /* Bus granted */
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF532_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * defBF533.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifndef _DEFBF533_H
+#define _DEFBF533_H
+
+#include <defBF532.h>
+
+#endif /* _DEFBF533_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF534_H
+#define _DEF_BF534_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+/************************************************************************************
+** System MMR Register Map
+*************************************************************************************/
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL 0xFFC00000 /* PLL Control Register */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
+#define PLL_STAT 0xFFC0000C /* PLL Status Register */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
+#define CHIPID 0xFFC00014 /* Device ID Register */
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST 0xFFC00100 /* Software Reset Register */
+#define SYSCR 0xFFC00104 /* System Configuration Register */
+#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
+
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT 0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
+#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART0_THR 0xFFC00400 /* Transmit Holding register */
+#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
+#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
+#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define UART0_LCR 0xFFC0040C /* Line Control Register */
+#define UART0_MCR 0xFFC00410 /* Modem Control Register */
+#define UART0_LSR 0xFFC00414 /* Line Status Register */
+#define UART0_MSR 0xFFC00418 /* Modem Status Register */
+#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
+#define UART0_GCTL 0xFFC00424 /* Global Control Register */
+
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL 0xFFC00500 /* SPI Control Register */
+#define SPI_FLG 0xFFC00504 /* SPI Flag register */
+#define SPI_STAT 0xFFC00508 /* SPI Status register */
+#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
+#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
+#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
+
+
+/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
+
+#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
+
+#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
+
+#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
+
+#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
+
+#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
+
+#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
+
+#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
+#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
+#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
+
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
+#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
+#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
+#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
+#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
+#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
+#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
+#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
+#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
+#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
+#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
+#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
+#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
+#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
+#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
+#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
+#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
+#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
+
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
+
+
+/* DMA Traffic Control Registers */
+#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
+#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+
+#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+
+#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+
+#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+
+#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+
+#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+
+#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+
+#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+
+#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
+
+#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
+
+#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
+
+#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
+
+#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
+
+#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
+
+#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
+
+#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
+
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
+
+
+/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
+#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
+#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
+#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
+#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
+#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
+#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
+#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
+#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
+#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
+#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
+#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
+#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
+#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
+#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
+#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
+#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
+#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
+#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
+#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
+#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
+#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
+#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
+#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
+#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
+#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
+#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
+#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
+#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
+#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
+#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
+
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
+#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
+#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
+#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
+#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
+#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
+#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
+#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
+#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
+#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
+#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
+#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
+#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
+#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
+#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
+#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
+#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
+#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
+
+
+/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
+#define UART1_THR 0xFFC02000 /* Transmit Holding register */
+#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
+#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
+#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
+#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
+#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
+#define UART1_LCR 0xFFC0200C /* Line Control Register */
+#define UART1_MCR 0xFFC02010 /* Modem Control Register */
+#define UART1_LSR 0xFFC02014 /* Line Status Register */
+#define UART1_MSR 0xFFC02018 /* Modem Status Register */
+#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
+#define UART1_GCTL 0xFFC02024 /* Global Control Register */
+
+
+/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
+/* For Mailboxes 0-15 */
+#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
+#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
+#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
+#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
+#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
+#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
+#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
+#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
+#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
+#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
+#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
+#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
+#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmit reg 1 */
+
+/* For Mailboxes 16-31 */
+#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
+#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
+#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
+#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
+#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
+#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
+#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
+#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
+#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
+#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
+#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
+#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
+#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmit reg 2 */
+
+/* CAN Configuration, Control, and Status Registers */
+#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
+#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
+#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
+#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
+#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
+#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
+#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
+#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
+#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
+#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
+#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
+#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
+#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
+#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
+#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
+#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
+#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
+
+/* Mailbox Acceptance Masks */
+#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
+#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
+#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
+#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
+#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
+#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
+#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
+#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
+#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
+#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
+#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
+#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
+#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
+#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
+#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
+#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
+#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
+#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
+#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
+#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
+#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
+#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
+#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
+#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
+#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
+#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
+#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
+#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
+#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
+#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
+#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
+#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
+
+#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
+#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
+#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
+#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
+#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
+#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
+#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
+#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
+#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
+#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
+#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
+#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
+#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
+#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
+#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
+#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
+#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
+#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
+#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
+#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
+#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
+#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
+#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
+#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
+#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
+#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
+#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
+#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
+#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
+#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
+#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
+#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
+
+/* CAN Acceptance Mask Macros */
+#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
+#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
+
+/* Mailbox Registers */
+#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
+#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
+#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
+#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
+#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
+#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
+#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
+#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
+
+#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
+#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
+#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
+#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
+#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
+#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
+#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
+#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
+
+#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
+#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
+#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
+#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
+#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
+#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
+#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
+#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
+
+#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
+#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
+#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
+#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
+#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
+#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
+#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
+#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
+
+#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
+#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
+#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
+#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
+#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
+#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
+#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
+#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
+
+#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
+#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
+#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
+#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
+#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
+#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
+#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
+#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
+
+#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
+#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
+#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
+#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
+#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
+#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
+#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
+#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
+
+#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
+#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
+#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
+#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
+#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
+#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
+#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
+#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
+
+#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
+#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
+#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
+#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
+#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
+#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
+#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
+#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
+
+#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
+#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
+#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
+#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
+#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
+#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
+#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
+#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
+
+#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
+#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
+#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
+#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
+#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
+#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
+#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
+#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
+
+#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
+#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
+#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
+#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
+#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
+#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
+#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
+#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
+
+#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
+#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
+#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
+#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
+#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
+#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
+#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
+#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
+
+#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
+#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
+#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
+#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
+#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
+#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
+#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
+#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
+
+#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
+#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
+#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
+#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
+#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
+#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
+#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
+#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
+
+#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
+#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
+#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
+#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
+#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
+#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
+#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
+#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
+
+#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
+#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
+#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
+#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
+#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
+#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
+#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
+#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
+
+#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
+#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
+#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
+#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
+#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
+#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
+#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
+#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
+
+#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
+#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
+#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
+#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
+#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
+#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
+#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
+#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
+
+#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
+#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
+#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
+#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
+#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
+#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
+#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
+#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
+
+#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
+#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
+#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
+#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
+#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
+#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
+#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
+#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
+
+#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
+#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
+#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
+#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
+#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
+#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
+#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
+#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
+
+#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
+#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
+#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
+#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
+#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
+#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
+#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
+#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
+
+#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
+#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
+#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
+#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
+#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
+#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
+#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
+#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
+
+#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
+#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
+#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
+#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
+#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
+#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
+#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
+#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
+
+#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
+#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
+#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
+#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
+#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
+#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
+#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
+#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
+
+#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
+#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
+#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
+#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
+#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
+#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
+#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
+#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
+
+#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
+#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
+#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
+#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
+#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
+#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
+#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
+#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
+
+#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
+#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
+#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
+#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
+#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
+#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
+#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
+#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
+
+#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
+#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
+#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
+#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
+#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
+#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
+#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
+#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
+
+#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
+#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
+#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
+#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
+#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
+#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
+#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
+#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
+
+#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
+#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
+#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
+#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
+#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
+#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
+#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
+#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
+
+/* CAN Mailbox Area Macros */
+#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
+#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
+#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
+#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
+#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
+#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
+#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
+#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
+
+
+/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
+#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
+#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
+#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
+#define PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
+
+
+/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
+#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
+
+#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
+
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer: All macros are intended to make C and Assembly code more readable.
+** Use these macros carefully, as any that do left shifts for field
+** depositing will result in the lower order bits being destroyed. Any
+** macro that shifts left to properly position the bit-field should be
+** used as part of an OR to initialize a register and NOT as a dynamic
+** modifier UNLESS the lower order bits are saved and ORed back in when
+** the macro is used.
+*************************************************************************************/
+/*
+** ********************* PLL AND RESET MASKS ****************************************/
+/* PLL_CTL Masks */
+#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF 0x0002 /* PLL Not Powered */
+#define STOPCK 0x0008 /* Core Clock Off */
+#define PDWN 0x0020 /* Enter Deep Sleep Mode */
+#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
+#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
+#define BYPASS 0x0100 /* Bypass the PLL */
+#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
+/* PLL_CTL Macros */
+#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+
+/* PLL_DIV Masks */
+#define SSEL 0x000F /* System Select */
+#define CSEL 0x0030 /* Core Select */
+#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
+#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
+#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
+#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
+/* PLL_DIV Macros */
+#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+
+/* VR_CTL Masks */
+#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
+#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
+#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
+
+#define GAIN 0x000C /* Voltage Level Gain */
+#define GAIN_5 0x0000 /* GAIN = 5 */
+#define GAIN_10 0x0004 /* GAIN = 10 */
+#define GAIN_20 0x0008 /* GAIN = 20 */
+#define GAIN_50 0x000C /* GAIN = 50 */
+
+#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
+#define VLEV_085 0x0060 /* VLEV = 0.85 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_090 0x0070 /* VLEV = 0.90 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_095 0x0080 /* VLEV = 0.95 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
+
+#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
+#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
+#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
+#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
+#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
+#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
+#define FULL_ON 0x0002 /* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
+#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
+
+/* SWRST Masks */
+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks */
+#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
+#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+
+
+/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
+#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
+
+#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
+#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
+#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
+#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
+#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
+#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
+#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
+
+#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
+#define IRQ_TWI 0x00000200 /* TWI Interrupt */
+#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
+#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
+#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
+#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
+#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
+#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
+
+#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
+#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
+#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
+#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
+#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
+#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
+#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
+#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
+#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
+#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
+
+#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
+#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
+#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
+#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
+#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
+#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
+#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
+#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
+#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
+#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
+#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
+
+/* SIC_IAR0 Macros */
+#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Macros */
+#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
+
+/* SIC_IAR2 Macros */
+#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
+
+/* SIC_IAR3 Macros */
+#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
+#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
+
+
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+
+#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#define WDEV_RESET 0x0000 /* generate reset event on roll over */
+#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
+#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
+#define WDEV_NONE 0x0006 /* no event on roll over */
+#define WDEN 0x0FF0 /* enable watchdog */
+#define WDDIS 0x0AD0 /* disable watchdog */
+#define WDRO 0x8000 /* watchdog rolled over latch */
+
+/* depreciated WDOG_CTL Register Masks for legacy code */
+
+
+#define ICTL WDEV
+#define ENABLE_RESET WDEV_RESET
+#define WDOG_RESET WDEV_RESET
+#define ENABLE_NMI WDEV_NMI
+#define WDOG_NMI WDEV_NMI
+#define ENABLE_GPI WDEV_GPI
+#define WDOG_GPI WDEV_GPI
+#define DISABLE_EVT WDEV_NONE
+#define WDOG_NONE WDEV_NONE
+
+#define TMR_EN WDEN
+#define WDOG_DISABLE WDDIS
+#define TRO WDRO
+#define ICTL_P0 0x01
+ #define ICTL_P1 0x02
+#define TRO_P 0x0F
+
+
+
+/* *************** REAL TIME CLOCK MASKS **************************/
+/* RTC_STAT and RTC_ALARM Masks */
+#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
+#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
+#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
+#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
+
+/* RTC_ALARM Macro z=day y=hr x=min w=sec */
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+
+/* RTC_ICTL and RTC_ISTAT Masks */
+#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
+#define ALARM 0x0002 /* Alarm Interrupt Enable */
+#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
+#define MINUTE 0x0008 /* Minutes Interrupt Enable */
+#define HOUR 0x0010 /* Hours Interrupt Enable */
+#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
+#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WRITE_PENDING 0x4000 /* Write Pending Status */
+#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
+
+/* RTC_FAST / RTC_PREN Mask */
+#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
+
+
+/* ************** UART CONTROLLER MASKS *************************/
+/* UARTx_LCR Masks */
+#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#define STB 0x04 /* Stop Bits */
+#define PEN 0x08 /* Parity Enable */
+#define EPS 0x10 /* Even Parity Select */
+#define STP 0x20 /* Stick Parity */
+#define SB 0x40 /* Set Break */
+#define DLAB 0x80 /* Divisor Latch Access */
+
+/* UARTx_MCR Mask */
+#define LOOP_ENA 0x10 /* Loopback Mode Enable */
+#define LOOP_ENA_P 0x04
+
+/* UARTx_LSR Masks */
+#define DR 0x01 /* Data Ready */
+#define OE 0x02 /* Overrun Error */
+#define PE 0x04 /* Parity Error */
+#define FE 0x08 /* Framing Error */
+#define BI 0x10 /* Break Interrupt */
+#define THRE 0x20 /* THR Empty */
+#define TEMT 0x40 /* TSR and UART_THR Empty */
+
+/* UARTx_IER Masks */
+#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
+#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI 0x04 /* Enable RX Status Interrupt */
+
+/* UARTx_IIR Masks */
+#define NINT 0x01 /* Pending Interrupt */
+#define STATUS 0x06 /* Highest Priority Pending Interrupt */
+
+/* UARTx_GCTL Masks */
+#define UCEN 0x01 /* Enable UARTx Clocks */
+#define IREN 0x02 /* Enable IrDA Mode */
+#define TPOLC 0x04 /* IrDA TX Polarity Change */
+#define RPOLC 0x08 /* IrDA RX Polarity Change */
+#define FPE 0x10 /* Force Parity Error On Transmit */
+#define FFE 0x20 /* Force Framing Error On Transmit */
+
+
+/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
+/* SPI_CTL Masks */
+#define TIMOD 0x0003 /* Transfer Initiate Mode */
+#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
+#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
+#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
+#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
+#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
+#define PSSE 0x0010 /* Slave-Select Input Enable */
+#define EMISO 0x0020 /* Enable MISO As Output */
+#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
+#define LSBF 0x0200 /* LSB First */
+#define CPHA 0x0400 /* Clock Phase */
+#define CPOL 0x0800 /* Clock Polarity */
+#define MSTR 0x1000 /* Master/Slave* */
+#define WOM 0x2000 /* Write Open Drain Master */
+#define SPE 0x4000 /* SPI Enable */
+
+/* SPI_FLG Masks */
+#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
+#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
+#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
+#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
+#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
+#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
+#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
+#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
+#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
+#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
+#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
+#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
+#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
+#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
+
+/* SPI_STAT Masks */
+#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
+#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
+#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
+#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
+#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
+#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
+#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
+
+
+/* **************** GENERAL PURPOSE TIMER MASKS **********************/
+/* TIMER_ENABLE Masks */
+#define TIMEN0 0x0001 /* Enable Timer 0 */
+#define TIMEN1 0x0002 /* Enable Timer 1 */
+#define TIMEN2 0x0004 /* Enable Timer 2 */
+#define TIMEN3 0x0008 /* Enable Timer 3 */
+#define TIMEN4 0x0010 /* Enable Timer 4 */
+#define TIMEN5 0x0020 /* Enable Timer 5 */
+#define TIMEN6 0x0040 /* Enable Timer 6 */
+#define TIMEN7 0x0080 /* Enable Timer 7 */
+
+/* TIMER_DISABLE Masks */
+#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
+#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
+#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
+#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
+#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
+#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
+#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
+#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
+
+/* TIMER_STATUS Masks */
+#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
+#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
+#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
+#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
+#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
+#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
+#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
+#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
+#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
+#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
+#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
+#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
+#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
+#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
+#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
+#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
+#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
+#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
+#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
+#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
+#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
+#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
+#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
+#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+
+/* TIMERx_CONFIG Masks */
+#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
+#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
+#define EXT_CLK 0x0003 /* External Clock Mode */
+#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
+#define PERIOD_CNT 0x0008 /* Period Count */
+#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
+#define TIN_SEL 0x0020 /* Timer Input Select */
+#define OUT_DIS 0x0040 /* Output Pad Disable */
+#define CLK_SEL 0x0080 /* Timer Clock Select */
+#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
+#define EMU_RUN 0x0200 /* Emulation Behavior Select */
+#define ERR_TYP 0xC000 /* Error Type */
+
+
+/* ****************** GPIO PORTS F, G, H MASKS ***********************/
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
+/* Port F Masks */
+#define PF0 0x0001
+#define PF1 0x0002
+#define PF2 0x0004
+#define PF3 0x0008
+#define PF4 0x0010
+#define PF5 0x0020
+#define PF6 0x0040
+#define PF7 0x0080
+#define PF8 0x0100
+#define PF9 0x0200
+#define PF10 0x0400
+#define PF11 0x0800
+#define PF12 0x1000
+#define PF13 0x2000
+#define PF14 0x4000
+#define PF15 0x8000
+
+/* Port G Masks */
+#define PG0 0x0001
+#define PG1 0x0002
+#define PG2 0x0004
+#define PG3 0x0008
+#define PG4 0x0010
+#define PG5 0x0020
+#define PG6 0x0040
+#define PG7 0x0080
+#define PG8 0x0100
+#define PG9 0x0200
+#define PG10 0x0400
+#define PG11 0x0800
+#define PG12 0x1000
+#define PG13 0x2000
+#define PG14 0x4000
+#define PG15 0x8000
+
+/* Port H Masks */
+#define PH0 0x0001
+#define PH1 0x0002
+#define PH2 0x0004
+#define PH3 0x0008
+#define PH4 0x0010
+#define PH5 0x0020
+#define PH6 0x0040
+#define PH7 0x0080
+#define PH8 0x0100
+#define PH9 0x0200
+#define PH10 0x0400
+#define PH11 0x0800
+#define PH12 0x1000
+#define PH13 0x2000
+#define PH14 0x4000
+#define PH15 0x8000
+
+
+/* ******************* SERIAL PORT MASKS **************************************/
+/* SPORTx_TCR1 Masks */
+#define TSPEN 0x0001 /* Transmit Enable */
+#define ITCLK 0x0002 /* Internal Transmit Clock Select */
+#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define TLSBIT 0x0010 /* Transmit Bit Order */
+#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
+#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
+#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
+#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
+#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
+#define TCKFE 0x4000 /* Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks and Macro */
+#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#define TXSE 0x0100 /* TX Secondary Enable */
+#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
+#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN 0x0001 /* Receive Enable */
+#define IRCLK 0x0002 /* Internal Receive Clock Select */
+#define DTYPE_NORM 0x0004 /* Data Format Normal */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define RLSBIT 0x0010 /* Receive Bit Order */
+#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
+#define RFSR 0x0400 /* Receive Frame Sync Required Select */
+#define LRFS 0x1000 /* Low Receive Frame Sync Select */
+#define LARFS 0x2000 /* Late Receive Frame Sync Select */
+#define RCKFE 0x4000 /* Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
+#define RXSE 0x0100 /* RX Secondary Enable */
+#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
+#define RRFST 0x0400 /* Right-First Data Order */
+
+/* SPORTx_STAT Masks */
+#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
+#define RUVF 0x0002 /* Sticky Receive Underflow Status */
+#define ROVF 0x0004 /* Sticky Receive Overflow Status */
+#define TXF 0x0008 /* Transmit FIFO Full Status */
+#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
+#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
+#define TXHRE 0x0040 /* Transmit Hold Register Empty */
+
+/* SPORTx_MCMC1 Macros */
+#define WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
+
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+
+/* SPORTx_MCMC2 Masks */
+#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
+#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
+#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
+#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
+#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
+#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
+#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
+#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
+#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
+#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
+#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
+#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
+#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
+#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
+#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
+#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
+#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
+#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
+#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
+#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
+
+
+/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
+/* EBIU_AMGCTL Masks */
+#define AMCKEN 0x0001 /* Enable CLKOUT */
+#define AMBEN_NONE 0x0000 /* All Banks Disabled */
+#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
+#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
+#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
+#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
+#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
+#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
+#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
+#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
+#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
+#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
+#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
+#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
+#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
+#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
+#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
+#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
+#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
+#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
+#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
+#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
+#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
+#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
+#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
+#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
+#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
+#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
+#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
+#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
+#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
+#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
+#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
+#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
+#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
+#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
+#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
+#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
+#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
+#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
+
+#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
+#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
+#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
+#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
+#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
+#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
+#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
+#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
+#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
+#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
+#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
+#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
+#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
+#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
+#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
+#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
+#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
+#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
+#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
+#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
+#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
+#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
+#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
+#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
+#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
+#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
+#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
+#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
+#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
+#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
+#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
+#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
+#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
+#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
+#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
+#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
+#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
+#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
+#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
+#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
+#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
+#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
+#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
+#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
+#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
+#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
+#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
+#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
+#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
+#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
+#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
+#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
+#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
+#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
+#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
+#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
+#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
+#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
+#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
+#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
+#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
+#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
+#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
+#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
+#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
+#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
+#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
+#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
+#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
+#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
+#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
+
+#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
+#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
+#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
+#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
+#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
+#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
+#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
+#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
+#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
+#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
+#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
+#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
+#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
+#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
+#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
+#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
+#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
+#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
+#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
+#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
+#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
+#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
+#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
+#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
+#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
+#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
+#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
+#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
+#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
+#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
+#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
+#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
+#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
+#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
+#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
+#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
+#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
+#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
+#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
+#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
+#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
+#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
+#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
+#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
+
+
+/* ********************** SDRAM CONTROLLER MASKS **********************************************/
+/* EBIU_SDGCTL Masks */
+#define SCTLE 0x00000001 /* Enable SDRAM Signals */
+#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
+#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
+#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
+#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
+#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
+#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
+#define EBUFE 0x02000000 /* Enable External Buffering Timing */
+#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
+#define EMREN 0x10000000 /* Extended Mode Register Enable */
+#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
+#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE 0x0001 /* Enable SDRAM External Bank */
+#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
+#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
+#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
+#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
+#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
+#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
+#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
+#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
+#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
+#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI 0x0001 /* SDRAM Controller Idle */
+#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
+#define SDPUA 0x0004 /* SDRAM Power-Up Active */
+#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
+#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
+#define BGSTAT 0x0020 /* Bus Grant Status */
+
+
+/* ************************** DMA CONTROLLER MASKS ********************************/
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN 0x0001 /* DMA Channel Enable */
+#define WNR 0x0002 /* Channel Direction (W/R*) */
+#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
+#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
+#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
+#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
+#define SYNC 0x0020 /* DMA Buffer Clear */
+#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
+#define DI_EN 0x0080 /* Data Interrupt Enable */
+#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
+#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
+#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
+#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
+#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
+#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
+#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
+#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
+#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
+#define FLOW_STOP 0x0000 /* Stop Mode */
+#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
+#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
+#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
+#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
+#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
+#define PMAP_PPI 0x0000 /* PPI Port DMA */
+#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
+#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
+#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
+#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
+#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
+#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
+#define PMAP_SPI 0x7000 /* SPI Port DMA */
+#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
+#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
+#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
+#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
+#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
+#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
+#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
+
+
+/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
+/* PPI_CONTROL Masks */
+#define PORT_EN 0x0001 /* PPI Port Enable */
+#define PORT_DIR 0x0002 /* PPI Port Direction */
+#define XFR_TYPE 0x000C /* PPI Transfer Type */
+#define PORT_CFG 0x0030 /* PPI Port Configuration */
+#define FLD_SEL 0x0040 /* PPI Active Field Select */
+#define PACK_EN 0x0080 /* PPI Packing Mode */
+/* previous versions of defBF534.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
+#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
+#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
+#define DLEN_8 0x0000 /* Data Length = 8 Bits */
+#define DLEN_10 0x0800 /* Data Length = 10 Bits */
+#define DLEN_11 0x1000 /* Data Length = 11 Bits */
+#define DLEN_12 0x1800 /* Data Length = 12 Bits */
+#define DLEN_13 0x2000 /* Data Length = 13 Bits */
+#define DLEN_14 0x2800 /* Data Length = 14 Bits */
+#define DLEN_15 0x3000 /* Data Length = 15 Bits */
+#define DLEN_16 0x3800 /* Data Length = 16 Bits */
+#define POLC 0x4000 /* PPI Clock Polarity */
+#define POLS 0x8000 /* PPI Frame Sync Polarity */
+
+/* PPI_STATUS Masks */
+#define FLD 0x0400 /* Field Indicator */
+#define FT_ERR 0x0800 /* Frame Track Error */
+#define OVR 0x1000 /* FIFO Overflow Error */
+#define UNDR 0x2000 /* FIFO Underrun Error */
+#define ERR_DET 0x4000 /* Error Detected Indicator */
+#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
+
+
+/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+
+/* TWI_PRESCALE Masks */
+#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
+#define TWI_ENA 0x0080 /* TWI Enable */
+#define SCCB 0x0200 /* SCCB Compatibility Enable */
+
+/* TWI_SLAVE_CTRL Masks */
+#define SEN 0x0001 /* Slave Enable */
+#define SADD_LEN 0x0002 /* Slave Address Length */
+#define STDVAL 0x0004 /* Slave Transmit Data Valid */
+#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN 0x0010 /* General Call Adrress Matching Enabled */
+
+/* TWI_SLAVE_STAT Masks */
+#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL 0x0002 /* General Call Indicator */
+
+/* TWI_MASTER_CTRL Masks */
+#define MEN 0x0001 /* Master Mode Enable */
+#define MADD_LEN 0x0002 /* Master Address Length */
+#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
+#define FAST 0x0008 /* Use Fast Mode Timing Specs */
+#define STOP 0x0010 /* Issue Stop Condition */
+#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
+#define DCNT 0x3FC0 /* Data Bytes To Transfer */
+#define SDAOVR 0x4000 /* Serial Data Override */
+#define SCLOVR 0x8000 /* Serial Clock Override */
+
+/* TWI_MASTER_STAT Masks */
+#define MPROG 0x0001 /* Master Transfer In Progress */
+#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
+#define ANAK 0x0004 /* Address Not Acknowledged */
+#define DNAK 0x0008 /* Data Not Acknowledged */
+#define BUFRDERR 0x0010 /* Buffer Read Error */
+#define BUFWRERR 0x0020 /* Buffer Write Error */
+#define SDASEN 0x0040 /* Serial Data Sense */
+#define SCLSEN 0x0080 /* Serial Clock Sense */
+#define BUSBUSY 0x0100 /* Bus Busy Indicator */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
+#define SINIT 0x0001 /* Slave Transfer Initiated */
+#define SCOMP 0x0002 /* Slave Transfer Complete */
+#define SERR 0x0004 /* Slave Transfer Error */
+#define SOVF 0x0008 /* Slave Overflow */
+#define MCOMP 0x0010 /* Master Transfer Complete */
+#define MERR 0x0020 /* Master Transfer Error */
+#define XMTSERV 0x0040 /* Transmit FIFO Service */
+#define RCVSERV 0x0080 /* Receive FIFO Service */
+
+/* TWI_FIFO_CTRL Masks */
+#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
+#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
+#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
+#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
+
+/* TWI_FIFO_STAT Masks */
+#define XMTSTAT 0x0003 /* Transmit FIFO Status */
+#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
+#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
+#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
+
+#define RCVSTAT 0x000C /* Receive FIFO Status */
+#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
+#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
+#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
+
+
+/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
+/* CAN_CONTROL Masks */
+#define SRS 0x0001 /* Software Reset */
+#define DNM 0x0002 /* Device Net Mode */
+#define ABO 0x0004 /* Auto-Bus On Enable */
+#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
+#define SMR 0x0020 /* Sleep Mode Request */
+#define CSR 0x0040 /* CAN Suspend Mode Request */
+#define CCR 0x0080 /* CAN Configuration Mode Request */
+
+/* CAN_STATUS Masks */
+#define WT 0x0001 /* TX Warning Flag */
+#define WR 0x0002 /* RX Warning Flag */
+#define EP 0x0004 /* Error Passive Mode */
+#define EBO 0x0008 /* Error Bus Off Mode */
+#define CSA 0x0040 /* Suspend Mode Acknowledge */
+#define CCA 0x0080 /* Configuration Mode Acknowledge */
+#define MBPTR 0x1F00 /* Mailbox Pointer */
+#define TRM 0x4000 /* Transmit Mode */
+#define REC 0x8000 /* Receive Mode */
+
+/* CAN_CLOCK Masks */
+#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
+
+/* CAN_TIMING Masks */
+#define TSEG1 0x000F /* Time Segment 1 */
+#define TSEG2 0x0070 /* Time Segment 2 */
+#define SAM 0x0080 /* Sampling */
+#define SJW 0x0300 /* Synchronization Jump Width */
+
+/* CAN_DEBUG Masks */
+#define DEC 0x0001 /* Disable CAN Error Counters */
+#define DRI 0x0002 /* Disable CAN RX Input */
+#define DTO 0x0004 /* Disable CAN TX Output */
+#define DIL 0x0008 /* Disable CAN Internal Loop */
+#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
+#define MRB 0x0020 /* Mode Read Back Enable */
+#define CDE 0x8000 /* CAN Debug Enable */
+
+/* CAN_CEC Masks */
+#define RXECNT 0x00FF /* Receive Error Counter */
+#define TXECNT 0xFF00 /* Transmit Error Counter */
+
+/* CAN_INTR Masks */
+#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
+#define MBRIF MBRIRQ /* legacy */
+#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
+#define MBTIF MBTIRQ /* legacy */
+#define GIRQ 0x0004 /* Global Interrupt */
+#define SMACK 0x0008 /* Sleep Mode Acknowledge */
+#define CANTX 0x0040 /* CAN TX Bus Value */
+#define CANRX 0x0080 /* CAN RX Bus Value */
+
+/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
+#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
+#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
+#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
+#define BASEID 0x1FFC /* Base Identifier */
+#define IDE 0x2000 /* Identifier Extension */
+#define RTR 0x4000 /* Remote Frame Transmission Request */
+#define AME 0x8000 /* Acceptance Mask Enable */
+
+/* CAN_MBxx_TIMESTAMP Masks */
+#define TSV 0xFFFF /* Timestamp */
+
+/* CAN_MBxx_LENGTH Masks */
+#define DLC 0x000F /* Data Length Code */
+
+/* CAN_AMxxH and CAN_AMxxL Masks */
+#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
+#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
+#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
+#define BASEID 0x1FFC /* Base Identifier */
+#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
+#define FMD 0x4000 /* Full Mask Data Field Enable */
+#define FDF 0x8000 /* Filter On Data Field Enable */
+
+/* CAN_MC1 Masks */
+#define MC0 0x0001 /* Enable Mailbox 0 */
+#define MC1 0x0002 /* Enable Mailbox 1 */
+#define MC2 0x0004 /* Enable Mailbox 2 */
+#define MC3 0x0008 /* Enable Mailbox 3 */
+#define MC4 0x0010 /* Enable Mailbox 4 */
+#define MC5 0x0020 /* Enable Mailbox 5 */
+#define MC6 0x0040 /* Enable Mailbox 6 */
+#define MC7 0x0080 /* Enable Mailbox 7 */
+#define MC8 0x0100 /* Enable Mailbox 8 */
+#define MC9 0x0200 /* Enable Mailbox 9 */
+#define MC10 0x0400 /* Enable Mailbox 10 */
+#define MC11 0x0800 /* Enable Mailbox 11 */
+#define MC12 0x1000 /* Enable Mailbox 12 */
+#define MC13 0x2000 /* Enable Mailbox 13 */
+#define MC14 0x4000 /* Enable Mailbox 14 */
+#define MC15 0x8000 /* Enable Mailbox 15 */
+
+/* CAN_MC2 Masks */
+#define MC16 0x0001 /* Enable Mailbox 16 */
+#define MC17 0x0002 /* Enable Mailbox 17 */
+#define MC18 0x0004 /* Enable Mailbox 18 */
+#define MC19 0x0008 /* Enable Mailbox 19 */
+#define MC20 0x0010 /* Enable Mailbox 20 */
+#define MC21 0x0020 /* Enable Mailbox 21 */
+#define MC22 0x0040 /* Enable Mailbox 22 */
+#define MC23 0x0080 /* Enable Mailbox 23 */
+#define MC24 0x0100 /* Enable Mailbox 24 */
+#define MC25 0x0200 /* Enable Mailbox 25 */
+#define MC26 0x0400 /* Enable Mailbox 26 */
+#define MC27 0x0800 /* Enable Mailbox 27 */
+#define MC28 0x1000 /* Enable Mailbox 28 */
+#define MC29 0x2000 /* Enable Mailbox 29 */
+#define MC30 0x4000 /* Enable Mailbox 30 */
+#define MC31 0x8000 /* Enable Mailbox 31 */
+
+/* CAN_MD1 Masks */
+#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
+#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
+#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
+#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
+#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
+#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
+#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
+#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
+#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
+#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
+#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
+#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
+#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
+#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
+#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
+#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
+
+/* CAN_MD2 Masks */
+#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
+#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
+#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
+#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
+#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
+#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
+#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
+#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
+#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
+#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
+#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
+#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
+#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
+#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
+#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
+#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
+
+/* CAN_RMP1 Masks */
+#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
+#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
+#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
+#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
+#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
+#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
+#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
+#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
+#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
+#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
+#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
+#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
+#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
+#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
+#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
+#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
+
+/* CAN_RMP2 Masks */
+#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
+#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
+#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
+#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
+#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
+#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
+#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
+#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
+#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
+#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
+#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
+#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
+#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
+#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
+#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
+#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
+
+/* CAN_RML1 Masks */
+#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
+#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
+#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
+#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
+#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
+#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
+#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
+#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
+#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
+#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
+#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
+#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
+#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
+#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
+#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
+#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
+
+/* CAN_RML2 Masks */
+#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
+#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
+#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
+#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
+#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
+#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
+#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
+#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
+#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
+#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
+#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
+#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
+#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
+#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
+#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
+#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
+
+/* CAN_OPSS1 Masks */
+#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
+#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
+#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
+#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
+#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
+#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
+#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
+#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
+#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
+#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
+#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
+#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
+#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
+#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
+#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
+#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
+
+/* CAN_OPSS2 Masks */
+#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
+#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
+#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
+#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
+#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
+#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
+#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
+#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
+#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
+#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
+#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
+#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
+#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
+#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
+#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
+#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
+
+/* CAN_TRR1 Masks */
+#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
+#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
+#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
+#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
+#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
+#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
+#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
+#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
+#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
+#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
+#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
+#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
+#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
+#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
+#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
+#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
+
+/* CAN_TRR2 Masks */
+#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
+#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
+#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
+#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
+#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
+#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
+#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
+#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
+#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
+#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
+#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
+#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
+#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
+#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
+#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
+#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
+
+/* CAN_TRS1 Masks */
+#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
+#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
+#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
+#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
+#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
+#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
+#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
+#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
+#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
+#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
+#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
+#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
+#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
+#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
+#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
+#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
+
+/* CAN_TRS2 Masks */
+#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
+#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
+#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
+#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
+#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
+#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
+#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
+#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
+#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
+#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
+#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
+#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
+#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
+#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
+#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
+#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
+
+/* CAN_AA1 Masks */
+#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
+#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
+#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
+#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
+#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
+#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
+#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
+#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
+#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
+#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
+#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
+#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
+#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
+#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
+#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
+#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
+
+/* CAN_AA2 Masks */
+#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
+#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
+#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
+#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
+#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
+#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
+#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
+#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
+#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
+#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
+#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
+#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
+#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
+#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
+#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
+#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
+
+/* CAN_TA1 Masks */
+#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
+#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
+#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
+#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
+#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
+#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
+#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
+#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
+#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
+#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
+#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
+#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
+#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
+#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
+#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
+#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
+
+/* CAN_TA2 Masks */
+#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
+#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
+#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
+#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
+#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
+#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
+#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
+#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
+#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
+#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
+#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
+#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
+#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
+#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
+#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
+#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
+
+/* CAN_MBTD Masks */
+#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
+#define TDA 0x0040 /* Temporary Disable Acknowledge */
+#define TDR 0x0080 /* Temporary Disable Request */
+
+/* CAN_RFH1 Masks */
+#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
+#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
+#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
+#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
+#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
+#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
+#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
+#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
+#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
+#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
+#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
+#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
+#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
+#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
+#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
+#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
+
+/* CAN_RFH2 Masks */
+#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
+#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
+#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
+#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
+#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
+#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
+#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
+#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
+#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
+#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
+#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
+#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
+#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
+#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
+#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
+#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
+
+/* CAN_MBTIF1 Masks */
+#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
+#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
+#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
+#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
+#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
+#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
+#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
+#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
+#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
+#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
+#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
+#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
+#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
+#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
+#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
+#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBTIF2 Masks */
+#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
+#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
+#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
+#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
+#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
+#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
+#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
+#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
+#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
+#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
+#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
+#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
+#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
+#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
+#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
+#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBRIF1 Masks */
+#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
+#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
+#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
+#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
+#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
+#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
+#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
+#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
+#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
+#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
+#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
+#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
+#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
+#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
+#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
+#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBRIF2 Masks */
+#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
+#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
+#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
+#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
+#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
+#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
+#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
+#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
+#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
+#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
+#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
+#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
+#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
+#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
+#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
+#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBIM1 Masks */
+#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
+#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
+#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
+#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
+#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
+#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
+#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
+#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
+#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
+#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
+#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
+#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
+#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
+#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
+#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
+#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
+
+/* CAN_MBIM2 Masks */
+#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
+#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
+#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
+#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
+#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
+#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
+#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
+#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
+#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
+#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
+#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
+#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
+#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
+#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
+#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
+#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
+
+/* CAN_GIM Masks */
+#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
+#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
+#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
+#define BOIM 0x0008 /* Enable Bus Off Interrupt */
+#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
+#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
+#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
+#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
+#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
+#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
+#define ADIM 0x0400 /* Enable Access Denied Interrupt */
+
+/* CAN_GIS Masks */
+#define EWTIS 0x0001 /* TX Error Count IRQ Status */
+#define EWRIS 0x0002 /* RX Error Count IRQ Status */
+#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
+#define BOIS 0x0008 /* Bus Off IRQ Status */
+#define WUIS 0x0010 /* Wake-Up IRQ Status */
+#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
+#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
+#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
+#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
+#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
+#define ADIS 0x0400 /* Access Denied IRQ Status */
+
+/* CAN_GIF Masks */
+#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
+#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
+#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
+#define BOIF 0x0008 /* Bus Off IRQ Flag */
+#define WUIF 0x0010 /* Wake-Up IRQ Flag */
+#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
+#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
+#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
+#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
+#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
+#define ADIF 0x0400 /* Access Denied IRQ Flag */
+
+/* CAN_UCCNF Masks */
+#define UCCNF 0x000F /* Universal Counter Mode */
+#define UC_STAMP 0x0001 /* Timestamp Mode */
+#define UC_WDOG 0x0002 /* Watchdog Mode */
+#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
+#define UC_ERROR 0x0006 /* CAN Error Frame Count */
+#define UC_OVER 0x0007 /* CAN Overload Frame Count */
+#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
+#define UC_AA 0x0009 /* TX Abort Count */
+#define UC_TA 0x000A /* TX Successful Count */
+#define UC_REJECT 0x000B /* RX Message Rejected Count */
+#define UC_RML 0x000C /* RX Message Lost Count */
+#define UC_RX 0x000D /* Total Successful RX Messages Count */
+#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
+#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
+#define UCRC 0x0020 /* Universal Counter Reload/Clear */
+#define UCCT 0x0040 /* Universal Counter CAN Trigger */
+#define UCE 0x0080 /* Universal Counter Enable */
+
+/* CAN_ESR Masks */
+#define ACKE 0x0004 /* Acknowledge Error */
+#define SER 0x0008 /* Stuff Error */
+#define CRCE 0x0010 /* CRC Error */
+#define SA0 0x0020 /* Stuck At Dominant Error */
+#define BEF 0x0040 /* Bit Error Flag */
+#define FER 0x0080 /* Form Error Flag */
+
+/* CAN_EWR Masks */
+#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
+#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
+
+
+/* ******************* PIN CONTROL REGISTER MASKS ************************/
+/* PORT_MUX Masks */
+#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
+#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
+#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
+
+#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
+#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
+#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
+#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
+
+#define PFDE 0x0008 /* Port F DMA Request Enable */
+#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
+#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
+
+#define PFTE 0x0010 /* Port F Timer Enable */
+#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
+#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
+
+#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
+#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
+#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
+
+#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
+#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
+#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
+
+#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
+#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
+#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
+
+#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
+#define PFFE_TIMER 0x0000 /* Enable TMR2 */
+#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
+
+#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
+#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
+#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
+
+#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
+#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
+#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
+
+#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
+#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
+#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
+
+
+/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
+/* HDMAx_CTL Masks */
+#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
+#define REP 0x0002 /* HDMA Request Polarity */
+#define UTE 0x0004 /* Urgency Threshold Enable */
+#define OIE 0x0010 /* Overflow Interrupt Enable */
+#define BDIE 0x0020 /* Block Done Interrupt Enable */
+#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
+#define DRQ 0x0300 /* HDMA Request Type */
+#define DRQ_NONE 0x0000 /* No Request */
+#define DRQ_SINGLE 0x0100 /* Channels Request Single */
+#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
+#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
+#define RBC 0x1000 /* Reload BCNT With IBCNT */
+#define PS 0x2000 /* HDMA Pin Status */
+#define OI 0x4000 /* Overflow Interrupt Generated */
+#define BDI 0x8000 /* Block Done Interrupt Generated */
+
+/* entry addresses of the user-callable Boot ROM functions */
+
+#define _BOOTROM_RESET 0xEF000000
+#define _BOOTROM_FINAL_INIT 0xEF000002
+#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
+#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
+#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
+#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
+#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
+#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
+#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define PGDE_UART PFDE_UART
+#define PGDE_DMA PFDE_DMA
+#define CKELOW SCKELOW
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF534_H */
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * defBF535.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF535 */
+
+#ifndef _DEF_BF535_H
+#define _DEF_BF535_H
+
+#if defined(__ADSPLPBLACKFIN__)
+#warning defBF535.h should only be included for 535 compatible chips.
+#endif
+/* include all Core registers and bit definitions */
+#include <defblackfin.h>
+
+
+/*********************************************************************************** */
+/* Memory Map */
+/*********************************************************************************** */
+
+/* Core MMRs */
+#define COREMMR_BASE 0xFFE00000 /* Core MMRs */
+#define COREMMR_SIZE 0x200000 /* 2MB */
+
+/* System MMRs */
+#define SYSMMR_BASE 0xFFC00000 /* System MMRs */
+#define SYSMMR_SIZE 0x200000 /* 2MB */
+
+/* L1 cache/SRAM internal memory */
+#define L1_DATA_A 0xFF800000 /* L1 Data Bank A */
+#define L1_DATA_B 0xFF900000 /* L1 Data Bank B */
+#define L1_DATA_SIZE 0x4000 /* 16K */
+#define L1_CODE 0xFFA00000 /* L1 Code SRAM */
+#define L1_CODE_SIZE 0x4000 /* 16K */
+#define L1_SCRATCH 0xFFB00000 /* L1 Scratch SRAM */
+#define L1_SCRATCH_SIZE 0x1000 /* 4K */
+
+/* L2 SRAM external memory */
+#define L2_BASE 0xF0000000 /* L2 SRAM */
+#define L2_SIZE 0x40000 /* 256K */
+
+/* PCI Spaces */
+#define PCI_CONFIG_SPACE_PORT 0xEEFFFFFC /* PCI config space reg */
+#define PCI_CONFIG_BASE 0xEEFFFF00 /* PCI config region */
+#define PCI_CONFIG_SIZE 0x10000 /* 64K */
+#define PCI_IO_BASE 0xEEFE0000 /* PCI I/O space */
+#define PCI_IO_SIZE 0x10000 /* 64K */
+#define PCI_MEM_BASE 0xE0000000 /* PCI Mem space */
+#define PCI_MEM_SIZE 0x8000000 /* 64K */
+
+/* Async Memory Banks */
+#define ASYNC_BANK3_BASE 0x2C000000 /* Async Bank 3 */
+#define ASYNC_BANK3_SIZE 0x4000000 /* 64 MB */
+#define ASYNC_BANK2_BASE 0x28000000 /* Async Bank 2 */
+#define ASYNC_BANK2_SIZE 0x4000000 /* 64 MB */
+#define ASYNC_BANK1_BASE 0x24000000 /* Async Bank 1 */
+#define ASYNC_BANK1_SIZE 0x4000000 /* 64 MB */
+#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
+#define ASYNC_BANK0_SIZE 0x4000000 /* 64 MB */
+
+/* Sync DRAM Banks */
+#define SDRAM_BANK3_BASE 0x18000000 /* Sync Bank 3 */
+#define SDRAM_BANK2_BASE 0x10000000 /* Sync Bank 2 */
+#define SDRAM_BANK1_BASE 0x08000000 /* Sync Bank 1 */
+#define SDRAM_BANK0_BASE 0x00000000 /* Sync Bank 0 */
+
+
+/*********************************************************************************** */
+/* System MMR Register Map */
+/*********************************************************************************** */
+
+/* L2 MISR MMRs (0xFFC0 0000-0xFFC0 03FF) */
+#define MISR_CTL 0xFFC00000 /* Control Register */
+#define MISR_RMISR0 0xFFC00004 /* coreL2[31:0] read bus */
+#define MISR_RMISR1 0xFFC00008 /* coreL2[63:32] read bus */
+#define MISR_RMISR2 0xFFC0000C /* sysL2[31:0] read bus */
+#define MISR_WMISR0 0xFFC00010 /* coreL2[31:0] write bus */
+#define MISR_WMISR1 0xFFC00014 /* coreL2[63:32] write bus */
+#define MISR_WMISR2 0xFFC00018 /* sysL2[31:0] write bus */
+
+/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
+#define PLL_CTL 0xFFC00400 /* PLL Control register (32-bit) */
+#define PLL_STAT 0xFFC00404 /* PLL Status register */
+#define PLL_LOCKCNT 0xFFC00406 /* PLL Lock Counter register */
+#define PLL_IOCKR 0xFFC00408 /* Peripheral Clock Enable register (32-bit) */
+#define PLL_IOCK 0xFFC00408 /* Peripheral Clock Enable register (32-bit) - alternate spelling */
+#define SWRST 0xFFC00410 /* Software Reset Register */
+
+#define PLLCTL PLL_CTL
+#define PLLSTAT PLL_STAT
+#define LOCKCNT PLL_LOCKCNT
+#define IOCKR PLL_IOCKR
+
+#define SYSCR 0xFFC00414 /* System Configuration register (RCSR) */
+
+/* JTAG/Debug Communication Channel (0xFFC0 0800-0xFFC0 0BFF) */
+#define CHIPID 0xFFC048C0 /* Device ID Register */
+
+/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
+#define SIC_RVECT 0xFFC00C00 /* Reset Vector Register */
+#define SIC_IAR0 0xFFC00C04 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00C08 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00C0C /* Interrupt Assignment Register 2 */
+#define SIC_IMASK 0xFFC00C10 /* Interrupt Mask Register */
+#define SIC_ISR 0xFFC00C14 /* Interrupt Status Register */
+#define SIC_IWR 0xFFC00C18 /* Interrupt Wakeup Register */
+
+/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
+#define WDOGCTL 0xFFC01000 /* Watchdog Control Register */
+#define WDOGCNT 0xFFC01004 /* Watchdog Count Register */
+#define WDOGSTAT 0xFFC01008 /* Watchdog Status Register */
+
+#define WDOG_CTL WDOGCTL
+#define WDOG_CNT WDOGCNT
+#define WDOG_STAT WDOGSTAT
+
+/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
+#define RTCSTAT 0xFFC01400 /* RTC Status Register */
+#define RTCICTL 0xFFC01404 /* RTC Interrupt Control Register */
+#define RTCISTAT 0xFFC01408 /* RTC Interrupt Status Register */
+#define RTCSWCNT 0xFFC0140C /* RTC Stopwatch Count Register */
+#define RTCALARM 0xFFC01410 /* RTC Alarm Time Register */
+#define RTCFAST 0xFFC01414 /* RTC Prescaler Control Register */
+
+#define RTC_STAT RTCSTAT
+#define RTC_ICTL RTCICTL
+#define RTC_ISTAT RTCISTAT
+#define RTC_SWCNT RTCSWCNT
+#define RTC_ALARM RTCALARM
+#define RTC_FAST RTCFAST
+
+/* UART 0 Controller (0xFFC0 1800-0xFFC0 1BFF) */
+#define UART0_THR 0xFFC01800 /* Transmit Holding register */
+#define UART0_RBR 0xFFC01800 /* Receive Buffer register */
+#define UART0_DLL 0xFFC01800 /* Divisor Latch (Low-Byte) */
+#define UART0_IER 0xFFC01802 /* Interrupt Enable Register */
+#define UART0_DLH 0xFFC01802 /* Divisor Latch (High-Byte) */
+#define UART0_IIR 0xFFC01804 /* Interrupt Identification Register */
+#define UART0_LCR 0xFFC01806 /* Line Control Register */
+#define UART0_MCR 0xFFC01808 /* Module Control Register */
+#define UART0_LSR 0xFFC0180A /* Line Status Register */
+#define UART0_MSR 0xFFC0180C /* MSR Modem Status Register */
+#define UART0_SCR 0xFFC0180E /* SCR Scratch Register */
+#define UART0_IRCR 0xFFC01810 /* IRCR IrDA Control Register */
+#define UART0_CURR_PTR_RX 0xFFC01A00 /* UART -DMA RCV Current Pointer register */
+#define UART0_CONFIG_RX 0xFFC01A02 /* UART -RCV DMA Configuration register */
+#define UART0_START_ADDR_HI_RX 0xFFC01A04 /* UART -RCV DMA Start Page register */
+#define UART0_START_ADDR_LO_RX 0xFFC01A06 /* UART -RCV DMA Start Address register */
+#define UART0_COUNT_RX 0xFFC01A08 /* UART -RCV DMA Count register */
+#define UART0_NEXT_DESCR_RX 0xFFC01A0A /* UART -RCV DMA Next Descriptor Pointer register */
+#define UART0_DESCR_RDY_RX 0xFFC01A0C /* UART -RCV DMA Descriptor Ready */
+#define UART0_IRQSTAT_RX 0xFFC01A0E /* UART -RCV DMA Interrupt Register */
+#define UART0_CURR_PTR_TX 0xFFC01B00 /* UART -XMT DMA Current Pointer register */
+#define UART0_CONFIG_TX 0xFFC01B02 /* UART -XMT DMA Configuration register */
+#define UART0_START_ADDR_HI_TX 0xFFC01B04 /* UART -XMT DMA Start Page register */
+#define UART0_START_ADDR_LO_TX 0xFFC01B06 /* UART -XMT DMA Start Address register */
+#define UART0_COUNT_TX 0xFFC01B08 /* UART -XMT DMA Count register */
+#define UART0_NEXT_DESCR_TX 0xFFC01B0A /* UART -XMT DMA Next Descriptor Pointer register */
+#define UART0_DESCR_RDY_TX 0xFFC01B0C /* UART -XMT DMA Descriptor Ready */
+#define UART0_IRQSTAT_TX 0xFFC01B0E /* UART -XMT DMA Interrupt register */
+
+/* UART 1 Controller (0xFFC0 1C00-0xFFC0 1FFF) */
+#define UART1_THR 0xFFC01C00 /* Transmit Holding register */
+#define UART1_RBR 0xFFC01C00 /* Receive Buffer register */
+#define UART1_DLL 0xFFC01C00 /* Divisor Latch (Low-Byte) */
+#define UART1_IER 0xFFC01C02 /* Interrupt Enable Register */
+#define UART1_DLH 0xFFC01C02 /* Divisor Latch (High-Byte) */
+#define UART1_IIR 0xFFC01C04 /* Interrupt Identification Register */
+#define UART1_LCR 0xFFC01C06 /* Line Control Register */
+#define UART1_MCR 0xFFC01C08 /* Module Control Register */
+#define UART1_LSR 0xFFC01C0A /* Line Status Register */
+#define UART1_MSR 0xFFC01C0C /* MSR Modem Status Register */
+#define UART1_SCR 0xFFC01C0E /* SCR Scratch Register */
+#define UART1_CURR_PTR_RX 0xFFC01E00 /* UART -DMA RCV Current Pointer register */
+#define UART1_CONFIG_RX 0xFFC01E02 /* UART -RCV DMA Configuration register */
+#define UART1_START_ADDR_HI_RX 0xFFC01E04 /* UART -RCV DMA Start Page register */
+#define UART1_START_ADDR_LO_RX 0xFFC01E06 /* UART -RCV DMA Start Address register */
+#define UART1_COUNT_RX 0xFFC01E08 /* UART -RCV DMA Count register */
+#define UART1_NEXT_DESCR_RX 0xFFC01E0A /* UART -RCV DMA Next Descriptor Pointer register */
+#define UART1_DESCR_RDY_RX 0xFFC01E0C /* UART -RCV DMA Descriptor Ready */
+#define UART1_IRQSTAT_RX 0xFFC01E0E /* UART -RCV DMA Interrupt Register */
+#define UART1_CURR_PTR_TX 0xFFC01F00 /* UART -XMT DMA Current Pointer register */
+#define UART1_CONFIG_TX 0xFFC01F02 /* UART -XMT DMA Configuration register */
+#define UART1_START_ADDR_HI_TX 0xFFC01F04 /* UART -XMT DMA Start Page register */
+#define UART1_START_ADDR_LO_TX 0xFFC01F06 /* UART -XMT DMA Start Address register */
+#define UART1_COUNT_TX 0xFFC01F08 /* UART -XMT DMA Count register */
+#define UART1_NEXT_DESCR_TX 0xFFC01F0A /* UART -XMT DMA Next Descriptor Pointer register */
+#define UART1_DESCR_RDY_TX 0xFFC01F0C /* UART -XMT DMA Descriptor Ready */
+#define UART1_IRQSTAT_TX 0xFFC01F0E /* UART -XMT DMA Interrupt register */
+
+/* TIMER 0, 1, 2 Registers (0xFFC0 2000-0xFFC0 23FF) */
+#define TIMER0_STATUS 0xFFC02000 /* Timer 0 Global Status and Sticky Register */
+#define TIMER0_CONFIG 0xFFC02002 /* Timer 0 configuration Register */
+#define TIMER0_COUNTER_LO 0xFFC02004 /* Timer 0 Counter Register (low word) */
+#define TIMER0_COUNTER_HI 0xFFC02006 /* Timer 0 Counter Register (high word) */
+#define TIMER0_PERIOD_LO 0xFFC02008 /* Timer 0 Period Register (low word) */
+#define TIMER0_PERIOD_HI 0xFFC0200A /* Timer 0 Period Register (high word) */
+#define TIMER0_WIDTH_LO 0xFFC0200C /* Timer 0 Width Register (low word) */
+#define TIMER0_WIDTH_HI 0xFFC0200E /* Timer 0 Width Register (high word) */
+#define TIMER1_STATUS 0xFFC02010 /* Timer 1 Global Status and Sticky Register */
+#define TIMER1_CONFIG 0xFFC02012 /* Timer 1 configuration register */
+#define TIMER1_COUNTER_LO 0xFFC02014 /* Timer 1 Counter Register (low word) */
+#define TIMER1_COUNTER_HI 0xFFC02016 /* Timer 1 Counter Register (high word) */
+#define TIMER1_PERIOD_LO 0xFFC02018 /* Timer 1 Period Register (low word) */
+#define TIMER1_PERIOD_HI 0xFFC0201A /* Timer 1 Period Register (high word) */
+#define TIMER1_WIDTH_LO 0xFFC0201C /* Timer 1 Width Register (low word) */
+#define TIMER1_WIDTH_HI 0xFFC0201E /* Timer 1 Width Register (high word) */
+#define TIMER2_STATUS 0xFFC02020 /* Timer 2 Global Status and Sticky Register */
+#define TIMER2_CONFIG 0xFFC02022 /* Timer 2 configuration register */
+#define TIMER2_COUNTER_LO 0xFFC02024 /* Timer 2 Counter Register (low word) */
+#define TIMER2_COUNTER_HI 0xFFC02026 /* Timer 2 Counter Register (high word) */
+#define TIMER2_PERIOD_LO 0xFFC02028 /* Timer 2 Period Register (low word) */
+#define TIMER2_PERIOD_HI 0xFFC0202A /* Timer 2 Period Register (high word) */
+#define TIMER2_WIDTH_LO 0xFFC0202C /* Timer 2 Width Register (low word) */
+#define TIMER2_WIDTH_HI 0xFFC0202E /* Timer 2 Width Register (high word) */
+
+/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
+#define FIO_DIR 0xFFC02400 /* Peripheral Flag Direction Register */
+#define FIO_FLAG_C 0xFFC02404 /* Peripheral Interrupt Flag Register (clear) */
+#define FIO_FLAG_S 0xFFC02406 /* Peripheral Interrupt Flag Register (set) */
+#define FIO_MASKA_C 0xFFC02408 /* Flag Mask Interrupt A Register (clear) */
+#define FIO_MASKA_S 0xFFC0240A /* Flag Mask Interrupt A Register (set) */
+#define FIO_MASKB_C 0xFFC0240C /* Flag Mask Interrupt B Register (clear) */
+#define FIO_MASKB_S 0xFFC0240E /* Flag Mask Interrupt B Register (set) */
+#define FIO_POLAR 0xFFC02410 /* Flag Source Polarity Register */
+#define FIO_EDGE 0xFFC02414 /* Flag Source Sensitivity Register */
+#define FIO_BOTH 0xFFC02418 /* Flag Set on BOTH Edges Register */
+
+/* SPORT0 Controller (0xFFC0 2800-0xFFC0 2BFF) */
+#define SPORT0_TX_CONFIG 0xFFC02800 /* SPORT0 Transmit Configuration Register */
+#define SPORT0_RX_CONFIG 0xFFC02802 /* SPORT0 Receive Configuration Register */
+#define SPORT0_TX 0xFFC02804 /* SPORT0 TX transmit Register */
+#define SPORT0_RX 0xFFC02806 /* SPORT0 RX Receive register */
+#define SPORT0_TSCLKDIV 0xFFC02808 /* SPORT0 Transmit Serial Clock Divider */
+#define SPORT0_RSCLKDIV 0xFFC0280A /* SPORT0 Receive Serial Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0280C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_RFSDIV 0xFFC0280E /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC02810 /* SPORT0 Status Register */
+#define SPORT0_MTCS0 0xFFC02812 /* SPORT0 Multi-Channel Transmit Select Register */
+#define SPORT0_MTCS1 0xFFC02814 /* SPORT0 Multi-Channel Transmit Select Register */
+#define SPORT0_MTCS2 0xFFC02816 /* SPORT0 Multi-Channel Transmit Select Register */
+#define SPORT0_MTCS3 0xFFC02818 /* SPORT0 Multi-Channel Transmit Select Register */
+#define SPORT0_MTCS4 0xFFC0281A /* SPORT0 Multi-Channel Transmit Select Register */
+#define SPORT0_MTCS5 0xFFC0281C /* SPORT0 Multi-Channel Transmit Select Register */
+#define SPORT0_MTCS6 0xFFC0281E /* SPORT0 Multi-Channel Transmit Select Register */
+#define SPORT0_MTCS7 0xFFC02820 /* SPORT0 Multi-Channel Transmit Select Register */
+#define SPORT0_MRCS0 0xFFC02822 /* SPORT0 Multi-Channel Receive Select Register */
+#define SPORT0_MRCS1 0xFFC02824 /* SPORT0 Multi-Channel Receive Select Register */
+#define SPORT0_MRCS2 0xFFC02826 /* SPORT0 Multi-Channel Receive Select Register */
+#define SPORT0_MRCS3 0xFFC02828 /* SPORT0 Multi-Channel Receive Select Register */
+#define SPORT0_MRCS4 0xFFC0282A /* SPORT0 Multi-Channel Receive Select Register */
+#define SPORT0_MRCS5 0xFFC0282C /* SPORT0 Multi-Channel Receive Select Register */
+#define SPORT0_MRCS6 0xFFC0282E /* SPORT0 Multi-Channel Receive Select Register */
+#define SPORT0_MRCS7 0xFFC02830 /* SPORT0 Multi-Channel Receive Select Register */
+#define SPORT0_MCMC1 0xFFC02832 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC02834 /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_CURR_PTR_RX 0xFFC02A00 /* SPORT0 -RCV DMA Current Pointer */
+#define SPORT0_CONFIG_DMA_RX 0xFFC02A02 /* SPORT0 -RCV DMA Configuration */
+#define SPORT0_START_ADDR_HI_RX 0xFFC02A04 /* SPORT0 -RCV DMA Start Page */
+#define SPORT0_START_ADDR_LO_RX 0xFFC02A06 /* SPORT0 -RCV DMA Start Address */
+#define SPORT0_COUNT_RX 0xFFC02A08 /* SPORT0 -RCV DMA Count */
+#define SPORT0_NEXT_DESCR_RX 0xFFC02A0A /* SPORT0 -RCV DMA Next Descriptor Pointer */
+#define SPORT0_DESCR_RDY_RX 0xFFC02A0C /* SPORT0 -RCV DMA Descriptor Ready */
+#define SPORT0_IRQSTAT_RX 0xFFC02A0E /* SPORT0 -RCV DMA Interrupt Register */
+#define SPORT0_CURR_PTR_TX 0xFFC02B00 /* SPORT0 -XMT DMA Current Pointer */
+#define SPORT0_CONFIG_DMA_TX 0xFFC02B02 /* SPORT0 -XMT DMA Configuration */
+#define SPORT0_START_ADDR_HI_TX 0xFFC02B04 /* SPORT0 -XMT DMA Start Page */
+#define SPORT0_START_ADDR_LO_TX 0xFFC02B06 /* SPORT0 -XMT DMA Start Address */
+#define SPORT0_COUNT_TX 0xFFC02B08 /* SPORT0 -XMT DMA Count */
+#define SPORT0_NEXT_DESCR_TX 0xFFC02B0A /* SPORT0 -XMT DMA Next Descriptor Pointer */
+#define SPORT0_DESCR_RDY_TX 0xFFC02B0C /* SPORT0 -XMT DMA Descriptor Ready */
+#define SPORT0_IRQSTAT_TX 0xFFC02B0E /* SPORT0 -XMT DMA Interrupt Register */
+
+/* SPORT1 Controller (0xFFC0 2C00-0xFFC0 2FFF) */
+#define SPORT1_TX_CONFIG 0xFFC02C00 /* SPORT1 Transmit Configuration Register */
+#define SPORT1_RX_CONFIG 0xFFC02C02 /* SPORT1 Receive Configuration Register */
+#define SPORT1_TX 0xFFC02C04 /* SPORT1 TX transmit Register */
+#define SPORT1_RX 0xFFC02C06 /* SPORT1 RX Receive register */
+#define SPORT1_TSCLKDIV 0xFFC02C08 /* SPORT1 Transmit Serial Clock Divider */
+#define SPORT1_RSCLKDIV 0xFFC02C0A /* SPORT1 Receive Serial Clock Divider */
+#define SPORT1_TFSDIV 0xFFC02C0C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_RFSDIV 0xFFC02C0E /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC02C10 /* SPORT1 Status Register */
+#define SPORT1_MTCS0 0xFFC02C12 /* SPORT1 Multi-Channel Transmit Select Register */
+#define SPORT1_MTCS1 0xFFC02C14 /* SPORT1 Multi-Channel Transmit Select Register */
+#define SPORT1_MTCS2 0xFFC02C16 /* SPORT1 Multi-Channel Transmit Select Register */
+#define SPORT1_MTCS3 0xFFC02C18 /* SPORT1 Multi-Channel Transmit Select Register */
+#define SPORT1_MTCS4 0xFFC02C1A /* SPORT1 Multi-Channel Transmit Select Register */
+#define SPORT1_MTCS5 0xFFC02C1C /* SPORT1 Multi-Channel Transmit Select Register */
+#define SPORT1_MTCS6 0xFFC02C1E /* SPORT1 Multi-Channel Transmit Select Register */
+#define SPORT1_MTCS7 0xFFC02C20 /* SPORT1 Multi-Channel Transmit Select Register */
+#define SPORT1_MRCS0 0xFFC02C22 /* SPORT1 Multi-Channel Receive Select Register */
+#define SPORT1_MRCS1 0xFFC02C24 /* SPORT1 Multi-Channel Receive Select Register */
+#define SPORT1_MRCS2 0xFFC02C26 /* SPORT1 Multi-Channel Receive Select Register */
+#define SPORT1_MRCS3 0xFFC02C28 /* SPORT1 Multi-Channel Receive Select Register */
+#define SPORT1_MRCS4 0xFFC02C2A /* SPORT1 Multi-Channel Receive Select Register */
+#define SPORT1_MRCS5 0xFFC02C2C /* SPORT1 Multi-Channel Receive Select Register */
+#define SPORT1_MRCS6 0xFFC02C2E /* SPORT1 Multi-Channel Receive Select Register */
+#define SPORT1_MRCS7 0xFFC02C30 /* SPORT1 Multi-Channel Receive Select Register */
+#define SPORT1_MCMC1 0xFFC02C32 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC02C34 /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_CURR_PTR_RX 0xFFC02E00 /* SPORT1 -RCV DMA Current Pointer */
+#define SPORT1_CONFIG_DMA_RX 0xFFC02E02 /* SPORT1 -RCV DMA Configuration */
+#define SPORT1_START_ADDR_HI_RX 0xFFC02E04 /* SPORT1 -RCV DMA Start Page */
+#define SPORT1_START_ADDR_LO_RX 0xFFC02E06 /* SPORT1 -RCV DMA Start Address */
+#define SPORT1_COUNT_RX 0xFFC02E08 /* SPORT1 -RCV DMA Count */
+#define SPORT1_NEXT_DESCR_RX 0xFFC02E0A /* SPORT1 -RCV DMA Next Descriptor Pointer */
+#define SPORT1_DESCR_RDY_RX 0xFFC02E0C /* SPORT1 -RCV DMA Descriptor Ready */
+#define SPORT1_IRQSTAT_RX 0xFFC02E0E /* SPORT1 -RCV DMA Interrupt Register */
+#define SPORT1_CURR_PTR_TX 0xFFC02F00 /* SPORT1 -XMT DMA Current Pointer */
+#define SPORT1_CONFIG_DMA_TX 0xFFC02F02 /* SPORT1 -XMT DMA Configuration */
+#define SPORT1_START_ADDR_HI_TX 0xFFC02F04 /* SPORT1 -XMT DMA Start Page */
+#define SPORT1_START_ADDR_LO_TX 0xFFC02F06 /* SPORT1 -XMT DMA Start Address */
+#define SPORT1_COUNT_TX 0xFFC02F08 /* SPORT1 -XMT DMA Count */
+#define SPORT1_NEXT_DESCR_TX 0xFFC02F0A /* SPORT1 -XMT DMA Next Descriptor Pointer */
+#define SPORT1_DESCR_RDY_TX 0xFFC02F0C /* SPORT1 -XMT DMA Descriptor Ready */
+#define SPORT1_IRQSTAT_TX 0xFFC02F0E /* SPORT1 -XMT DMA Interrupt Register */
+
+/* SPI 0 Controller (0xFFC0 3000-0xFFC0 33FF) */
+#define SPI0_CTL 0xFFC03000 /* SPI0 Control Register */
+#define SPI0_FLG 0xFFC03002 /* SPI0 Flag register */
+#define SPI0_ST 0xFFC03004 /* SPI0 Status register */
+#define SPI0_TDBR 0xFFC03006 /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR 0xFFC03008 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD 0xFFC0300A /* SPI0 Baud rate Register */
+#define SPI0_SHADOW 0xFFC0300C
+#define SPI0_CURR_PTR 0xFFC03200 /* SPI0 -DMA Current Pointer register */
+#define SPI0_CONFIG 0xFFC03202 /* SPI0 -DMA Configuration register */
+#define SPI0_START_ADDR_HI 0xFFC03204 /* SPI0 -DMA Start Page register */
+#define SPI0_START_ADDR_LO 0xFFC03206 /* SPI0 -DMA Start Address register */
+#define SPI0_COUNT 0xFFC03208 /* SPI0 -DMA Count register */
+#define SPI0_NEXT_DESCR 0xFFC0320A /* SPI0 -DMA Next Descriptor Pointer */
+#define SPI0_DESCR_RDY 0xFFC0320C /* SPI0 -DMA Descriptor Ready */
+#define SPI0_DMA_INT 0xFFC0320E /* SPI0 -DMA Interrupt register */
+
+/* SPI 1 Controller (0xFFC0 3400-0xFFC0 37FF) */
+#define SPI1_CTL 0xFFC03400 /* SPI1 Control Register */
+#define SPI1_FLG 0xFFC03402 /* SPI1 Flag register */
+#define SPI1_ST 0xFFC03404 /* SPI1 Status register */
+#define SPI1_TDBR 0xFFC03406 /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR 0xFFC03408 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD 0xFFC0340A /* SPI1 Baud rate Register */
+#define SPI1_SHADOW 0xFFC0340C
+#define SPI1_CURR_PTR 0xFFC03600 /* SPI1 -DMA Current Pointer register */
+#define SPI1_CONFIG 0xFFC03602 /* SPI1 -DMA Configuration register */
+#define SPI1_START_ADDR_HI 0xFFC03604 /* SPI1 -DMA Start Page register */
+#define SPI1_START_ADDR_LO 0xFFC03606 /* SPI1 -DMA Start Address register */
+#define SPI1_COUNT 0xFFC03608 /* SPI1 -DMA Count register */
+#define SPI1_NEXT_DESCR 0xFFC0360A /* SPI1 -DMA Next Descriptor Pointer */
+#define SPI1_DESCR_RDY 0xFFC0360C /* SPI1 -DMA Descriptor Ready */
+#define SPI1_DMA_INT 0xFFC0360E /* SPI1 -DMA Interrupt register */
+
+/* Memory DMA Controller (0xFFC0 3800-0xFFC0 3BFF) */
+#define MDD_DCP 0xFFC03800 /* Current Pointer - Write Channel */
+#define MDD_DCFG 0xFFC03802 /* DMA Configuration - Write Channel */
+#define MDD_DSAH 0xFFC03804 /* Start Address Hi - Write Channel */
+#define MDD_DSAL 0xFFC03806 /* Start Address Lo - Write Channel */
+#define MDD_DCT 0xFFC03808 /* DMA Count - Write Channel */
+#define MDD_DND 0xFFC0380A /* Next Descriptor Pointer - Write Channel */
+#define MDD_DDR 0xFFC0380C /* Descriptor Ready - Write Channel */
+#define MDD_DI 0xFFC0380E /* DMA Interrupt - Write Channel */
+#define MDS_DCP 0xFFC03900 /* Current Pointer - Read Channel */
+#define MDS_DCFG 0xFFC03902 /* DMA Configuration - Read Channel */
+#define MDS_DSAH 0xFFC03904 /* Start Address Hi - Read Channel */
+#define MDS_DSAL 0xFFC03906 /* Start Address Lo - Read Channel */
+#define MDS_DCT 0xFFC03908 /* DMA Count - Read Channel */
+#define MDS_DND 0xFFC0390A /* Next Descriptor Pointer - Read Channel */
+#define MDS_DDR 0xFFC0390C /* Descriptor Ready - Read Channel */
+#define MDS_DI 0xFFC0390E /* DMA Interrupt - Read Channel */
+
+/* For backwards-compatibility with VDSP++3.0 and earlier code... */
+#define MDW_DCP MDD_DCP
+#define MDW_DCFG MDD_DCFG
+#define MDW_DSAH MDD_DSAH
+#define MDW_DSAL MDD_DSAL
+#define MDW_DCT MDD_DCT
+#define MDW_DND MDD_DND
+#define MDW_DDR MDD_DDR
+#define MDW_DI MDD_DI
+#define MDR_DCP MDS_DCP
+#define MDR_DCFG MDS_DCFG
+#define MDR_DSAH MDS_DSAH
+#define MDR_DSAL MDS_DSAL
+#define MDR_DCT MDS_DCT
+#define MDR_DND MDS_DND
+#define MDR_DDR MDS_DDR
+#define MDR_DI MDS_DI
+
+/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
+#define EBIU_AMGCTL 0xFFC03C00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC03C04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC03C08 /* Asynchronous Memory Bank Control Register 1 */
+
+/* PCI Bridge PAB Registers (0xFFC0 4000-0xFFC0 43FF) */
+#define PCI_CTL 0xFFC04000 /* PCI Bridge Control */
+#define PCI_CTL_HOST 0x01
+#define PCI_CTL_ENABPCI 0x02
+#define PCI_CTL_FASTBCK2BCK 0x04
+#define PCI_CTL_ENABINTA 0x08
+#define PCI_CTL_OUTPUTINTA 0x10
+#define PCI_CTL_ENABRST 0x20
+#define PCI_CTL_OUTPUTRST 0x40
+
+
+#define PCI_STAT 0xFFC04004 /* PCI Bridge Status */
+#define PCI_STAT_INTA 0x0001
+#define PCI_STAT_INTB 0x0002
+#define PCI_STAT_INTC 0x0004
+#define PCI_STAT_INTD 0x0008
+#define PCI_STAT_PARERR 0x0010
+#define PCI_STAT_FATERR 0x0020
+#define PCI_STAT_RESET 0x0040
+#define PCI_STAT_TXEMPTY 0x0080
+#define PCI_STAT_TXFULL 0x0100
+#define PCI_STAT_QUEFULL 0x0200
+#define PCI_STAT_MEMWRINV 0x0400
+#define PCI_STAT_INRDERR 0x0800
+#define PCI_STAT_INWRERR 0x1000
+#define PCI_STAT_INVEABACC 0x2000
+#define PCI_STAT_SYSERR 0x4000
+
+#define PCI_ICTL 0xFFC04008 /* PCI Bridge Interrupt Control */
+#define PCI_ICTL_INTA 0x0001
+#define PCI_ICTL_INTB 0x0002
+#define PCI_ICTL_INTC 0x0004
+#define PCI_ICTL_INTD 0x0008
+#define PCI_ICTL_PARERR 0x0010
+#define PCI_ICTL_FATERR 0x0020
+#define PCI_ICTL_RESET 0x0040
+#define PCI_ICTL_TXFULL 0x0080
+#define PCI_ICTL_MEMWRINV 0x0400
+#define PCI_ICTL_INRDERR 0x0800
+#define PCI_ICTL_INWRERR 0x1000
+#define PCI_ICTL_INVEABACC 0x2000
+#define PCI_ICTL_SYSERR 0x4000
+
+#define PCI_MBAP 0xFFC0400C /* PCI Memory Space Base Address Pointer [31:27] */
+#define PCI_IBAP 0xFFC04010 /* PCI IO Space Base Address Pointer */
+#define PCI_CBAP 0xFFC04014 /* PCI Config Space Base Address Port */
+#define PCI_TMBAP 0xFFC04018 /* PCI to BF535 Memory Base Address Pointer */
+#define PCI_TIBAP 0xFFC0401C /* PCI to BF535 IO Base Address Pointer */
+
+/* PCI Bridge External Access Bus Registers (0xEEFF FF00-0xEEFF FFFF) */
+#define PCI_DMBARM 0xEEFFFF00 /* PCI Device Memory Bar Mask */
+#define PCI_DIBARM 0xEEFFFF04 /* PCI Device IO Bar Mask */
+#define PCI_CFG_DIC 0xEEFFFF08 /* PCI Config Device ID */
+#define PCI_CFG_VIC 0xEEFFFF0C /* PCI Config Vendor ID */
+#define PCI_CFG_STAT 0xEEFFFF10 /* PCI Config Status (Read-only) */
+#define PCI_CFG_CMD 0xEEFFFF14 /* PCI Config Command */
+#define PCI_CFG_CC 0xEEFFFF18 /* PCI Config Class Code */
+#define PCI_CFG_RID 0xEEFFFF1C /* PCI Config Revision ID */
+#define PCI_CFG_BIST 0xEEFFFF20 /* PCI Config BIST */
+#define PCI_CFG_HT 0xEEFFFF24 /* PCI Config Header Type */
+#define PCI_CFG_MLT 0xEEFFFF28 /* PCI Config Memory Latency Timer */
+#define PCI_CFG_CLS 0xEEFFFF2C /* PCI Config Cache Line Size */
+#define PCI_CFG_MBAR 0xEEFFFF30 /* PCI Config Memory Base Address Register */
+#define PCI_CFG_IBAR 0xEEFFFF34 /* PCI Config IO Base Address Register */
+#define PCI_CFG_SID 0xEEFFFF38 /* PCI Config Sub-system ID */
+#define PCI_CFG_SVID 0xEEFFFF3C /* PCI Config Sub-system Vendor ID */
+#define PCI_CFG_MAXL 0xEEFFFF40 /* PCI Config Maximum Latency Cycles */
+#define PCI_CFG_MING 0xEEFFFF44 /* PCI Config Minimum Grant Cycles */
+#define PCI_CFG_IP 0xEEFFFF48 /* PCI Config Interrupt Pin */
+#define PCI_CFG_IL 0xEEFFFF4C /* PCI Config Interrupt Line */
+#define PCI_HMCTL 0xEEFFFF50 /* PCI Blocking BAR Host Mode Control */
+
+#define PCI_HMCTL_SYSMMRENAB 0x1
+#define PCI_HMCTL_L2ENAB 0x2
+#define PCI_HMCTL_ASYNCENAB 0x4
+#define PCI_HMCTL_ASYNCSIZE 0x18 /* 00-64MB, 01-128MB, 10-192MB, 11-256MB */
+#define PCI_HMCTL_SDRAMENAB 0x20
+#define PCI_HMCTL_SDRAMSIZE 0x7C0 /* 0-32MB, 1-64MB, 2-96MB, 128MB, 160MB */
+
+/* USB Registers (0xFFC0 4400 - 0xFFC0 47FF) */
+#define USBD_ID 0xFFC04400 /* USB Device ID Register */
+#define USBD_FRM 0xFFC04402 /* Current USB Frame Number */
+#define USBD_FRMAT 0xFFC04404 /* Match value for USB frame number. */
+#define USBD_EPBUF 0xFFC04406 /* Enables Download of Configuration Into UDC Core */
+#define USBD_STAT 0xFFC04408 /* Returns USBD Module Status */
+#define USBD_CTRL 0xFFC0440A /* Allows Configuration and Control of USBD Module. */
+#define USBD_GINTR 0xFFC0440C /* Global Interrupt Register */
+#define USBD_GMASK 0xFFC0440E /* Global Interrupt Register Mask */
+#define USBD_DMACFG 0xFFC04440 /* DMA Master Channel Configuration Register */
+#define USBD_DMABL 0xFFC04442 /* DMA Master Channel Base Address, Low */
+#define USBD_DMABH 0xFFC04444 /* DMA Master Channel Base Address, High */
+#define USBD_DMACT 0xFFC04446 /* DMA Master Channel Count Register */
+#define USBD_DMAIRQ 0xFFC04448 /* DMA Master Channel DMA Count Register */
+#define USBD_INTR0 0xFFC04480 /* USB Endpoint 0 Interrupt Register */
+#define USBD_MASK0 0xFFC04482 /* USB Endpoint 0 Mask Register */
+#define USBD_EPCFG0 0xFFC04484 /* USB Endpoint 0 Control Register */
+#define USBD_EPADR0 0xFFC04486 /* USB Endpoint 0 Address Offset Register */
+#define USBD_EPLEN0 0xFFC04488 /* USB Endpoint 0 Buffer Length Register */
+#define USBD_INTR1 0xFFC0448A /* USB Endpoint 1 Interrupt Register */
+#define USBD_MASK1 0xFFC0448C /* USB Endpoint 1 Mask Register */
+#define USBD_EPCFG1 0xFFC0448E /* USB Endpoint 1 Control Register */
+#define USBD_EPADR1 0xFFC04490 /* USB Endpoint 1 Address Offset Register */
+#define USBD_EPLEN1 0xFFC04492 /* USB Endpoint 1 Buffer Length Register */
+#define USBD_INTR2 0xFFC04494 /* USB Endpoint 2 Interrupt Register */
+#define USBD_MASK2 0xFFC04496 /* USB Endpoint 2 Mask Register */
+#define USBD_EPCFG2 0xFFC04498 /* USB Endpoint 2 Control Register */
+#define USBD_EPADR2 0xFFC0449A /* USB Endpoint 2 Address Offset Register */
+#define USBD_EPLEN2 0xFFC0449C /* USB Endpoint 2 Buffer Length Register */
+#define USBD_INTR3 0xFFC0449E /* USB Endpoint 3 Interrupt Register */
+#define USBD_MASK3 0xFFC044A0 /* USB Endpoint 3 Mask Register */
+#define USBD_EPCFG3 0xFFC044A2 /* USB Endpoint 3 Control Register */
+#define USBD_EPADR3 0xFFC044A4 /* USB Endpoint 3 Address Offset Register */
+#define USBD_EPLEN3 0xFFC044A6 /* USB Endpoint 3 Buffer Length Register */
+#define USBD_INTR4 0xFFC044A8 /* USB Endpoint 4 Interrupt Register */
+#define USBD_MASK4 0xFFC044AA /* USB Endpoint 4 Mask Register */
+#define USBD_EPCFG4 0xFFC044AC /* USB Endpoint 4 Control Register */
+#define USBD_EPADR4 0xFFC044AE /* USB Endpoint 4 Address Offset Register */
+#define USBD_EPLEN4 0xFFC044B0 /* USB Endpoint 4 Buffer Length Register */
+#define USBD_INTR5 0xFFC044B2 /* USB Endpoint 5 Interrupt Register */
+#define USBD_MASK5 0xFFC044B4 /* USB Endpoint 5 Mask Register */
+#define USBD_EPCFG5 0xFFC044B6 /* USB Endpoint 5 Control Register */
+#define USBD_EPADR5 0xFFC044B8 /* USB Endpoint 5 Address Offset Register */
+#define USBD_EPLEN5 0xFFC044BA /* USB Endpoint 5 Buffer Length Register */
+#define USBD_INTR6 0xFFC044BC /* USB Endpoint 6 Interrupt Register */
+#define USBD_MASK6 0xFFC044BE /* USB Endpoint 6 Mask Register */
+#define USBD_EPCFG6 0xFFC044C0 /* USB Endpoint 6 Control Register */
+#define USBD_EPADR6 0xFFC044C2 /* USB Endpoint 6 Address Offset Register */
+#define USBD_EPLEN6 0xFFC044C4 /* USB Endpoint 6 Buffer Length Register */
+#define USBD_INTR7 0xFFC044C6 /* USB Endpoint 7 Interrupt Register */
+#define USBD_MASK7 0xFFC044C8 /* USB Endpoint 7 Mask Register */
+#define USBD_EPCFG7 0xFFC044CA /* USB Endpoint 7 Control Register */
+#define USBD_EPADR7 0xFFC044CC /* USB Endpoint 7 Address Offset Register */
+#define USBD_EPLEN7 0xFFC044CE /* USB Endpoint 7 Buffer Length Register */
+
+/* System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF) */
+#define L1SBAR 0xFFC04840 /* L1 SRAM Base Address Register */
+#define L1CSR 0xFFC04844 /* L1 SRAM Control Initialization Register */
+#define DMA_DBP 0xFFC04880 /* Next Descriptor Base Pointer */
+#define DB_ACOMP 0xFFC04884 /* DMA Bus Address Comparator */
+#define DB_CCOMP 0xFFC04888 /* DMA Bus Control Comparator */
+
+#define DB_NDBP DMA_DBP /* Backward compatibility */
+
+#define L1_SBAR L1SBAR
+#define L1_CSR L1CSR
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
+#define EBIU_SDGCTL 0xFFC04C00 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC04C04 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC 0xFFC04C0A /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT 0xFFC04C0E /* SDRAM Status Register */
+
+/* PAB Reserved (0xFFC0 5000-0xFFDF FFFF) (**Reserved**) */
+
+/*********************************************************************************** */
+/* System MMR Register Bits */
+/*********************************************************************************** */
+
+/* PLLCTL Masks */
+#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */
+#define PLL_OFF 0x00000002 /* Shut off PLL clocks */
+#define STOPCK_OFF 0x00000008 /* Core clock off */
+#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */
+#define BYPASS 0x00000100 /* Bypass the PLL */
+#define CCLK_DIV2 0x00000000 /* SCLK = CCLK / 2 */
+#define CCLK_DIV2_5 0x00010000 /* SCLK = CCLK / 2.5 */
+#define CCLK_DIV3 0x00020000 /* SCLK = CCLK / 3 */
+#define CCLK_DIV4 0x00030000 /* SCLK = CCLK / 4 */
+
+/* IOCKR Masks */
+#define IOCK_PCI 0x00000001 /* Enable PCI peripheral clock */
+#define IOCK_L2 0x00000002 /* Enable L2 memory peripheral clock */
+#define IOCK_EBIU 0x00000004 /* Enable EBIU controller peripheral clock */
+#define IOCK_GPIO 0x00000008 /* Enable GPIO peripheral clock */
+#define IOCK_MEMDMA 0x00000010 /* Enable MemDMA controller peripheral clock */
+#define IOCK_SPORT0 0x00000020 /* Enable SPORT0 controller peripheral clock */
+#define IOCK_SPORT1 0x00000040 /* Enable SPORT1 controller peripheral clock */
+#define IOCK_SPI0 0x00000080 /* Enable SPI0 controller peripheral clock */
+#define IOCK_SPI1 0x00000100 /* Enable SPI1 controller peripheral clock */
+#define IOCK_UART0 0x00000200 /* Enable UART0 controller peripheral clock */
+#define IOCK_UART1 0x00000400 /* Enable UART1 controller peripheral clock */
+#define IOCK_TIMER0 0x00000800 /* Enable TIMER0 peripheral clock */
+#define IOCK_TIMER1 0x00001000 /* Enable TIMER1 peripheral clock */
+#define IOCK_TIMER2 0x00002000 /* Enable TIMER2 peripheral clock */
+#define IOCK_USB 0x00004000 /* Enable USB peripheral clock */
+
+/* SWRST Mask */
+#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
+
+/* System Interrupt Controller Masks (SIC_IAR0, SIC_IAR1, SIC_IAR2, SIC_IMASK, SIC_IWR) */
+/* SIC_IAR0 Masks */
+
+/* */
+#define P0_IVG7 0x00000000 /* Peripheral #0 assigned IVG7 */
+#define P0_IVG8 0x00000001 /* Peripheral #0 assigned IVG8 */
+#define P0_IVG9 0x00000002 /* Peripheral #0 assigned IVG9 */
+#define P0_IVG10 0x00000003 /* Peripheral #0 assigned IVG10 */
+#define P0_IVG11 0x00000004 /* Peripheral #0 assigned IVG11 */
+#define P0_IVG12 0x00000005 /* Peripheral #0 assigned IVG12 */
+#define P0_IVG13 0x00000006 /* Peripheral #0 assigned IVG13 */
+#define P0_IVG14 0x00000007 /* Peripheral #0 assigned IVG14 */
+#define P0_IVG15 0x00000008 /* Peripheral #0 assigned IVG15 */
+#define P1_IVG7 0x00000000 /* Peripheral #1 assigned IVG7 */
+#define P1_IVG8 0x00000010 /* Peripheral #1 assigned IVG8 */
+#define P1_IVG9 0x00000020 /* Peripheral #1 assigned IVG9 */
+#define P1_IVG10 0x00000030 /* Peripheral #1 assigned IVG10 */
+#define P1_IVG11 0x00000040 /* Peripheral #1 assigned IVG11 */
+#define P1_IVG12 0x00000050 /* Peripheral #1 assigned IVG12 */
+#define P1_IVG13 0x00000060 /* Peripheral #1 assigned IVG13 */
+#define P1_IVG14 0x00000070 /* Peripheral #1 assigned IVG14 */
+#define P1_IVG15 0x00000080 /* Peripheral #1 assigned IVG15 */
+#define P2_IVG7 0x00000000 /* Peripheral #2 assigned IVG7 */
+#define P2_IVG8 0x00000100 /* Peripheral #2 assigned IVG8 */
+#define P2_IVG9 0x00000200 /* Peripheral #2 assigned IVG9 */
+#define P2_IVG10 0x00000300 /* Peripheral #2 assigned IVG10 */
+#define P2_IVG11 0x00000400 /* Peripheral #2 assigned IVG11 */
+#define P2_IVG12 0x00000500 /* Peripheral #2 assigned IVG12 */
+#define P2_IVG13 0x00000600 /* Peripheral #2 assigned IVG13 */
+#define P2_IVG14 0x00000700 /* Peripheral #2 assigned IVG14 */
+#define P2_IVG15 0x00000800 /* Peripheral #2 assigned IVG15 */
+#define P3_IVG7 0x00000000 /* Peripheral #3 assigned IVG7 */
+#define P3_IVG8 0x00001000 /* Peripheral #3 assigned IVG8 */
+#define P3_IVG9 0x00002000 /* Peripheral #3 assigned IVG9 */
+#define P3_IVG10 0x00003000 /* Peripheral #3 assigned IVG10 */
+#define P3_IVG11 0x00004000 /* Peripheral #3 assigned IVG11 */
+#define P3_IVG12 0x00005000 /* Peripheral #3 assigned IVG12 */
+#define P3_IVG13 0x00006000 /* Peripheral #3 assigned IVG13 */
+#define P3_IVG14 0x00007000 /* Peripheral #3 assigned IVG14 */
+#define P3_IVG15 0x00008000 /* Peripheral #3 assigned IVG15 */
+#define P4_IVG7 0x00000000 /* Peripheral #4 assigned IVG7 */
+#define P4_IVG8 0x00010000 /* Peripheral #4 assigned IVG8 */
+#define P4_IVG9 0x00020000 /* Peripheral #4 assigned IVG9 */
+#define P4_IVG10 0x00030000 /* Peripheral #4 assigned IVG10 */
+#define P4_IVG11 0x00040000 /* Peripheral #4 assigned IVG11 */
+#define P4_IVG12 0x00050000 /* Peripheral #4 assigned IVG12 */
+#define P4_IVG13 0x00060000 /* Peripheral #4 assigned IVG13 */
+#define P4_IVG14 0x00070000 /* Peripheral #4 assigned IVG14 */
+#define P4_IVG15 0x00080000 /* Peripheral #4 assigned IVG15 */
+#define P5_IVG7 0x00000000 /* Peripheral #5 assigned IVG7 */
+#define P5_IVG8 0x00100000 /* Peripheral #5 assigned IVG8 */
+#define P5_IVG9 0x00200000 /* Peripheral #5 assigned IVG9 */
+#define P5_IVG10 0x00300000 /* Peripheral #5 assigned IVG10 */
+#define P5_IVG11 0x00400000 /* Peripheral #5 assigned IVG11 */
+#define P5_IVG12 0x00500000 /* Peripheral #5 assigned IVG12 */
+#define P5_IVG13 0x00600000 /* Peripheral #5 assigned IVG13 */
+#define P5_IVG14 0x00700000 /* Peripheral #5 assigned IVG14 */
+#define P5_IVG15 0x00800000 /* Peripheral #5 assigned IVG15 */
+#define P6_IVG7 0x00000000 /* Peripheral #6 assigned IVG7 */
+#define P6_IVG8 0x01000000 /* Peripheral #6 assigned IVG8 */
+#define P6_IVG9 0x02000000 /* Peripheral #6 assigned IVG9 */
+#define P6_IVG10 0x03000000 /* Peripheral #6 assigned IVG10 */
+#define P6_IVG11 0x04000000 /* Peripheral #6 assigned IVG11 */
+#define P6_IVG12 0x05000000 /* Peripheral #6 assigned IVG12 */
+#define P6_IVG13 0x06000000 /* Peripheral #6 assigned IVG13 */
+#define P6_IVG14 0x07000000 /* Peripheral #6 assigned IVG14 */
+#define P6_IVG15 0x08000000 /* Peripheral #6 assigned IVG15 */
+#define P7_IVG7 0x00000000 /* Peripheral #7 assigned IVG7 */
+#define P7_IVG8 0x10000000 /* Peripheral #7 assigned IVG8 */
+#define P7_IVG9 0x20000000 /* Peripheral #7 assigned IVG9 */
+#define P7_IVG10 0x30000000 /* Peripheral #7 assigned IVG10 */
+#define P7_IVG11 0x40000000 /* Peripheral #7 assigned IVG11 */
+#define P7_IVG12 0x50000000 /* Peripheral #7 assigned IVG12 */
+#define P7_IVG13 0x60000000 /* Peripheral #7 assigned IVG13 */
+#define P7_IVG14 0x70000000 /* Peripheral #7 assigned IVG14 */
+#define P7_IVG15 0x80000000 /* Peripheral #7 assigned IVG15 */
+
+/* SIC_IAR1 Masks */
+#define P8_IVG7 0x00000000 /* Peripheral #8 assigned IVG7 */
+#define P8_IVG8 0x00000001 /* Peripheral #8 assigned IVG8 */
+#define P8_IVG9 0x00000002 /* Peripheral #8 assigned IVG9 */
+#define P8_IVG10 0x00000003 /* Peripheral #8 assigned IVG10 */
+#define P8_IVG11 0x00000004 /* Peripheral #8 assigned IVG11 */
+#define P8_IVG12 0x00000005 /* Peripheral #8 assigned IVG12 */
+#define P8_IVG13 0x00000006 /* Peripheral #8 assigned IVG13 */
+#define P8_IVG14 0x00000007 /* Peripheral #8 assigned IVG14 */
+#define P8_IVG15 0x00000008 /* Peripheral #8 assigned IVG15 */
+#define P9_IVG7 0x00000000 /* Peripheral #9 assigned IVG7 */
+#define P9_IVG8 0x00000010 /* Peripheral #9 assigned IVG8 */
+#define P9_IVG9 0x00000020 /* Peripheral #9 assigned IVG9 */
+#define P9_IVG10 0x00000030 /* Peripheral #9 assigned IVG10 */
+#define P9_IVG11 0x00000040 /* Peripheral #9 assigned IVG11 */
+#define P9_IVG12 0x00000050 /* Peripheral #9 assigned IVG12 */
+#define P9_IVG13 0x00000060 /* Peripheral #9 assigned IVG13 */
+#define P9_IVG14 0x00000070 /* Peripheral #9 assigned IVG14 */
+#define P9_IVG15 0x00000080 /* Peripheral #9 assigned IVG15 */
+#define P10_IVG7 0x00000000 /* Peripheral #10 assigned IVG7 */
+#define P10_IVG8 0x00000100 /* Peripheral #10 assigned IVG8 */
+#define P10_IVG9 0x00000200 /* Peripheral #10 assigned IVG9 */
+#define P10_IVG10 0x00000300 /* Peripheral #10 assigned IVG10 */
+#define P10_IVG11 0x00000400 /* Peripheral #10 assigned IVG11 */
+#define P10_IVG12 0x00000500 /* Peripheral #10 assigned IVG12 */
+#define P10_IVG13 0x00000600 /* Peripheral #10 assigned IVG13 */
+#define P10_IVG14 0x00000700 /* Peripheral #10 assigned IVG14 */
+#define P10_IVG15 0x00000800 /* Peripheral #10 assigned IVG15 */
+#define P11_IVG7 0x00000000 /* Peripheral #11 assigned IVG7 */
+#define P11_IVG8 0x00001000 /* Peripheral #11 assigned IVG8 */
+#define P11_IVG9 0x00002000 /* Peripheral #11 assigned IVG9 */
+#define P11_IVG10 0x00003000 /* Peripheral #11 assigned IVG10 */
+#define P11_IVG11 0x00004000 /* Peripheral #11 assigned IVG11 */
+#define P11_IVG12 0x00005000 /* Peripheral #11 assigned IVG12 */
+#define P11_IVG13 0x00006000 /* Peripheral #11 assigned IVG13 */
+#define P11_IVG14 0x00007000 /* Peripheral #11 assigned IVG14 */
+#define P11_IVG15 0x00008000 /* Peripheral #11 assigned IVG15 */
+#define P12_IVG7 0x00000000 /* Peripheral #12 assigned IVG7 */
+#define P12_IVG8 0x00010000 /* Peripheral #12 assigned IVG8 */
+#define P12_IVG9 0x00020000 /* Peripheral #12 assigned IVG9 */
+#define P12_IVG10 0x00030000 /* Peripheral #12 assigned IVG10 */
+#define P12_IVG11 0x00040000 /* Peripheral #12 assigned IVG11 */
+#define P12_IVG12 0x00050000 /* Peripheral #12 assigned IVG12 */
+#define P12_IVG13 0x00060000 /* Peripheral #12 assigned IVG13 */
+#define P12_IVG14 0x00070000 /* Peripheral #12 assigned IVG14 */
+#define P12_IVG15 0x00080000 /* Peripheral #12 assigned IVG15 */
+#define P13_IVG7 0x00000000 /* Peripheral #13 assigned IVG7 */
+#define P13_IVG8 0x00100000 /* Peripheral #13 assigned IVG8 */
+#define P13_IVG9 0x00200000 /* Peripheral #13 assigned IVG9 */
+#define P13_IVG10 0x00300000 /* Peripheral #13 assigned IVG10 */
+#define P13_IVG11 0x00400000 /* Peripheral #13 assigned IVG11 */
+#define P13_IVG12 0x00500000 /* Peripheral #13 assigned IVG12 */
+#define P13_IVG13 0x00600000 /* Peripheral #13 assigned IVG13 */
+#define P13_IVG14 0x00700000 /* Peripheral #14 assigned IVG14 */
+#define P13_IVG15 0x00800000 /* Peripheral #14 assigned IVG15 */
+#define P14_IVG7 0x00000000 /* Peripheral #14 assigned IVG7 */
+#define P14_IVG8 0x01000000 /* Peripheral #14 assigned IVG8 */
+#define P14_IVG9 0x02000000 /* Peripheral #14 assigned IVG9 */
+#define P14_IVG10 0x03000000 /* Peripheral #14 assigned IVG10 */
+#define P14_IVG11 0x04000000 /* Peripheral #14 assigned IVG11 */
+#define P14_IVG12 0x05000000 /* Peripheral #14 assigned IVG12 */
+#define P14_IVG13 0x06000000 /* Peripheral #14 assigned IVG13 */
+#define P14_IVG14 0x07000000 /* Peripheral #14 assigned IVG14 */
+#define P14_IVG15 0x08000000 /* Peripheral #14 assigned IVG15 */
+#define P15_IVG7 0x00000000 /* Peripheral #15 assigned IVG7 */
+#define P15_IVG8 0x10000000 /* Peripheral #15 assigned IVG8 */
+#define P15_IVG9 0x20000000 /* Peripheral #15 assigned IVG9 */
+#define P15_IVG10 0x30000000 /* Peripheral #15 assigned IVG10 */
+#define P15_IVG11 0x40000000 /* Peripheral #15 assigned IVG11 */
+#define P15_IVG12 0x50000000 /* Peripheral #15 assigned IVG12 */
+#define P15_IVG13 0x60000000 /* Peripheral #15 assigned IVG13 */
+#define P15_IVG14 0x70000000 /* Peripheral #15 assigned IVG14 */
+#define P15_IVG15 0x80000000 /* Peripheral #15 assigned IVG15 */
+
+/* SIC_IAR2 Masks */
+#define P16_IVG7 0x00000000 /* Peripheral #16 assigned IVG7 */
+#define P16_IVG8 0x00000001 /* Peripheral #16 assigned IVG8 */
+#define P16_IVG9 0x00000002 /* Peripheral #16 assigned IVG9 */
+#define P16_IVG10 0x00000003 /* Peripheral #16 assigned IVG10 */
+#define P16_IVG11 0x00000004 /* Peripheral #16 assigned IVG11 */
+#define P16_IVG12 0x00000005 /* Peripheral #16 assigned IVG12 */
+#define P16_IVG13 0x00000006 /* Peripheral #16 assigned IVG13 */
+#define P16_IVG14 0x00000007 /* Peripheral #16 assigned IVG14 */
+#define P16_IVG15 0x00000008 /* Peripheral #16 assigned IVG15 */
+#define P17_IVG7 0x00000000 /* Peripheral #17 assigned IVG7 */
+#define P17_IVG8 0x00000010 /* Peripheral #17 assigned IVG8 */
+#define P17_IVG9 0x00000020 /* Peripheral #17 assigned IVG9 */
+#define P17_IVG10 0x00000030 /* Peripheral #17 assigned IVG10 */
+#define P17_IVG11 0x00000040 /* Peripheral #17 assigned IVG11 */
+#define P17_IVG12 0x00000050 /* Peripheral #17 assigned IVG12 */
+#define P17_IVG13 0x00000060 /* Peripheral #17 assigned IVG13 */
+#define P17_IVG14 0x00000070 /* Peripheral #17 assigned IVG14 */
+#define P17_IVG15 0x00000080 /* Peripheral #17 assigned IVG15 */
+#define P18_IVG7 0x00000000 /* Peripheral #18 assigned IVG7 */
+#define P18_IVG8 0x00000100 /* Peripheral #18 assigned IVG8 */
+#define P18_IVG9 0x00000200 /* Peripheral #18 assigned IVG9 */
+#define P18_IVG10 0x00000300 /* Peripheral #18 assigned IVG10 */
+#define P18_IVG11 0x00000400 /* Peripheral #18 assigned IVG11 */
+#define P18_IVG12 0x00000500 /* Peripheral #18 assigned IVG12 */
+#define P18_IVG13 0x00000600 /* Peripheral #18 assigned IVG13 */
+#define P18_IVG14 0x00000700 /* Peripheral #18 assigned IVG14 */
+#define P18_IVG15 0x00000800 /* Peripheral #18 assigned IVG15 */
+#define P19_IVG7 0x00000000 /* Peripheral #19 assigned IVG7 */
+#define P19_IVG8 0x00001000 /* Peripheral #19 assigned IVG8 */
+#define P19_IVG9 0x00002000 /* Peripheral #19 assigned IVG9 */
+#define P19_IVG10 0x00003000 /* Peripheral #19 assigned IVG10 */
+#define P19_IVG11 0x00004000 /* Peripheral #19 assigned IVG11 */
+#define P19_IVG12 0x00005000 /* Peripheral #19 assigned IVG12 */
+#define P19_IVG13 0x00006000 /* Peripheral #19 assigned IVG13 */
+#define P19_IVG14 0x00007000 /* Peripheral #19 assigned IVG14 */
+#define P19_IVG15 0x00008000 /* Peripheral #19 assigned IVG15 */
+#define P20_IVG7 0x00000000 /* Peripheral #20 assigned IVG7 */
+#define P20_IVG8 0x00010000 /* Peripheral #20 assigned IVG8 */
+#define P20_IVG9 0x00020000 /* Peripheral #20 assigned IVG9 */
+#define P20_IVG10 0x00030000 /* Peripheral #20 assigned IVG10 */
+#define P20_IVG11 0x00040000 /* Peripheral #20 assigned IVG11 */
+#define P20_IVG12 0x00050000 /* Peripheral #20 assigned IVG12 */
+#define P20_IVG13 0x00060000 /* Peripheral #20 assigned IVG13 */
+#define P20_IVG14 0x00070000 /* Peripheral #20 assigned IVG14 */
+#define P20_IVG15 0x00080000 /* Peripheral #20 assigned IVG15 */
+/* */
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#define SIC_MASK0 0x00000001 /* Mask Peripheral #0 interrupt */
+#define SIC_MASK1 0x00000002 /* Mask Peripheral #1 interrupt */
+#define SIC_MASK2 0x00000004 /* Mask Peripheral #2 interrupt */
+#define SIC_MASK3 0x00000008 /* Mask Peripheral #3 interrupt */
+#define SIC_MASK4 0x00000010 /* Mask Peripheral #4 interrupt */
+#define SIC_MASK5 0x00000020 /* Mask Peripheral #5 interrupt */
+#define SIC_MASK6 0x00000040 /* Mask Peripheral #6 interrupt */
+#define SIC_MASK7 0x00000080 /* Mask Peripheral #7 interrupt */
+#define SIC_MASK8 0x00000100 /* Mask Peripheral #8 interrupt */
+#define SIC_MASK9 0x00000200 /* Mask Peripheral #9 interrupt */
+#define SIC_MASK10 0x00000400 /* Mask Peripheral #10 interrupt */
+#define SIC_MASK11 0x00000800 /* Mask Peripheral #11 interrupt */
+#define SIC_MASK12 0x00001000 /* Mask Peripheral #12 interrupt */
+#define SIC_MASK13 0x00002000 /* Mask Peripheral #13 interrupt */
+#define SIC_MASK14 0x00004000 /* Mask Peripheral #14 interrupt */
+#define SIC_MASK15 0x00008000 /* Mask Peripheral #15 interrupt */
+#define SIC_MASK16 0x00010000 /* Mask Peripheral #16 interrupt */
+#define SIC_MASK17 0x00020000 /* Mask Peripheral #17 interrupt */
+#define SIC_MASK18 0x00040000 /* Mask Peripheral #18 interrupt */
+#define SIC_MASK19 0x00080000 /* Mask Peripheral #19 interrupt */
+#define SIC_MASK20 0x00100000 /* Mask Peripheral #20 interrupt */
+#define SIC_MASK_DFR 0x80000000 /* Mask Core Double Fault Reset */
+#define SIC_UNMASK0 0xFFFFFFFE /* Unmask Peripheral #0 interrupt */
+#define SIC_UNMASK1 0xFFFFFFFD /* Unmask Peripheral #1 interrupt */
+#define SIC_UNMASK2 0xFFFFFFFB /* Unmask Peripheral #2 interrupt */
+#define SIC_UNMASK3 0xFFFFFFF7 /* Unmask Peripheral #3 interrupt */
+#define SIC_UNMASK4 0xFFFFFFEF /* Unmask Peripheral #4 interrupt */
+#define SIC_UNMASK5 0xFFFFFFDF /* Unmask Peripheral #5 interrupt */
+#define SIC_UNMASK6 0xFFFFFFBF /* Unmask Peripheral #6 interrupt */
+#define SIC_UNMASK7 0xFFFFFF7F /* Unmask Peripheral #7 interrupt */
+#define SIC_UNMASK8 0xFFFFFEFF /* Unmask Peripheral #8 interrupt */
+#define SIC_UNMASK9 0xFFFFFDFF /* Unmask Peripheral #9 interrupt */
+#define SIC_UNMASK10 0xFFFFFBFF /* Unmask Peripheral #10 interrupt */
+#define SIC_UNMASK11 0xFFFFF7FF /* Unmask Peripheral #11 interrupt */
+#define SIC_UNMASK12 0xFFFFEFFF /* Unmask Peripheral #12 interrupt */
+#define SIC_UNMASK13 0xFFFFDFFF /* Unmask Peripheral #13 interrupt */
+#define SIC_UNMASK14 0xFFFFBFFF /* Unmask Peripheral #14 interrupt */
+#define SIC_UNMASK15 0xFFFF7FFF /* Unmask Peripheral #15 interrupt */
+#define SIC_UNMASK16 0xFFFEFFFF /* Unmask Peripheral #16 interrupt */
+#define SIC_UNMASK17 0xFFFDFFFF /* Unmask Peripheral #17 interrupt */
+#define SIC_UNMASK18 0xFFFBFFFF /* Unmask Peripheral #18 interrupt */
+#define SIC_UNMASK19 0xFFF7FFFF /* Unmask Peripheral #19 interrupt */
+#define SIC_UNMASK20 0xFFEFFFFF /* Unmask Peripheral #20 interrupt */
+#define SIC_UNMASK_DFR 0x7FFFFFFF /* Unmask Core Double Fault Reset */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+#define IWR_ENABLE0 0x00000001 /* Wakeup Enable Peripheral #0 */
+#define IWR_ENABLE1 0x00000002 /* Wakeup Enable Peripheral #1 */
+#define IWR_ENABLE2 0x00000004 /* Wakeup Enable Peripheral #2 */
+#define IWR_ENABLE3 0x00000008 /* Wakeup Enable Peripheral #3 */
+#define IWR_ENABLE4 0x00000010 /* Wakeup Enable Peripheral #4 */
+#define IWR_ENABLE5 0x00000020 /* Wakeup Enable Peripheral #5 */
+#define IWR_ENABLE6 0x00000040 /* Wakeup Enable Peripheral #6 */
+#define IWR_ENABLE7 0x00000080 /* Wakeup Enable Peripheral #7 */
+#define IWR_ENABLE8 0x00000100 /* Wakeup Enable Peripheral #8 */
+#define IWR_ENABLE9 0x00000200 /* Wakeup Enable Peripheral #9 */
+#define IWR_ENABLE10 0x00000400 /* Wakeup Enable Peripheral #10 */
+#define IWR_ENABLE11 0x00000800 /* Wakeup Enable Peripheral #11 */
+#define IWR_ENABLE12 0x00001000 /* Wakeup Enable Peripheral #12 */
+#define IWR_ENABLE13 0x00002000 /* Wakeup Enable Peripheral #13 */
+#define IWR_ENABLE14 0x00004000 /* Wakeup Enable Peripheral #14 */
+#define IWR_ENABLE15 0x00008000 /* Wakeup Enable Peripheral #15 */
+#define IWR_ENABLE16 0x00010000 /* Wakeup Enable Peripheral #16 */
+#define IWR_ENABLE17 0x00020000 /* Wakeup Enable Peripheral #17 */
+#define IWR_ENABLE18 0x00040000 /* Wakeup Enable Peripheral #18 */
+#define IWR_ENABLE19 0x00080000 /* Wakeup Enable Peripheral #19 */
+#define IWR_ENABLE20 0x00100000 /* Wakeup Enable Peripheral #20 */
+#define IWR_DISABLE0 0xFFFFFFFE /* Wakeup Disable Peripheral #0 */
+#define IWR_DISABLE1 0xFFFFFFFD /* Wakeup Disable Peripheral #1 */
+#define IWR_DISABLE2 0xFFFFFFFB /* Wakeup Disable Peripheral #2 */
+#define IWR_DISABLE3 0xFFFFFFF7 /* Wakeup Disable Peripheral #3 */
+#define IWR_DISABLE4 0xFFFFFFEF /* Wakeup Disable Peripheral #4 */
+#define IWR_DISABLE5 0xFFFFFFDF /* Wakeup Disable Peripheral #5 */
+#define IWR_DISABLE6 0xFFFFFFBF /* Wakeup Disable Peripheral #6 */
+#define IWR_DISABLE7 0xFFFFFF7F /* Wakeup Disable Peripheral #7 */
+#define IWR_DISABLE8 0xFFFFFEFF /* Wakeup Disable Peripheral #8 */
+#define IWR_DISABLE9 0xFFFFFDFF /* Wakeup Disable Peripheral #9 */
+#define IWR_DISABLE10 0xFFFFFBFF /* Wakeup Disable Peripheral #10 */
+#define IWR_DISABLE11 0xFFFFF7FF /* Wakeup Disable Peripheral #11 */
+#define IWR_DISABLE12 0xFFFFEFFF /* Wakeup Disable Peripheral #12 */
+#define IWR_DISABLE13 0xFFFFDFFF /* Wakeup Disable Peripheral #13 */
+#define IWR_DISABLE14 0xFFFFBFFF /* Wakeup Disable Peripheral #14 */
+#define IWR_DISABLE15 0xFFFF7FFF /* Wakeup Disable Peripheral #15 */
+#define IWR_DISABLE16 0xFFFEFFFF /* Wakeup Disable Peripheral #16 */
+#define IWR_DISABLE17 0xFFFDFFFF /* Wakeup Disable Peripheral #17 */
+#define IWR_DISABLE18 0xFFFBFFFF /* Wakeup Disable Peripheral #18 */
+#define IWR_DISABLE19 0xFFF7FFFF /* Wakeup Disable Peripheral #19 */
+#define IWR_DISABLE20 0xFFEFFFFF /* Wakeup Disable Peripheral #20 */
+
+/* WDOGCTL Masks */
+#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
+#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
+#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
+#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
+
+/* RTCFAST Mask */
+#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
+ /* Must be set after power-up for proper operation of RTC */
+
+/* SPICTLx Masks */
+#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
+#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
+#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
+#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
+#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
+#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
+#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
+#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
+#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
+#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
+#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
+#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
+
+/* SPIFLGx Masks */
+#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPIFLGx Bit Positions */
+#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* AMGCTL Masks */
+#define AMCKEN 0x00000001 /* Enable CLKOUT */
+#define AMBEN_B4 0x00000002 /* Enable Asynchronous Memory Bank 6 only */
+#define AMBEN_B4_B5 0x00000004 /* Enable Asynchronous Memory Banks 4 & 5 only */
+#define AMBEN_ALL 0x00000006 /* Enable Asynchronous Memory Banks (all) 4, 5, 6, and 7 */
+#define B4PEN 0x00000010 /* Enable 16-bit packing for Asynchronous Memory Bank 4 */
+#define B5PEN 0x00000020 /* Enable 16-bit packing for Asynchronous Memory Bank 5 */
+#define B6PEN 0x00000040 /* Enable 16-bit packing for Asynchronous Memory Bank 6 */
+#define B7PEN 0x00000080 /* Enable 16-bit packing for Asynchronous Memory Bank 7 */
+
+/* AMGCTL Bit Positions */
+#define AMCKEN_P 0x00000000 /* Enable CLKOUT */
+#define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 00 - banks 4-7 disabled, 01 - bank 4 enabled */
+#define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 10 - banks 4&5 enabled, 11 - banks 4-7 enabled */
+#define B4PEN_P 0x00000004 /* Enable 16-bit packing for Asynchronous Memory Bank 4 */
+#define B5PEN_P 0x00000005 /* Enable 16-bit packing for Asynchronous Memory Bank 5 */
+#define B6PEN_P 0x00000006 /* Enable 16-bit packing for Asynchronous Memory Bank 6 */
+#define B7PEN_P 0x00000007 /* Enable 16-bit packing for Asynchronous Memory Bank 7 */
+
+/* AMBCTL0 Masks */
+#define B4RDYEN 0x00000001 /* Bank 4 RDY Enable, 0=disable, 1=enable */
+#define B4RDYPOL 0x00000002 /* Bank 4 RDY Active high, 0=active low, 1=active high */
+#define B4TT_1 0x00000004 /* Bank 4 Transition Time from Read to Write = 1 cycle */
+#define B4TT_2 0x00000008 /* Bank 4 Transition Time from Read to Write = 2 cycles */
+#define B4TT_3 0x0000000C /* Bank 4 Transition Time from Read to Write = 3 cycles */
+#define B4TT_4 0x00000000 /* Bank 4 Transition Time from Read to Write = 4 cycles */
+#define B4ST_1 0x00000010 /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B4ST_2 0x00000020 /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B4ST_3 0x00000030 /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B4ST_4 0x00000000 /* Bank 4 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B4HT_1 0x00000040 /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B4HT_2 0x00000080 /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B4HT_3 0x000000C0 /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B4HT_4 0x00000000 /* Bank 4 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
+#define B4RAT_1 0x00000100 /* Bank 4 Read Access Time = 1 cycle */
+#define B4RAT_2 0x00000200 /* Bank 4 Read Access Time = 2 cycles */
+#define B4RAT_3 0x00000300 /* Bank 4 Read Access Time = 3 cycles */
+#define B4RAT_4 0x00000400 /* Bank 4 Read Access Time = 4 cycles */
+#define B4RAT_5 0x00000500 /* Bank 4 Read Access Time = 5 cycles */
+#define B4RAT_6 0x00000600 /* Bank 4 Read Access Time = 6 cycles */
+#define B4RAT_7 0x00000700 /* Bank 4 Read Access Time = 7 cycles */
+#define B4RAT_8 0x00000800 /* Bank 4 Read Access Time = 8 cycles */
+#define B4RAT_9 0x00000900 /* Bank 4 Read Access Time = 9 cycles */
+#define B4RAT_10 0x00000A00 /* Bank 4 Read Access Time = 10 cycles */
+#define B4RAT_11 0x00000B00 /* Bank 4 Read Access Time = 11 cycles */
+#define B4RAT_12 0x00000C00 /* Bank 4 Read Access Time = 12 cycles */
+#define B4RAT_13 0x00000D00 /* Bank 4 Read Access Time = 13 cycles */
+#define B4RAT_14 0x00000E00 /* Bank 4 Read Access Time = 14 cycles */
+#define B4RAT_15 0x00000F00 /* Bank 4 Read Access Time = 15 cycles */
+#define B4WAT_1 0x00001000 /* Bank 4 Write Access Time = 1 cycle */
+#define B4WAT_2 0x00002000 /* Bank 4 Write Access Time = 2 cycles */
+#define B4WAT_3 0x00003000 /* Bank 4 Write Access Time = 3 cycles */
+#define B4WAT_4 0x00004000 /* Bank 4 Write Access Time = 4 cycles */
+#define B4WAT_5 0x00005000 /* Bank 4 Write Access Time = 5 cycles */
+#define B4WAT_6 0x00006000 /* Bank 4 Write Access Time = 6 cycles */
+#define B4WAT_7 0x00007000 /* Bank 4 Write Access Time = 7 cycles */
+#define B4WAT_8 0x00008000 /* Bank 4 Write Access Time = 8 cycles */
+#define B4WAT_9 0x00009000 /* Bank 4 Write Access Time = 9 cycles */
+#define B4WAT_10 0x0000A000 /* Bank 4 Write Access Time = 10 cycles */
+#define B4WAT_11 0x0000B000 /* Bank 4 Write Access Time = 11 cycles */
+#define B4WAT_12 0x0000C000 /* Bank 4 Write Access Time = 12 cycles */
+#define B4WAT_13 0x0000D000 /* Bank 4 Write Access Time = 13 cycles */
+#define B4WAT_14 0x0000E000 /* Bank 4 Write Access Time = 14 cycles */
+#define B4WAT_15 0x0000F000 /* Bank 4 Write Access Time = 15 cycles */
+#define B5RDYEN 0x00000001 /* Bank 5 RDY enable, 0=disable, 1=enable */
+#define B5RDYPOL 0x00000002 /* Bank 5 RDY Active high, 0=active low, 1=active high */
+#define B5TT_1 0x00000004 /* Bank 5 Transition Time from Read to Write = 1 cycle */
+#define B5TT_2 0x00000008 /* Bank 5 Transition Time from Read to Write = 2 cycles */
+#define B5TT_3 0x0000000C /* Bank 5 Transition Time from Read to Write = 3 cycles */
+#define B5TT_4 0x00000000 /* Bank 5 Transition Time from Read to Write = 4 cycles */
+#define B5ST_1 0x00000010 /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B5ST_2 0x00000020 /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B5ST_3 0x00000030 /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B5ST_4 0x00000000 /* Bank 5 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B5HT_1 0x00000040 /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B5HT_2 0x00000080 /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B5HT_3 0x000000C0 /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B5HT_4 0x00000000 /* Bank 5 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
+#define B5RAT_1 0x00000100 /* Bank 5 Read Access Time = 1 cycle */
+#define B5RAT_2 0x00000200 /* Bank 5 Read Access Time = 2 cycles */
+#define B5RAT_3 0x00000300 /* Bank 5 Read Access Time = 3 cycles */
+#define B5RAT_4 0x00000400 /* Bank 5 Read Access Time = 4 cycles */
+#define B5RAT_5 0x00000500 /* Bank 5 Read Access Time = 5 cycles */
+#define B5RAT_6 0x00000600 /* Bank 5 Read Access Time = 6 cycles */
+#define B5RAT_7 0x00000700 /* Bank 5 Read Access Time = 7 cycles */
+#define B5RAT_8 0x00000800 /* Bank 5 Read Access Time = 8 cycles */
+#define B5RAT_9 0x00000900 /* Bank 5 Read Access Time = 9 cycles */
+#define B5RAT_10 0x00000A00 /* Bank 5 Read Access Time = 10 cycles */
+#define B5RAT_11 0x00000B00 /* Bank 5 Read Access Time = 11 cycles */
+#define B5RAT_12 0x00000C00 /* Bank 5 Read Access Time = 12 cycles */
+#define B5RAT_13 0x00000D00 /* Bank 5 Read Access Time = 13 cycles */
+#define B5RAT_14 0x00000E00 /* Bank 5 Read Access Time = 14 cycles */
+#define B5RAT_15 0x00000F00 /* Bank 5 Read Access Time = 15 cycles */
+#define B5WAT_1 0x00001000 /* Bank 5 Write Access Time = 1 cycle */
+#define B5WAT_2 0x00002000 /* Bank 5 Write Access Time = 2 cycles */
+#define B5WAT_3 0x00003000 /* Bank 5 Write Access Time = 3 cycles */
+#define B5WAT_4 0x00004000 /* Bank 5 Write Access Time = 4 cycles */
+#define B5WAT_5 0x00005000 /* Bank 5 Write Access Time = 5 cycles */
+#define B5WAT_6 0x00006000 /* Bank 5 Write Access Time = 6 cycles */
+#define B5WAT_7 0x00007000 /* Bank 5 Write Access Time = 7 cycles */
+#define B5WAT_8 0x00008000 /* Bank 5 Write Access Time = 8 cycles */
+#define B5WAT_9 0x00009000 /* Bank 5 Write Access Time = 9 cycles */
+#define B5WAT_10 0x0000A000 /* Bank 5 Write Access Time = 10 cycles */
+#define B5WAT_11 0x0000B000 /* Bank 5 Write Access Time = 11 cycles */
+#define B5WAT_12 0x0000C000 /* Bank 5 Write Access Time = 12 cycles */
+#define B5WAT_13 0x0000D000 /* Bank 5 Write Access Time = 13 cycles */
+#define B5WAT_14 0x0000E000 /* Bank 5 Write Access Time = 14 cycles */
+#define B5WAT_15 0x0000F000 /* Bank 5 Write Access Time = 15 cycles */
+
+/* AMBCTL1 Masks */
+#define B6RDYEN 0x00000001 /* Bank 6 RDY Enable, 0=disable, 1=enable */
+#define B6RDYPOL 0x00000002 /* Bank 6 RDY Active high, 0=active low, 1=active high */
+#define B6TT_1 0x00000004 /* Bank 6 Transition Time from Read to Write = 1 cycle */
+#define B6TT_2 0x00000008 /* Bank 6 Transition Time from Read to Write = 2 cycles */
+#define B6TT_3 0x0000000C /* Bank 6 Transition Time from Read to Write = 3 cycles */
+#define B6TT_4 0x00000000 /* Bank 6 Transition Time from Read to Write = 4 cycles */
+#define B6ST_1 0x00000010 /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B6ST_2 0x00000020 /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B6ST_3 0x00000030 /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B6ST_4 0x00000000 /* Bank 6 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B6HT_1 0x00000040 /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B6HT_2 0x00000080 /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B6HT_3 0x000000C0 /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B6HT_4 0x00000000 /* Bank 6 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
+#define B6RAT_1 0x00000100 /* Bank 6 Read Access Time = 1 cycle */
+#define B6RAT_2 0x00000200 /* Bank 6 Read Access Time = 2 cycles */
+#define B6RAT_3 0x00000300 /* Bank 6 Read Access Time = 3 cycles */
+#define B6RAT_4 0x00000400 /* Bank 6 Read Access Time = 4 cycles */
+#define B6RAT_5 0x00000500 /* Bank 6 Read Access Time = 5 cycles */
+#define B6RAT_6 0x00000600 /* Bank 6 Read Access Time = 6 cycles */
+#define B6RAT_7 0x00000700 /* Bank 6 Read Access Time = 7 cycles */
+#define B6RAT_8 0x00000800 /* Bank 6 Read Access Time = 8 cycles */
+#define B6RAT_9 0x00000900 /* Bank 6 Read Access Time = 9 cycles */
+#define B6RAT_10 0x00000A00 /* Bank 6 Read Access Time = 10 cycles */
+#define B6RAT_11 0x00000B00 /* Bank 6 Read Access Time = 11 cycles */
+#define B6RAT_12 0x00000C00 /* Bank 6 Read Access Time = 12 cycles */
+#define B6RAT_13 0x00000D00 /* Bank 6 Read Access Time = 13 cycles */
+#define B6RAT_14 0x00000E00 /* Bank 6 Read Access Time = 14 cycles */
+#define B6RAT_15 0x00000F00 /* Bank 6 Read Access Time = 15 cycles */
+#define B6WAT_1 0x00001000 /* Bank 6 Write Access Time = 1 cycle */
+#define B6WAT_2 0x00002000 /* Bank 6 Write Access Time = 2 cycles */
+#define B6WAT_3 0x00003000 /* Bank 6 Write Access Time = 3 cycles */
+#define B6WAT_4 0x00004000 /* Bank 6 Write Access Time = 4 cycles */
+#define B6WAT_5 0x00005000 /* Bank 6 Write Access Time = 5 cycles */
+#define B6WAT_6 0x00006000 /* Bank 6 Write Access Time = 6 cycles */
+#define B6WAT_7 0x00007000 /* Bank 6 Write Access Time = 7 cycles */
+#define B6WAT_8 0x00008000 /* Bank 6 Write Access Time = 8 cycles */
+#define B6WAT_9 0x00009000 /* Bank 6 Write Access Time = 9 cycles */
+#define B6WAT_10 0x0000A000 /* Bank 6 Write Access Time = 10 cycles */
+#define B6WAT_11 0x0000B000 /* Bank 6 Write Access Time = 11 cycles */
+#define B6WAT_12 0x0000C000 /* Bank 6 Write Access Time = 12 cycles */
+#define B6WAT_13 0x0000D000 /* Bank 6 Write Access Time = 13 cycles */
+#define B6WAT_14 0x0000E000 /* Bank 6 Write Access Time = 14 cycles */
+#define B6WAT_15 0x0000F000 /* Bank 6 Write Access Time = 15 cycles */
+#define B7RDYEN 0x00000001 /* Bank 7 RDY enable, 0=disable, 1=enable */
+#define B7RDYPOL 0x00000002 /* Bank 7 RDY Active high, 0=active low, 1=active high */
+#define B7TT_1 0x00000004 /* Bank 7 Transition Time from Read to Write = 1 cycle */
+#define B7TT_2 0x00000008 /* Bank 7 Transition Time from Read to Write = 2 cycles */
+#define B7TT_3 0x0000000C /* Bank 7 Transition Time from Read to Write = 3 cycles */
+#define B7TT_4 0x00000000 /* Bank 7 Transition Time from Read to Write = 4 cycles */
+#define B7ST_1 0x00000010 /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B7ST_2 0x00000020 /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B7ST_3 0x00000030 /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B7ST_4 0x00000000 /* Bank 7 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B7HT_1 0x00000040 /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B7HT_2 0x00000080 /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B7HT_3 0x000000C0 /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B7HT_4 0x00000000 /* Bank 7 Hold Time from Read or Write deasserted to AOE deasserted = 4 cycles */
+#define B7RAT_1 0x00000100 /* Bank 7 Read Access Time = 1 cycle */
+#define B7RAT_2 0x00000200 /* Bank 7 Read Access Time = 2 cycles */
+#define B7RAT_3 0x00000300 /* Bank 7 Read Access Time = 3 cycles */
+#define B7RAT_4 0x00000400 /* Bank 7 Read Access Time = 4 cycles */
+#define B7RAT_5 0x00000500 /* Bank 7 Read Access Time = 5 cycles */
+#define B7RAT_6 0x00000600 /* Bank 7 Read Access Time = 6 cycles */
+#define B7RAT_7 0x00000700 /* Bank 7 Read Access Time = 7 cycles */
+#define B7RAT_8 0x00000800 /* Bank 7 Read Access Time = 8 cycles */
+#define B7RAT_9 0x00000900 /* Bank 7 Read Access Time = 9 cycles */
+#define B7RAT_10 0x00000A00 /* Bank 7 Read Access Time = 10 cycles */
+#define B7RAT_11 0x00000B00 /* Bank 7 Read Access Time = 11 cycles */
+#define B7RAT_12 0x00000C00 /* Bank 7 Read Access Time = 12 cycles */
+#define B7RAT_13 0x00000D00 /* Bank 7 Read Access Time = 13 cycles */
+#define B7RAT_14 0x00000E00 /* Bank 7 Read Access Time = 14 cycles */
+#define B7RAT_15 0x00000F00 /* Bank 7 Read Access Time = 15 cycles */
+#define B7WAT_1 0x00001000 /* Bank 7 Write Access Time = 1 cycle */
+#define B7WAT_2 0x00002000 /* Bank 7 Write Access Time = 2 cycles */
+#define B7WAT_3 0x00003000 /* Bank 7 Write Access Time = 3 cycles */
+#define B7WAT_4 0x00004000 /* Bank 7 Write Access Time = 4 cycles */
+#define B7WAT_5 0x00005000 /* Bank 7 Write Access Time = 5 cycles */
+#define B7WAT_6 0x00006000 /* Bank 7 Write Access Time = 6 cycles */
+#define B7WAT_7 0x00007000 /* Bank 7 Write Access Time = 7 cycles */
+#define B7WAT_8 0x00008000 /* Bank 7 Write Access Time = 8 cycles */
+#define B7WAT_9 0x00009000 /* Bank 7 Write Access Time = 9 cycles */
+#define B7WAT_10 0x0000A000 /* Bank 7 Write Access Time = 10 cycles */
+#define B7WAT_11 0x0000B000 /* Bank 7 Write Access Time = 11 cycles */
+#define B7WAT_12 0x0000C000 /* Bank 7 Write Access Time = 12 cycles */
+#define B7WAT_13 0x0000D000 /* Bank 7 Write Access Time = 13 cycles */
+#define B7WAT_14 0x0000E000 /* Bank 7 Write Access Time = 14 cycles */
+#define B7WAT_15 0x0000F000 /* Bank 7 Write Access Time = 15 cycles */
+
+
+#endif /* __DEF_BF535_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF536_H
+#define _DEF_BF536_H
+
+/* Identical MMR Space To BF537 Processor */
+#include <defBF537.h>
+
+#endif /* _DEF_BF536_H */
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF537_H
+#define _DEF_BF537_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* Include all MMR and bit defines common to BF534 */
+#include <defBF534.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+
+/************************************************************************************
+** Define EMAC Section Unique to BF536/BF537
+*************************************************************************************/
+
+/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
+#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
+#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
+#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
+#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
+#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
+#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
+#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
+#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
+#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
+#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
+#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
+#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
+#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
+#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
+#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
+#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
+#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
+#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
+#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
+
+#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
+#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
+#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
+#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
+#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
+#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
+#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
+#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
+
+#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
+#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
+#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
+#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
+#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
+
+#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
+#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
+#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
+#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
+#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
+#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
+#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
+#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
+#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
+#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
+#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
+#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
+#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
+#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
+#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
+#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
+#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
+#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
+#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
+#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
+#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
+#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
+#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
+#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
+#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
+#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
+#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
+#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
+#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
+#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
+#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
+#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
+#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
+#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
+#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
+#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
+#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
+#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
+
+/* Listing for IEEE-Supported Count Registers */
+#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
+#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
+#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
+#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
+#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
+#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
+#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
+#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
+#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
+#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
+#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
+#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
+#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
+#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
+#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
+#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
+#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
+#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
+#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
+#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
+
+#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
+#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
+#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
+#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
+#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
+#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
+#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
+#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
+#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
+#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
+#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
+#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
+#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
+#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
+#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
+#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
+#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
+#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
+#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
+#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
+#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
+#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
+
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer: All macros are intended to make C and Assembly code more readable.
+** Use these macros carefully, as any that do left shifts for field
+** depositing will result in the lower order bits being destroyed. Any
+** macro that shifts left to properly position the bit-field should be
+** used as part of an OR to initialize a register and NOT as a dynamic
+** modifier UNLESS the lower order bits are saved and ORed back in when
+** the macro is used.
+*************************************************************************************/
+/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
+/* EMAC_OPMODE Masks */
+#define RE 0x00000001 /* Receiver Enable */
+#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
+#define HU 0x00000010 /* Hash Filter Unicast Address */
+#define HM 0x00000020 /* Hash Filter Multicast Address */
+#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
+#define PR 0x00000080 /* Promiscuous Mode Enable */
+#define IFE 0x00000100 /* Inverse Filtering Enable */
+#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
+#define PBF 0x00000400 /* Pass Bad Frames Enable */
+#define PSF 0x00000800 /* Pass Short Frames Enable */
+#define RAF 0x00001000 /* Receive-All Mode */
+#define TE 0x00010000 /* Transmitter Enable */
+#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
+#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
+#define DC 0x00080000 /* Deferral Check */
+#define BOLMT 0x00300000 /* Back-Off Limit */
+#define BOLMT_10 0x00000000 /* 10-bit range */
+#define BOLMT_8 0x00100000 /* 8-bit range */
+#define BOLMT_4 0x00200000 /* 4-bit range */
+#define BOLMT_1 0x00300000 /* 1-bit range */
+#define DRTY 0x00400000 /* Disable TX Retry On Collision */
+#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
+#define RMII 0x01000000 /* RMII/MII* Mode */
+#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
+#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
+#define LB 0x08000000 /* Internal Loopback Enable */
+#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
+
+/* EMAC_STAADD Masks */
+#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
+#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
+#define STADISPRE 0x00000004 /* Disable Preamble Generation */
+#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
+#define REGAD 0x000007C0 /* STA Register Address */
+#define PHYAD 0x0000F800 /* PHY Device Address */
+
+#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
+#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
+
+/* EMAC_STADAT Mask */
+#define STADATA 0x0000FFFF /* Station Management Data */
+
+/* EMAC_FLC Masks */
+#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
+#define FLCE 0x00000002 /* Flow Control Enable */
+#define PCF 0x00000004 /* Pass Control Frames */
+#define BKPRSEN 0x00000008 /* Enable Backpressure */
+#define FLCPAUSE 0xFFFF0000 /* Pause Time */
+
+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
+
+/* EMAC_WKUP_CTL Masks */
+#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
+#define MPKE 0x00000002 /* Magic Packet Enable */
+#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
+#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
+#define MPKS 0x00000020 /* Magic Packet Received Status */
+#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
+
+/* EMAC_WKUP_FFCMD Masks */
+#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
+#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
+#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
+#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
+#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
+#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
+#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
+#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
+
+/* EMAC_WKUP_FFOFF Masks */
+#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
+#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
+#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
+#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
+
+#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
+#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
+/* Set ALL Offsets */
+#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks */
+#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
+#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
+
+#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
+#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
+
+/* EMAC_WKUP_FFCRC1 Masks */
+#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
+#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
+
+#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
+#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
+
+/* EMAC_SYSCTL Masks */
+#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
+#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
+#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
+#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
+
+#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
+
+/* EMAC_SYSTAT Masks */
+#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
+#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
+#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
+#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
+#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
+#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
+#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
+#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
+#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
+#define RX_COMP 0x00001000 /* RX Frame Complete */
+#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
+#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
+#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
+#define RX_CRC 0x00010000 /* RX Frame CRC Error */
+#define RX_LEN 0x00020000 /* RX Frame Length Error */
+#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
+#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
+#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
+#define RX_PHY 0x00200000 /* RX Frame PHY Error */
+#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
+#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
+#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
+#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
+#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
+#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
+#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
+#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
+#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
+#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
+
+/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
+#define TX_COMP 0x00000001 /* TX Frame Complete */
+#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
+#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
+#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
+#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
+#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
+#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
+#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
+#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
+#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
+#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
+#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
+#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
+#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
+#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
+
+/* EMAC_MMC_CTL Masks */
+#define RSTC 0x00000001 /* Reset All Counters */
+#define CROLL 0x00000002 /* Counter Roll-Over Enable */
+#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
+#define MMCE 0x00000008 /* Enable MMC Counter Operation */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
+#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
+#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
+#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
+#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
+#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
+#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
+#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
+#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
+#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
+#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
+#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
+#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
+#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
+#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
+#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
+#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
+#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
+#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
+#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
+#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
+#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
+#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
+#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
+#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
+#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
+#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
+#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
+#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
+#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
+#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
+#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
+#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
+#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
+#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
+#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
+#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
+#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
+#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
+#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
+#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
+#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
+#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
+#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
+#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
+#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
+#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
+#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF537_H */
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+**
+** defBF538.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+*************************************************************************/
+
+/*
+** This include file contains a list of macro "defines" to enable the
+** programmer to use symbolic names for ADSP-BF538 peripherals.
+*/
+
+#ifndef _DEF_BF538_H
+#define _DEF_BF538_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* Include all System registers and bit definitions common to ADSP-BF532 */
+#include <defBF532.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_6)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+
+/********************************************************************************
+ * System MMR Register Map
+ ********************************************************************************/
+/* Define MMR Space for Additional BF538 Peripherals */
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+/* SIC0 on ADSP-BF538 Is Same As SIC on ADSP-BF532 */
+#define SIC_IMASK0 SIC_IMASK /* Interrupt Mask Register 0 */
+#define SIC_ISR0 SIC_ISR /* Interrupt Status Register 0 */
+#define SIC_IWR0 SIC_IWR /* Interrupt Wakeup Register 0 */
+
+/* Add SIC1 MMRs for ADSP-BF538 Processors */
+#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
+#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
+#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
+
+/* Add SIC1 Interrupt Sources for ADSP-BF538 Processors */
+#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
+#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
+#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+/* UART0 on ADSP-BF538 Is Same As UART on ADSP-BF532 */
+#define UART0_THR UART_THR /* Transmit Holding register */
+#define UART0_RBR UART_RBR /* Receive Buffer register */
+#define UART0_DLL UART_DLL /* Divisor Latch (Low-Byte) */
+#define UART0_IER UART_IER /* Interrupt Enable Register */
+#define UART0_DLH UART_DLH /* Divisor Latch (High-Byte) */
+#define UART0_IIR UART_IIR /* Interrupt Identification Register */
+#define UART0_LCR UART_LCR /* Line Control Register */
+#define UART0_MCR UART_MCR /* Modem Control Register */
+#define UART0_LSR UART_LSR /* Line Status Register */
+#define UART0_SCR UART_SCR /* SCR Scratch Register */
+#define UART0_GCTL UART_GCTL /* Global Control Register */
+
+
+/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
+/* SPI0 on ADSP-BF538 Is Same As SPI on ADSP-BF532 */
+#define SPI0_CTL SPI_CTL /* SPI0 Control Register */
+#define SPI0_FLG SPI_FLG /* SPI0 Flag register */
+#define SPI0_STAT SPI_STAT /* SPI0 Status register */
+#define SPI0_TDBR SPI_TDBR /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR SPI_RDBR /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD SPI_BAUD /* SPI0 Baud rate Register */
+#define SPI0_SHADOW SPI_SHADOW /* SPI0_RDBR Shadow Register */
+
+
+/* General-Purpose Port F (0xFFC00700 - 0xFFC007FF) */
+/* ADSP-BF538 Refers to FIO as GPIO Port F */
+#define PORTFIO FIO_FLAG_D /* GPIO Port F Pin State Specify Register */
+#define PORTFIO_CLEAR FIO_FLAG_C /* Peripheral Interrupt GPIO Clear Register */
+#define PORTFIO_SET FIO_FLAG_S /* Peripheral Interrupt GPIO Set Register */
+#define PORTFIO_TOGGLE FIO_FLAG_T /* GPIO Port F Pin State Toggle Register */
+#define PORTFIO_MASKA FIO_MASKA_D /* GPIO Port F Mask State Specify Interrupt A Register */
+#define PORTFIO_MASKA_CLEAR FIO_MASKA_C /* GPIO Port F Mask Disable Interrupt A Register */
+#define PORTFIO_MASKA_SET FIO_MASKA_S /* GPIO Port F Mask Enable Interrupt A Register */
+#define PORTFIO_MASKA_TOGGLE FIO_MASKA_T /* GPIO Port F Mask Toggle Enable Interrupt A Register */
+#define PORTFIO_MASKB FIO_MASKB_D /* GPIO Port F Mask State Specify Interrupt B Register */
+#define PORTFIO_MASKB_CLEAR FIO_MASKB_C /* GPIO Port F Mask Disable Interrupt B Register */
+#define PORTFIO_MASKB_SET FIO_MASKB_S /* GPIO Port F Mask Enable Interrupt B Register */
+#define PORTFIO_MASKB_TOGGLE FIO_MASKB_T /* GPIO Port F Mask Toggle Enable Interrupt B Register */
+#define PORTFIO_DIR FIO_DIR /* GPIO Port F Direction Register */
+#define PORTFIO_POLAR FIO_POLAR /* GPIO Port F Source Polarity Register */
+#define PORTFIO_EDGE FIO_EDGE /* GPIO Port F Source Sensitivity Register */
+#define PORTFIO_BOTH FIO_BOTH /* GPIO Port F Set on BOTH Edges Register */
+#define PORTFIO_INEN FIO_INEN /* GPIO Port F Input Enable Register */
+
+
+/* DMA0 Test Registers (0xFFC00B00 - 0xFFC00BFF) */
+/* ADSP-BF538 DMA0 Controller Is Same As ADSP-BF532 DMA Controller */
+#define DMAC0_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
+#define DMAC0_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA0_TC_PER DMAC0_TC_PER /* Traffic Control Periods Register */
+#define DMA0_TC_CNT DMAC0_TC_CNT /* Traffic Control Current Counts Register */
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA0_TCPER DMA0_TC_PER /* Traffic Control Periods Register */
+#define DMA0_TCCNT DMA0_TC_CNT /* Traffic Control Current Counts Register */
+
+/* ADSP-BF538 Must Enumerate Memory DMA Channels By Controller */
+#define MDMA0_D0_NEXT_DESC_PTR MDMA_D0_NEXT_DESC_PTR /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA0_D0_START_ADDR MDMA_D0_START_ADDR /* MemDMA0 Stream 0 Destination Start Address Register */
+#define MDMA0_D0_CONFIG MDMA_D0_CONFIG /* MemDMA0 Stream 0 Destination Configuration Register */
+#define MDMA0_D0_X_COUNT MDMA_D0_X_COUNT /* MemDMA0 Stream 0 Destination X Count Register */
+#define MDMA0_D0_X_MODIFY MDMA_D0_X_MODIFY /* MemDMA0 Stream 0 Destination X Modify Register */
+#define MDMA0_D0_Y_COUNT MDMA_D0_Y_COUNT /* MemDMA0 Stream 0 Destination Y Count Register */
+#define MDMA0_D0_Y_MODIFY MDMA_D0_Y_MODIFY /* MemDMA0 Stream 0 Destination Y Modify Register */
+#define MDMA0_D0_CURR_DESC_PTR MDMA_D0_CURR_DESC_PTR /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA0_D0_CURR_ADDR MDMA_D0_CURR_ADDR /* MemDMA0 Stream 0 Destination Current Address Register */
+#define MDMA0_D0_IRQ_STATUS MDMA_D0_IRQ_STATUS /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
+#define MDMA0_D0_PERIPHERAL_MAP MDMA_D0_PERIPHERAL_MAP /* MemDMA0 Stream 0 Destination Peripheral Map Register */
+#define MDMA0_D0_CURR_X_COUNT MDMA_D0_CURR_X_COUNT /* MemDMA0 Stream 0 Destination Current X Count Register */
+#define MDMA0_D0_CURR_Y_COUNT MDMA_D0_CURR_Y_COUNT /* MemDMA0 Stream 0 Destination Current Y Count Register */
+
+#define MDMA0_S0_NEXT_DESC_PTR MDMA_S0_NEXT_DESC_PTR /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA0_S0_START_ADDR MDMA_S0_START_ADDR /* MemDMA0 Stream 0 Source Start Address Register */
+#define MDMA0_S0_CONFIG MDMA_S0_CONFIG /* MemDMA0 Stream 0 Source Configuration Register */
+#define MDMA0_S0_X_COUNT MDMA_S0_X_COUNT /* MemDMA Stream 0 Source X Count Register */
+#define MDMA0_S0_X_MODIFY MDMA_S0_X_MODIFY /* MemDMA0 Stream 0 Source X Modify Register */
+#define MDMA0_S0_Y_COUNT MDMA_S0_Y_COUNT /* MemDMA0 Stream 0 Source Y Count Register */
+#define MDMA0_S0_Y_MODIFY MDMA_S0_Y_MODIFY /* MemDMA0 Stream 0 Source Y Modify Register */
+#define MDMA0_S0_CURR_DESC_PTR MDMA_S0_CURR_DESC_PTR /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA0_S0_CURR_ADDR MDMA_S0_CURR_ADDR /* MemDMA0 Stream 0 Source Current Address Register */
+#define MDMA0_S0_IRQ_STATUS MDMA_S0_IRQ_STATUS /* MemDMA0 Stream 0 Source Interrupt/Status Register */
+#define MDMA0_S0_PERIPHERAL_MAP MDMA_S0_PERIPHERAL_MAP /* MemDMA0 Stream 0 Source Peripheral Map Register */
+#define MDMA0_S0_CURR_X_COUNT MDMA_S0_CURR_X_COUNT /* MemDMA0 Stream 0 Source Current X Count Register */
+#define MDMA0_S0_CURR_Y_COUNT MDMA_S0_CURR_Y_COUNT /* MemDMA0 Stream 0 Source Current Y Count Register */
+
+#define MDMA0_D1_NEXT_DESC_PTR MDMA_D1_NEXT_DESC_PTR /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA0_D1_START_ADDR MDMA_D1_START_ADDR /* MemDMA0 Stream 1 Destination Start Address Register */
+#define MDMA0_D1_CONFIG MDMA_D1_CONFIG /* MemDMA0 Stream 1 Destination Configuration Register */
+#define MDMA0_D1_X_COUNT MDMA_D1_X_COUNT /* MemDMA0 Stream 1 Destination X Count Register */
+#define MDMA0_D1_X_MODIFY MDMA_D1_X_MODIFY /* MemDMA0 Stream 1 Destination X Modify Register */
+#define MDMA0_D1_Y_COUNT MDMA_D1_Y_COUNT /* MemDMA0 Stream 1 Destination Y Count Register */
+#define MDMA0_D1_Y_MODIFY MDMA_D1_Y_MODIFY /* MemDMA0 Stream 1 Destination Y Modify Register */
+#define MDMA0_D1_CURR_DESC_PTR MDMA_D1_CURR_DESC_PTR /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA0_D1_CURR_ADDR MDMA_D1_CURR_ADDR /* MemDMA0 Stream 1 Destination Current Address Register */
+#define MDMA0_D1_IRQ_STATUS MDMA_D1_IRQ_STATUS /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
+#define MDMA0_D1_PERIPHERAL_MAP MDMA_D1_PERIPHERAL_MAP /* MemDMA0 Stream 1 Destination Peripheral Map Register */
+#define MDMA0_D1_CURR_X_COUNT MDMA_D1_CURR_X_COUNT /* MemDMA0 Stream 1 Destination Current X Count Register */
+#define MDMA0_D1_CURR_Y_COUNT MDMA_D1_CURR_Y_COUNT /* MemDMA0 Stream 1 Destination Current Y Count Register */
+
+#define MDMA0_S1_NEXT_DESC_PTR MDMA_S1_NEXT_DESC_PTR /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA0_S1_START_ADDR MDMA_S1_START_ADDR /* MemDMA0 Stream 1 Source Start Address Register */
+#define MDMA0_S1_CONFIG MDMA_S1_CONFIG /* MemDMA0 Stream 1 Source Configuration Register */
+#define MDMA0_S1_X_COUNT MDMA_S1_X_COUNT /* MemDMA0 Stream 1 Source X Count Register */
+#define MDMA0_S1_X_MODIFY MDMA_S1_X_MODIFY /* MemDMA0 Stream 1 Source X Modify Register */
+#define MDMA0_S1_Y_COUNT MDMA_S1_Y_COUNT /* MemDMA0 Stream 1 Source Y Count Register */
+#define MDMA0_S1_Y_MODIFY MDMA_S1_Y_MODIFY /* MemDMA0 Stream 1 Source Y Modify Register */
+#define MDMA0_S1_CURR_DESC_PTR MDMA_S1_CURR_DESC_PTR /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA0_S1_CURR_ADDR MDMA_S1_CURR_ADDR /* MemDMA0 Stream 1 Source Current Address Register */
+#define MDMA0_S1_IRQ_STATUS MDMA_S1_IRQ_STATUS /* MemDMA0 Stream 1 Source Interrupt/Status Register */
+#define MDMA0_S1_PERIPHERAL_MAP MDMA_S1_PERIPHERAL_MAP /* MemDMA0 Stream 1 Source Peripheral Map Register */
+#define MDMA0_S1_CURR_X_COUNT MDMA_S1_CURR_X_COUNT /* MemDMA0 Stream 1 Source Current X Count Register */
+#define MDMA0_S1_CURR_Y_COUNT MDMA_S1_CURR_Y_COUNT /* MemDMA0 Stream 1 Source Current Y Count Register */
+
+
+/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
+#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
+#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
+#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */
+#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
+#define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */
+#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
+#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
+#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
+#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
+#define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */
+#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
+#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+
+
+/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
+/* Port C */
+#define PORTCIO_FER 0xFFC01500 /* GPIO Pin Port C Configuration Register */
+#define PORTCIO 0xFFC01510 /* GPIO Pin Port C Data Register */
+#define PORTCIO_CLEAR 0xFFC01520 /* Clear GPIO Pin Port C Register */
+#define PORTCIO_SET 0xFFC01530 /* Set GPIO Pin Port C Register */
+#define PORTCIO_TOGGLE 0xFFC01540 /* Toggle GPIO Pin Port C Register */
+#define PORTCIO_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
+#define PORTCIO_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
+
+/* Port D */
+#define PORTDIO_FER 0xFFC01504 /* GPIO Pin Port D Configuration Register */
+#define PORTDIO 0xFFC01514 /* GPIO Pin Port D Data Register */
+#define PORTDIO_CLEAR 0xFFC01524 /* Clear GPIO Pin Port D Register */
+#define PORTDIO_SET 0xFFC01534 /* Set GPIO Pin Port D Register */
+#define PORTDIO_TOGGLE 0xFFC01544 /* Toggle GPIO Pin Port D Register */
+#define PORTDIO_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
+#define PORTDIO_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
+
+/* Port E */
+#define PORTEIO_FER 0xFFC01508 /* GPIO Pin Port E Configuration Register */
+#define PORTEIO 0xFFC01518 /* GPIO Pin Port E Data Register */
+#define PORTEIO_CLEAR 0xFFC01528 /* Clear GPIO Pin Port E Register */
+#define PORTEIO_SET 0xFFC01538 /* Set GPIO Pin Port E Register */
+#define PORTEIO_TOGGLE 0xFFC01548 /* Toggle GPIO Pin Port E Register */
+#define PORTEIO_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
+#define PORTEIO_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
+
+
+/* ADSP-BF538 Adds DMA1 Controller */
+/* DMA1 Test Registers (0xFFC01B00 - 0xFFC01BFF) */
+#define DMAC1_TC_PER 0xFFC01B0C /* Traffic Control Periods Register */
+#define DMAC1_TC_CNT 0xFFC01B10 /* Traffic Control Current Counts Register */
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA1_TC_PER DMAC1_TC_PER /* Traffic Control Periods Register */
+#define DMA1_TC_CNT DMAC1_TC_CNT /* Traffic Control Current Counts Register */
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA1_TCPER DMA1_TC_PER /* Traffic Control Periods Register */
+#define DMA1_TCCNT DMA1_TC_CNT /* Traffic Control Current Counts Register */
+
+/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
+#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
+
+#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
+
+#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
+
+#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
+
+#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
+
+#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
+
+#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
+
+#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
+
+#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
+
+#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
+
+#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
+
+#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
+
+#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
+#define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
+#define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
+#define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */
+#define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */
+#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */
+#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */
+#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
+#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
+#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */
+#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */
+
+#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */
+#define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */
+#define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */
+#define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */
+#define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */
+#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */
+#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */
+#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
+#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
+#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */
+#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */
+
+#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */
+#define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */
+#define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */
+#define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */
+#define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */
+#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */
+#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */
+#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
+#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
+#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */
+#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */
+
+#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */
+#define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */
+#define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */
+#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */
+#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */
+#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */
+#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */
+#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
+#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
+#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */
+#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */
+
+
+/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
+#define UART1_THR 0xFFC02000 /* Transmit Holding register */
+#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
+#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
+#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
+#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
+#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
+#define UART1_LCR 0xFFC0200C /* Line Control Register */
+#define UART1_MCR 0xFFC02010 /* Modem Control Register */
+#define UART1_LSR 0xFFC02014 /* Line Status Register */
+#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
+#define UART1_GCTL 0xFFC02024 /* Global Control Register */
+
+
+/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
+#define UART2_THR 0xFFC02100 /* Transmit Holding register */
+#define UART2_RBR 0xFFC02100 /* Receive Buffer register */
+#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
+#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
+#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
+#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
+#define UART2_LCR 0xFFC0210C /* Line Control Register */
+#define UART2_MCR 0xFFC02110 /* Modem Control Register */
+#define UART2_LSR 0xFFC02114 /* Line Status Register */
+#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */
+#define UART2_GCTL 0xFFC02124 /* Global Control Register */
+
+
+/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
+#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
+#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
+#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */
+#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
+#define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */
+#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
+#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
+#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
+#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
+#define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */
+#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
+#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
+
+
+/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
+#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */
+#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */
+#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */
+#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */
+
+
+/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
+#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
+#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */
+#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */
+#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */
+#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */
+
+
+/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
+#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */
+#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */
+#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */
+#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */
+#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */
+#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */
+#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
+#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
+#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
+#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
+#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
+#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
+#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
+#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
+#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
+#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
+#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */
+#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */
+#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */
+#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */
+#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */
+#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */
+#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
+#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
+#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
+#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
+#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
+#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
+#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
+#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
+#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
+#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
+
+
+/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
+/* For Mailboxes 0-15 */
+#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
+#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
+#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
+#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
+#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
+#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
+#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
+#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
+#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
+#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
+#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
+#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
+#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
+
+/* For Mailboxes 16-31 */
+#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
+#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
+#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
+#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
+#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
+#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
+#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
+#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
+#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
+#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
+#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
+#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
+#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
+
+#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
+#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
+#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
+#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
+#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
+#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
+#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
+#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
+#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
+#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
+#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
+#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
+#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
+#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
+#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
+#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
+#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
+
+/* Mailbox Acceptance Masks */
+#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
+#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
+#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
+#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
+#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
+#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
+#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
+#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
+#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
+#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
+#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
+#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
+#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
+#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
+#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
+#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
+#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
+#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
+#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
+#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
+#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
+#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
+#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
+#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
+#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
+#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
+#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
+#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
+#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
+#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
+#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
+#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
+
+#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
+#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
+#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
+#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
+#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
+#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
+#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
+#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
+#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
+#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
+#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
+#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
+#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
+#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
+#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
+#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
+#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
+#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
+#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
+#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
+#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
+#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
+#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
+#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
+#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
+#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
+#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
+#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
+#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
+#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
+#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
+#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
+
+/* CAN Acceptance Mask Macros */
+#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
+#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
+
+/* Mailbox Registers */
+#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
+#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
+#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
+#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
+#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
+#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
+#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
+#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
+
+#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
+#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
+#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
+#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
+#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
+#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
+#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
+#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
+
+#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
+#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
+#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
+#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
+#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
+#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
+#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
+#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
+
+#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
+#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
+#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
+#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
+#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
+#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
+#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
+#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
+
+#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
+#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
+#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
+#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
+#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
+#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
+#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
+#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
+
+#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
+#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
+#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
+#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
+#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
+#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
+#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
+#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
+
+#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
+#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
+#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
+#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
+#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
+#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
+#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
+#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
+
+#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
+#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
+#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
+#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
+#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
+#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
+#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
+#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
+
+#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
+#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
+#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
+#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
+#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
+#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
+#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
+#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
+
+#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
+#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
+#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
+#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
+#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
+#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
+#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
+#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
+
+#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
+#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
+#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
+#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
+#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
+#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
+#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
+#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
+
+#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
+#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
+#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
+#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
+#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
+#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
+#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
+#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
+
+#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
+#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
+#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
+#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
+#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
+#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
+#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
+#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
+
+#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
+#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
+#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
+#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
+#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
+#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
+#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
+#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
+
+#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
+#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
+#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
+#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
+#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
+#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
+#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
+#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
+
+#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
+#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
+#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
+#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
+#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
+#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
+#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
+#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
+
+#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
+#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
+#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
+#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
+#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
+#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
+#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
+#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
+
+#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
+#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
+#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
+#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
+#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
+#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
+#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
+#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
+
+#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
+#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
+#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
+#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
+#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
+#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
+#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
+#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
+
+#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
+#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
+#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
+#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
+#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
+#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
+#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
+#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
+
+#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
+#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
+#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
+#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
+#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
+#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
+#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
+#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
+
+#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
+#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
+#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
+#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
+#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
+#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
+#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
+#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
+
+#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
+#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
+#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
+#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
+#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
+#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
+#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
+#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
+
+#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
+#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
+#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
+#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
+#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
+#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
+#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
+#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
+
+#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
+#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
+#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
+#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
+#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
+#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
+#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
+#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
+
+#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
+#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
+#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
+#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
+#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
+#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
+#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
+#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
+
+#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
+#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
+#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
+#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
+#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
+#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
+#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
+#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
+
+#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
+#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
+#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
+#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
+#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
+#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
+#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
+#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
+
+#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
+#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
+#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
+#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
+#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
+#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
+#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
+#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
+
+#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
+#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
+#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
+#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
+#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
+#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
+#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
+#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
+
+#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
+#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
+#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
+#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
+#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
+#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
+#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
+#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
+
+#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
+#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
+#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
+#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
+#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
+#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
+#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
+#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
+
+/* CAN Mailbox Area Macros */
+#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
+#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
+#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
+#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
+#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
+#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
+#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
+#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
+
+
+/************************************************************************************
+** System MMR Register Bits And Macros
+*************************************************************************************
+**/
+
+/* ********************* PLL AND RESET MASKS ****************************************/
+
+/* PLL_CTL Masks (IN_DELAY and OUT_DELAY bit field definitions differ from BF533/BF532/BF531) */
+#define IN_DELAY 0x0014 /* EBIU Input Delay Select */
+#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */
+
+#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
+#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
+
+/* VR_CTL Masks (Additional WakeUp Events) */
+#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
+#define GPWE 0x0400 /* Enable General-Purpose Wakeup From Hibernate */
+
+
+/* ********************** SYSTEM INTERRUPT CONTROLLER MASKS ********************** */
+/* Peripheral Masks For SIC_ISR0, SIC_IWR0, SIC_IMASK0 */
+#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
+#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
+#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
+#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
+#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
+#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
+#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
+#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
+#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
+#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
+#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
+#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
+
+#define DMA0_ERR_IRQ DMAC0_ERR_IRQ /* legacy */
+#define DMA1_ERR_IRQ DMAC1_ERR_IRQ /* legacy */
+
+/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
+#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
+#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
+#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
+#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
+#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
+#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
+#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
+#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
+#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
+#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
+#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
+#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
+#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
+#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
+#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
+#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
+#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
+#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
+#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
+
+
+/* SIC_IAR3 Macros */
+#define P24_IVG(x) (((x)-7)&0xF) /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #29 assigned IVG #x */
+#define P30_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #31 assigned IVG #x */
+
+/* SIC_IAR4 Macros */
+#define P32_IVG(x) (((x)-7)&0xF) /* Peripheral #32 assigned IVG #x */
+#define P33_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #33 assigned IVG #x */
+#define P34_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #34 assigned IVG #x */
+#define P35_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #35 assigned IVG #x */
+#define P36_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #36 assigned IVG #x */
+#define P37_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #37 assigned IVG #x */
+#define P38_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #38 assigned IVG #x */
+#define P39_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #39 assigned IVG #x */
+
+/* SIC_IAR5 Macros */
+#define P40_IVG(x) (((x)-7)&0xF) /* Peripheral #40 assigned IVG #x */
+#define P41_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #41 assigned IVG #x */
+#define P42_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #42 assigned IVG #x */
+#define P43_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #43 assigned IVG #x */
+#define P44_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #44 assigned IVG #x */
+#define P45_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #45 assigned IVG #x */
+#define P46_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #46 assigned IVG #x */
+#define P47_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #47 assigned IVG #x */
+
+/* SIC_IAR6 Macros */
+#define P48_IVG(x) (((x)-7)&0xF) /* Peripheral #48 assigned IVG #x */
+#define P49_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #49 assigned IVG #x */
+#define P50_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #50 assigned IVG #x */
+#define P51_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #51 assigned IVG #x */
+#define P52_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #52 assigned IVG #x */
+#define P53_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #53 assigned IVG #x */
+#define P54_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #54 assigned IVG #x */
+#define P55_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #55 assigned IVG #x */
+
+
+/******************* GPIO MASKS *********************/
+/* Port C Masks */
+#define PC0 0x0001
+#define PC1 0x0002
+#define PC4 0x0010
+#define PC5 0x0020
+#define PC6 0x0040
+#define PC7 0x0080
+#define PC8 0x0100
+#define PC9 0x0200
+/* Port C Bit Positions */
+#define PC0_P 0x0
+#define PC1_P 0x1
+#define PC4_P 0x4
+#define PC5_P 0x5
+#define PC6_P 0x6
+#define PC7_P 0x7
+#define PC8_P 0x8
+#define PC9_P 0x9
+
+/* Port D */
+#define PD0 0x0001
+#define PD1 0x0002
+#define PD2 0x0004
+#define PD3 0x0008
+#define PD4 0x0010
+#define PD5 0x0020
+#define PD6 0x0040
+#define PD7 0x0080
+#define PD8 0x0100
+#define PD9 0x0200
+#define PD10 0x0400
+#define PD11 0x0800
+#define PD12 0x1000
+#define PD13 0x2000
+#define PD14 0x4000
+#define PD15 0x8000
+/* Port D Bit Positions */
+#define PD0_P 0x0
+#define PD1_P 0x1
+#define PD2_P 0x2
+#define PD3_P 0x3
+#define PD4_P 0x4
+#define PD5_P 0x5
+#define PD6_P 0x6
+#define PD7_P 0x7
+#define PD8_P 0x8
+#define PD9_P 0x9
+#define PD10_P 0xA
+#define PD11_P 0xB
+#define PD12_P 0xC
+#define PD13_P 0xD
+#define PD14_P 0xE
+#define PD15_P 0xF
+
+/* Port E */
+#define PE0 0x0001
+#define PE1 0x0002
+#define PE2 0x0004
+#define PE3 0x0008
+#define PE4 0x0010
+#define PE5 0x0020
+#define PE6 0x0040
+#define PE7 0x0080
+#define PE8 0x0100
+#define PE9 0x0200
+#define PE10 0x0400
+#define PE11 0x0800
+#define PE12 0x1000
+#define PE13 0x2000
+#define PE14 0x4000
+#define PE15 0x8000
+/* Port E Bit Positions */
+#define PE0_P 0x0
+#define PE1_P 0x1
+#define PE2_P 0x2
+#define PE3_P 0x3
+#define PE4_P 0x4
+#define PE5_P 0x5
+#define PE6_P 0x6
+#define PE7_P 0x7
+#define PE8_P 0x8
+#define PE9_P 0x9
+#define PE10_P 0xA
+#define PE11_P 0xB
+#define PE12_P 0xC
+#define PE13_P 0xD
+#define PE14_P 0xE
+#define PE15_P 0xF
+
+
+/* **************** DMA CONTROLLER 0 (DMAC0) MASKS ***************************/
+/* PMAP Encodings For DMA Controller 0 */
+#define PMAP_SPI0 PMAP_SPI /* PMAP SPI0 DMA */
+#define PMAP_UART0RX PMAP_UARTRX /* PMAP UART0 Receive DMA */
+#define PMAP_UART0TX PMAP_UARTTX /* PMAP UART0 Transmit DMA */
+
+/* **************** DMA CONTROLLER 1 (DMAC1) MASKS ***************************/
+/* PMAP Encodings For DMA Controller 1 */
+#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */
+#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */
+#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */
+#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */
+#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */
+#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */
+#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */
+#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */
+#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
+#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
+
+
+/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
+/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+
+/* TWIx_PRESCALE Masks */
+#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
+#define TWI_ENA 0x0080 /* TWI Enable */
+#define SCCB 0x0200 /* SCCB Compatibility Enable */
+
+/* TWIx_SLAVE_CTRL Masks */
+#define SEN 0x0001 /* Slave Enable */
+#define SADD_LEN 0x0002 /* Slave Address Length */
+#define STDVAL 0x0004 /* Slave Transmit Data Valid */
+#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN 0x0010 /* General Call Adrress Matching Enabled */
+
+/* TWIx_SLAVE_STAT Masks */
+#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL 0x0002 /* General Call Indicator */
+
+/* TWIx_MASTER_CTRL Masks */
+#define MEN 0x0001 /* Master Mode Enable */
+#define MADD_LEN 0x0002 /* Master Address Length */
+#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
+#define FAST 0x0008 /* Use Fast Mode Timing Specs */
+#define STOP 0x0010 /* Issue Stop Condition */
+#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
+#define DCNT 0x3FC0 /* Data Bytes To Transfer */
+#define SDAOVR 0x4000 /* Serial Data Override */
+#define SCLOVR 0x8000 /* Serial Clock Override */
+
+/* TWIx_MASTER_STAT Masks */
+#define MPROG 0x0001 /* Master Transfer In Progress */
+#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
+#define ANAK 0x0004 /* Address Not Acknowledged */
+#define DNAK 0x0008 /* Data Not Acknowledged */
+#define BUFRDERR 0x0010 /* Buffer Read Error */
+#define BUFWRERR 0x0020 /* Buffer Write Error */
+#define SDASEN 0x0040 /* Serial Data Sense */
+#define SCLSEN 0x0080 /* Serial Clock Sense */
+#define BUSBUSY 0x0100 /* Bus Busy Indicator */
+
+/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
+#define SINIT 0x0001 /* Slave Transfer Initiated */
+#define SCOMP 0x0002 /* Slave Transfer Complete */
+#define SERR 0x0004 /* Slave Transfer Error */
+#define SOVF 0x0008 /* Slave Overflow */
+#define MCOMP 0x0010 /* Master Transfer Complete */
+#define MERR 0x0020 /* Master Transfer Error */
+#define XMTSERV 0x0040 /* Transmit FIFO Service */
+#define RCVSERV 0x0080 /* Receive FIFO Service */
+
+/* TWIx_FIFO_CTRL Masks */
+#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
+#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
+#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
+#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
+
+/* TWIx_FIFO_STAT Masks */
+#define XMTSTAT 0x0003 /* Transmit FIFO Status */
+#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
+#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
+#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
+
+#define RCVSTAT 0x000C /* Receive FIFO Status */
+#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
+#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
+#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
+
+
+/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
+/* CAN_CONTROL Masks */
+#define SRS 0x0001 /* Software Reset */
+#define DNM 0x0002 /* Device Net Mode */
+#define ABO 0x0004 /* Auto-Bus On Enable */
+#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
+#define SMR 0x0020 /* Sleep Mode Request */
+#define CSR 0x0040 /* CAN Suspend Mode Request */
+#define CCR 0x0080 /* CAN Configuration Mode Request */
+
+/* CAN_STATUS Masks */
+#define WT 0x0001 /* TX Warning Flag */
+#define WR 0x0002 /* RX Warning Flag */
+#define EP 0x0004 /* Error Passive Mode */
+#define EBO 0x0008 /* Error Bus Off Mode */
+#define CSA 0x0040 /* Suspend Mode Acknowledge */
+#define CCA 0x0080 /* Configuration Mode Acknowledge */
+#define MBPTR 0x1F00 /* Mailbox Pointer */
+#define TRM 0x4000 /* Transmit Mode */
+#define REC 0x8000 /* Receive Mode */
+
+/* CAN_CLOCK Masks */
+#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
+
+/* CAN_TIMING Masks */
+#define TSEG1 0x000F /* Time Segment 1 */
+#define TSEG2 0x0070 /* Time Segment 2 */
+#define SAM 0x0080 /* Sampling */
+#define SJW 0x0300 /* Synchronization Jump Width */
+
+/* CAN_DEBUG Masks */
+#define DEC 0x0001 /* Disable CAN Error Counters */
+#define DRI 0x0002 /* Disable CAN RX Input */
+#define DTO 0x0004 /* Disable CAN TX Output */
+#define DIL 0x0008 /* Disable CAN Internal Loop */
+#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
+#define MRB 0x0020 /* Mode Read Back Enable */
+#define CDE 0x8000 /* CAN Debug Enable */
+
+/* CAN_CEC Masks */
+#define RXECNT 0x00FF /* Receive Error Counter */
+#define TXECNT 0xFF00 /* Transmit Error Counter */
+
+/* CAN_INTR Masks */
+#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
+#define MBRIF MBRIRQ /* legacy */
+#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
+#define MBTIF MBTIRQ /* legacy */
+#define GIRQ 0x0004 /* Global Interrupt */
+#define SMACK 0x0008 /* Sleep Mode Acknowledge */
+#define CANTX 0x0040 /* CAN TX Bus Value */
+#define CANRX 0x0080 /* CAN RX Bus Value */
+
+/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
+#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
+#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
+#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
+#define BASEID 0x1FFC /* Base Identifier */
+#define IDE 0x2000 /* Identifier Extension */
+#define RTR 0x4000 /* Remote Frame Transmission Request */
+#define AME 0x8000 /* Acceptance Mask Enable */
+
+/* CAN_MBxx_TIMESTAMP Masks */
+#define TSV 0xFFFF /* Timestamp */
+
+/* CAN_MBxx_LENGTH Masks */
+#define DLC 0x000F /* Data Length Code */
+
+/* CAN_AMxxH and CAN_AMxxL Masks */
+#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
+#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
+#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
+#define BASEID 0x1FFC /* Base Identifier */
+#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
+#define FMD 0x4000 /* Full Mask Data Field Enable */
+#define FDF 0x8000 /* Filter On Data Field Enable */
+
+/* CAN_MC1 Masks */
+#define MC0 0x0001 /* Enable Mailbox 0 */
+#define MC1 0x0002 /* Enable Mailbox 1 */
+#define MC2 0x0004 /* Enable Mailbox 2 */
+#define MC3 0x0008 /* Enable Mailbox 3 */
+#define MC4 0x0010 /* Enable Mailbox 4 */
+#define MC5 0x0020 /* Enable Mailbox 5 */
+#define MC6 0x0040 /* Enable Mailbox 6 */
+#define MC7 0x0080 /* Enable Mailbox 7 */
+#define MC8 0x0100 /* Enable Mailbox 8 */
+#define MC9 0x0200 /* Enable Mailbox 9 */
+#define MC10 0x0400 /* Enable Mailbox 10 */
+#define MC11 0x0800 /* Enable Mailbox 11 */
+#define MC12 0x1000 /* Enable Mailbox 12 */
+#define MC13 0x2000 /* Enable Mailbox 13 */
+#define MC14 0x4000 /* Enable Mailbox 14 */
+#define MC15 0x8000 /* Enable Mailbox 15 */
+
+/* CAN_MC2 Masks */
+#define MC16 0x0001 /* Enable Mailbox 16 */
+#define MC17 0x0002 /* Enable Mailbox 17 */
+#define MC18 0x0004 /* Enable Mailbox 18 */
+#define MC19 0x0008 /* Enable Mailbox 19 */
+#define MC20 0x0010 /* Enable Mailbox 20 */
+#define MC21 0x0020 /* Enable Mailbox 21 */
+#define MC22 0x0040 /* Enable Mailbox 22 */
+#define MC23 0x0080 /* Enable Mailbox 23 */
+#define MC24 0x0100 /* Enable Mailbox 24 */
+#define MC25 0x0200 /* Enable Mailbox 25 */
+#define MC26 0x0400 /* Enable Mailbox 26 */
+#define MC27 0x0800 /* Enable Mailbox 27 */
+#define MC28 0x1000 /* Enable Mailbox 28 */
+#define MC29 0x2000 /* Enable Mailbox 29 */
+#define MC30 0x4000 /* Enable Mailbox 30 */
+#define MC31 0x8000 /* Enable Mailbox 31 */
+
+/* CAN_MD1 Masks */
+#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
+#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
+#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
+#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
+#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
+#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
+#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
+#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
+#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
+#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
+#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
+#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
+#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
+#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
+#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
+#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
+
+/* CAN_MD2 Masks */
+#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
+#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
+#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
+#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
+#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
+#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
+#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
+#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
+#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
+#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
+#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
+#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
+#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
+#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
+#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
+#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
+
+/* CAN_RMP1 Masks */
+#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
+#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
+#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
+#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
+#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
+#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
+#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
+#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
+#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
+#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
+#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
+#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
+#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
+#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
+#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
+#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
+
+/* CAN_RMP2 Masks */
+#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
+#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
+#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
+#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
+#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
+#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
+#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
+#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
+#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
+#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
+#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
+#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
+#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
+#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
+#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
+#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
+
+/* CAN_RML1 Masks */
+#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
+#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
+#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
+#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
+#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
+#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
+#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
+#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
+#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
+#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
+#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
+#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
+#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
+#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
+#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
+#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
+
+/* CAN_RML2 Masks */
+#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
+#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
+#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
+#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
+#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
+#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
+#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
+#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
+#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
+#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
+#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
+#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
+#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
+#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
+#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
+#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
+
+/* CAN_OPSS1 Masks */
+#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
+#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
+#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
+#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
+#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
+#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
+#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
+#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
+#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
+#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
+#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
+#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
+#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
+#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
+#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
+#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
+
+/* CAN_OPSS2 Masks */
+#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
+#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
+#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
+#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
+#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
+#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
+#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
+#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
+#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
+#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
+#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
+#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
+#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
+#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
+#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
+#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
+
+/* CAN_TRR1 Masks */
+#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
+#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
+#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
+#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
+#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
+#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
+#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
+#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
+#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
+#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
+#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
+#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
+#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
+#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
+#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
+#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
+
+/* CAN_TRR2 Masks */
+#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
+#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
+#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
+#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
+#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
+#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
+#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
+#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
+#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
+#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
+#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
+#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
+#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
+#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
+#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
+#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
+
+/* CAN_TRS1 Masks */
+#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
+#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
+#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
+#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
+#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
+#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
+#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
+#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
+#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
+#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
+#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
+#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
+#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
+#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
+#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
+#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
+
+/* CAN_TRS2 Masks */
+#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
+#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
+#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
+#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
+#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
+#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
+#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
+#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
+#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
+#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
+#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
+#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
+#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
+#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
+#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
+#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
+
+/* CAN_AA1 Masks */
+#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
+#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
+#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
+#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
+#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
+#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
+#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
+#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
+#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
+#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
+#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
+#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
+#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
+#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
+#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
+#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
+
+/* CAN_AA2 Masks */
+#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
+#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
+#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
+#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
+#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
+#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
+#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
+#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
+#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
+#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
+#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
+#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
+#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
+#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
+#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
+#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
+
+/* CAN_TA1 Masks */
+#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
+#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
+#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
+#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
+#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
+#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
+#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
+#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
+#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
+#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
+#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
+#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
+#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
+#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
+#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
+#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
+
+/* CAN_TA2 Masks */
+#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
+#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
+#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
+#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
+#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
+#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
+#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
+#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
+#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
+#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
+#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
+#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
+#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
+#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
+#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
+#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
+
+/* CAN_MBTD Masks */
+#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
+#define TDA 0x0040 /* Temporary Disable Acknowledge */
+#define TDR 0x0080 /* Temporary Disable Request */
+
+/* CAN_RFH1 Masks */
+#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
+#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
+#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
+#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
+#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
+#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
+#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
+#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
+#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
+#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
+#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
+#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
+#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
+#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
+#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
+#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
+
+/* CAN_RFH2 Masks */
+#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
+#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
+#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
+#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
+#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
+#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
+#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
+#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
+#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
+#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
+#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
+#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
+#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
+#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
+#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
+#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
+
+/* CAN_MBTIF1 Masks */
+#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
+#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
+#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
+#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
+#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
+#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
+#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
+#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
+#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
+#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
+#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
+#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
+#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
+#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
+#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
+#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBTIF2 Masks */
+#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
+#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
+#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
+#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
+#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
+#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
+#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
+#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
+#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
+#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
+#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
+#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
+#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
+#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
+#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
+#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBRIF1 Masks */
+#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
+#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
+#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
+#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
+#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
+#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
+#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
+#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
+#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
+#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
+#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
+#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
+#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
+#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
+#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
+#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBRIF2 Masks */
+#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
+#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
+#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
+#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
+#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
+#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
+#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
+#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
+#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
+#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
+#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
+#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
+#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
+#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
+#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
+#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBIM1 Masks */
+#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
+#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
+#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
+#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
+#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
+#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
+#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
+#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
+#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
+#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
+#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
+#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
+#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
+#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
+#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
+#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
+
+/* CAN_MBIM2 Masks */
+#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
+#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
+#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
+#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
+#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
+#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
+#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
+#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
+#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
+#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
+#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
+#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
+#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
+#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
+#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
+#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
+
+/* CAN_GIM Masks */
+#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
+#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
+#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
+#define BOIM 0x0008 /* Enable Bus Off Interrupt */
+#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
+#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
+#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
+#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
+#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
+#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
+#define ADIM 0x0400 /* Enable Access Denied Interrupt */
+
+/* CAN_GIS Masks */
+#define EWTIS 0x0001 /* TX Error Count IRQ Status */
+#define EWRIS 0x0002 /* RX Error Count IRQ Status */
+#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
+#define BOIS 0x0008 /* Bus Off IRQ Status */
+#define WUIS 0x0010 /* Wake-Up IRQ Status */
+#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
+#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
+#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
+#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
+#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
+#define ADIS 0x0400 /* Access Denied IRQ Status */
+
+/* CAN_GIF Masks */
+#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
+#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
+#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
+#define BOIF 0x0008 /* Bus Off IRQ Flag */
+#define WUIF 0x0010 /* Wake-Up IRQ Flag */
+#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
+#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
+#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
+#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
+#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
+#define ADIF 0x0400 /* Access Denied IRQ Flag */
+
+/* CAN_UCCNF Masks */
+#define UCCNF 0x000F /* Universal Counter Mode */
+#define UC_STAMP 0x0001 /* Timestamp Mode */
+#define UC_WDOG 0x0002 /* Watchdog Mode */
+#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
+#define UC_ERROR 0x0006 /* CAN Error Frame Count */
+#define UC_OVER 0x0007 /* CAN Overload Frame Count */
+#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
+#define UC_AA 0x0009 /* TX Abort Count */
+#define UC_TA 0x000A /* TX Successful Count */
+#define UC_REJECT 0x000B /* RX Message Rejected Count */
+#define UC_RML 0x000C /* RX Message Lost Count */
+#define UC_RX 0x000D /* Total Successful RX Messages Count */
+#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
+#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
+#define UCRC 0x0020 /* Universal Counter Reload/Clear */
+#define UCCT 0x0040 /* Universal Counter CAN Trigger */
+#define UCE 0x0080 /* Universal Counter Enable */
+
+/* CAN_ESR Masks */
+#define ACKE 0x0004 /* Acknowledge Error */
+#define SER 0x0008 /* Stuff Error */
+#define CRCE 0x0010 /* CRC Error */
+#define SA0 0x0020 /* Stuck At Dominant Error */
+#define BEF 0x0040 /* Bit Error Flag */
+#define FER 0x0080 /* Form Error Flag */
+
+/* CAN_EWR Masks */
+#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
+#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define CAN_CNF CAN_DEBUG
+#define TWI0_PRESCALE TWI0_CONTROL
+#define TWI0_INT_SRC TWI0_INT_STAT
+#define TWI0_INT_ENABLE TWI0_INT_MASK
+#define TWI1_PRESCALE TWI1_CONTROL
+#define TWI1_INT_SRC TWI1_INT_STAT
+#define TWI1_INT_ENABLE TWI1_INT_MASK
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF538_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for Stirling peripherals.
+**
+*/
+#ifndef _DEF_BF539_H
+#define _DEF_BF539_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/*********************************************************************************** */
+/* System MMR Register Map */
+/*********************************************************************************** */
+/* Clock/Regulator Control (0xFFC00000 - 0xFFC000FF) */
+#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
+#define CHIPID 0xFFC00014 /* Chip ID Register */
+
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
+#define SYSCR 0xFFC00104 /* System Configuration registe */
+#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */
+#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
+#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
+#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */
+#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */
+#define SIC_IMASK1 0xFFC00128 /* Interrupt Mask Register 1 */
+#define SIC_ISR1 0xFFC0012C /* Interrupt Status Register 1 */
+#define SIC_IWR1 0xFFC00130 /* Interrupt Wakeup Register 1 */
+#define SIC_IAR4 0xFFC00134 /* Interrupt Assignment Register 4 */
+#define SIC_IAR5 0xFFC00138 /* Interrupt Assignment Register 5 */
+#define SIC_IAR6 0xFFC0013C /* Interrupt Assignment Register 6 */
+
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
+
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT 0xFFC00300 /* RTC Status Register */
+#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
+#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
+#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
+#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
+
+
+/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART0_THR 0xFFC00400 /* Transmit Holding register */
+#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
+#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
+#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define UART0_LCR 0xFFC0040C /* Line Control Register */
+#define UART0_MCR 0xFFC00410 /* Modem Control Register */
+#define UART0_LSR 0xFFC00414 /* Line Status Register */
+#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
+#define UART0_GCTL 0xFFC00424 /* Global Control Register */
+
+
+/* SPI0 Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */
+#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */
+#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */
+#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */
+#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */
+
+
+/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
+#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
+
+#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
+
+#define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */
+#define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */
+#define TIMER_STATUS 0xFFC00648 /* Timer Status Register */
+
+
+/* Programmable Flags (0xFFC00700 - 0xFFC007FF) */
+#define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */
+#define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */
+#define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */
+#define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */
+#define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */
+#define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */
+#define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */
+#define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */
+#define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */
+#define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */
+#define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */
+#define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */
+#define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */
+#define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */
+#define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */
+#define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */
+#define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */
+
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+/* Asynchronous Memory Controller */
+#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller */
+#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
+
+
+
+/* DMA Controller 0 Traffic Control Registers (0xFFC00B00 - 0xFFC00BFF) */
+
+#define DMAC0_TC_PER 0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TC_CNT 0xFFC00B10 /* DMA Controller 0 Traffic Control Current Counts Register */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA0_TCPER DMAC0_TC_PER
+#define DMA0_TCCNT DMAC0_TC_CNT
+
+
+/* DMA Controller 0 (0xFFC00C00 - 0xFFC00FFF) */
+
+#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
+
+#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
+
+#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
+
+#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
+
+#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
+
+#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
+
+#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
+
+#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
+
+#define MDMA0_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA0 Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA0_D0_START_ADDR 0xFFC00E04 /* MemDMA0 Stream 0 Destination Start Address Register */
+#define MDMA0_D0_CONFIG 0xFFC00E08 /* MemDMA0 Stream 0 Destination Configuration Register */
+#define MDMA0_D0_X_COUNT 0xFFC00E10 /* MemDMA0 Stream 0 Destination X Count Register */
+#define MDMA0_D0_X_MODIFY 0xFFC00E14 /* MemDMA0 Stream 0 Destination X Modify Register */
+#define MDMA0_D0_Y_COUNT 0xFFC00E18 /* MemDMA0 Stream 0 Destination Y Count Register */
+#define MDMA0_D0_Y_MODIFY 0xFFC00E1C /* MemDMA0 Stream 0 Destination Y Modify Register */
+#define MDMA0_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA0 Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA0_D0_CURR_ADDR 0xFFC00E24 /* MemDMA0 Stream 0 Destination Current Address Register */
+#define MDMA0_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA0 Stream 0 Destination Interrupt/Status Register */
+#define MDMA0_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA0 Stream 0 Destination Peripheral Map Register */
+#define MDMA0_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA0 Stream 0 Destination Current X Count Register */
+#define MDMA0_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA0 Stream 0 Destination Current Y Count Register */
+
+#define MDMA0_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA0 Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA0_S0_START_ADDR 0xFFC00E44 /* MemDMA0 Stream 0 Source Start Address Register */
+#define MDMA0_S0_CONFIG 0xFFC00E48 /* MemDMA0 Stream 0 Source Configuration Register */
+#define MDMA0_S0_X_COUNT 0xFFC00E50 /* MemDMA0 Stream 0 Source X Count Register */
+#define MDMA0_S0_X_MODIFY 0xFFC00E54 /* MemDMA0 Stream 0 Source X Modify Register */
+#define MDMA0_S0_Y_COUNT 0xFFC00E58 /* MemDMA0 Stream 0 Source Y Count Register */
+#define MDMA0_S0_Y_MODIFY 0xFFC00E5C /* MemDMA0 Stream 0 Source Y Modify Register */
+#define MDMA0_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA0 Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA0_S0_CURR_ADDR 0xFFC00E64 /* MemDMA0 Stream 0 Source Current Address Register */
+#define MDMA0_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA0 Stream 0 Source Interrupt/Status Register */
+#define MDMA0_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA0 Stream 0 Source Peripheral Map Register */
+#define MDMA0_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA0 Stream 0 Source Current X Count Register */
+#define MDMA0_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA0 Stream 0 Source Current Y Count Register */
+
+#define MDMA0_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA0 Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA0_D1_START_ADDR 0xFFC00E84 /* MemDMA0 Stream 1 Destination Start Address Register */
+#define MDMA0_D1_CONFIG 0xFFC00E88 /* MemDMA0 Stream 1 Destination Configuration Register */
+#define MDMA0_D1_X_COUNT 0xFFC00E90 /* MemDMA0 Stream 1 Destination X Count Register */
+#define MDMA0_D1_X_MODIFY 0xFFC00E94 /* MemDMA0 Stream 1 Destination X Modify Register */
+#define MDMA0_D1_Y_COUNT 0xFFC00E98 /* MemDMA0 Stream 1 Destination Y Count Register */
+#define MDMA0_D1_Y_MODIFY 0xFFC00E9C /* MemDMA0 Stream 1 Destination Y Modify Register */
+#define MDMA0_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA0 Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA0_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA0 Stream 1 Destination Current Address Register */
+#define MDMA0_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA0 Stream 1 Destination Interrupt/Status Register */
+#define MDMA0_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA0 Stream 1 Destination Peripheral Map Register */
+#define MDMA0_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA0 Stream 1 Destination Current X Count Register */
+#define MDMA0_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA0 Stream 1 Destination Current Y Count Register */
+
+#define MDMA0_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA0 Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA0_S1_START_ADDR 0xFFC00EC4 /* MemDMA0 Stream 1 Source Start Address Register */
+#define MDMA0_S1_CONFIG 0xFFC00EC8 /* MemDMA0 Stream 1 Source Configuration Register */
+#define MDMA0_S1_X_COUNT 0xFFC00ED0 /* MemDMA0 Stream 1 Source X Count Register */
+#define MDMA0_S1_X_MODIFY 0xFFC00ED4 /* MemDMA0 Stream 1 Source X Modify Register */
+#define MDMA0_S1_Y_COUNT 0xFFC00ED8 /* MemDMA0 Stream 1 Source Y Count Register */
+#define MDMA0_S1_Y_MODIFY 0xFFC00EDC /* MemDMA0 Stream 1 Source Y Modify Register */
+#define MDMA0_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA0 Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA0_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA0 Stream 1 Source Current Address Register */
+#define MDMA0_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA0 Stream 1 Source Interrupt/Status Register */
+#define MDMA0_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA0 Stream 1 Source Peripheral Map Register */
+#define MDMA0_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA0 Stream 1 Source Current X Count Register */
+#define MDMA0_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA0 Stream 1 Source Current Y Count Register */
+
+
+/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
+#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
+#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
+#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
+#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
+#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
+
+
+/* Two-Wire Interface 0 (0xFFC01400 - 0xFFC014FF) */
+#define TWI0_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
+#define TWI0_CONTROL 0xFFC01404 /* TWI0 Master Internal Time Reference Register */
+#define TWI0_SLAVE_CTRL 0xFFC01408 /* Slave Mode Control Register */
+#define TWI0_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
+#define TWI0_MASTER_CTRL 0xFFC01414 /* Master Mode Control Register */
+#define TWI0_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
+#define TWI0_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
+#define TWI0_INT_STAT 0xFFC01420 /* TWI0 Master Interrupt Register */
+#define TWI0_INT_MASK 0xFFC01424 /* TWI0 Master Interrupt Mask Register */
+#define TWI0_FIFO_CTRL 0xFFC01428 /* FIFO Control Register */
+#define TWI0_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
+#define TWI0_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
+
+/* the following are for backwards compatibility */
+#define TWI0_PRESCALE TWI0_CONTROL
+#define TWI0_INT_SRC TWI0_INT_STAT
+#define TWI0_INT_ENABLE TWI0_INT_MASK
+
+
+/* General-Purpose Ports (0xFFC01500 - 0xFFC015FF) */
+
+/* GPIO Port C Register Names */
+#define GPIO_C_CNFG 0xFFC01500 /* GPIO Pin Port C Configuration Register */
+#define GPIO_C_D 0xFFC01510 /* GPIO Pin Port C Data Register */
+#define GPIO_C_C 0xFFC01520 /* Clear GPIO Pin Port C Register */
+#define GPIO_C_S 0xFFC01530 /* Set GPIO Pin Port C Register */
+#define GPIO_C_T 0xFFC01540 /* Toggle GPIO Pin Port C Register */
+#define GPIO_C_DIR 0xFFC01550 /* GPIO Pin Port C Direction Register */
+#define GPIO_C_INEN 0xFFC01560 /* GPIO Pin Port C Input Enable Register */
+
+/* GPIO Port D Register Names */
+#define GPIO_D_CNFG 0xFFC01504 /* GPIO Pin Port D Configuration Register */
+#define GPIO_D_D 0xFFC01514 /* GPIO Pin Port D Data Register */
+#define GPIO_D_C 0xFFC01524 /* Clear GPIO Pin Port D Register */
+#define GPIO_D_S 0xFFC01534 /* Set GPIO Pin Port D Register */
+#define GPIO_D_T 0xFFC01544 /* Toggle GPIO Pin Port D Register */
+#define GPIO_D_DIR 0xFFC01554 /* GPIO Pin Port D Direction Register */
+#define GPIO_D_INEN 0xFFC01564 /* GPIO Pin Port D Input Enable Register */
+
+/* GPIO Port E Register Names */
+#define GPIO_E_CNFG 0xFFC01508 /* GPIO Pin Port E Configuration Register */
+#define GPIO_E_D 0xFFC01518 /* GPIO Pin Port E Data Register */
+#define GPIO_E_C 0xFFC01528 /* Clear GPIO Pin Port E Register */
+#define GPIO_E_S 0xFFC01538 /* Set GPIO Pin Port E Register */
+#define GPIO_E_T 0xFFC01548 /* Toggle GPIO Pin Port E Register */
+#define GPIO_E_DIR 0xFFC01558 /* GPIO Pin Port E Direction Register */
+#define GPIO_E_INEN 0xFFC01568 /* GPIO Pin Port E Input Enable Register */
+
+/* Deprecate old macros */
+#define GPIO_C_DAT GPIO_C_D
+#define GPIO_C_CLR GPIO_C_C
+#define GPIO_C_SET GPIO_C_S
+#define GPIO_C_TGL GPIO_C_T
+
+#define GPIO_D_DAT GPIO_D_D
+#define GPIO_D_CLR GPIO_D_C
+#define GPIO_D_SET GPIO_D_S
+#define GPIO_D_TGL GPIO_D_T
+
+#define GPIO_E_DAT GPIO_E_D
+#define GPIO_E_CLR GPIO_E_C
+#define GPIO_E_SET GPIO_E_S
+#define GPIO_E_TGL GPIO_E_T
+
+/* DMA Controller 1 Traffic Control Registers (0xFFC01B00 - 0xFFC01BFF) */
+
+#define DMAC1_TC_PER 0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TC_CNT 0xFFC01B10 /* DMA Controller 1 Traffic Control Current Counts Register */
+
+/* Alternate deprecated register names (below) provided for backwards code compatibility */
+#define DMA1_TCPER DMAC1_TC_PER
+#define DMA1_TCCNT DMAC1_TC_CNT
+
+
+/* DMA Controller 1 (0xFFC01C00 - 0xFFC01FFF) */
+#define DMA8_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR 0xFFC01C04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG 0xFFC01C08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT 0xFFC01C10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY 0xFFC01C14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT 0xFFC01C18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY 0xFFC01C1C /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR 0xFFC01C24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS 0xFFC01C28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 8 Current Y Count Register */
+
+#define DMA9_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR 0xFFC01C44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG 0xFFC01C48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT 0xFFC01C50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY 0xFFC01C54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT 0xFFC01C58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY 0xFFC01C5C /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR 0xFFC01C64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS 0xFFC01C68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 9 Current Y Count Register */
+
+#define DMA10_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR 0xFFC01C84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG 0xFFC01C88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT 0xFFC01C90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY 0xFFC01C94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT 0xFFC01C98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY 0xFFC01C9C /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR 0xFFC01CA4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 10 Current Y Count Register */
+
+#define DMA11_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR 0xFFC01CC4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG 0xFFC01CC8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT 0xFFC01CD0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY 0xFFC01CD4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT 0xFFC01CD8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY 0xFFC01CDC /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR 0xFFC01CE4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 11 Current Y Count Register */
+
+#define DMA12_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR 0xFFC01D04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG 0xFFC01D08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT 0xFFC01D10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY 0xFFC01D14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT 0xFFC01D18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY 0xFFC01D1C /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR 0xFFC01D24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS 0xFFC01D28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 12 Current Y Count Register */
+
+#define DMA13_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR 0xFFC01D44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG 0xFFC01D48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT 0xFFC01D50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY 0xFFC01D54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT 0xFFC01D58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY 0xFFC01D5C /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR 0xFFC01D64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS 0xFFC01D68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 13 Current Y Count Register */
+
+#define DMA14_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR 0xFFC01D84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG 0xFFC01D88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT 0xFFC01D90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY 0xFFC01D94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT 0xFFC01D98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY 0xFFC01D9C /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR 0xFFC01DA4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT 0xFFC01DB8 /* DMA Channel 14 Current Y Count Register */
+
+#define DMA15_NEXT_DESC_PTR 0xFFC01DC0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR 0xFFC01DC4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG 0xFFC01DC8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT 0xFFC01DD0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY 0xFFC01DD4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT 0xFFC01DD8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY 0xFFC01DDC /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR 0xFFC01DE0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR 0xFFC01DE4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS 0xFFC01DE8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP 0xFFC01DEC /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT 0xFFC01DF0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT 0xFFC01DF8 /* DMA Channel 15 Current Y Count Register */
+
+#define DMA16_NEXT_DESC_PTR 0xFFC01E00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR 0xFFC01E04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG 0xFFC01E08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT 0xFFC01E10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY 0xFFC01E14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT 0xFFC01E18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY 0xFFC01E1C /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR 0xFFC01E20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR 0xFFC01E24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS 0xFFC01E28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP 0xFFC01E2C /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT 0xFFC01E30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT 0xFFC01E38 /* DMA Channel 16 Current Y Count Register */
+
+#define DMA17_NEXT_DESC_PTR 0xFFC01E40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR 0xFFC01E44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG 0xFFC01E48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT 0xFFC01E50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY 0xFFC01E54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT 0xFFC01E58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY 0xFFC01E5C /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR 0xFFC01E60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR 0xFFC01E64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS 0xFFC01E68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP 0xFFC01E6C /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT 0xFFC01E70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT 0xFFC01E78 /* DMA Channel 17 Current Y Count Register */
+
+#define DMA18_NEXT_DESC_PTR 0xFFC01E80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR 0xFFC01E84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG 0xFFC01E88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT 0xFFC01E90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY 0xFFC01E94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT 0xFFC01E98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY 0xFFC01E9C /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR 0xFFC01EA0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR 0xFFC01EA4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS 0xFFC01EA8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP 0xFFC01EAC /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT 0xFFC01EB0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT 0xFFC01EB8 /* DMA Channel 18 Current Y Count Register */
+
+#define DMA19_NEXT_DESC_PTR 0xFFC01EC0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR 0xFFC01EC4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG 0xFFC01EC8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT 0xFFC01ED0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY 0xFFC01ED4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT 0xFFC01ED8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY 0xFFC01EDC /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR 0xFFC01EE0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR 0xFFC01EE4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS 0xFFC01EE8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP 0xFFC01EEC /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT 0xFFC01EF0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT 0xFFC01EF8 /* DMA Channel 19 Current Y Count Register */
+
+#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /* MemDMA1 Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA1_D0_START_ADDR 0xFFC01F04 /* MemDMA1 Stream 0 Destination Start Address Register */
+#define MDMA1_D0_CONFIG 0xFFC01F08 /* MemDMA1 Stream 0 Destination Configuration Register */
+#define MDMA1_D0_X_COUNT 0xFFC01F10 /* MemDMA1 Stream 0 Destination X Count Register */
+#define MDMA1_D0_X_MODIFY 0xFFC01F14 /* MemDMA1 Stream 0 Destination X Modify Register */
+#define MDMA1_D0_Y_COUNT 0xFFC01F18 /* MemDMA1 Stream 0 Destination Y Count Register */
+#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /* MemDMA1 Stream 0 Destination Y Modify Register */
+#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /* MemDMA1 Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /* MemDMA1 Stream 0 Destination Current Address Register */
+#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /* MemDMA1 Stream 0 Destination Interrupt/Status Register */
+#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /* MemDMA1 Stream 0 Destination Peripheral Map Register */
+#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /* MemDMA1 Stream 0 Destination Current X Count Register */
+#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /* MemDMA1 Stream 0 Destination Current Y Count Register */
+
+#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /* MemDMA1 Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA1_S0_START_ADDR 0xFFC01F44 /* MemDMA1 Stream 0 Source Start Address Register */
+#define MDMA1_S0_CONFIG 0xFFC01F48 /* MemDMA1 Stream 0 Source Configuration Register */
+#define MDMA1_S0_X_COUNT 0xFFC01F50 /* MemDMA1 Stream 0 Source X Count Register */
+#define MDMA1_S0_X_MODIFY 0xFFC01F54 /* MemDMA1 Stream 0 Source X Modify Register */
+#define MDMA1_S0_Y_COUNT 0xFFC01F58 /* MemDMA1 Stream 0 Source Y Count Register */
+#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /* MemDMA1 Stream 0 Source Y Modify Register */
+#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /* MemDMA1 Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /* MemDMA1 Stream 0 Source Current Address Register */
+#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /* MemDMA1 Stream 0 Source Interrupt/Status Register */
+#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /* MemDMA1 Stream 0 Source Peripheral Map Register */
+#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /* MemDMA1 Stream 0 Source Current X Count Register */
+#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /* MemDMA1 Stream 0 Source Current Y Count Register */
+
+#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /* MemDMA1 Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA1_D1_START_ADDR 0xFFC01F84 /* MemDMA1 Stream 1 Destination Start Address Register */
+#define MDMA1_D1_CONFIG 0xFFC01F88 /* MemDMA1 Stream 1 Destination Configuration Register */
+#define MDMA1_D1_X_COUNT 0xFFC01F90 /* MemDMA1 Stream 1 Destination X Count Register */
+#define MDMA1_D1_X_MODIFY 0xFFC01F94 /* MemDMA1 Stream 1 Destination X Modify Register */
+#define MDMA1_D1_Y_COUNT 0xFFC01F98 /* MemDMA1 Stream 1 Destination Y Count Register */
+#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /* MemDMA1 Stream 1 Destination Y Modify Register */
+#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /* MemDMA1 Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /* MemDMA1 Stream 1 Destination Current Address Register */
+#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /* MemDMA1 Stream 1 Destination Interrupt/Status Register */
+#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /* MemDMA1 Stream 1 Destination Peripheral Map Register */
+#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /* MemDMA1 Stream 1 Destination Current X Count Register */
+#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /* MemDMA1 Stream 1 Destination Current Y Count Register */
+
+#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /* MemDMA1 Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA1_S1_START_ADDR 0xFFC01FC4 /* MemDMA1 Stream 1 Source Start Address Register */
+#define MDMA1_S1_CONFIG 0xFFC01FC8 /* MemDMA1 Stream 1 Source Configuration Register */
+#define MDMA1_S1_X_COUNT 0xFFC01FD0 /* MemDMA1 Stream 1 Source X Count Register */
+#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /* MemDMA1 Stream 1 Source X Modify Register */
+#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /* MemDMA1 Stream 1 Source Y Count Register */
+#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /* MemDMA1 Stream 1 Source Y Modify Register */
+#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /* MemDMA1 Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /* MemDMA1 Stream 1 Source Current Address Register */
+#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /* MemDMA1 Stream 1 Source Interrupt/Status Register */
+#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /* MemDMA1 Stream 1 Source Peripheral Map Register */
+#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /* MemDMA1 Stream 1 Source Current X Count Register */
+#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /* MemDMA1 Stream 1 Source Current Y Count Register */
+
+
+/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
+#define UART1_THR 0xFFC02000 /* Transmit Holding register */
+#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
+#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
+#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
+#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
+#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
+#define UART1_LCR 0xFFC0200C /* Line Control Register */
+#define UART1_MCR 0xFFC02010 /* Modem Control Register */
+#define UART1_LSR 0xFFC02014 /* Line Status Register */
+#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
+#define UART1_GCTL 0xFFC02024 /* Global Control Register */
+
+
+/* UART2 Controller (0xFFC02100 - 0xFFC021FF) */
+#define UART2_THR 0xFFC02100 /* Transmit Holding register */
+#define UART2_RBR 0xFFC02100 /* Receive Buffer register */
+#define UART2_DLL 0xFFC02100 /* Divisor Latch (Low-Byte) */
+#define UART2_IER 0xFFC02104 /* Interrupt Enable Register */
+#define UART2_DLH 0xFFC02104 /* Divisor Latch (High-Byte) */
+#define UART2_IIR 0xFFC02108 /* Interrupt Identification Register */
+#define UART2_LCR 0xFFC0210C /* Line Control Register */
+#define UART2_MCR 0xFFC02110 /* Modem Control Register */
+#define UART2_LSR 0xFFC02114 /* Line Status Register */
+#define UART2_SCR 0xFFC0211C /* SCR Scratch Register */
+#define UART2_GCTL 0xFFC02124 /* Global Control Register */
+
+
+/* Two-Wire Interface 1 (0xFFC02200 - 0xFFC022FF) */
+#define TWI1_CLKDIV 0xFFC02200 /* Serial Clock Divider Register */
+#define TWI1_CONTROL 0xFFC02204 /* TWI1 Master Internal Time Reference Register */
+#define TWI1_SLAVE_CTRL 0xFFC02208 /* Slave Mode Control Register */
+#define TWI1_SLAVE_STAT 0xFFC0220C /* Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR 0xFFC02210 /* Slave Mode Address Register */
+#define TWI1_MASTER_CTRL 0xFFC02214 /* Master Mode Control Register */
+#define TWI1_MASTER_STAT 0xFFC02218 /* Master Mode Status Register */
+#define TWI1_MASTER_ADDR 0xFFC0221C /* Master Mode Address Register */
+#define TWI1_INT_STAT 0xFFC02220 /* TWI1 Master Interrupt Register */
+#define TWI1_INT_MASK 0xFFC02224 /* TWI1 Master Interrupt Mask Register */
+#define TWI1_FIFO_CTRL 0xFFC02228 /* FIFO Control Register */
+#define TWI1_FIFO_STAT 0xFFC0222C /* FIFO Status Register */
+#define TWI1_XMT_DATA8 0xFFC02280 /* FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16 0xFFC02284 /* FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8 0xFFC02288 /* FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16 0xFFC0228C /* FIFO Receive Data Double Byte Register */
+
+/* the following are for backwards compatibility */
+#define TWI1_PRESCALE TWI1_CONTROL
+#define TWI1_INT_SRC TWI1_INT_STAT
+#define TWI1_INT_ENABLE TWI1_INT_MASK
+
+
+/* SPI1 Controller (0xFFC02300 - 0xFFC023FF) */
+#define SPI1_CTL 0xFFC02300 /* SPI1 Control Register */
+#define SPI1_FLG 0xFFC02304 /* SPI1 Flag register */
+#define SPI1_STAT 0xFFC02308 /* SPI1 Status register */
+#define SPI1_TDBR 0xFFC0230C /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR 0xFFC02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD 0xFFC02314 /* SPI1 Baud rate Register */
+#define SPI1_SHADOW 0xFFC02318 /* SPI1_RDBR Shadow Register */
+
+
+/* SPI2 Controller (0xFFC02400 - 0xFFC024FF) */
+#define SPI2_CTL 0xFFC02400 /* SPI2 Control Register */
+#define SPI2_FLG 0xFFC02404 /* SPI2 Flag register */
+#define SPI2_STAT 0xFFC02408 /* SPI2 Status register */
+#define SPI2_TDBR 0xFFC0240C /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR 0xFFC02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD 0xFFC02414 /* SPI2 Baud rate Register */
+#define SPI2_SHADOW 0xFFC02418 /* SPI2_RDBR Shadow Register */
+
+
+/* SPORT2 Controller (0xFFC02500 - 0xFFC025FF) */
+#define SPORT2_TCR1 0xFFC02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2 0xFFC02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV 0xFFC02508 /* SPORT2 Transmit Clock Divider */
+#define SPORT2_TFSDIV 0xFFC0250C /* SPORT2 Transmit Frame Sync Divider */
+#define SPORT2_TX 0xFFC02510 /* SPORT2 TX Data Register */
+#define SPORT2_RX 0xFFC02518 /* SPORT2 RX Data Register */
+#define SPORT2_RCR1 0xFFC02520 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_RCR2 0xFFC02524 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_RCLKDIV 0xFFC02528 /* SPORT2 Receive Clock Divider */
+#define SPORT2_RFSDIV 0xFFC0252C /* SPORT2 Receive Frame Sync Divider */
+#define SPORT2_STAT 0xFFC02530 /* SPORT2 Status Register */
+#define SPORT2_CHNL 0xFFC02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MCMC1 0xFFC02538 /* SPORT2 Multi-Channel Configuration Register 1 */
+#define SPORT2_MCMC2 0xFFC0253C /* SPORT2 Multi-Channel Configuration Register 2 */
+#define SPORT2_MTCS0 0xFFC02540 /* SPORT2 Multi-Channel Transmit Select Register 0 */
+#define SPORT2_MTCS1 0xFFC02544 /* SPORT2 Multi-Channel Transmit Select Register 1 */
+#define SPORT2_MTCS2 0xFFC02548 /* SPORT2 Multi-Channel Transmit Select Register 2 */
+#define SPORT2_MTCS3 0xFFC0254C /* SPORT2 Multi-Channel Transmit Select Register 3 */
+#define SPORT2_MRCS0 0xFFC02550 /* SPORT2 Multi-Channel Receive Select Register 0 */
+#define SPORT2_MRCS1 0xFFC02554 /* SPORT2 Multi-Channel Receive Select Register 1 */
+#define SPORT2_MRCS2 0xFFC02558 /* SPORT2 Multi-Channel Receive Select Register 2 */
+#define SPORT2_MRCS3 0xFFC0255C /* SPORT2 Multi-Channel Receive Select Register 3 */
+
+
+/* SPORT3 Controller (0xFFC02600 - 0xFFC026FF) */
+#define SPORT3_TCR1 0xFFC02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2 0xFFC02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV 0xFFC02608 /* SPORT3 Transmit Clock Divider */
+#define SPORT3_TFSDIV 0xFFC0260C /* SPORT3 Transmit Frame Sync Divider */
+#define SPORT3_TX 0xFFC02610 /* SPORT3 TX Data Register */
+#define SPORT3_RX 0xFFC02618 /* SPORT3 RX Data Register */
+#define SPORT3_RCR1 0xFFC02620 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_RCR2 0xFFC02624 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */
+#define SPORT3_RFSDIV 0xFFC0262C /* SPORT3 Receive Frame Sync Divider */
+#define SPORT3_STAT 0xFFC02630 /* SPORT3 Status Register */
+#define SPORT3_CHNL 0xFFC02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MCMC1 0xFFC02638 /* SPORT3 Multi-Channel Configuration Register 1 */
+#define SPORT3_MCMC2 0xFFC0263C /* SPORT3 Multi-Channel Configuration Register 2 */
+#define SPORT3_MTCS0 0xFFC02640 /* SPORT3 Multi-Channel Transmit Select Register 0 */
+#define SPORT3_MTCS1 0xFFC02644 /* SPORT3 Multi-Channel Transmit Select Register 1 */
+#define SPORT3_MTCS2 0xFFC02648 /* SPORT3 Multi-Channel Transmit Select Register 2 */
+#define SPORT3_MTCS3 0xFFC0264C /* SPORT3 Multi-Channel Transmit Select Register 3 */
+#define SPORT3_MRCS0 0xFFC02650 /* SPORT3 Multi-Channel Receive Select Register 0 */
+#define SPORT3_MRCS1 0xFFC02654 /* SPORT3 Multi-Channel Receive Select Register 1 */
+#define SPORT3_MRCS2 0xFFC02658 /* SPORT3 Multi-Channel Receive Select Register 2 */
+#define SPORT3_MRCS3 0xFFC0265C /* SPORT3 Multi-Channel Receive Select Register 3 */
+
+
+/* Media Transceiver (MXVR) (0xFFC02700 - 0xFFC028FF) */
+
+#define MXVR_CONFIG 0xFFC02700 /* MXVR Configuration Register */
+#define MXVR_PLL_CTL_0 0xFFC02704 /* MXVR Phase Lock Loop Control Register 0 */
+
+#define MXVR_STATE_0 0xFFC02708 /* MXVR State Register 0 */
+#define MXVR_STATE_1 0xFFC0270C /* MXVR State Register 1 */
+
+#define MXVR_INT_STAT_0 0xFFC02710 /* MXVR Interrupt Status Register 0 */
+#define MXVR_INT_STAT_1 0xFFC02714 /* MXVR Interrupt Status Register 1 */
+
+#define MXVR_INT_EN_0 0xFFC02718 /* MXVR Interrupt Enable Register 0 */
+#define MXVR_INT_EN_1 0xFFC0271C /* MXVR Interrupt Enable Register 1 */
+
+#define MXVR_POSITION 0xFFC02720 /* MXVR Node Position Register */
+#define MXVR_MAX_POSITION 0xFFC02724 /* MXVR Maximum Node Position Register */
+
+#define MXVR_DELAY 0xFFC02728 /* MXVR Node Frame Delay Register */
+#define MXVR_MAX_DELAY 0xFFC0272C /* MXVR Maximum Node Frame Delay Register */
+
+#define MXVR_LADDR 0xFFC02730 /* MXVR Logical Address Register */
+#define MXVR_GADDR 0xFFC02734 /* MXVR Group Address Register */
+#define MXVR_AADDR 0xFFC02738 /* MXVR Alternate Address Register */
+
+#define MXVR_ALLOC_0 0xFFC0273C /* MXVR Allocation Table Register 0 */
+#define MXVR_ALLOC_1 0xFFC02740 /* MXVR Allocation Table Register 1 */
+#define MXVR_ALLOC_2 0xFFC02744 /* MXVR Allocation Table Register 2 */
+#define MXVR_ALLOC_3 0xFFC02748 /* MXVR Allocation Table Register 3 */
+#define MXVR_ALLOC_4 0xFFC0274C /* MXVR Allocation Table Register 4 */
+#define MXVR_ALLOC_5 0xFFC02750 /* MXVR Allocation Table Register 5 */
+#define MXVR_ALLOC_6 0xFFC02754 /* MXVR Allocation Table Register 6 */
+#define MXVR_ALLOC_7 0xFFC02758 /* MXVR Allocation Table Register 7 */
+#define MXVR_ALLOC_8 0xFFC0275C /* MXVR Allocation Table Register 8 */
+#define MXVR_ALLOC_9 0xFFC02760 /* MXVR Allocation Table Register 9 */
+#define MXVR_ALLOC_10 0xFFC02764 /* MXVR Allocation Table Register 10 */
+#define MXVR_ALLOC_11 0xFFC02768 /* MXVR Allocation Table Register 11 */
+#define MXVR_ALLOC_12 0xFFC0276C /* MXVR Allocation Table Register 12 */
+#define MXVR_ALLOC_13 0xFFC02770 /* MXVR Allocation Table Register 13 */
+#define MXVR_ALLOC_14 0xFFC02774 /* MXVR Allocation Table Register 14 */
+
+#define MXVR_SYNC_LCHAN_0 0xFFC02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
+#define MXVR_SYNC_LCHAN_1 0xFFC0277C /* MXVR Sync Data Logical Channel Assign Register 1 */
+#define MXVR_SYNC_LCHAN_2 0xFFC02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
+#define MXVR_SYNC_LCHAN_3 0xFFC02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
+#define MXVR_SYNC_LCHAN_4 0xFFC02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
+#define MXVR_SYNC_LCHAN_5 0xFFC0278C /* MXVR Sync Data Logical Channel Assign Register 5 */
+#define MXVR_SYNC_LCHAN_6 0xFFC02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
+#define MXVR_SYNC_LCHAN_7 0xFFC02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
+
+#define MXVR_DMA0_CONFIG 0xFFC02798 /* MXVR Sync Data DMA0 Config Register */
+#define MXVR_DMA0_START_ADDR 0xFFC0279C /* MXVR Sync Data DMA0 Start Address Register */
+#define MXVR_DMA0_COUNT 0xFFC027A0 /* MXVR Sync Data DMA0 Loop Count Register */
+#define MXVR_DMA0_CURR_ADDR 0xFFC027A4 /* MXVR Sync Data DMA0 Current Address Register */
+#define MXVR_DMA0_CURR_COUNT 0xFFC027A8 /* MXVR Sync Data DMA0 Current Loop Count Register */
+
+#define MXVR_DMA1_CONFIG 0xFFC027AC /* MXVR Sync Data DMA1 Config Register */
+#define MXVR_DMA1_START_ADDR 0xFFC027B0 /* MXVR Sync Data DMA1 Start Address Register */
+#define MXVR_DMA1_COUNT 0xFFC027B4 /* MXVR Sync Data DMA1 Loop Count Register */
+#define MXVR_DMA1_CURR_ADDR 0xFFC027B8 /* MXVR Sync Data DMA1 Current Address Register */
+#define MXVR_DMA1_CURR_COUNT 0xFFC027BC /* MXVR Sync Data DMA1 Current Loop Count Register */
+
+#define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */
+#define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */
+#define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */
+#define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */
+#define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */
+
+#define MXVR_DMA3_CONFIG 0xFFC027D4 /* MXVR Sync Data DMA3 Config Register */
+#define MXVR_DMA3_START_ADDR 0xFFC027D8 /* MXVR Sync Data DMA3 Start Address Register */
+#define MXVR_DMA3_COUNT 0xFFC027DC /* MXVR Sync Data DMA3 Loop Count Register */
+#define MXVR_DMA3_CURR_ADDR 0xFFC027E0 /* MXVR Sync Data DMA3 Current Address Register */
+#define MXVR_DMA3_CURR_COUNT 0xFFC027E4 /* MXVR Sync Data DMA3 Current Loop Count Register */
+
+#define MXVR_DMA4_CONFIG 0xFFC027E8 /* MXVR Sync Data DMA4 Config Register */
+#define MXVR_DMA4_START_ADDR 0xFFC027EC /* MXVR Sync Data DMA4 Start Address Register */
+#define MXVR_DMA4_COUNT 0xFFC027F0 /* MXVR Sync Data DMA4 Loop Count Register */
+#define MXVR_DMA4_CURR_ADDR 0xFFC027F4 /* MXVR Sync Data DMA4 Current Address Register */
+#define MXVR_DMA4_CURR_COUNT 0xFFC027F8 /* MXVR Sync Data DMA4 Current Loop Count Register */
+
+#define MXVR_DMA5_CONFIG 0xFFC027FC /* MXVR Sync Data DMA5 Config Register */
+#define MXVR_DMA5_START_ADDR 0xFFC02800 /* MXVR Sync Data DMA5 Start Address Register */
+#define MXVR_DMA5_COUNT 0xFFC02804 /* MXVR Sync Data DMA5 Loop Count Register */
+#define MXVR_DMA5_CURR_ADDR 0xFFC02808 /* MXVR Sync Data DMA5 Current Address Register */
+#define MXVR_DMA5_CURR_COUNT 0xFFC0280C /* MXVR Sync Data DMA5 Current Loop Count Register */
+
+#define MXVR_DMA6_CONFIG 0xFFC02810 /* MXVR Sync Data DMA6 Config Register */
+#define MXVR_DMA6_START_ADDR 0xFFC02814 /* MXVR Sync Data DMA6 Start Address Register */
+#define MXVR_DMA6_COUNT 0xFFC02818 /* MXVR Sync Data DMA6 Loop Count Register */
+#define MXVR_DMA6_CURR_ADDR 0xFFC0281C /* MXVR Sync Data DMA6 Current Address Register */
+#define MXVR_DMA6_CURR_COUNT 0xFFC02820 /* MXVR Sync Data DMA6 Current Loop Count Register */
+
+#define MXVR_DMA7_CONFIG 0xFFC02824 /* MXVR Sync Data DMA7 Config Register */
+#define MXVR_DMA7_START_ADDR 0xFFC02828 /* MXVR Sync Data DMA7 Start Address Register */
+#define MXVR_DMA7_COUNT 0xFFC0282C /* MXVR Sync Data DMA7 Loop Count Register */
+#define MXVR_DMA7_CURR_ADDR 0xFFC02830 /* MXVR Sync Data DMA7 Current Address Register */
+#define MXVR_DMA7_CURR_COUNT 0xFFC02834 /* MXVR Sync Data DMA7 Current Loop Count Register */
+
+#define MXVR_AP_CTL 0xFFC02838 /* MXVR Async Packet Control Register */
+#define MXVR_APRB_START_ADDR 0xFFC0283C /* MXVR Async Packet RX Buffer Start Addr Register */
+#define MXVR_APRB_CURR_ADDR 0xFFC02840 /* MXVR Async Packet RX Buffer Current Addr Register */
+#define MXVR_APTB_START_ADDR 0xFFC02844 /* MXVR Async Packet TX Buffer Start Addr Register */
+#define MXVR_APTB_CURR_ADDR 0xFFC02848 /* MXVR Async Packet TX Buffer Current Addr Register */
+
+#define MXVR_CM_CTL 0xFFC0284C /* MXVR Control Message Control Register */
+#define MXVR_CMRB_START_ADDR 0xFFC02850 /* MXVR Control Message RX Buffer Start Addr Register */
+#define MXVR_CMRB_CURR_ADDR 0xFFC02854 /* MXVR Control Message RX Buffer Current Address */
+#define MXVR_CMTB_START_ADDR 0xFFC02858 /* MXVR Control Message TX Buffer Start Addr Register */
+#define MXVR_CMTB_CURR_ADDR 0xFFC0285C /* MXVR Control Message TX Buffer Current Address */
+
+#define MXVR_RRDB_START_ADDR 0xFFC02860 /* MXVR Remote Read Buffer Start Addr Register */
+#define MXVR_RRDB_CURR_ADDR 0xFFC02864 /* MXVR Remote Read Buffer Current Addr Register */
+
+#define MXVR_PAT_DATA_0 0xFFC02868 /* MXVR Pattern Data Register 0 */
+#define MXVR_PAT_EN_0 0xFFC0286C /* MXVR Pattern Enable Register 0 */
+#define MXVR_PAT_DATA_1 0xFFC02870 /* MXVR Pattern Data Register 1 */
+#define MXVR_PAT_EN_1 0xFFC02874 /* MXVR Pattern Enable Register 1 */
+
+#define MXVR_FRAME_CNT_0 0xFFC02878 /* MXVR Frame Counter 0 */
+#define MXVR_FRAME_CNT_1 0xFFC0287C /* MXVR Frame Counter 1 */
+
+#define MXVR_ROUTING_0 0xFFC02880 /* MXVR Routing Table Register 0 */
+#define MXVR_ROUTING_1 0xFFC02884 /* MXVR Routing Table Register 1 */
+#define MXVR_ROUTING_2 0xFFC02888 /* MXVR Routing Table Register 2 */
+#define MXVR_ROUTING_3 0xFFC0288C /* MXVR Routing Table Register 3 */
+#define MXVR_ROUTING_4 0xFFC02890 /* MXVR Routing Table Register 4 */
+#define MXVR_ROUTING_5 0xFFC02894 /* MXVR Routing Table Register 5 */
+#define MXVR_ROUTING_6 0xFFC02898 /* MXVR Routing Table Register 6 */
+#define MXVR_ROUTING_7 0xFFC0289C /* MXVR Routing Table Register 7 */
+#define MXVR_ROUTING_8 0xFFC028A0 /* MXVR Routing Table Register 8 */
+#define MXVR_ROUTING_9 0xFFC028A4 /* MXVR Routing Table Register 9 */
+#define MXVR_ROUTING_10 0xFFC028A8 /* MXVR Routing Table Register 10 */
+#define MXVR_ROUTING_11 0xFFC028AC /* MXVR Routing Table Register 11 */
+#define MXVR_ROUTING_12 0xFFC028B0 /* MXVR Routing Table Register 12 */
+#define MXVR_ROUTING_13 0xFFC028B4 /* MXVR Routing Table Register 13 */
+#define MXVR_ROUTING_14 0xFFC028B8 /* MXVR Routing Table Register 14 */
+
+#define MXVR_PLL_CTL_1 0xFFC028BC /* MXVR Phase Lock Loop Control Register 1 */
+#define MXVR_BLOCK_CNT 0xFFC028C0 /* MXVR Block Counter */
+#define MXVR_PLL_CTL_2 0xFFC028C4 /* MXVR Phase Lock Loop Control Register 2 */
+
+
+/* CAN Controller (0xFFC02A00 - 0xFFC02FFF) */
+/* For Mailboxes 0-15 */
+#define CAN_MC1 0xFFC02A00 /* Mailbox config reg 1 */
+#define CAN_MD1 0xFFC02A04 /* Mailbox direction reg 1 */
+#define CAN_TRS1 0xFFC02A08 /* Transmit Request Set reg 1 */
+#define CAN_TRR1 0xFFC02A0C /* Transmit Request Reset reg 1 */
+#define CAN_TA1 0xFFC02A10 /* Transmit Acknowledge reg 1 */
+#define CAN_AA1 0xFFC02A14 /* Transmit Abort Acknowledge reg 1 */
+#define CAN_RMP1 0xFFC02A18 /* Receive Message Pending reg 1 */
+#define CAN_RML1 0xFFC02A1C /* Receive Message Lost reg 1 */
+#define CAN_MBTIF1 0xFFC02A20 /* Mailbox Transmit Interrupt Flag reg 1 */
+#define CAN_MBRIF1 0xFFC02A24 /* Mailbox Receive Interrupt Flag reg 1 */
+#define CAN_MBIM1 0xFFC02A28 /* Mailbox Interrupt Mask reg 1 */
+#define CAN_RFH1 0xFFC02A2C /* Remote Frame Handling reg 1 */
+#define CAN_OPSS1 0xFFC02A30 /* Overwrite Protection Single Shot Xmission reg 1 */
+
+/* For Mailboxes 16-31 */
+#define CAN_MC2 0xFFC02A40 /* Mailbox config reg 2 */
+#define CAN_MD2 0xFFC02A44 /* Mailbox direction reg 2 */
+#define CAN_TRS2 0xFFC02A48 /* Transmit Request Set reg 2 */
+#define CAN_TRR2 0xFFC02A4C /* Transmit Request Reset reg 2 */
+#define CAN_TA2 0xFFC02A50 /* Transmit Acknowledge reg 2 */
+#define CAN_AA2 0xFFC02A54 /* Transmit Abort Acknowledge reg 2 */
+#define CAN_RMP2 0xFFC02A58 /* Receive Message Pending reg 2 */
+#define CAN_RML2 0xFFC02A5C /* Receive Message Lost reg 2 */
+#define CAN_MBTIF2 0xFFC02A60 /* Mailbox Transmit Interrupt Flag reg 2 */
+#define CAN_MBRIF2 0xFFC02A64 /* Mailbox Receive Interrupt Flag reg 2 */
+#define CAN_MBIM2 0xFFC02A68 /* Mailbox Interrupt Mask reg 2 */
+#define CAN_RFH2 0xFFC02A6C /* Remote Frame Handling reg 2 */
+#define CAN_OPSS2 0xFFC02A70 /* Overwrite Protection Single Shot Xmission reg 2 */
+
+#define CAN_CLOCK 0xFFC02A80 /* Bit Timing Configuration register 0 */
+#define CAN_TIMING 0xFFC02A84 /* Bit Timing Configuration register 1 */
+
+#define CAN_DEBUG 0xFFC02A88 /* Debug Register */
+/* the following is for backwards compatibility */
+#define CAN_CNF CAN_DEBUG
+
+#define CAN_STATUS 0xFFC02A8C /* Global Status Register */
+#define CAN_CEC 0xFFC02A90 /* Error Counter Register */
+#define CAN_GIS 0xFFC02A94 /* Global Interrupt Status Register */
+#define CAN_GIM 0xFFC02A98 /* Global Interrupt Mask Register */
+#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
+#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
+#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
+#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
+#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
+#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
+#define CAN_UCREG 0xFFC02AC0 /* Universal Counter Register/Capture Register */
+#define CAN_UCCNT 0xFFC02AC4 /* Universal Counter */
+#define CAN_UCRC 0xFFC02AC8 /* Universal Counter Force Reload Register */
+#define CAN_UCCNF 0xFFC02ACC /* Universal Counter Configuration Register */
+
+/* Mailbox Acceptance Masks */
+#define CAN_AM00L 0xFFC02B00 /* Mailbox 0 Low Acceptance Mask */
+#define CAN_AM00H 0xFFC02B04 /* Mailbox 0 High Acceptance Mask */
+#define CAN_AM01L 0xFFC02B08 /* Mailbox 1 Low Acceptance Mask */
+#define CAN_AM01H 0xFFC02B0C /* Mailbox 1 High Acceptance Mask */
+#define CAN_AM02L 0xFFC02B10 /* Mailbox 2 Low Acceptance Mask */
+#define CAN_AM02H 0xFFC02B14 /* Mailbox 2 High Acceptance Mask */
+#define CAN_AM03L 0xFFC02B18 /* Mailbox 3 Low Acceptance Mask */
+#define CAN_AM03H 0xFFC02B1C /* Mailbox 3 High Acceptance Mask */
+#define CAN_AM04L 0xFFC02B20 /* Mailbox 4 Low Acceptance Mask */
+#define CAN_AM04H 0xFFC02B24 /* Mailbox 4 High Acceptance Mask */
+#define CAN_AM05L 0xFFC02B28 /* Mailbox 5 Low Acceptance Mask */
+#define CAN_AM05H 0xFFC02B2C /* Mailbox 5 High Acceptance Mask */
+#define CAN_AM06L 0xFFC02B30 /* Mailbox 6 Low Acceptance Mask */
+#define CAN_AM06H 0xFFC02B34 /* Mailbox 6 High Acceptance Mask */
+#define CAN_AM07L 0xFFC02B38 /* Mailbox 7 Low Acceptance Mask */
+#define CAN_AM07H 0xFFC02B3C /* Mailbox 7 High Acceptance Mask */
+#define CAN_AM08L 0xFFC02B40 /* Mailbox 8 Low Acceptance Mask */
+#define CAN_AM08H 0xFFC02B44 /* Mailbox 8 High Acceptance Mask */
+#define CAN_AM09L 0xFFC02B48 /* Mailbox 9 Low Acceptance Mask */
+#define CAN_AM09H 0xFFC02B4C /* Mailbox 9 High Acceptance Mask */
+#define CAN_AM10L 0xFFC02B50 /* Mailbox 10 Low Acceptance Mask */
+#define CAN_AM10H 0xFFC02B54 /* Mailbox 10 High Acceptance Mask */
+#define CAN_AM11L 0xFFC02B58 /* Mailbox 11 Low Acceptance Mask */
+#define CAN_AM11H 0xFFC02B5C /* Mailbox 11 High Acceptance Mask */
+#define CAN_AM12L 0xFFC02B60 /* Mailbox 12 Low Acceptance Mask */
+#define CAN_AM12H 0xFFC02B64 /* Mailbox 12 High Acceptance Mask */
+#define CAN_AM13L 0xFFC02B68 /* Mailbox 13 Low Acceptance Mask */
+#define CAN_AM13H 0xFFC02B6C /* Mailbox 13 High Acceptance Mask */
+#define CAN_AM14L 0xFFC02B70 /* Mailbox 14 Low Acceptance Mask */
+#define CAN_AM14H 0xFFC02B74 /* Mailbox 14 High Acceptance Mask */
+#define CAN_AM15L 0xFFC02B78 /* Mailbox 15 Low Acceptance Mask */
+#define CAN_AM15H 0xFFC02B7C /* Mailbox 15 High Acceptance Mask */
+
+#define CAN_AM16L 0xFFC02B80 /* Mailbox 16 Low Acceptance Mask */
+#define CAN_AM16H 0xFFC02B84 /* Mailbox 16 High Acceptance Mask */
+#define CAN_AM17L 0xFFC02B88 /* Mailbox 17 Low Acceptance Mask */
+#define CAN_AM17H 0xFFC02B8C /* Mailbox 17 High Acceptance Mask */
+#define CAN_AM18L 0xFFC02B90 /* Mailbox 18 Low Acceptance Mask */
+#define CAN_AM18H 0xFFC02B94 /* Mailbox 18 High Acceptance Mask */
+#define CAN_AM19L 0xFFC02B98 /* Mailbox 19 Low Acceptance Mask */
+#define CAN_AM19H 0xFFC02B9C /* Mailbox 19 High Acceptance Mask */
+#define CAN_AM20L 0xFFC02BA0 /* Mailbox 20 Low Acceptance Mask */
+#define CAN_AM20H 0xFFC02BA4 /* Mailbox 20 High Acceptance Mask */
+#define CAN_AM21L 0xFFC02BA8 /* Mailbox 21 Low Acceptance Mask */
+#define CAN_AM21H 0xFFC02BAC /* Mailbox 21 High Acceptance Mask */
+#define CAN_AM22L 0xFFC02BB0 /* Mailbox 22 Low Acceptance Mask */
+#define CAN_AM22H 0xFFC02BB4 /* Mailbox 22 High Acceptance Mask */
+#define CAN_AM23L 0xFFC02BB8 /* Mailbox 23 Low Acceptance Mask */
+#define CAN_AM23H 0xFFC02BBC /* Mailbox 23 High Acceptance Mask */
+#define CAN_AM24L 0xFFC02BC0 /* Mailbox 24 Low Acceptance Mask */
+#define CAN_AM24H 0xFFC02BC4 /* Mailbox 24 High Acceptance Mask */
+#define CAN_AM25L 0xFFC02BC8 /* Mailbox 25 Low Acceptance Mask */
+#define CAN_AM25H 0xFFC02BCC /* Mailbox 25 High Acceptance Mask */
+#define CAN_AM26L 0xFFC02BD0 /* Mailbox 26 Low Acceptance Mask */
+#define CAN_AM26H 0xFFC02BD4 /* Mailbox 26 High Acceptance Mask */
+#define CAN_AM27L 0xFFC02BD8 /* Mailbox 27 Low Acceptance Mask */
+#define CAN_AM27H 0xFFC02BDC /* Mailbox 27 High Acceptance Mask */
+#define CAN_AM28L 0xFFC02BE0 /* Mailbox 28 Low Acceptance Mask */
+#define CAN_AM28H 0xFFC02BE4 /* Mailbox 28 High Acceptance Mask */
+#define CAN_AM29L 0xFFC02BE8 /* Mailbox 29 Low Acceptance Mask */
+#define CAN_AM29H 0xFFC02BEC /* Mailbox 29 High Acceptance Mask */
+#define CAN_AM30L 0xFFC02BF0 /* Mailbox 30 Low Acceptance Mask */
+#define CAN_AM30H 0xFFC02BF4 /* Mailbox 30 High Acceptance Mask */
+#define CAN_AM31L 0xFFC02BF8 /* Mailbox 31 Low Acceptance Mask */
+#define CAN_AM31H 0xFFC02BFC /* Mailbox 31 High Acceptance Mask */
+
+/* CAN Acceptance Mask Macros */
+#define CAN_AM_L(x) (CAN_AM00L+((x)*0x8))
+#define CAN_AM_H(x) (CAN_AM00H+((x)*0x8))
+
+/* Mailbox Registers */
+#define CAN_MB00_DATA0 0xFFC02C00 /* Mailbox 0 Data Word 0 [15:0] Register */
+#define CAN_MB00_DATA1 0xFFC02C04 /* Mailbox 0 Data Word 1 [31:16] Register */
+#define CAN_MB00_DATA2 0xFFC02C08 /* Mailbox 0 Data Word 2 [47:32] Register */
+#define CAN_MB00_DATA3 0xFFC02C0C /* Mailbox 0 Data Word 3 [63:48] Register */
+#define CAN_MB00_LENGTH 0xFFC02C10 /* Mailbox 0 Data Length Code Register */
+#define CAN_MB00_TIMESTAMP 0xFFC02C14 /* Mailbox 0 Time Stamp Value Register */
+#define CAN_MB00_ID0 0xFFC02C18 /* Mailbox 0 Identifier Low Register */
+#define CAN_MB00_ID1 0xFFC02C1C /* Mailbox 0 Identifier High Register */
+
+#define CAN_MB01_DATA0 0xFFC02C20 /* Mailbox 1 Data Word 0 [15:0] Register */
+#define CAN_MB01_DATA1 0xFFC02C24 /* Mailbox 1 Data Word 1 [31:16] Register */
+#define CAN_MB01_DATA2 0xFFC02C28 /* Mailbox 1 Data Word 2 [47:32] Register */
+#define CAN_MB01_DATA3 0xFFC02C2C /* Mailbox 1 Data Word 3 [63:48] Register */
+#define CAN_MB01_LENGTH 0xFFC02C30 /* Mailbox 1 Data Length Code Register */
+#define CAN_MB01_TIMESTAMP 0xFFC02C34 /* Mailbox 1 Time Stamp Value Register */
+#define CAN_MB01_ID0 0xFFC02C38 /* Mailbox 1 Identifier Low Register */
+#define CAN_MB01_ID1 0xFFC02C3C /* Mailbox 1 Identifier High Register */
+
+#define CAN_MB02_DATA0 0xFFC02C40 /* Mailbox 2 Data Word 0 [15:0] Register */
+#define CAN_MB02_DATA1 0xFFC02C44 /* Mailbox 2 Data Word 1 [31:16] Register */
+#define CAN_MB02_DATA2 0xFFC02C48 /* Mailbox 2 Data Word 2 [47:32] Register */
+#define CAN_MB02_DATA3 0xFFC02C4C /* Mailbox 2 Data Word 3 [63:48] Register */
+#define CAN_MB02_LENGTH 0xFFC02C50 /* Mailbox 2 Data Length Code Register */
+#define CAN_MB02_TIMESTAMP 0xFFC02C54 /* Mailbox 2 Time Stamp Value Register */
+#define CAN_MB02_ID0 0xFFC02C58 /* Mailbox 2 Identifier Low Register */
+#define CAN_MB02_ID1 0xFFC02C5C /* Mailbox 2 Identifier High Register */
+
+#define CAN_MB03_DATA0 0xFFC02C60 /* Mailbox 3 Data Word 0 [15:0] Register */
+#define CAN_MB03_DATA1 0xFFC02C64 /* Mailbox 3 Data Word 1 [31:16] Register */
+#define CAN_MB03_DATA2 0xFFC02C68 /* Mailbox 3 Data Word 2 [47:32] Register */
+#define CAN_MB03_DATA3 0xFFC02C6C /* Mailbox 3 Data Word 3 [63:48] Register */
+#define CAN_MB03_LENGTH 0xFFC02C70 /* Mailbox 3 Data Length Code Register */
+#define CAN_MB03_TIMESTAMP 0xFFC02C74 /* Mailbox 3 Time Stamp Value Register */
+#define CAN_MB03_ID0 0xFFC02C78 /* Mailbox 3 Identifier Low Register */
+#define CAN_MB03_ID1 0xFFC02C7C /* Mailbox 3 Identifier High Register */
+
+#define CAN_MB04_DATA0 0xFFC02C80 /* Mailbox 4 Data Word 0 [15:0] Register */
+#define CAN_MB04_DATA1 0xFFC02C84 /* Mailbox 4 Data Word 1 [31:16] Register */
+#define CAN_MB04_DATA2 0xFFC02C88 /* Mailbox 4 Data Word 2 [47:32] Register */
+#define CAN_MB04_DATA3 0xFFC02C8C /* Mailbox 4 Data Word 3 [63:48] Register */
+#define CAN_MB04_LENGTH 0xFFC02C90 /* Mailbox 4 Data Length Code Register */
+#define CAN_MB04_TIMESTAMP 0xFFC02C94 /* Mailbox 4 Time Stamp Value Register */
+#define CAN_MB04_ID0 0xFFC02C98 /* Mailbox 4 Identifier Low Register */
+#define CAN_MB04_ID1 0xFFC02C9C /* Mailbox 4 Identifier High Register */
+
+#define CAN_MB05_DATA0 0xFFC02CA0 /* Mailbox 5 Data Word 0 [15:0] Register */
+#define CAN_MB05_DATA1 0xFFC02CA4 /* Mailbox 5 Data Word 1 [31:16] Register */
+#define CAN_MB05_DATA2 0xFFC02CA8 /* Mailbox 5 Data Word 2 [47:32] Register */
+#define CAN_MB05_DATA3 0xFFC02CAC /* Mailbox 5 Data Word 3 [63:48] Register */
+#define CAN_MB05_LENGTH 0xFFC02CB0 /* Mailbox 5 Data Length Code Register */
+#define CAN_MB05_TIMESTAMP 0xFFC02CB4 /* Mailbox 5 Time Stamp Value Register */
+#define CAN_MB05_ID0 0xFFC02CB8 /* Mailbox 5 Identifier Low Register */
+#define CAN_MB05_ID1 0xFFC02CBC /* Mailbox 5 Identifier High Register */
+
+#define CAN_MB06_DATA0 0xFFC02CC0 /* Mailbox 6 Data Word 0 [15:0] Register */
+#define CAN_MB06_DATA1 0xFFC02CC4 /* Mailbox 6 Data Word 1 [31:16] Register */
+#define CAN_MB06_DATA2 0xFFC02CC8 /* Mailbox 6 Data Word 2 [47:32] Register */
+#define CAN_MB06_DATA3 0xFFC02CCC /* Mailbox 6 Data Word 3 [63:48] Register */
+#define CAN_MB06_LENGTH 0xFFC02CD0 /* Mailbox 6 Data Length Code Register */
+#define CAN_MB06_TIMESTAMP 0xFFC02CD4 /* Mailbox 6 Time Stamp Value Register */
+#define CAN_MB06_ID0 0xFFC02CD8 /* Mailbox 6 Identifier Low Register */
+#define CAN_MB06_ID1 0xFFC02CDC /* Mailbox 6 Identifier High Register */
+
+#define CAN_MB07_DATA0 0xFFC02CE0 /* Mailbox 7 Data Word 0 [15:0] Register */
+#define CAN_MB07_DATA1 0xFFC02CE4 /* Mailbox 7 Data Word 1 [31:16] Register */
+#define CAN_MB07_DATA2 0xFFC02CE8 /* Mailbox 7 Data Word 2 [47:32] Register */
+#define CAN_MB07_DATA3 0xFFC02CEC /* Mailbox 7 Data Word 3 [63:48] Register */
+#define CAN_MB07_LENGTH 0xFFC02CF0 /* Mailbox 7 Data Length Code Register */
+#define CAN_MB07_TIMESTAMP 0xFFC02CF4 /* Mailbox 7 Time Stamp Value Register */
+#define CAN_MB07_ID0 0xFFC02CF8 /* Mailbox 7 Identifier Low Register */
+#define CAN_MB07_ID1 0xFFC02CFC /* Mailbox 7 Identifier High Register */
+
+#define CAN_MB08_DATA0 0xFFC02D00 /* Mailbox 8 Data Word 0 [15:0] Register */
+#define CAN_MB08_DATA1 0xFFC02D04 /* Mailbox 8 Data Word 1 [31:16] Register */
+#define CAN_MB08_DATA2 0xFFC02D08 /* Mailbox 8 Data Word 2 [47:32] Register */
+#define CAN_MB08_DATA3 0xFFC02D0C /* Mailbox 8 Data Word 3 [63:48] Register */
+#define CAN_MB08_LENGTH 0xFFC02D10 /* Mailbox 8 Data Length Code Register */
+#define CAN_MB08_TIMESTAMP 0xFFC02D14 /* Mailbox 8 Time Stamp Value Register */
+#define CAN_MB08_ID0 0xFFC02D18 /* Mailbox 8 Identifier Low Register */
+#define CAN_MB08_ID1 0xFFC02D1C /* Mailbox 8 Identifier High Register */
+
+#define CAN_MB09_DATA0 0xFFC02D20 /* Mailbox 9 Data Word 0 [15:0] Register */
+#define CAN_MB09_DATA1 0xFFC02D24 /* Mailbox 9 Data Word 1 [31:16] Register */
+#define CAN_MB09_DATA2 0xFFC02D28 /* Mailbox 9 Data Word 2 [47:32] Register */
+#define CAN_MB09_DATA3 0xFFC02D2C /* Mailbox 9 Data Word 3 [63:48] Register */
+#define CAN_MB09_LENGTH 0xFFC02D30 /* Mailbox 9 Data Length Code Register */
+#define CAN_MB09_TIMESTAMP 0xFFC02D34 /* Mailbox 9 Time Stamp Value Register */
+#define CAN_MB09_ID0 0xFFC02D38 /* Mailbox 9 Identifier Low Register */
+#define CAN_MB09_ID1 0xFFC02D3C /* Mailbox 9 Identifier High Register */
+
+#define CAN_MB10_DATA0 0xFFC02D40 /* Mailbox 10 Data Word 0 [15:0] Register */
+#define CAN_MB10_DATA1 0xFFC02D44 /* Mailbox 10 Data Word 1 [31:16] Register */
+#define CAN_MB10_DATA2 0xFFC02D48 /* Mailbox 10 Data Word 2 [47:32] Register */
+#define CAN_MB10_DATA3 0xFFC02D4C /* Mailbox 10 Data Word 3 [63:48] Register */
+#define CAN_MB10_LENGTH 0xFFC02D50 /* Mailbox 10 Data Length Code Register */
+#define CAN_MB10_TIMESTAMP 0xFFC02D54 /* Mailbox 10 Time Stamp Value Register */
+#define CAN_MB10_ID0 0xFFC02D58 /* Mailbox 10 Identifier Low Register */
+#define CAN_MB10_ID1 0xFFC02D5C /* Mailbox 10 Identifier High Register */
+
+#define CAN_MB11_DATA0 0xFFC02D60 /* Mailbox 11 Data Word 0 [15:0] Register */
+#define CAN_MB11_DATA1 0xFFC02D64 /* Mailbox 11 Data Word 1 [31:16] Register */
+#define CAN_MB11_DATA2 0xFFC02D68 /* Mailbox 11 Data Word 2 [47:32] Register */
+#define CAN_MB11_DATA3 0xFFC02D6C /* Mailbox 11 Data Word 3 [63:48] Register */
+#define CAN_MB11_LENGTH 0xFFC02D70 /* Mailbox 11 Data Length Code Register */
+#define CAN_MB11_TIMESTAMP 0xFFC02D74 /* Mailbox 11 Time Stamp Value Register */
+#define CAN_MB11_ID0 0xFFC02D78 /* Mailbox 11 Identifier Low Register */
+#define CAN_MB11_ID1 0xFFC02D7C /* Mailbox 11 Identifier High Register */
+
+#define CAN_MB12_DATA0 0xFFC02D80 /* Mailbox 12 Data Word 0 [15:0] Register */
+#define CAN_MB12_DATA1 0xFFC02D84 /* Mailbox 12 Data Word 1 [31:16] Register */
+#define CAN_MB12_DATA2 0xFFC02D88 /* Mailbox 12 Data Word 2 [47:32] Register */
+#define CAN_MB12_DATA3 0xFFC02D8C /* Mailbox 12 Data Word 3 [63:48] Register */
+#define CAN_MB12_LENGTH 0xFFC02D90 /* Mailbox 12 Data Length Code Register */
+#define CAN_MB12_TIMESTAMP 0xFFC02D94 /* Mailbox 12 Time Stamp Value Register */
+#define CAN_MB12_ID0 0xFFC02D98 /* Mailbox 12 Identifier Low Register */
+#define CAN_MB12_ID1 0xFFC02D9C /* Mailbox 12 Identifier High Register */
+
+#define CAN_MB13_DATA0 0xFFC02DA0 /* Mailbox 13 Data Word 0 [15:0] Register */
+#define CAN_MB13_DATA1 0xFFC02DA4 /* Mailbox 13 Data Word 1 [31:16] Register */
+#define CAN_MB13_DATA2 0xFFC02DA8 /* Mailbox 13 Data Word 2 [47:32] Register */
+#define CAN_MB13_DATA3 0xFFC02DAC /* Mailbox 13 Data Word 3 [63:48] Register */
+#define CAN_MB13_LENGTH 0xFFC02DB0 /* Mailbox 13 Data Length Code Register */
+#define CAN_MB13_TIMESTAMP 0xFFC02DB4 /* Mailbox 13 Time Stamp Value Register */
+#define CAN_MB13_ID0 0xFFC02DB8 /* Mailbox 13 Identifier Low Register */
+#define CAN_MB13_ID1 0xFFC02DBC /* Mailbox 13 Identifier High Register */
+
+#define CAN_MB14_DATA0 0xFFC02DC0 /* Mailbox 14 Data Word 0 [15:0] Register */
+#define CAN_MB14_DATA1 0xFFC02DC4 /* Mailbox 14 Data Word 1 [31:16] Register */
+#define CAN_MB14_DATA2 0xFFC02DC8 /* Mailbox 14 Data Word 2 [47:32] Register */
+#define CAN_MB14_DATA3 0xFFC02DCC /* Mailbox 14 Data Word 3 [63:48] Register */
+#define CAN_MB14_LENGTH 0xFFC02DD0 /* Mailbox 14 Data Length Code Register */
+#define CAN_MB14_TIMESTAMP 0xFFC02DD4 /* Mailbox 14 Time Stamp Value Register */
+#define CAN_MB14_ID0 0xFFC02DD8 /* Mailbox 14 Identifier Low Register */
+#define CAN_MB14_ID1 0xFFC02DDC /* Mailbox 14 Identifier High Register */
+
+#define CAN_MB15_DATA0 0xFFC02DE0 /* Mailbox 15 Data Word 0 [15:0] Register */
+#define CAN_MB15_DATA1 0xFFC02DE4 /* Mailbox 15 Data Word 1 [31:16] Register */
+#define CAN_MB15_DATA2 0xFFC02DE8 /* Mailbox 15 Data Word 2 [47:32] Register */
+#define CAN_MB15_DATA3 0xFFC02DEC /* Mailbox 15 Data Word 3 [63:48] Register */
+#define CAN_MB15_LENGTH 0xFFC02DF0 /* Mailbox 15 Data Length Code Register */
+#define CAN_MB15_TIMESTAMP 0xFFC02DF4 /* Mailbox 15 Time Stamp Value Register */
+#define CAN_MB15_ID0 0xFFC02DF8 /* Mailbox 15 Identifier Low Register */
+#define CAN_MB15_ID1 0xFFC02DFC /* Mailbox 15 Identifier High Register */
+
+#define CAN_MB16_DATA0 0xFFC02E00 /* Mailbox 16 Data Word 0 [15:0] Register */
+#define CAN_MB16_DATA1 0xFFC02E04 /* Mailbox 16 Data Word 1 [31:16] Register */
+#define CAN_MB16_DATA2 0xFFC02E08 /* Mailbox 16 Data Word 2 [47:32] Register */
+#define CAN_MB16_DATA3 0xFFC02E0C /* Mailbox 16 Data Word 3 [63:48] Register */
+#define CAN_MB16_LENGTH 0xFFC02E10 /* Mailbox 16 Data Length Code Register */
+#define CAN_MB16_TIMESTAMP 0xFFC02E14 /* Mailbox 16 Time Stamp Value Register */
+#define CAN_MB16_ID0 0xFFC02E18 /* Mailbox 16 Identifier Low Register */
+#define CAN_MB16_ID1 0xFFC02E1C /* Mailbox 16 Identifier High Register */
+
+#define CAN_MB17_DATA0 0xFFC02E20 /* Mailbox 17 Data Word 0 [15:0] Register */
+#define CAN_MB17_DATA1 0xFFC02E24 /* Mailbox 17 Data Word 1 [31:16] Register */
+#define CAN_MB17_DATA2 0xFFC02E28 /* Mailbox 17 Data Word 2 [47:32] Register */
+#define CAN_MB17_DATA3 0xFFC02E2C /* Mailbox 17 Data Word 3 [63:48] Register */
+#define CAN_MB17_LENGTH 0xFFC02E30 /* Mailbox 17 Data Length Code Register */
+#define CAN_MB17_TIMESTAMP 0xFFC02E34 /* Mailbox 17 Time Stamp Value Register */
+#define CAN_MB17_ID0 0xFFC02E38 /* Mailbox 17 Identifier Low Register */
+#define CAN_MB17_ID1 0xFFC02E3C /* Mailbox 17 Identifier High Register */
+
+#define CAN_MB18_DATA0 0xFFC02E40 /* Mailbox 18 Data Word 0 [15:0] Register */
+#define CAN_MB18_DATA1 0xFFC02E44 /* Mailbox 18 Data Word 1 [31:16] Register */
+#define CAN_MB18_DATA2 0xFFC02E48 /* Mailbox 18 Data Word 2 [47:32] Register */
+#define CAN_MB18_DATA3 0xFFC02E4C /* Mailbox 18 Data Word 3 [63:48] Register */
+#define CAN_MB18_LENGTH 0xFFC02E50 /* Mailbox 18 Data Length Code Register */
+#define CAN_MB18_TIMESTAMP 0xFFC02E54 /* Mailbox 18 Time Stamp Value Register */
+#define CAN_MB18_ID0 0xFFC02E58 /* Mailbox 18 Identifier Low Register */
+#define CAN_MB18_ID1 0xFFC02E5C /* Mailbox 18 Identifier High Register */
+
+#define CAN_MB19_DATA0 0xFFC02E60 /* Mailbox 19 Data Word 0 [15:0] Register */
+#define CAN_MB19_DATA1 0xFFC02E64 /* Mailbox 19 Data Word 1 [31:16] Register */
+#define CAN_MB19_DATA2 0xFFC02E68 /* Mailbox 19 Data Word 2 [47:32] Register */
+#define CAN_MB19_DATA3 0xFFC02E6C /* Mailbox 19 Data Word 3 [63:48] Register */
+#define CAN_MB19_LENGTH 0xFFC02E70 /* Mailbox 19 Data Length Code Register */
+#define CAN_MB19_TIMESTAMP 0xFFC02E74 /* Mailbox 19 Time Stamp Value Register */
+#define CAN_MB19_ID0 0xFFC02E78 /* Mailbox 19 Identifier Low Register */
+#define CAN_MB19_ID1 0xFFC02E7C /* Mailbox 19 Identifier High Register */
+
+#define CAN_MB20_DATA0 0xFFC02E80 /* Mailbox 20 Data Word 0 [15:0] Register */
+#define CAN_MB20_DATA1 0xFFC02E84 /* Mailbox 20 Data Word 1 [31:16] Register */
+#define CAN_MB20_DATA2 0xFFC02E88 /* Mailbox 20 Data Word 2 [47:32] Register */
+#define CAN_MB20_DATA3 0xFFC02E8C /* Mailbox 20 Data Word 3 [63:48] Register */
+#define CAN_MB20_LENGTH 0xFFC02E90 /* Mailbox 20 Data Length Code Register */
+#define CAN_MB20_TIMESTAMP 0xFFC02E94 /* Mailbox 20 Time Stamp Value Register */
+#define CAN_MB20_ID0 0xFFC02E98 /* Mailbox 20 Identifier Low Register */
+#define CAN_MB20_ID1 0xFFC02E9C /* Mailbox 20 Identifier High Register */
+
+#define CAN_MB21_DATA0 0xFFC02EA0 /* Mailbox 21 Data Word 0 [15:0] Register */
+#define CAN_MB21_DATA1 0xFFC02EA4 /* Mailbox 21 Data Word 1 [31:16] Register */
+#define CAN_MB21_DATA2 0xFFC02EA8 /* Mailbox 21 Data Word 2 [47:32] Register */
+#define CAN_MB21_DATA3 0xFFC02EAC /* Mailbox 21 Data Word 3 [63:48] Register */
+#define CAN_MB21_LENGTH 0xFFC02EB0 /* Mailbox 21 Data Length Code Register */
+#define CAN_MB21_TIMESTAMP 0xFFC02EB4 /* Mailbox 21 Time Stamp Value Register */
+#define CAN_MB21_ID0 0xFFC02EB8 /* Mailbox 21 Identifier Low Register */
+#define CAN_MB21_ID1 0xFFC02EBC /* Mailbox 21 Identifier High Register */
+
+#define CAN_MB22_DATA0 0xFFC02EC0 /* Mailbox 22 Data Word 0 [15:0] Register */
+#define CAN_MB22_DATA1 0xFFC02EC4 /* Mailbox 22 Data Word 1 [31:16] Register */
+#define CAN_MB22_DATA2 0xFFC02EC8 /* Mailbox 22 Data Word 2 [47:32] Register */
+#define CAN_MB22_DATA3 0xFFC02ECC /* Mailbox 22 Data Word 3 [63:48] Register */
+#define CAN_MB22_LENGTH 0xFFC02ED0 /* Mailbox 22 Data Length Code Register */
+#define CAN_MB22_TIMESTAMP 0xFFC02ED4 /* Mailbox 22 Time Stamp Value Register */
+#define CAN_MB22_ID0 0xFFC02ED8 /* Mailbox 22 Identifier Low Register */
+#define CAN_MB22_ID1 0xFFC02EDC /* Mailbox 22 Identifier High Register */
+
+#define CAN_MB23_DATA0 0xFFC02EE0 /* Mailbox 23 Data Word 0 [15:0] Register */
+#define CAN_MB23_DATA1 0xFFC02EE4 /* Mailbox 23 Data Word 1 [31:16] Register */
+#define CAN_MB23_DATA2 0xFFC02EE8 /* Mailbox 23 Data Word 2 [47:32] Register */
+#define CAN_MB23_DATA3 0xFFC02EEC /* Mailbox 23 Data Word 3 [63:48] Register */
+#define CAN_MB23_LENGTH 0xFFC02EF0 /* Mailbox 23 Data Length Code Register */
+#define CAN_MB23_TIMESTAMP 0xFFC02EF4 /* Mailbox 23 Time Stamp Value Register */
+#define CAN_MB23_ID0 0xFFC02EF8 /* Mailbox 23 Identifier Low Register */
+#define CAN_MB23_ID1 0xFFC02EFC /* Mailbox 23 Identifier High Register */
+
+#define CAN_MB24_DATA0 0xFFC02F00 /* Mailbox 24 Data Word 0 [15:0] Register */
+#define CAN_MB24_DATA1 0xFFC02F04 /* Mailbox 24 Data Word 1 [31:16] Register */
+#define CAN_MB24_DATA2 0xFFC02F08 /* Mailbox 24 Data Word 2 [47:32] Register */
+#define CAN_MB24_DATA3 0xFFC02F0C /* Mailbox 24 Data Word 3 [63:48] Register */
+#define CAN_MB24_LENGTH 0xFFC02F10 /* Mailbox 24 Data Length Code Register */
+#define CAN_MB24_TIMESTAMP 0xFFC02F14 /* Mailbox 24 Time Stamp Value Register */
+#define CAN_MB24_ID0 0xFFC02F18 /* Mailbox 24 Identifier Low Register */
+#define CAN_MB24_ID1 0xFFC02F1C /* Mailbox 24 Identifier High Register */
+
+#define CAN_MB25_DATA0 0xFFC02F20 /* Mailbox 25 Data Word 0 [15:0] Register */
+#define CAN_MB25_DATA1 0xFFC02F24 /* Mailbox 25 Data Word 1 [31:16] Register */
+#define CAN_MB25_DATA2 0xFFC02F28 /* Mailbox 25 Data Word 2 [47:32] Register */
+#define CAN_MB25_DATA3 0xFFC02F2C /* Mailbox 25 Data Word 3 [63:48] Register */
+#define CAN_MB25_LENGTH 0xFFC02F30 /* Mailbox 25 Data Length Code Register */
+#define CAN_MB25_TIMESTAMP 0xFFC02F34 /* Mailbox 25 Time Stamp Value Register */
+#define CAN_MB25_ID0 0xFFC02F38 /* Mailbox 25 Identifier Low Register */
+#define CAN_MB25_ID1 0xFFC02F3C /* Mailbox 25 Identifier High Register */
+
+#define CAN_MB26_DATA0 0xFFC02F40 /* Mailbox 26 Data Word 0 [15:0] Register */
+#define CAN_MB26_DATA1 0xFFC02F44 /* Mailbox 26 Data Word 1 [31:16] Register */
+#define CAN_MB26_DATA2 0xFFC02F48 /* Mailbox 26 Data Word 2 [47:32] Register */
+#define CAN_MB26_DATA3 0xFFC02F4C /* Mailbox 26 Data Word 3 [63:48] Register */
+#define CAN_MB26_LENGTH 0xFFC02F50 /* Mailbox 26 Data Length Code Register */
+#define CAN_MB26_TIMESTAMP 0xFFC02F54 /* Mailbox 26 Time Stamp Value Register */
+#define CAN_MB26_ID0 0xFFC02F58 /* Mailbox 26 Identifier Low Register */
+#define CAN_MB26_ID1 0xFFC02F5C /* Mailbox 26 Identifier High Register */
+
+#define CAN_MB27_DATA0 0xFFC02F60 /* Mailbox 27 Data Word 0 [15:0] Register */
+#define CAN_MB27_DATA1 0xFFC02F64 /* Mailbox 27 Data Word 1 [31:16] Register */
+#define CAN_MB27_DATA2 0xFFC02F68 /* Mailbox 27 Data Word 2 [47:32] Register */
+#define CAN_MB27_DATA3 0xFFC02F6C /* Mailbox 27 Data Word 3 [63:48] Register */
+#define CAN_MB27_LENGTH 0xFFC02F70 /* Mailbox 27 Data Length Code Register */
+#define CAN_MB27_TIMESTAMP 0xFFC02F74 /* Mailbox 27 Time Stamp Value Register */
+#define CAN_MB27_ID0 0xFFC02F78 /* Mailbox 27 Identifier Low Register */
+#define CAN_MB27_ID1 0xFFC02F7C /* Mailbox 27 Identifier High Register */
+
+#define CAN_MB28_DATA0 0xFFC02F80 /* Mailbox 28 Data Word 0 [15:0] Register */
+#define CAN_MB28_DATA1 0xFFC02F84 /* Mailbox 28 Data Word 1 [31:16] Register */
+#define CAN_MB28_DATA2 0xFFC02F88 /* Mailbox 28 Data Word 2 [47:32] Register */
+#define CAN_MB28_DATA3 0xFFC02F8C /* Mailbox 28 Data Word 3 [63:48] Register */
+#define CAN_MB28_LENGTH 0xFFC02F90 /* Mailbox 28 Data Length Code Register */
+#define CAN_MB28_TIMESTAMP 0xFFC02F94 /* Mailbox 28 Time Stamp Value Register */
+#define CAN_MB28_ID0 0xFFC02F98 /* Mailbox 28 Identifier Low Register */
+#define CAN_MB28_ID1 0xFFC02F9C /* Mailbox 28 Identifier High Register */
+
+#define CAN_MB29_DATA0 0xFFC02FA0 /* Mailbox 29 Data Word 0 [15:0] Register */
+#define CAN_MB29_DATA1 0xFFC02FA4 /* Mailbox 29 Data Word 1 [31:16] Register */
+#define CAN_MB29_DATA2 0xFFC02FA8 /* Mailbox 29 Data Word 2 [47:32] Register */
+#define CAN_MB29_DATA3 0xFFC02FAC /* Mailbox 29 Data Word 3 [63:48] Register */
+#define CAN_MB29_LENGTH 0xFFC02FB0 /* Mailbox 29 Data Length Code Register */
+#define CAN_MB29_TIMESTAMP 0xFFC02FB4 /* Mailbox 29 Time Stamp Value Register */
+#define CAN_MB29_ID0 0xFFC02FB8 /* Mailbox 29 Identifier Low Register */
+#define CAN_MB29_ID1 0xFFC02FBC /* Mailbox 29 Identifier High Register */
+
+#define CAN_MB30_DATA0 0xFFC02FC0 /* Mailbox 30 Data Word 0 [15:0] Register */
+#define CAN_MB30_DATA1 0xFFC02FC4 /* Mailbox 30 Data Word 1 [31:16] Register */
+#define CAN_MB30_DATA2 0xFFC02FC8 /* Mailbox 30 Data Word 2 [47:32] Register */
+#define CAN_MB30_DATA3 0xFFC02FCC /* Mailbox 30 Data Word 3 [63:48] Register */
+#define CAN_MB30_LENGTH 0xFFC02FD0 /* Mailbox 30 Data Length Code Register */
+#define CAN_MB30_TIMESTAMP 0xFFC02FD4 /* Mailbox 30 Time Stamp Value Register */
+#define CAN_MB30_ID0 0xFFC02FD8 /* Mailbox 30 Identifier Low Register */
+#define CAN_MB30_ID1 0xFFC02FDC /* Mailbox 30 Identifier High Register */
+
+#define CAN_MB31_DATA0 0xFFC02FE0 /* Mailbox 31 Data Word 0 [15:0] Register */
+#define CAN_MB31_DATA1 0xFFC02FE4 /* Mailbox 31 Data Word 1 [31:16] Register */
+#define CAN_MB31_DATA2 0xFFC02FE8 /* Mailbox 31 Data Word 2 [47:32] Register */
+#define CAN_MB31_DATA3 0xFFC02FEC /* Mailbox 31 Data Word 3 [63:48] Register */
+#define CAN_MB31_LENGTH 0xFFC02FF0 /* Mailbox 31 Data Length Code Register */
+#define CAN_MB31_TIMESTAMP 0xFFC02FF4 /* Mailbox 31 Time Stamp Value Register */
+#define CAN_MB31_ID0 0xFFC02FF8 /* Mailbox 31 Identifier Low Register */
+#define CAN_MB31_ID1 0xFFC02FFC /* Mailbox 31 Identifier High Register */
+
+/* CAN Mailbox Area Macros */
+#define CAN_MB_ID1(x) (CAN_MB00_ID1+((x)*0x20))
+#define CAN_MB_ID0(x) (CAN_MB00_ID0+((x)*0x20))
+#define CAN_MB_TIMESTAMP(x) (CAN_MB00_TIMESTAMP+((x)*0x20))
+#define CAN_MB_LENGTH(x) (CAN_MB00_LENGTH+((x)*0x20))
+#define CAN_MB_DATA3(x) (CAN_MB00_DATA3+((x)*0x20))
+#define CAN_MB_DATA2(x) (CAN_MB00_DATA2+((x)*0x20))
+#define CAN_MB_DATA1(x) (CAN_MB00_DATA1+((x)*0x20))
+#define CAN_MB_DATA0(x) (CAN_MB00_DATA0+((x)*0x20))
+
+
+/*********************************************************************************** */
+/* System MMR Register Bits and Macros */
+/******************************************************************************* */
+
+/* ********************* PLL AND RESET MASKS ************************ */
+/* PLL_CTL Masks */
+#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
+#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
+#define PLL_OFF 0x0002 /* Shut off PLL clocks */
+#define STOPCK_OFF 0x0008 /* Core clock off */
+#define STOPCK 0x0008 /* Core Clock Off */
+#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
+#define IN_DELAY 0x0014 /* EBIU Input Delay Select */
+#define OUT_DELAY 0x00C0 /* EBIU Output Delay Select */
+#define BYPASS 0x0100 /* Bypass the PLL */
+#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
+
+/* PLL_CTL Macros */
+#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+
+#define SET_OUT_DELAY(x) (((x)&0x03) << 0x6)
+#define SET_IN_DELAY(x) ((((x)&0x02) << 0x3) | (((x)&0x01) << 0x2))
+
+/* PLL_DIV Masks */
+#define SSEL 0x000F /* System Select */
+#define CSEL 0x0030 /* Core Select */
+#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
+#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
+#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
+#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
+
+#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
+
+#define CCLK_DIV1 0x0000 /* CCLK = VCO / 1 */
+#define CCLK_DIV2 0x0010 /* CCLK = VCO / 2 */
+#define CCLK_DIV4 0x0020 /* CCLK = VCO / 4 */
+#define CCLK_DIV8 0x0030 /* CCLK = VCO / 8 */
+
+/* PLL_DIV Macros */
+#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+
+/* PLL_STAT Masks */
+#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
+#define FULL_ON 0x0002 /* Processor In Full On Mode */
+#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
+#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
+
+/* VR_CTL Masks */
+#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
+#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
+#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
+
+#define GAIN 0x000C /* Voltage Level Gain */
+#define GAIN_5 0x0000 /* GAIN = 5 */
+#define GAIN_10 0x0004 /* GAIN = 10 */
+#define GAIN_20 0x0008 /* GAIN = 20 */
+#define GAIN_50 0x000C /* GAIN = 50 */
+
+#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
+#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
+
+#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
+#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
+#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
+#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
+
+/* SWRST Mask */
+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks */
+#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
+#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+
+
+/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
+
+/* Peripheral Masks For SIC0_ISR, SIC0_IWR, SIC0_IMASK */
+#define PLL_WAKEUP_IRQ 0x00000001 /* PLL Wakeup Interrupt Request */
+#define DMAC0_ERR_IRQ 0x00000002 /* DMA Controller 0 Error Interrupt Request */
+#define PPI_ERR_IRQ 0x00000004 /* PPI Error Interrupt Request */
+#define SPORT0_ERR_IRQ 0x00000008 /* SPORT0 Error Interrupt Request */
+#define SPORT1_ERR_IRQ 0x00000010 /* SPORT1 Error Interrupt Request */
+#define SPI0_ERR_IRQ 0x00000020 /* SPI0 Error Interrupt Request */
+#define UART0_ERR_IRQ 0x00000040 /* UART0 Error Interrupt Request */
+#define RTC_IRQ 0x00000080 /* Real-Time Clock Interrupt Request */
+#define DMA0_IRQ 0x00000100 /* DMA Channel 0 (PPI) Interrupt Request */
+#define DMA1_IRQ 0x00000200 /* DMA Channel 1 (SPORT0 RX) Interrupt Request */
+#define DMA2_IRQ 0x00000400 /* DMA Channel 2 (SPORT0 TX) Interrupt Request */
+#define DMA3_IRQ 0x00000800 /* DMA Channel 3 (SPORT1 RX) Interrupt Request */
+#define DMA4_IRQ 0x00001000 /* DMA Channel 4 (SPORT1 TX) Interrupt Request */
+#define DMA5_IRQ 0x00002000 /* DMA Channel 5 (SPI) Interrupt Request */
+#define DMA6_IRQ 0x00004000 /* DMA Channel 6 (UART RX) Interrupt Request */
+#define DMA7_IRQ 0x00008000 /* DMA Channel 7 (UART TX) Interrupt Request */
+#define TIMER0_IRQ 0x00010000 /* Timer 0 Interrupt Request */
+#define TIMER1_IRQ 0x00020000 /* Timer 1 Interrupt Request */
+#define TIMER2_IRQ 0x00040000 /* Timer 2 Interrupt Request */
+#define PFA_IRQ 0x00080000 /* Programmable Flag Interrupt Request A */
+#define PFB_IRQ 0x00100000 /* Programmable Flag Interrupt Request B */
+#define MDMA0_0_IRQ 0x00200000 /* MemDMA0 Stream 0 Interrupt Request */
+#define MDMA0_1_IRQ 0x00400000 /* MemDMA0 Stream 1 Interrupt Request */
+#define WDOG_IRQ 0x00800000 /* Software Watchdog Timer Interrupt Request */
+#define DMAC1_ERR_IRQ 0x01000000 /* DMA Controller 1 Error Interrupt Request */
+#define SPORT2_ERR_IRQ 0x02000000 /* SPORT2 Error Interrupt Request */
+#define SPORT3_ERR_IRQ 0x04000000 /* SPORT3 Error Interrupt Request */
+#define MXVR_SD_IRQ 0x08000000 /* MXVR Synchronous Data Interrupt Request */
+#define SPI1_ERR_IRQ 0x10000000 /* SPI1 Error Interrupt Request */
+#define SPI2_ERR_IRQ 0x20000000 /* SPI2 Error Interrupt Request */
+#define UART1_ERR_IRQ 0x40000000 /* UART1 Error Interrupt Request */
+#define UART2_ERR_IRQ 0x80000000 /* UART2 Error Interrupt Request */
+
+/* the following are for backwards compatibility */
+#define DMA0_ERR_IRQ DMAC0_ERR_IRQ
+#define DMA1_ERR_IRQ DMAC1_ERR_IRQ
+
+
+/* Peripheral Masks For SIC_ISR1, SIC_IWR1, SIC_IMASK1 */
+#define CAN_ERR_IRQ 0x00000001 /* CAN Error Interrupt Request */
+#define DMA8_IRQ 0x00000002 /* DMA Channel 8 (SPORT2 RX) Interrupt Request */
+#define DMA9_IRQ 0x00000004 /* DMA Channel 9 (SPORT2 TX) Interrupt Request */
+#define DMA10_IRQ 0x00000008 /* DMA Channel 10 (SPORT3 RX) Interrupt Request */
+#define DMA11_IRQ 0x00000010 /* DMA Channel 11 (SPORT3 TX) Interrupt Request */
+#define DMA12_IRQ 0x00000020 /* DMA Channel 12 Interrupt Request */
+#define DMA13_IRQ 0x00000040 /* DMA Channel 13 Interrupt Request */
+#define DMA14_IRQ 0x00000080 /* DMA Channel 14 (SPI1) Interrupt Request */
+#define DMA15_IRQ 0x00000100 /* DMA Channel 15 (SPI2) Interrupt Request */
+#define DMA16_IRQ 0x00000200 /* DMA Channel 16 (UART1 RX) Interrupt Request */
+#define DMA17_IRQ 0x00000400 /* DMA Channel 17 (UART1 TX) Interrupt Request */
+#define DMA18_IRQ 0x00000800 /* DMA Channel 18 (UART2 RX) Interrupt Request */
+#define DMA19_IRQ 0x00001000 /* DMA Channel 19 (UART2 TX) Interrupt Request */
+#define TWI0_IRQ 0x00002000 /* TWI0 Interrupt Request */
+#define TWI1_IRQ 0x00004000 /* TWI1 Interrupt Request */
+#define CAN_RX_IRQ 0x00008000 /* CAN Receive Interrupt Request */
+#define CAN_TX_IRQ 0x00010000 /* CAN Transmit Interrupt Request */
+#define MDMA1_0_IRQ 0x00020000 /* MemDMA1 Stream 0 Interrupt Request */
+#define MDMA1_1_IRQ 0x00040000 /* MemDMA1 Stream 1 Interrupt Request */
+#define MXVR_STAT_IRQ 0x00080000 /* MXVR Status Interrupt Request */
+#define MXVR_CM_IRQ 0x00100000 /* MXVR Control Message Interrupt Request */
+#define MXVR_AP_IRQ 0x00200000 /* MXVR Asynchronous Packet Interrupt */
+
+/* the following are for backwards compatibility */
+#define MDMA0_IRQ MDMA1_0_IRQ
+#define MDMA1_IRQ MDMA1_1_IRQ
+
+/* SIC_IAR0 Macros */
+#define P0_IVG(x) (((x)-7)&0xF) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Macros */
+#define P8_IVG(x) (((x)-7)&0xF) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #15 assigned IVG #x */
+
+/* SIC_IAR2 Macros */
+#define P16_IVG(x) (((x)-7)&0xF) /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #23 assigned IVG #x */
+
+/* SIC_IAR3 Macros */
+#define P24_IVG(x) (((x)-7)&0xF) /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #29 assigned IVG #x */
+#define P30_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #31 assigned IVG #x */
+
+/* SIC_IAR4 Macros */
+#define P32_IVG(x) (((x)-7)&0xF) /* Peripheral #32 assigned IVG #x */
+#define P33_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #33 assigned IVG #x */
+#define P34_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #34 assigned IVG #x */
+#define P35_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #35 assigned IVG #x */
+#define P36_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #36 assigned IVG #x */
+#define P37_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #37 assigned IVG #x */
+#define P38_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #38 assigned IVG #x */
+#define P39_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #39 assigned IVG #x */
+
+/* SIC_IAR5 Macros */
+#define P40_IVG(x) (((x)-7)&0xF) /* Peripheral #40 assigned IVG #x */
+#define P41_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #41 assigned IVG #x */
+#define P42_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #42 assigned IVG #x */
+#define P43_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #43 assigned IVG #x */
+#define P44_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #44 assigned IVG #x */
+#define P45_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #45 assigned IVG #x */
+#define P46_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #46 assigned IVG #x */
+#define P47_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #47 assigned IVG #x */
+
+/* SIC_IAR6 Macros */
+#define P48_IVG(x) (((x)-7)&0xF) /* Peripheral #48 assigned IVG #x */
+#define P49_IVG(x) (((x)-7)&0xF) << 0x4 /* Peripheral #49 assigned IVG #x */
+#define P50_IVG(x) (((x)-7)&0xF) << 0x8 /* Peripheral #50 assigned IVG #x */
+#define P51_IVG(x) (((x)-7)&0xF) << 0xC /* Peripheral #51 assigned IVG #x */
+#define P52_IVG(x) (((x)-7)&0xF) << 0x10 /* Peripheral #52 assigned IVG #x */
+#define P53_IVG(x) (((x)-7)&0xF) << 0x14 /* Peripheral #53 assigned IVG #x */
+#define P54_IVG(x) (((x)-7)&0xF) << 0x18 /* Peripheral #54 assigned IVG #x */
+#define P55_IVG(x) (((x)-7)&0xF) << 0x1C /* Peripheral #55 assigned IVG #x */
+
+/* SIC_IARx Macros */
+
+#define PX_IVG_CLR(x) (0xFFFFFFFF ^ (0xF << (((x)%8)*4))) /* Clear IVG Select for Peripheral #x */
+/* Usage: *pSIC_IAR1 &= PX_IVG_CLR(11); // Clears IVG Level of Peripheral #11 */
+
+#define PX_IVG(x,y) ((((y)-7)&0xF) << (((x)%8)*4)) /* Set IVG Select to #y for Peripheral #x */
+/* Usage: *pSIC_IAR1 |= PX_IVG(11, 8); // Sets Peripheral #11 to IVG8 */
+
+/* SIC_IMASKx Masks */
+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWRx Masks */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
+
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+/* Watchdog Timer WDOG_CTL Register Masks */
+#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#define WDEV_RESET 0x0000 /* generate reset event on roll over */
+#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
+#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
+#define WDEV_NONE 0x0006 /* no event on roll over */
+#define WDEN 0x0FF0 /* enable watchdog */
+#define WDDIS 0x0AD0 /* disable watchdog */
+#define WDRO 0x8000 /* watchdog rolled over latch */
+
+/* deprecated WDOG_CTL Register Masks for legacy code */
+#define ICTL WDEV
+#define ENABLE_RESET WDEV_RESET
+#define WDOG_RESET WDEV_RESET
+#define ENABLE_NMI WDEV_NMI
+#define WDOG_NMI WDEV_NMI
+#define ENABLE_GPI WDEV_GPI
+#define WDOG_GPI WDEV_GPI
+#define DISABLE_EVT WDEV_NONE
+#define WDOG_NONE WDEV_NONE
+
+#define TMR_EN WDEN
+#define WDOG_DISABLE WDDIS
+#define TRO WDRO
+
+#define ICTL_P0 0x01
+#define ICTL_P1 0x02
+#define TRO_P 0x0F
+
+
+/* *************** REAL TIME CLOCK MASKS **************************/
+/* RTC_STAT and RTC_ALARM register */
+#define RTSEC 0x0000003F /* Real-Time Clock Seconds */
+#define RTMIN 0x00000FC0 /* Real-Time Clock Minutes */
+#define RTHR 0x0001F000 /* Real-Time Clock Hours */
+#define RTDAY 0xFFFE0000 /* Real-Time Clock Days */
+
+/* RTC_ICTL register */
+#define SWIE 0x0001 /* Stopwatch Interrupt Enable */
+#define AIE 0x0002 /* Alarm Interrupt Enable */
+#define SIE 0x0004 /* Seconds (1 Hz) Interrupt Enable */
+#define MIE 0x0008 /* Minutes Interrupt Enable */
+#define HIE 0x0010 /* Hours Interrupt Enable */
+#define DIE 0x0020 /* 24 Hours (Days) Interrupt Enable */
+#define DAIE 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WCIE 0x8000 /* Write Complete Interrupt Enable */
+
+/* RTC_ISTAT register */
+#define SWEF 0x0001 /* Stopwatch Event Flag */
+#define AEF 0x0002 /* Alarm Event Flag */
+#define SEF 0x0004 /* Seconds (1 Hz) Event Flag */
+#define MEF 0x0008 /* Minutes Event Flag */
+#define HEF 0x0010 /* Hours Event Flag */
+#define DEF 0x0020 /* 24 Hours (Days) Event Flag */
+#define DAEF 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Event Flag */
+#define WPS 0x4000 /* Write Pending Status (RO) */
+#define WCOM 0x8000 /* Write Complete */
+
+/* RTC_FAST Mask (RTC_PREN Mask) */
+#define ENABLE_PRESCALE 0x00000001 /* Enable prescaler so RTC runs at 1 Hz */
+#define PREN 0x00000001
+ /* ** Must be set after power-up for proper operation of RTC */
+
+/* RTC_ALARM Macro z=day y=hr x=min w=sec */
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+
+/* Deprecated RTC_STAT and RTC_ALARM Masks */
+#define RTC_SEC RTSEC /* Real-Time Clock Seconds */
+#define RTC_MIN RTMIN /* Real-Time Clock Minutes */
+#define RTC_HR RTHR /* Real-Time Clock Hours */
+#define RTC_DAY RTDAY /* Real-Time Clock Days */
+
+/* Deprecated RTC_ICTL/RTC_ISTAT Masks */
+#define STOPWATCH SWIE /* Stopwatch Interrupt Enable */
+#define ALARM AIE /* Alarm Interrupt Enable */
+#define SECOND SIE /* Seconds (1 Hz) Interrupt Enable */
+#define MINUTE MIE /* Minutes Interrupt Enable */
+#define HOUR HIE /* Hours Interrupt Enable */
+#define DAY DIE /* 24 Hours (Days) Interrupt Enable */
+#define DAY_ALARM DAIE /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
+#define WRITE_COMPLETE WCIE /* Write Complete Interrupt Enable */
+
+
+/* ***************************** UART CONTROLLER MASKS ********************** */
+/* UARTx_LCR Register */
+#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#define STB 0x04 /* Stop Bits */
+#define PEN 0x08 /* Parity Enable */
+#define EPS 0x10 /* Even Parity Select */
+#define STP 0x20 /* Stick Parity */
+#define SB 0x40 /* Set Break */
+#define DLAB 0x80 /* Divisor Latch Access */
+
+#define DLAB_P 0x07
+#define SB_P 0x06
+#define STP_P 0x05
+#define EPS_P 0x04
+#define PEN_P 0x03
+#define STB_P 0x02
+#define WLS_P1 0x01
+#define WLS_P0 0x00
+
+/* UARTx_MCR Register */
+#define LOOP_ENA 0x10 /* Loopback Mode Enable */
+#define LOOP_ENA_P 0x04
+/* Deprecated UARTx_MCR Mask */
+
+/* UARTx_LSR Register */
+#define DR 0x01 /* Data Ready */
+#define OE 0x02 /* Overrun Error */
+#define PE 0x04 /* Parity Error */
+#define FE 0x08 /* Framing Error */
+#define BI 0x10 /* Break Interrupt */
+#define THRE 0x20 /* THR Empty */
+#define TEMT 0x40 /* TSR and UART_THR Empty */
+
+#define TEMP_P 0x06
+#define THRE_P 0x05
+#define BI_P 0x04
+#define FE_P 0x03
+#define PE_P 0x02
+#define OE_P 0x01
+#define DR_P 0x00
+
+/* UARTx_IER Register */
+#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
+#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
+#define ELSI 0x04 /* Enable RX Status Interrupt */
+
+#define ELSI_P 0x02
+#define ETBEI_P 0x01
+#define ERBFI_P 0x00
+
+/* UARTx_IIR Register */
+#define STATUS(x) (((x) << 1) & 0x06)
+#define NINT 0x01
+#define STATUS_P1 0x02
+#define STATUS_P0 0x01
+#define NINT_P 0x00
+
+/* UARTx_GCTL Register */
+#define UCEN 0x01 /* Enable UARTx Clocks */
+#define IREN 0x02 /* Enable IrDA Mode */
+#define TPOLC 0x04 /* IrDA TX Polarity Change */
+#define RPOLC 0x08 /* IrDA RX Polarity Change */
+#define FPE 0x10 /* Force Parity Error On Transmit */
+#define FFE 0x20 /* Force Framing Error On Transmit */
+
+#define FFE_P 0x05
+#define FPE_P 0x04
+#define RPOLC_P 0x03
+#define TPOLC_P 0x02
+#define IREN_P 0x01
+#define UCEN_P 0x00
+
+
+/* ********** SERIAL PORT MASKS ********************** */
+/* SPORTx_TCR1 Masks */
+#define TSPEN 0x0001 /* TX enable */
+#define ITCLK 0x0002 /* Internal TX Clock Select */
+#define TDTYPE 0x000C /* TX Data Formatting Select */
+#define DTYPE_NORM 0x0000 /* Data Format Normal */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define TLSBIT 0x0010 /* TX Bit Order */
+#define ITFS 0x0200 /* Internal TX Frame Sync Select */
+#define TFSR 0x0400 /* TX Frame Sync Required Select */
+#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
+#define LTFS 0x1000 /* Low TX Frame Sync Select */
+#define LATFS 0x2000 /* Late TX Frame Sync Select */
+#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
+/* SPORTx_RCR1 Deprecated Masks */
+#define TULAW DTYPE_ULAW /* Compand Using u-Law */
+#define TALAW DTYPE_ALAW /* Compand Using A-Law */
+
+/* SPORTx_TCR2 Masks */
+#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
+#define TXSE 0x0100 /*TX Secondary Enable */
+#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
+#define TRFST 0x0400 /*TX Right-First Data Order */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN 0x0001 /* RX enable */
+#define IRCLK 0x0002 /* Internal RX Clock Select */
+#define RDTYPE 0x000C /* RX Data Formatting Select */
+#define DTYPE_NORM 0x0000 /* no companding */
+#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
+#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
+#define RLSBIT 0x0010 /* RX Bit Order */
+#define IRFS 0x0200 /* Internal RX Frame Sync Select */
+#define RFSR 0x0400 /* RX Frame Sync Required Select */
+#define LRFS 0x1000 /* Low RX Frame Sync Select */
+#define LARFS 0x2000 /* Late RX Frame Sync Select */
+#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
+/* SPORTx_RCR1 Deprecated Masks */
+#define RULAW DTYPE_ULAW /* Compand Using u-Law */
+#define RALAW DTYPE_ALAW /* Compand Using A-Law */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
+#define RXSE 0x0100 /*RX Secondary Enable */
+#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
+#define RRFST 0x0400 /*Right-First Data Order */
+
+/*SPORTx_STAT Masks */
+#define RXNE 0x0001 /*RX FIFO Not Empty Status */
+#define RUVF 0x0002 /*RX Underflow Status */
+#define ROVF 0x0004 /*RX Overflow Status */
+#define TXF 0x0008 /*TX FIFO Full Status */
+#define TUVF 0x0010 /*TX Underflow Status */
+#define TOVF 0x0020 /*TX Overflow Status */
+#define TXHRE 0x0040 /*TX Hold Register Empty */
+
+/*SPORTx_MCMC1 Masks */
+#define WSIZE 0x0000F000 /*Multichannel Window Size Field */
+#define WOFF 0x000003FF /*Multichannel Window Offset Field */
+/* SPORTx_MCMC1 Macros */
+#define SET_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
+/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
+#define SET_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
+
+/*SPORTx_MCMC2 Masks */
+#define MCCRM 0x0003 /*Multichannel Clock Recovery Mode */
+#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
+#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
+#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
+#define MCDTXPE 0x0004 /*Multichannel DMA Transmit Packing */
+#define MCDRXPE 0x0008 /*Multichannel DMA Receive Packing */
+#define MCMEN 0x0010 /*Multichannel Frame Mode Enable */
+#define FSDR 0x0080 /*Multichannel Frame Sync to Data Relationship */
+#define MFD 0xF000 /*Multichannel Frame Delay */
+#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
+#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
+#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
+#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
+#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
+#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
+#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
+#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
+#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
+#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
+#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
+#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
+#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
+#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
+#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
+#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
+
+
+/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
+/* PPI_CONTROL Masks */
+#define PORT_EN 0x0001 /* PPI Port Enable */
+#define PORT_DIR 0x0002 /* PPI Port Direction */
+#define XFR_TYPE 0x000C /* PPI Transfer Type */
+#define PORT_CFG 0x0030 /* PPI Port Configuration */
+#define FLD_SEL 0x0040 /* PPI Active Field Select */
+#define PACK_EN 0x0080 /* PPI Packing Mode */
+/* previous versions of defBF539.h erroneously included DMA32 (PPI 32-bit DMA Enable) */
+#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
+#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
+#define DLENGTH 0x3800 /* PPI Data Length */
+#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
+#define DLEN_10 0x0800 /* Data Length = 10 Bits */
+#define DLEN_11 0x1000 /* Data Length = 11 Bits */
+#define DLEN_12 0x1800 /* Data Length = 12 Bits */
+#define DLEN_13 0x2000 /* Data Length = 13 Bits */
+#define DLEN_14 0x2800 /* Data Length = 14 Bits */
+#define DLEN_15 0x3000 /* Data Length = 15 Bits */
+#define DLEN_16 0x3800 /* Data Length = 16 Bits */
+#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
+#define POL 0xC000 /* PPI Signal Polarities */
+#define POLC 0x4000 /* PPI Clock Polarity */
+#define POLS 0x8000 /* PPI Frame Sync Polarity */
+
+
+/* PPI_STATUS Masks */
+#define FLD 0x0400 /* Field Indicator */
+#define FT_ERR 0x0800 /* Frame Track Error */
+#define OVR 0x1000 /* FIFO Overflow Error */
+#define UNDR 0x2000 /* FIFO Underrun Error */
+#define ERR_DET 0x4000 /* Error Detected Indicator */
+#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
+
+
+/* ********** DMA CONTROLLER MASKS ***********************/
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN 0x0001 /* Channel Enable */
+#define WNR 0x0002 /* Channel Direction (W/R*) */
+#define WDSIZE_8 0x0000 /* Word Size 8 bits */
+#define WDSIZE_16 0x0004 /* Word Size 16 bits */
+#define WDSIZE_32 0x0008 /* Word Size 32 bits */
+#define DMA2D 0x0010 /* 2D/1D* Mode */
+#define RESTART 0x0020 /* Restart */
+#define DI_SEL 0x0040 /* Data Interrupt Select */
+#define DI_EN 0x0080 /* Data Interrupt Enable */
+#define NDSIZE 0x0900 /* Next Descriptor Size */
+#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
+#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
+#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
+#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
+#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
+#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
+#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
+#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
+#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
+#define FLOW 0x7000 /* Flow Control */
+#define FLOW_STOP 0x0000 /* Stop Mode */
+#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
+#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
+#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
+#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
+
+#define DMAEN_P 0x0 /* Channel Enable */
+#define WNR_P 0x1 /* Channel Direction (W/R*) */
+#define DMA2D_P 0x4 /* 2D/1D* Mode */
+#define RESTART_P 0x5 /* Restart */
+#define DI_SEL_P 0x6 /* Data Interrupt Select */
+#define DI_EN_P 0x7 /* Data Interrupt Enable */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+#define DMA_DONE 0x0001 /* DMA Done Indicator */
+#define DMA_ERR 0x0002 /* DMA Error Indicator */
+#define DFETCH 0x0004 /* Descriptor Fetch Indicator */
+#define DMA_RUN 0x0008 /* DMA Running Indicator */
+
+#define DMA_DONE_P 0x0 /* DMA Done Indicator */
+#define DMA_ERR_P 0x1 /* DMA Error Indicator */
+#define DFETCH_P 0x2 /* Descriptor Fetch Indicator */
+#define DMA_RUN_P 0x3 /* DMA Running Indicator */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+
+#define CTYPE 0x0040 /* DMA Channel Type Indicator */
+#define CTYPE_P 0x6 /* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8 0x0080 /* DMA 8-bit Operation Indicator */
+#define PCAP16 0x0100 /* DMA 16-bit Operation Indicator */
+#define PCAP32 0x0200 /* DMA 32-bit Operation Indicator */
+#define PCAPWR 0x0400 /* DMA Write Operation Indicator */
+#define PCAPRD 0x0800 /* DMA Read Operation Indicator */
+#define PMAP 0xF000 /* DMA Peripheral Map Field */
+
+/* PMAP Encodings For DMA Controller 0 */
+#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
+#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
+#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
+#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
+#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
+#define PMAP_SPI0 0x5000 /* PMAP SPI DMA */
+#define PMAP_UART0RX 0x6000 /* PMAP UART Receive DMA */
+#define PMAP_UART0TX 0x7000 /* PMAP UART Transmit DMA */
+
+/* PMAP Encodings For DMA Controller 1 */
+#define PMAP_SPORT2RX 0x0000 /* PMAP SPORT2 Receive DMA */
+#define PMAP_SPORT2TX 0x1000 /* PMAP SPORT2 Transmit DMA */
+#define PMAP_SPORT3RX 0x2000 /* PMAP SPORT3 Receive DMA */
+#define PMAP_SPORT3TX 0x3000 /* PMAP SPORT3 Transmit DMA */
+#define PMAP_SPI1 0x6000 /* PMAP SPI1 DMA */
+#define PMAP_SPI2 0x7000 /* PMAP SPI2 DMA */
+#define PMAP_UART1RX 0x8000 /* PMAP UART1 Receive DMA */
+#define PMAP_UART1TX 0x9000 /* PMAP UART1 Transmit DMA */
+#define PMAP_UART2RX 0xA000 /* PMAP UART2 Receive DMA */
+#define PMAP_UART2TX 0xB000 /* PMAP UART2 Transmit DMA */
+
+
+/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
+/* PWM Timer bit definitions */
+/* TIMER_ENABLE Register */
+#define TIMEN0 0x0001 /* Enable Timer 0 */
+#define TIMEN1 0x0002 /* Enable Timer 1 */
+#define TIMEN2 0x0004 /* Enable Timer 2 */
+
+#define TIMEN0_P 0x00
+#define TIMEN1_P 0x01
+#define TIMEN2_P 0x02
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0 0x0001 /* Disable Timer 0 */
+#define TIMDIS1 0x0002 /* Disable Timer 1 */
+#define TIMDIS2 0x0004 /* Disable Timer 2 */
+
+#define TIMDIS0_P 0x00
+#define TIMDIS1_P 0x01
+#define TIMDIS2_P 0x02
+
+/* TIMER_STATUS Register */
+#define TIMIL0 0x0001 /* Timer 0 Interrupt */
+#define TIMIL1 0x0002 /* Timer 1 Interrupt */
+#define TIMIL2 0x0004 /* Timer 2 Interrupt */
+#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
+#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
+#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
+#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
+#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
+#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
+
+#define TIMIL0_P 0x00
+#define TIMIL1_P 0x01
+#define TIMIL2_P 0x02
+#define TOVF_ERR0_P 0x04
+#define TOVF_ERR1_P 0x05
+#define TOVF_ERR2_P 0x06
+#define TRUN0_P 0x0C
+#define TRUN1_P 0x0D
+#define TRUN2_P 0x0E
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR0_P TOVF_ERR0_P
+#define TOVL_ERR1_P TOVF_ERR1_P
+#define TOVL_ERR2_P TOVF_ERR2_P
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT 0x0001
+#define WDTH_CAP 0x0002
+#define EXT_CLK 0x0003
+#define PULSE_HI 0x0004
+#define PERIOD_CNT 0x0008
+#define IRQ_ENA 0x0010
+#define TIN_SEL 0x0020
+#define OUT_DIS 0x0040
+#define CLK_SEL 0x0080
+#define TOGGLE_HI 0x0100
+#define EMU_RUN 0x0200
+#define ERR_TYP(x) (((x) & 0x03) << 14)
+
+#define TMODE_P0 0x00
+#define TMODE_P1 0x01
+#define PULSE_HI_P 0x02
+#define PERIOD_CNT_P 0x03
+#define IRQ_ENA_P 0x04
+#define TIN_SEL_P 0x05
+#define OUT_DIS_P 0x06
+#define CLK_SEL_P 0x07
+#define TOGGLE_HI_P 0x08
+#define EMU_RUN_P 0x09
+#define ERR_TYP_P0 0x0E
+#define ERR_TYP_P1 0x0F
+
+
+/*/ ****************** GENERAL-PURPOSE I/O ********************* */
+/* Flag I/O (FIO_) Masks */
+#define PF0 0x0001
+#define PF1 0x0002
+#define PF2 0x0004
+#define PF3 0x0008
+#define PF4 0x0010
+#define PF5 0x0020
+#define PF6 0x0040
+#define PF7 0x0080
+#define PF8 0x0100
+#define PF9 0x0200
+#define PF10 0x0400
+#define PF11 0x0800
+#define PF12 0x1000
+#define PF13 0x2000
+#define PF14 0x4000
+#define PF15 0x8000
+
+/* PORT F BIT POSITIONS */
+#define PF0_P 0x0
+#define PF1_P 0x1
+#define PF2_P 0x2
+#define PF3_P 0x3
+#define PF4_P 0x4
+#define PF5_P 0x5
+#define PF6_P 0x6
+#define PF7_P 0x7
+#define PF8_P 0x8
+#define PF9_P 0x9
+#define PF10_P 0xA
+#define PF11_P 0xB
+#define PF12_P 0xC
+#define PF13_P 0xD
+#define PF14_P 0xE
+#define PF15_P 0xF
+
+
+/******************* GPIO MASKS *********************/
+/* Port C Masks */
+#define PC0 0x0001
+#define PC1 0x0002
+#define PC4 0x0010
+#define PC5 0x0020
+#define PC6 0x0040
+#define PC7 0x0080
+#define PC8 0x0100
+#define PC9 0x0200
+/* Port C Bit Positions */
+#define PC0_P 0x0
+#define PC1_P 0x1
+#define PC4_P 0x4
+#define PC5_P 0x5
+#define PC6_P 0x6
+#define PC7_P 0x7
+#define PC8_P 0x8
+#define PC9_P 0x9
+
+/* Port D */
+#define PD0 0x0001
+#define PD1 0x0002
+#define PD2 0x0004
+#define PD3 0x0008
+#define PD4 0x0010
+#define PD5 0x0020
+#define PD6 0x0040
+#define PD7 0x0080
+#define PD8 0x0100
+#define PD9 0x0200
+#define PD10 0x0400
+#define PD11 0x0800
+#define PD12 0x1000
+#define PD13 0x2000
+#define PD14 0x4000
+#define PD15 0x8000
+/* Port D Bit Positions */
+#define PD0_P 0x0
+#define PD1_P 0x1
+#define PD2_P 0x2
+#define PD3_P 0x3
+#define PD4_P 0x4
+#define PD5_P 0x5
+#define PD6_P 0x6
+#define PD7_P 0x7
+#define PD8_P 0x8
+#define PD9_P 0x9
+#define PD10_P 0xA
+#define PD11_P 0xB
+#define PD12_P 0xC
+#define PD13_P 0xD
+#define PD14_P 0xE
+#define PD15_P 0xF
+
+/* Port E */
+#define PE0 0x0001
+#define PE1 0x0002
+#define PE2 0x0004
+#define PE3 0x0008
+#define PE4 0x0010
+#define PE5 0x0020
+#define PE6 0x0040
+#define PE7 0x0080
+#define PE8 0x0100
+#define PE9 0x0200
+#define PE10 0x0400
+#define PE11 0x0800
+#define PE12 0x1000
+#define PE13 0x2000
+#define PE14 0x4000
+#define PE15 0x8000
+/* Port E Bit Positions */
+#define PE0_P 0x0
+#define PE1_P 0x1
+#define PE2_P 0x2
+#define PE3_P 0x3
+#define PE4_P 0x4
+#define PE5_P 0x5
+#define PE6_P 0x6
+#define PE7_P 0x7
+#define PE8_P 0x8
+#define PE9_P 0x9
+#define PE10_P 0xA
+#define PE11_P 0xB
+#define PE12_P 0xC
+#define PE13_P 0xD
+#define PE14_P 0xE
+#define PE15_P 0xF
+
+
+/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
+/* SPIx_CTL Masks */
+#define TIMOD 0x0003 /* Transfer Initiate Mode */
+#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
+#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
+#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
+#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
+#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
+#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
+#define PSSE 0x0010 /* Slave-Select Input Enable */
+#define EMISO 0x0020 /* Enable MISO As Output */
+#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
+#define LSBF 0x0200 /* LSB First */
+#define CPHA 0x0400 /* Clock Phase */
+#define CPOL 0x0800 /* Clock Polarity */
+#define MSTR 0x1000 /* Master/Slave* */
+#define WOM 0x2000 /* Write Open Drain Master */
+#define SPE 0x4000 /* SPI Enable */
+
+/* SPIx_FLG Masks */
+#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPIx_FLG Bit Positions */
+#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPIx_STAT Masks */
+#define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */
+#define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */
+#define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
+#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
+#define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */
+#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
+#define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */
+
+/* SPIx_FLG Masks */
+#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
+#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
+#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
+#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
+#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
+#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
+#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
+
+
+/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
+/* EBIU_AMGCTL Masks */
+#define AMCKEN 0x0001 /* Enable CLKOUT */
+#define AMBEN_NONE 0x0000 /* All Banks Disabled */
+#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
+
+/* EBIU_AMGCTL Bit Positions */
+#define AMCKEN_P 0x0000 /* Enable CLKOUT */
+#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
+#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+
+/* EBIU_AMBCTL0 Masks */
+#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
+
+/* EBIU_AMBCTL1 Masks */
+#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
+
+/* ********************** SDRAM CONTROLLER MASKS *************************** */
+/* EBIU_SDGCTL Masks */
+#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
+#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
+#define PFE 0x00000010 /* Enable SDRAM prefetch */
+#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
+#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD 0x00200000 /*Power-up start delay */
+#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
+#define EBUFE 0x02000000 /* Enable external buffering timing */
+#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
+#define EMREN 0x10000000 /* Extended mode register enable */
+#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
+#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE 0x00000001 /* Enable SDRAM external bank */
+#define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */
+#define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */
+#define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */
+#define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */
+#define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI 0x00000001 /* SDRAM controller is idle */
+#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
+#define SDPUA 0x00000004 /* SDRAM power up active */
+#define SDRS 0x00000008 /* SDRAM is in reset state */
+#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
+#define BGSTAT 0x00000020 /* Bus granted */
+
+
+/* ******************** TWO-WIRE INTERFACE (TWIx) MASKS ***********************/
+/* TWIx_CLKDIV Macros (Use: *pTWIx_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
+#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
+#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
+
+/* TWIx_PRESCALE Masks */
+#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
+#define TWI_ENA 0x0080 /* TWI Enable */
+#define SCCB 0x0200 /* SCCB Compatibility Enable */
+
+/* TWIx_SLAVE_CTRL Masks */
+#define SEN 0x0001 /* Slave Enable */
+#define SADD_LEN 0x0002 /* Slave Address Length */
+#define STDVAL 0x0004 /* Slave Transmit Data Valid */
+#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN 0x0010 /* General Call Adrress Matching Enabled */
+
+/* TWIx_SLAVE_STAT Masks */
+#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL 0x0002 /* General Call Indicator */
+
+/* TWIx_MASTER_CTRL Masks */
+#define MEN 0x0001 /* Master Mode Enable */
+#define MADD_LEN 0x0002 /* Master Address Length */
+#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
+#define FAST 0x0008 /* Use Fast Mode Timing Specs */
+#define STOP 0x0010 /* Issue Stop Condition */
+#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
+#define DCNT 0x3FC0 /* Data Bytes To Transfer */
+#define SDAOVR 0x4000 /* Serial Data Override */
+#define SCLOVR 0x8000 /* Serial Clock Override */
+
+/* TWIx_MASTER_STAT Masks */
+#define MPROG 0x0001 /* Master Transfer In Progress */
+#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
+#define ANAK 0x0004 /* Address Not Acknowledged */
+#define DNAK 0x0008 /* Data Not Acknowledged */
+#define BUFRDERR 0x0010 /* Buffer Read Error */
+#define BUFWRERR 0x0020 /* Buffer Write Error */
+#define SDASEN 0x0040 /* Serial Data Sense */
+#define SCLSEN 0x0080 /* Serial Clock Sense */
+#define BUSBUSY 0x0100 /* Bus Busy Indicator */
+
+/* TWIx_INT_SRC and TWIx_INT_ENABLE Masks */
+#define SINIT 0x0001 /* Slave Transfer Initiated */
+#define SCOMP 0x0002 /* Slave Transfer Complete */
+#define SERR 0x0004 /* Slave Transfer Error */
+#define SOVF 0x0008 /* Slave Overflow */
+#define MCOMP 0x0010 /* Master Transfer Complete */
+#define MERR 0x0020 /* Master Transfer Error */
+#define XMTSERV 0x0040 /* Transmit FIFO Service */
+#define RCVSERV 0x0080 /* Receive FIFO Service */
+
+/* TWIx_FIFO_CTRL Masks */
+#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
+#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
+#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
+#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
+
+/* TWIx_FIFO_STAT Masks */
+#define XMTSTAT 0x0003 /* Transmit FIFO Status */
+#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
+#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
+#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
+
+#define RCVSTAT 0x000C /* Receive FIFO Status */
+#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
+#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
+#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
+
+
+/********************************* MXVR MASKS ****************************************/
+
+/* MXVR_CONFIG Masks */
+
+#define MXVREN 0x00000001lu
+#define MMSM 0x00000002lu
+#define ACTIVE 0x00000004lu
+#define SDELAY 0x00000008lu
+#define NCMRXEN 0x00000010lu
+#define RWRRXEN 0x00000020lu
+#define MTXEN 0x00000040lu
+#define MTXON 0x00000080lu /*legacy*/
+#define MTXONB 0x00000080lu
+#define EPARITY 0x00000100lu
+#define MSB 0x00001E00lu
+#define APRXEN 0x00002000lu
+#define WAKEUP 0x00004000lu
+#define LMECH 0x00008000lu
+
+#define SET_MSB(x) (((x)&0xF) << 0x9)
+
+
+/* MXVR_PLL_CTL_0 Masks */
+
+#define MXTALCEN 0x00000001lu
+#define MXTALFEN 0x00000002lu
+#define MPLLMS 0x00000008lu
+#define MXTALMUL 0x00000030lu
+#define MPLLEN 0x00000040lu
+#define MPLLEN0 0x00000040lu /* legacy */
+#define MPLLEN1 0x00000080lu /* legacy */
+#define MMCLKEN 0x00000100lu
+#define MMCLKMUL 0x00001E00lu
+#define MPLLRSTB 0x00002000lu
+#define MPLLRSTB0 0x00002000lu /* legacy */
+#define MPLLRSTB1 0x00004000lu /* legacy */
+#define MBCLKEN 0x00010000lu
+#define MBCLKDIV 0x001E0000lu
+#define MPLLCDR 0x00200000lu
+#define MPLLCDR0 0x00200000lu /* legacy */
+#define MPLLCDR1 0x00400000lu /* legacy */
+#define INVRX 0x00800000lu
+#define MFSEN 0x01000000lu
+#define MFSDIV 0x1E000000lu
+#define MFSSEL 0x60000000lu
+#define MFSSYNC 0x80000000lu
+
+#define MXTALMUL_256FS 0x00000000lu /* legacy */
+#define MXTALMUL_384FS 0x00000010lu /* legacy */
+#define MXTALMUL_512FS 0x00000020lu /* legacy */
+#define MXTALMUL_1024FS 0x00000030lu
+
+#define MMCLKMUL_1024FS 0x00000000lu
+#define MMCLKMUL_512FS 0x00000200lu
+#define MMCLKMUL_256FS 0x00000400lu
+#define MMCLKMUL_128FS 0x00000600lu
+#define MMCLKMUL_64FS 0x00000800lu
+#define MMCLKMUL_32FS 0x00000A00lu
+#define MMCLKMUL_16FS 0x00000C00lu
+#define MMCLKMUL_8FS 0x00000E00lu
+#define MMCLKMUL_4FS 0x00001000lu
+#define MMCLKMUL_2FS 0x00001200lu
+#define MMCLKMUL_1FS 0x00001400lu
+#define MMCLKMUL_1536FS 0x00001A00lu
+#define MMCLKMUL_768FS 0x00001C00lu
+#define MMCLKMUL_384FS 0x00001E00lu
+
+#define MBCLKDIV_DIV2 0x00020000lu
+#define MBCLKDIV_DIV4 0x00040000lu
+#define MBCLKDIV_DIV8 0x00060000lu
+#define MBCLKDIV_DIV16 0x00080000lu
+#define MBCLKDIV_DIV32 0x000A0000lu
+#define MBCLKDIV_DIV64 0x000C0000lu
+#define MBCLKDIV_DIV128 0x000E0000lu
+#define MBCLKDIV_DIV256 0x00100000lu
+#define MBCLKDIV_DIV512 0x00120000lu
+#define MBCLKDIV_DIV1024 0x00140000lu
+
+#define MFSDIV_DIV2 0x02000000lu
+#define MFSDIV_DIV4 0x04000000lu
+#define MFSDIV_DIV8 0x06000000lu
+#define MFSDIV_DIV16 0x08000000lu
+#define MFSDIV_DIV32 0x0A000000lu
+#define MFSDIV_DIV64 0x0C000000lu
+#define MFSDIV_DIV128 0x0E000000lu
+#define MFSDIV_DIV256 0x10000000lu
+#define MFSDIV_DIV512 0x12000000lu
+#define MFSDIV_DIV1024 0x14000000lu
+
+#define MFSSEL_CLOCK 0x00000000lu
+#define MFSSEL_PULSE_HI 0x20000000lu
+#define MFSSEL_PULSE_LO 0x40000000lu
+
+
+/* MXVR_PLL_CTL_1 Masks */
+
+#define MSTO 0x00000001lu
+#define MSTO0 0x00000001lu /* legacy */
+#define MHOGGD 0x00000004lu
+#define MHOGGD0 0x00000004lu /* legacy */
+#define MHOGGD1 0x00000008lu /* legacy */
+#define MSHAPEREN 0x00000010lu
+#define MSHAPEREN0 0x00000010lu /* legacy */
+#define MSHAPEREN1 0x00000020lu /* legacy */
+#define MPLLCNTEN 0x00008000lu
+#define MPLLCNT 0xFFFF0000lu
+
+#define SET_MPLLCNT(x) (((x)&0xFFFF) << 0x10)
+
+
+/* MXVR_PLL_CTL_2 Masks */
+
+#define MSHAPERSEL 0x00000007lu
+#define MCPSEL 0x000000E0lu
+
+#define SET_MSHAPERSEL(x) ( (x) & 0x0007 )
+#define SET_MCPSEL(x) ( ( (x) & 0x0007 ) << 0x5 )
+
+
+/* MXVR_INT_STAT_0 Masks */
+
+#define NI2A 0x00000001lu
+#define NA2I 0x00000002lu
+#define SBU2L 0x00000004lu
+#define SBL2U 0x00000008lu
+#define PRU 0x00000010lu
+#define MPRU 0x00000020lu
+#define DRU 0x00000040lu
+#define MDRU 0x00000080lu
+#define SBU 0x00000100lu
+#define ATU 0x00000200lu
+#define FCZ0 0x00000400lu
+#define FCZ1 0x00000800lu
+#define PERR 0x00001000lu
+#define MH2L 0x00002000lu
+#define ML2H 0x00004000lu
+#define WUP 0x00008000lu
+#define FU2L 0x00010000lu
+#define FL2U 0x00020000lu
+#define BU2L 0x00040000lu
+#define BL2U 0x00080000lu
+#define PCZ 0x00400000lu
+#define FERR 0x00800000lu
+#define CMR 0x01000000lu
+#define CMROF 0x02000000lu
+#define CMTS 0x04000000lu
+#define CMTC 0x08000000lu
+#define RWRC 0x10000000lu
+#define BCZ 0x20000000lu
+#define BMERR 0x40000000lu
+#define DERR 0x80000000lu
+
+
+/* MXVR_INT_EN_0 Masks */
+
+#define NI2AEN NI2A
+#define NA2IEN NA2I
+#define SBU2LEN SBU2L
+#define SBL2UEN SBL2U
+#define PRUEN PRU
+#define MPRUEN MPRU
+#define DRUEN DRU
+#define MDRUEN MDRU
+#define SBUEN SBU
+#define ATUEN ATU
+#define FCZ0EN FCZ0
+#define FCZ1EN FCZ1
+#define PERREN PERR
+#define MH2LEN MH2L
+#define ML2HEN ML2H
+#define WUPEN WUP
+#define FU2LEN FU2L
+#define FL2UEN FL2U
+#define BU2LEN BU2L
+#define BL2UEN BL2U
+#define PCZEN PCZ
+#define FERREN FERR
+#define CMREN CMR
+#define CMROFEN CMROF
+#define CMTSEN CMTS
+#define CMTCEN CMTC
+#define RWRCEN RWRC
+#define BCZEN BCZ
+#define BMERREN BMERR
+#define DERREN DERR
+
+
+/* MXVR_INT_STAT_1 Masks */
+
+#define APR 0x00000004lu
+#define APROF 0x00000008lu
+#define APTS 0x00000040lu
+#define APTC 0x00000080lu
+#define APRCE 0x00000400lu
+#define APRPE 0x00000800lu
+
+#define HDONE0 0x00000001lu
+#define DONE0 0x00000002lu
+#define HDONE1 0x00000010lu
+#define DONE1 0x00000020lu
+#define HDONE2 0x00000100lu
+#define DONE2 0x00000200lu
+#define HDONE3 0x00001000lu
+#define DONE3 0x00002000lu
+#define HDONE4 0x00010000lu
+#define DONE4 0x00020000lu
+#define HDONE5 0x00100000lu
+#define DONE5 0x00200000lu
+#define HDONE6 0x01000000lu
+#define DONE6 0x02000000lu
+#define HDONE7 0x10000000lu
+#define DONE7 0x20000000lu
+
+#define DONEX(x) (0x00000002 << (4 * (x)))
+#define HDONEX(x) (0x00000001 << (4 * (x)))
+
+
+/* MXVR_INT_EN_1 Masks */
+
+#define APREN APR
+#define APROFEN APROF
+#define APTSEN APTS
+#define APTCEN APTC
+#define APRCEEN APRCE
+#define APRPEEN APRPE
+
+#define HDONEEN0 HDONE0
+#define DONEEN0 DONE0
+#define HDONEEN1 HDONE1
+#define DONEEN1 DONE1
+#define HDONEEN2 HDONE2
+#define DONEEN2 DONE2
+#define HDONEEN3 HDONE3
+#define DONEEN3 DONE3
+#define HDONEEN4 HDONE4
+#define DONEEN4 DONE4
+#define HDONEEN5 HDONE5
+#define DONEEN5 DONE5
+#define HDONEEN6 HDONE6
+#define DONEEN6 DONE6
+#define HDONEEN7 HDONE7
+#define DONEEN7 DONE7
+
+#define DONEENX(x) (0x00000002 << (4 * (x)))
+#define HDONEENX(x) (0x00000001 << (4 * (x)))
+
+
+/* MXVR_STATE_0 Masks */
+
+#define NACT 0x00000001lu
+#define SBLOCK 0x00000002lu
+#define PFDLOCK 0x00000004lu
+#define PFDLOCK0 0x00000004lu /* legacy */
+#define PDD 0x00000008lu
+#define PDD0 0x00000008lu /* legacy */
+#define PVCO 0x00000010lu
+#define PVCO0 0x00000010lu /* legacy */
+#define PFDLOCK1 0x00000020lu /* legacy */
+#define PDD1 0x00000040lu /* legacy */
+#define PVCO1 0x00000080lu /* legacy */
+#define APBSY 0x00000100lu
+#define APARB 0x00000200lu
+#define APTX 0x00000400lu
+#define APRX 0x00000800lu
+#define CMBSY 0x00001000lu
+#define CMARB 0x00002000lu
+#define CMTX 0x00004000lu
+#define CMRX 0x00008000lu
+#define MRXONB 0x00010000lu
+#define RGSIP 0x00020000lu
+#define DALIP 0x00040000lu
+#define ALIP 0x00080000lu
+#define RRDIP 0x00100000lu
+#define RWRIP 0x00200000lu
+#define FLOCK 0x00400000lu
+#define BLOCK 0x00800000lu
+#define RSB 0x0F000000lu
+#define DERRNUM 0xF0000000lu
+
+
+/* MXVR_STATE_1 Masks */
+
+#define STXNUMB 0x0000000Flu
+#define SRXNUMB 0x000000F0lu
+#define APCONT 0x00000100lu
+#define DMAACTIVEX 0x00FF0000lu
+#define DMAACTIVE0 0x00010000lu
+#define DMAACTIVE1 0x00020000lu
+#define DMAACTIVE2 0x00040000lu
+#define DMAACTIVE3 0x00080000lu
+#define DMAACTIVE4 0x00100000lu
+#define DMAACTIVE5 0x00200000lu
+#define DMAACTIVE6 0x00400000lu
+#define DMAACTIVE7 0x00800000lu
+#define DMAPMENX 0xFF000000lu
+#define DMAPMEN0 0x01000000lu
+#define DMAPMEN1 0x02000000lu
+#define DMAPMEN2 0x04000000lu
+#define DMAPMEN3 0x08000000lu
+#define DMAPMEN4 0x10000000lu
+#define DMAPMEN5 0x20000000lu
+#define DMAPMEN6 0x40000000lu
+#define DMAPMEN7 0x80000000lu
+
+
+/* MXVR_POSITION Masks */
+
+#define PVALID 0x8000
+#define POSITION 0x003F
+
+
+/* MXVR_MAX_POSITION Masks */
+
+#define MPVALID 0x8000
+#define MPOSITION 0x003F
+
+
+/* MXVR_DELAY Masks */
+
+#define DVALID 0x8000
+#define DELAY 0x003F
+
+
+/* MXVR_MAX_DELAY Masks */
+
+#define MDVALID 0x8000
+#define MDELAY 0x003F
+
+
+/* MXVR_LADDR Masks */
+
+#define LVALID 0x80000000lu
+#define LADDR 0x0000FFFFlu
+
+
+/* MXVR_GADDR Masks */
+
+#define GVALID 0x8000
+#define GADDRL 0x00FF
+
+
+/* MXVR_AADDR Masks */
+
+#define AVALID 0x80000000lu
+#define AADDR 0x0000FFFFlu
+
+
+/* MXVR_ALLOC_0 Masks */
+
+#define CIU0 0x00000080lu
+#define CIU1 0x00008000lu
+#define CIU2 0x00800000lu
+#define CIU3 0x80000000lu
+
+#define CL0 0x0000007Flu
+#define CL1 0x00007F00lu
+#define CL2 0x007F0000lu
+#define CL3 0x7F000000lu
+
+
+/* MXVR_ALLOC_1 Masks */
+
+#define CIU4 0x00000080lu
+#define CIU5 0x00008000lu
+#define CIU6 0x00800000lu
+#define CIU7 0x80000000lu
+
+#define CL4 0x0000007Flu
+#define CL5 0x00007F00lu
+#define CL6 0x007F0000lu
+#define CL7 0x7F000000lu
+
+
+/* MXVR_ALLOC_2 Masks */
+
+#define CIU8 0x00000080lu
+#define CIU9 0x00008000lu
+#define CIU10 0x00800000lu
+#define CIU11 0x80000000lu
+
+#define CL8 0x0000007Flu
+#define CL9 0x00007F00lu
+#define CL10 0x007F0000lu
+#define CL11 0x7F000000lu
+
+
+/* MXVR_ALLOC_3 Masks */
+
+#define CIU12 0x00000080lu
+#define CIU13 0x00008000lu
+#define CIU14 0x00800000lu
+#define CIU15 0x80000000lu
+
+#define CL12 0x0000007Flu
+#define CL13 0x00007F00lu
+#define CL14 0x007F0000lu
+#define CL15 0x7F000000lu
+
+
+/* MXVR_ALLOC_4 Masks */
+
+#define CIU16 0x00000080lu
+#define CIU17 0x00008000lu
+#define CIU18 0x00800000lu
+#define CIU19 0x80000000lu
+
+#define CL16 0x0000007Flu
+#define CL17 0x00007F00lu
+#define CL18 0x007F0000lu
+#define CL19 0x7F000000lu
+
+
+/* MXVR_ALLOC_5 Masks */
+
+#define CIU20 0x00000080lu
+#define CIU21 0x00008000lu
+#define CIU22 0x00800000lu
+#define CIU23 0x80000000lu
+
+#define CL20 0x0000007Flu
+#define CL21 0x00007F00lu
+#define CL22 0x007F0000lu
+#define CL23 0x7F000000lu
+
+
+/* MXVR_ALLOC_6 Masks */
+
+#define CIU24 0x00000080lu
+#define CIU25 0x00008000lu
+#define CIU26 0x00800000lu
+#define CIU27 0x80000000lu
+
+#define CL24 0x0000007Flu
+#define CL25 0x00007F00lu
+#define CL26 0x007F0000lu
+#define CL27 0x7F000000lu
+
+
+/* MXVR_ALLOC_7 Masks */
+
+#define CIU28 0x00000080lu
+#define CIU29 0x00008000lu
+#define CIU30 0x00800000lu
+#define CIU31 0x80000000lu
+
+#define CL28 0x0000007Flu
+#define CL29 0x00007F00lu
+#define CL30 0x007F0000lu
+#define CL31 0x7F000000lu
+
+
+/* MXVR_ALLOC_8 Masks */
+
+#define CIU32 0x00000080lu
+#define CIU33 0x00008000lu
+#define CIU34 0x00800000lu
+#define CIU35 0x80000000lu
+
+#define CL32 0x0000007Flu
+#define CL33 0x00007F00lu
+#define CL34 0x007F0000lu
+#define CL35 0x7F000000lu
+
+
+/* MXVR_ALLOC_9 Masks */
+
+#define CIU36 0x00000080lu
+#define CIU37 0x00008000lu
+#define CIU38 0x00800000lu
+#define CIU39 0x80000000lu
+
+#define CL36 0x0000007Flu
+#define CL37 0x00007F00lu
+#define CL38 0x007F0000lu
+#define CL39 0x7F000000lu
+
+
+/* MXVR_ALLOC_10 Masks */
+
+#define CIU40 0x00000080lu
+#define CIU41 0x00008000lu
+#define CIU42 0x00800000lu
+#define CIU43 0x80000000lu
+
+#define CL40 0x0000007Flu
+#define CL41 0x00007F00lu
+#define CL42 0x007F0000lu
+#define CL43 0x7F000000lu
+
+
+/* MXVR_ALLOC_11 Masks */
+
+#define CIU44 0x00000080lu
+#define CIU45 0x00008000lu
+#define CIU46 0x00800000lu
+#define CIU47 0x80000000lu
+
+#define CL44 0x0000007Flu
+#define CL45 0x00007F00lu
+#define CL46 0x007F0000lu
+#define CL47 0x7F000000lu
+
+
+/* MXVR_ALLOC_12 Masks */
+
+#define CIU48 0x00000080lu
+#define CIU49 0x00008000lu
+#define CIU50 0x00800000lu
+#define CIU51 0x80000000lu
+
+#define CL48 0x0000007Flu
+#define CL49 0x00007F00lu
+#define CL50 0x007F0000lu
+#define CL51 0x7F000000lu
+
+
+/* MXVR_ALLOC_13 Masks */
+
+#define CIU52 0x00000080lu
+#define CIU53 0x00008000lu
+#define CIU54 0x00800000lu
+#define CIU55 0x80000000lu
+
+#define CL52 0x0000007Flu
+#define CL53 0x00007F00lu
+#define CL54 0x007F0000lu
+#define CL55 0x7F000000lu
+
+
+/* MXVR_ALLOC_14 Masks */
+
+#define CIU56 0x00000080lu
+#define CIU57 0x00008000lu
+#define CIU58 0x00800000lu
+#define CIU59 0x80000000lu
+
+#define CL56 0x0000007Flu
+#define CL57 0x00007F00lu
+#define CL58 0x007F0000lu
+#define CL59 0x7F000000lu
+
+
+/* MXVR_SYNC_LCHAN_0 Masks */
+
+#define LCHANPC0 0x0000000Flu
+#define LCHANPC1 0x000000F0lu
+#define LCHANPC2 0x00000F00lu
+#define LCHANPC3 0x0000F000lu
+#define LCHANPC4 0x000F0000lu
+#define LCHANPC5 0x00F00000lu
+#define LCHANPC6 0x0F000000lu
+#define LCHANPC7 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_1 Masks */
+
+#define LCHANPC8 0x0000000Flu
+#define LCHANPC9 0x000000F0lu
+#define LCHANPC10 0x00000F00lu
+#define LCHANPC11 0x0000F000lu
+#define LCHANPC12 0x000F0000lu
+#define LCHANPC13 0x00F00000lu
+#define LCHANPC14 0x0F000000lu
+#define LCHANPC15 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_2 Masks */
+
+#define LCHANPC16 0x0000000Flu
+#define LCHANPC17 0x000000F0lu
+#define LCHANPC18 0x00000F00lu
+#define LCHANPC19 0x0000F000lu
+#define LCHANPC20 0x000F0000lu
+#define LCHANPC21 0x00F00000lu
+#define LCHANPC22 0x0F000000lu
+#define LCHANPC23 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_3 Masks */
+
+#define LCHANPC24 0x0000000Flu
+#define LCHANPC25 0x000000F0lu
+#define LCHANPC26 0x00000F00lu
+#define LCHANPC27 0x0000F000lu
+#define LCHANPC28 0x000F0000lu
+#define LCHANPC29 0x00F00000lu
+#define LCHANPC30 0x0F000000lu
+#define LCHANPC31 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_4 Masks */
+
+#define LCHANPC32 0x0000000Flu
+#define LCHANPC33 0x000000F0lu
+#define LCHANPC34 0x00000F00lu
+#define LCHANPC35 0x0000F000lu
+#define LCHANPC36 0x000F0000lu
+#define LCHANPC37 0x00F00000lu
+#define LCHANPC38 0x0F000000lu
+#define LCHANPC39 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_5 Masks */
+
+#define LCHANPC40 0x0000000Flu
+#define LCHANPC41 0x000000F0lu
+#define LCHANPC42 0x00000F00lu
+#define LCHANPC43 0x0000F000lu
+#define LCHANPC44 0x000F0000lu
+#define LCHANPC45 0x00F00000lu
+#define LCHANPC46 0x0F000000lu
+#define LCHANPC47 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_6 Masks */
+
+#define LCHANPC48 0x0000000Flu
+#define LCHANPC49 0x000000F0lu
+#define LCHANPC50 0x00000F00lu
+#define LCHANPC51 0x0000F000lu
+#define LCHANPC52 0x000F0000lu
+#define LCHANPC53 0x00F00000lu
+#define LCHANPC54 0x0F000000lu
+#define LCHANPC55 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_7 Masks */
+
+#define LCHANPC56 0x0000000Flu
+#define LCHANPC57 0x000000F0lu
+#define LCHANPC58 0x00000F00lu
+#define LCHANPC59 0x0000F000lu
+
+
+/* MXVR_DMAx_CONFIG Masks */
+
+#define MDMAEN 0x00000001lu
+#define DD 0x00000002lu
+#define LCHAN 0x000003C0lu
+#define BITSWAPEN 0x00000400lu
+#define BYSWAPEN 0x00000800lu
+#define MFLOW 0x00007000lu
+#define FIXEDPM 0x00080000lu
+#define STARTPAT 0x00300000lu
+#define STOPPAT 0x00C00000lu
+#define COUNTPOS 0x1C000000lu
+
+#define DD_TX 0x00000000lu
+#define DD_RX 0x00000002lu
+
+#define LCHAN_0 0x00000000lu
+#define LCHAN_1 0x00000040lu
+#define LCHAN_2 0x00000080lu
+#define LCHAN_3 0x000000C0lu
+#define LCHAN_4 0x00000100lu
+#define LCHAN_5 0x00000140lu
+#define LCHAN_6 0x00000180lu
+#define LCHAN_7 0x000001C0lu
+
+#define MFLOW_STOP 0x00000000lu
+#define MFLOW_AUTO 0x00001000lu
+#define MFLOW_PVC 0x00002000lu
+#define MFLOW_PSS 0x00003000lu
+#define MFLOW_PFC 0x00004000lu
+
+#define STARTPAT_0 0x00000000lu
+#define STARTPAT_1 0x00100000lu
+
+#define STOPPAT_0 0x00000000lu
+#define STOPPAT_1 0x00400000lu
+
+#define COUNTPOS_0 0x00000000lu
+#define COUNTPOS_1 0x04000000lu
+#define COUNTPOS_2 0x08000000lu
+#define COUNTPOS_3 0x0C000000lu
+#define COUNTPOS_4 0x10000000lu
+#define COUNTPOS_5 0x14000000lu
+#define COUNTPOS_6 0x18000000lu
+#define COUNTPOS_7 0x1C000000lu
+
+
+/* MXVR_AP_CTL Masks */
+
+#define STARTAP 0x00000001lu
+#define CANCELAP 0x00000002lu
+#define RESETAP 0x00000004lu
+#define APRBE0 0x00004000lu
+#define APRBE1 0x00008000lu
+#define APRBEX 0x0000C000lu
+
+
+/* MXVR_CM_CTL Masks */
+
+#define STARTCM 0x00000001lu
+#define CANCELCM 0x00000002lu
+#define CMRBEX 0xFFFF0000lu
+#define CMRBE0 0x00010000lu
+#define CMRBE1 0x00020000lu
+#define CMRBE2 0x00040000lu
+#define CMRBE3 0x00080000lu
+#define CMRBE4 0x00100000lu
+#define CMRBE5 0x00200000lu
+#define CMRBE6 0x00400000lu
+#define CMRBE7 0x00800000lu
+#define CMRBE8 0x01000000lu
+#define CMRBE9 0x02000000lu
+#define CMRBE10 0x04000000lu
+#define CMRBE11 0x08000000lu
+#define CMRBE12 0x10000000lu
+#define CMRBE13 0x20000000lu
+#define CMRBE14 0x40000000lu
+#define CMRBE15 0x80000000lu
+
+
+/* MXVR_PAT_DATA_x Masks */
+
+#define MATCH_DATA_0 0x000000FFlu
+#define MATCH_DATA_1 0x0000FF00lu
+#define MATCH_DATA_2 0x00FF0000lu
+#define MATCH_DATA_3 0xFF000000lu
+
+
+
+/* MXVR_PAT_EN_x Masks */
+
+#define MATCH_EN_0_0 0x00000001lu
+#define MATCH_EN_0_1 0x00000002lu
+#define MATCH_EN_0_2 0x00000004lu
+#define MATCH_EN_0_3 0x00000008lu
+#define MATCH_EN_0_4 0x00000010lu
+#define MATCH_EN_0_5 0x00000020lu
+#define MATCH_EN_0_6 0x00000040lu
+#define MATCH_EN_0_7 0x00000080lu
+
+#define MATCH_EN_1_0 0x00000100lu
+#define MATCH_EN_1_1 0x00000200lu
+#define MATCH_EN_1_2 0x00000400lu
+#define MATCH_EN_1_3 0x00000800lu
+#define MATCH_EN_1_4 0x00001000lu
+#define MATCH_EN_1_5 0x00002000lu
+#define MATCH_EN_1_6 0x00004000lu
+#define MATCH_EN_1_7 0x00008000lu
+
+#define MATCH_EN_2_0 0x00010000lu
+#define MATCH_EN_2_1 0x00020000lu
+#define MATCH_EN_2_2 0x00040000lu
+#define MATCH_EN_2_3 0x00080000lu
+#define MATCH_EN_2_4 0x00100000lu
+#define MATCH_EN_2_5 0x00200000lu
+#define MATCH_EN_2_6 0x00400000lu
+#define MATCH_EN_2_7 0x00800000lu
+
+#define MATCH_EN_3_0 0x01000000lu
+#define MATCH_EN_3_1 0x02000000lu
+#define MATCH_EN_3_2 0x04000000lu
+#define MATCH_EN_3_3 0x08000000lu
+#define MATCH_EN_3_4 0x10000000lu
+#define MATCH_EN_3_5 0x20000000lu
+#define MATCH_EN_3_6 0x40000000lu
+#define MATCH_EN_3_7 0x80000000lu
+
+
+/* MXVR_ROUTING_0 Masks */
+
+#define MUTE_CH0 0x00000080lu
+#define MUTE_CH1 0x00008000lu
+#define MUTE_CH2 0x00800000lu
+#define MUTE_CH3 0x80000000lu
+
+#define TX_CH0 0x0000007Flu
+#define TX_CH1 0x00007F00lu
+#define TX_CH2 0x007F0000lu
+#define TX_CH3 0x7F000000lu
+
+
+/* MXVR_ROUTING_1 Masks */
+
+#define MUTE_CH4 0x00000080lu
+#define MUTE_CH5 0x00008000lu
+#define MUTE_CH6 0x00800000lu
+#define MUTE_CH7 0x80000000lu
+
+#define TX_CH4 0x0000007Flu
+#define TX_CH5 0x00007F00lu
+#define TX_CH6 0x007F0000lu
+#define TX_CH7 0x7F000000lu
+
+
+/* MXVR_ROUTING_2 Masks */
+
+#define MUTE_CH8 0x00000080lu
+#define MUTE_CH9 0x00008000lu
+#define MUTE_CH10 0x00800000lu
+#define MUTE_CH11 0x80000000lu
+
+#define TX_CH8 0x0000007Flu
+#define TX_CH9 0x00007F00lu
+#define TX_CH10 0x007F0000lu
+#define TX_CH11 0x7F000000lu
+
+/* MXVR_ROUTING_3 Masks */
+
+#define MUTE_CH12 0x00000080lu
+#define MUTE_CH13 0x00008000lu
+#define MUTE_CH14 0x00800000lu
+#define MUTE_CH15 0x80000000lu
+
+#define TX_CH12 0x0000007Flu
+#define TX_CH13 0x00007F00lu
+#define TX_CH14 0x007F0000lu
+#define TX_CH15 0x7F000000lu
+
+
+/* MXVR_ROUTING_4 Masks */
+
+#define MUTE_CH16 0x00000080lu
+#define MUTE_CH17 0x00008000lu
+#define MUTE_CH18 0x00800000lu
+#define MUTE_CH19 0x80000000lu
+
+#define TX_CH16 0x0000007Flu
+#define TX_CH17 0x00007F00lu
+#define TX_CH18 0x007F0000lu
+#define TX_CH19 0x7F000000lu
+
+
+/* MXVR_ROUTING_5 Masks */
+
+#define MUTE_CH20 0x00000080lu
+#define MUTE_CH21 0x00008000lu
+#define MUTE_CH22 0x00800000lu
+#define MUTE_CH23 0x80000000lu
+
+#define TX_CH20 0x0000007Flu
+#define TX_CH21 0x00007F00lu
+#define TX_CH22 0x007F0000lu
+#define TX_CH23 0x7F000000lu
+
+
+/* MXVR_ROUTING_6 Masks */
+
+#define MUTE_CH24 0x00000080lu
+#define MUTE_CH25 0x00008000lu
+#define MUTE_CH26 0x00800000lu
+#define MUTE_CH27 0x80000000lu
+
+#define TX_CH24 0x0000007Flu
+#define TX_CH25 0x00007F00lu
+#define TX_CH26 0x007F0000lu
+#define TX_CH27 0x7F000000lu
+
+
+/* MXVR_ROUTING_7 Masks */
+
+#define MUTE_CH28 0x00000080lu
+#define MUTE_CH29 0x00008000lu
+#define MUTE_CH30 0x00800000lu
+#define MUTE_CH31 0x80000000lu
+
+#define TX_CH28 0x0000007Flu
+#define TX_CH29 0x00007F00lu
+#define TX_CH30 0x007F0000lu
+#define TX_CH31 0x7F000000lu
+
+
+/* MXVR_ROUTING_8 Masks */
+
+#define MUTE_CH32 0x00000080lu
+#define MUTE_CH33 0x00008000lu
+#define MUTE_CH34 0x00800000lu
+#define MUTE_CH35 0x80000000lu
+
+#define TX_CH32 0x0000007Flu
+#define TX_CH33 0x00007F00lu
+#define TX_CH34 0x007F0000lu
+#define TX_CH35 0x7F000000lu
+
+
+/* MXVR_ROUTING_9 Masks */
+
+#define MUTE_CH36 0x00000080lu
+#define MUTE_CH37 0x00008000lu
+#define MUTE_CH38 0x00800000lu
+#define MUTE_CH39 0x80000000lu
+
+#define TX_CH36 0x0000007Flu
+#define TX_CH37 0x00007F00lu
+#define TX_CH38 0x007F0000lu
+#define TX_CH39 0x7F000000lu
+
+
+/* MXVR_ROUTING_10 Masks */
+
+#define MUTE_CH40 0x00000080lu
+#define MUTE_CH41 0x00008000lu
+#define MUTE_CH42 0x00800000lu
+#define MUTE_CH43 0x80000000lu
+
+#define TX_CH40 0x0000007Flu
+#define TX_CH41 0x00007F00lu
+#define TX_CH42 0x007F0000lu
+#define TX_CH43 0x7F000000lu
+
+
+/* MXVR_ROUTING_11 Masks */
+
+#define MUTE_CH44 0x00000080lu
+#define MUTE_CH45 0x00008000lu
+#define MUTE_CH46 0x00800000lu
+#define MUTE_CH47 0x80000000lu
+
+#define TX_CH44 0x0000007Flu
+#define TX_CH45 0x00007F00lu
+#define TX_CH46 0x007F0000lu
+#define TX_CH47 0x7F000000lu
+
+
+/* MXVR_ROUTING_12 Masks */
+
+#define MUTE_CH48 0x00000080lu
+#define MUTE_CH49 0x00008000lu
+#define MUTE_CH50 0x00800000lu
+#define MUTE_CH51 0x80000000lu
+
+#define TX_CH48 0x0000007Flu
+#define TX_CH49 0x00007F00lu
+#define TX_CH50 0x007F0000lu
+#define TX_CH51 0x7F000000lu
+
+
+/* MXVR_ROUTING_13 Masks */
+
+#define MUTE_CH52 0x00000080lu
+#define MUTE_CH53 0x00008000lu
+#define MUTE_CH54 0x00800000lu
+#define MUTE_CH55 0x80000000lu
+
+#define TX_CH52 0x0000007Flu
+#define TX_CH53 0x00007F00lu
+#define TX_CH54 0x007F0000lu
+#define TX_CH55 0x7F000000lu
+
+
+/* MXVR_ROUTING_14 Masks */
+
+#define MUTE_CH56 0x00000080lu
+#define MUTE_CH57 0x00008000lu
+#define MUTE_CH58 0x00800000lu
+#define MUTE_CH59 0x80000000lu
+
+#define TX_CH56 0x0000007Flu
+#define TX_CH57 0x00007F00lu
+#define TX_CH58 0x007F0000lu
+#define TX_CH59 0x7F000000lu
+
+
+/* Control Message Receive Buffer (CMRB) Address Offsets */
+
+#define CMRB_STRIDE 0x00000016lu
+
+#define CMRB_DST_OFFSET 0x00000000lu
+#define CMRB_SRC_OFFSET 0x00000002lu
+#define CMRB_DATA_OFFSET 0x00000005lu
+
+
+/* Control Message Transmit Buffer (CMTB) Address Offsets */
+
+#define CMTB_PRIO_OFFSET 0x00000000lu
+#define CMTB_DST_OFFSET 0x00000002lu
+#define CMTB_SRC_OFFSET 0x00000004lu
+#define CMTB_TYPE_OFFSET 0x00000006lu
+#define CMTB_DATA_OFFSET 0x00000007lu
+
+#define CMTB_ANSWER_OFFSET 0x0000000Alu
+
+#define CMTB_STAT_N_OFFSET 0x00000018lu
+#define CMTB_STAT_A_OFFSET 0x00000016lu
+#define CMTB_STAT_D_OFFSET 0x0000000Elu
+#define CMTB_STAT_R_OFFSET 0x00000014lu
+#define CMTB_STAT_W_OFFSET 0x00000014lu
+#define CMTB_STAT_G_OFFSET 0x00000014lu
+
+
+/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
+
+#define APRB_STRIDE 0x00000400lu
+
+#define APRB_DST_OFFSET 0x00000000lu
+#define APRB_LEN_OFFSET 0x00000002lu
+#define APRB_SRC_OFFSET 0x00000004lu
+#define APRB_DATA_OFFSET 0x00000006lu
+
+
+/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
+
+#define APTB_PRIO_OFFSET 0x00000000lu
+#define APTB_DST_OFFSET 0x00000002lu
+#define APTB_LEN_OFFSET 0x00000004lu
+#define APTB_SRC_OFFSET 0x00000006lu
+#define APTB_DATA_OFFSET 0x00000008lu
+
+
+/* Remote Read Buffer (RRDB) Address Offsets */
+
+#define RRDB_WADDR_OFFSET 0x00000100lu
+#define RRDB_WLEN_OFFSET 0x00000101lu
+
+
+
+/* ************ CONTROLLER AREA NETWORK (CAN) MASKS ***************/
+/* CAN_CONTROL Masks */
+#define SRS 0x0001 /* Software Reset */
+#define DNM 0x0002 /* Device Net Mode */
+#define ABO 0x0004 /* Auto-Bus On Enable */
+#define WBA 0x0010 /* Wake-Up On CAN Bus Activity Enable */
+#define SMR 0x0020 /* Sleep Mode Request */
+#define CSR 0x0040 /* CAN Suspend Mode Request */
+#define CCR 0x0080 /* CAN Configuration Mode Request */
+
+/* CAN_STATUS Masks */
+#define WT 0x0001 /* TX Warning Flag */
+#define WR 0x0002 /* RX Warning Flag */
+#define EP 0x0004 /* Error Passive Mode */
+#define EBO 0x0008 /* Error Bus Off Mode */
+#define CSA 0x0040 /* Suspend Mode Acknowledge */
+#define CCA 0x0080 /* Configuration Mode Acknowledge */
+#define MBPTR 0x1F00 /* Mailbox Pointer */
+#define TRM 0x4000 /* Transmit Mode */
+#define REC 0x8000 /* Receive Mode */
+
+/* CAN_CLOCK Masks */
+#define BRP 0x03FF /* Bit-Rate Pre-Scaler */
+
+/* CAN_TIMING Masks */
+#define TSEG1 0x000F /* Time Segment 1 */
+#define TSEG2 0x0070 /* Time Segment 2 */
+#define SAM 0x0080 /* Sampling */
+#define SJW 0x0300 /* Synchronization Jump Width */
+
+/* CAN_DEBUG Masks */
+#define DEC 0x0001 /* Disable CAN Error Counters */
+#define DRI 0x0002 /* Disable CAN RX Input */
+#define DTO 0x0004 /* Disable CAN TX Output */
+#define DIL 0x0008 /* Disable CAN Internal Loop */
+#define MAA 0x0010 /* Mode Auto-Acknowledge Enable */
+#define MRB 0x0020 /* Mode Read Back Enable */
+#define CDE 0x8000 /* CAN Debug Enable */
+
+/* CAN_CEC Masks */
+#define RXECNT 0x00FF /* Receive Error Counter */
+#define TXECNT 0xFF00 /* Transmit Error Counter */
+
+/* CAN_INTR Masks */
+#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
+#define MBRIF MBRIRQ /* legacy */
+#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
+#define MBTIF MBTIRQ /* legacy */
+#define GIRQ 0x0004 /* Global Interrupt */
+#define SMACK 0x0008 /* Sleep Mode Acknowledge */
+#define CANTX 0x0040 /* CAN TX Bus Value */
+#define CANRX 0x0080 /* CAN RX Bus Value */
+
+/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks */
+#define DFC 0xFFFF /* Data Filtering Code (If Enabled) (ID0) */
+#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (ID0) */
+#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (ID1) */
+#define BASEID 0x1FFC /* Base Identifier */
+#define IDE 0x2000 /* Identifier Extension */
+#define RTR 0x4000 /* Remote Frame Transmission Request */
+#define AME 0x8000 /* Acceptance Mask Enable */
+
+/* CAN_MBxx_TIMESTAMP Masks */
+#define TSV 0xFFFF /* Timestamp */
+
+/* CAN_MBxx_LENGTH Masks */
+#define DLC 0x000F /* Data Length Code */
+
+/* CAN_AMxxH and CAN_AMxxL Masks */
+#define DFM 0xFFFF /* Data Field Mask (If Enabled) (CAN_AMxxL) */
+#define EXTID_LO 0xFFFF /* Lower 16 Bits of Extended Identifier (CAN_AMxxL) */
+#define EXTID_HI 0x0003 /* Upper 2 Bits of Extended Identifier (CAN_AMxxH) */
+#define BASEID 0x1FFC /* Base Identifier */
+#define AMIDE 0x2000 /* Acceptance Mask ID Extension Enable */
+#define FMD 0x4000 /* Full Mask Data Field Enable */
+#define FDF 0x8000 /* Filter On Data Field Enable */
+
+/* CAN_MC1 Masks */
+#define MC0 0x0001 /* Enable Mailbox 0 */
+#define MC1 0x0002 /* Enable Mailbox 1 */
+#define MC2 0x0004 /* Enable Mailbox 2 */
+#define MC3 0x0008 /* Enable Mailbox 3 */
+#define MC4 0x0010 /* Enable Mailbox 4 */
+#define MC5 0x0020 /* Enable Mailbox 5 */
+#define MC6 0x0040 /* Enable Mailbox 6 */
+#define MC7 0x0080 /* Enable Mailbox 7 */
+#define MC8 0x0100 /* Enable Mailbox 8 */
+#define MC9 0x0200 /* Enable Mailbox 9 */
+#define MC10 0x0400 /* Enable Mailbox 10 */
+#define MC11 0x0800 /* Enable Mailbox 11 */
+#define MC12 0x1000 /* Enable Mailbox 12 */
+#define MC13 0x2000 /* Enable Mailbox 13 */
+#define MC14 0x4000 /* Enable Mailbox 14 */
+#define MC15 0x8000 /* Enable Mailbox 15 */
+
+/* CAN_MC2 Masks */
+#define MC16 0x0001 /* Enable Mailbox 16 */
+#define MC17 0x0002 /* Enable Mailbox 17 */
+#define MC18 0x0004 /* Enable Mailbox 18 */
+#define MC19 0x0008 /* Enable Mailbox 19 */
+#define MC20 0x0010 /* Enable Mailbox 20 */
+#define MC21 0x0020 /* Enable Mailbox 21 */
+#define MC22 0x0040 /* Enable Mailbox 22 */
+#define MC23 0x0080 /* Enable Mailbox 23 */
+#define MC24 0x0100 /* Enable Mailbox 24 */
+#define MC25 0x0200 /* Enable Mailbox 25 */
+#define MC26 0x0400 /* Enable Mailbox 26 */
+#define MC27 0x0800 /* Enable Mailbox 27 */
+#define MC28 0x1000 /* Enable Mailbox 28 */
+#define MC29 0x2000 /* Enable Mailbox 29 */
+#define MC30 0x4000 /* Enable Mailbox 30 */
+#define MC31 0x8000 /* Enable Mailbox 31 */
+
+/* CAN_MD1 Masks */
+#define MD0 0x0001 /* Enable Mailbox 0 For Receive */
+#define MD1 0x0002 /* Enable Mailbox 1 For Receive */
+#define MD2 0x0004 /* Enable Mailbox 2 For Receive */
+#define MD3 0x0008 /* Enable Mailbox 3 For Receive */
+#define MD4 0x0010 /* Enable Mailbox 4 For Receive */
+#define MD5 0x0020 /* Enable Mailbox 5 For Receive */
+#define MD6 0x0040 /* Enable Mailbox 6 For Receive */
+#define MD7 0x0080 /* Enable Mailbox 7 For Receive */
+#define MD8 0x0100 /* Enable Mailbox 8 For Receive */
+#define MD9 0x0200 /* Enable Mailbox 9 For Receive */
+#define MD10 0x0400 /* Enable Mailbox 10 For Receive */
+#define MD11 0x0800 /* Enable Mailbox 11 For Receive */
+#define MD12 0x1000 /* Enable Mailbox 12 For Receive */
+#define MD13 0x2000 /* Enable Mailbox 13 For Receive */
+#define MD14 0x4000 /* Enable Mailbox 14 For Receive */
+#define MD15 0x8000 /* Enable Mailbox 15 For Receive */
+
+/* CAN_MD2 Masks */
+#define MD16 0x0001 /* Enable Mailbox 16 For Receive */
+#define MD17 0x0002 /* Enable Mailbox 17 For Receive */
+#define MD18 0x0004 /* Enable Mailbox 18 For Receive */
+#define MD19 0x0008 /* Enable Mailbox 19 For Receive */
+#define MD20 0x0010 /* Enable Mailbox 20 For Receive */
+#define MD21 0x0020 /* Enable Mailbox 21 For Receive */
+#define MD22 0x0040 /* Enable Mailbox 22 For Receive */
+#define MD23 0x0080 /* Enable Mailbox 23 For Receive */
+#define MD24 0x0100 /* Enable Mailbox 24 For Receive */
+#define MD25 0x0200 /* Enable Mailbox 25 For Receive */
+#define MD26 0x0400 /* Enable Mailbox 26 For Receive */
+#define MD27 0x0800 /* Enable Mailbox 27 For Receive */
+#define MD28 0x1000 /* Enable Mailbox 28 For Receive */
+#define MD29 0x2000 /* Enable Mailbox 29 For Receive */
+#define MD30 0x4000 /* Enable Mailbox 30 For Receive */
+#define MD31 0x8000 /* Enable Mailbox 31 For Receive */
+
+/* CAN_RMP1 Masks */
+#define RMP0 0x0001 /* RX Message Pending In Mailbox 0 */
+#define RMP1 0x0002 /* RX Message Pending In Mailbox 1 */
+#define RMP2 0x0004 /* RX Message Pending In Mailbox 2 */
+#define RMP3 0x0008 /* RX Message Pending In Mailbox 3 */
+#define RMP4 0x0010 /* RX Message Pending In Mailbox 4 */
+#define RMP5 0x0020 /* RX Message Pending In Mailbox 5 */
+#define RMP6 0x0040 /* RX Message Pending In Mailbox 6 */
+#define RMP7 0x0080 /* RX Message Pending In Mailbox 7 */
+#define RMP8 0x0100 /* RX Message Pending In Mailbox 8 */
+#define RMP9 0x0200 /* RX Message Pending In Mailbox 9 */
+#define RMP10 0x0400 /* RX Message Pending In Mailbox 10 */
+#define RMP11 0x0800 /* RX Message Pending In Mailbox 11 */
+#define RMP12 0x1000 /* RX Message Pending In Mailbox 12 */
+#define RMP13 0x2000 /* RX Message Pending In Mailbox 13 */
+#define RMP14 0x4000 /* RX Message Pending In Mailbox 14 */
+#define RMP15 0x8000 /* RX Message Pending In Mailbox 15 */
+
+/* CAN_RMP2 Masks */
+#define RMP16 0x0001 /* RX Message Pending In Mailbox 16 */
+#define RMP17 0x0002 /* RX Message Pending In Mailbox 17 */
+#define RMP18 0x0004 /* RX Message Pending In Mailbox 18 */
+#define RMP19 0x0008 /* RX Message Pending In Mailbox 19 */
+#define RMP20 0x0010 /* RX Message Pending In Mailbox 20 */
+#define RMP21 0x0020 /* RX Message Pending In Mailbox 21 */
+#define RMP22 0x0040 /* RX Message Pending In Mailbox 22 */
+#define RMP23 0x0080 /* RX Message Pending In Mailbox 23 */
+#define RMP24 0x0100 /* RX Message Pending In Mailbox 24 */
+#define RMP25 0x0200 /* RX Message Pending In Mailbox 25 */
+#define RMP26 0x0400 /* RX Message Pending In Mailbox 26 */
+#define RMP27 0x0800 /* RX Message Pending In Mailbox 27 */
+#define RMP28 0x1000 /* RX Message Pending In Mailbox 28 */
+#define RMP29 0x2000 /* RX Message Pending In Mailbox 29 */
+#define RMP30 0x4000 /* RX Message Pending In Mailbox 30 */
+#define RMP31 0x8000 /* RX Message Pending In Mailbox 31 */
+
+/* CAN_RML1 Masks */
+#define RML0 0x0001 /* RX Message Lost In Mailbox 0 */
+#define RML1 0x0002 /* RX Message Lost In Mailbox 1 */
+#define RML2 0x0004 /* RX Message Lost In Mailbox 2 */
+#define RML3 0x0008 /* RX Message Lost In Mailbox 3 */
+#define RML4 0x0010 /* RX Message Lost In Mailbox 4 */
+#define RML5 0x0020 /* RX Message Lost In Mailbox 5 */
+#define RML6 0x0040 /* RX Message Lost In Mailbox 6 */
+#define RML7 0x0080 /* RX Message Lost In Mailbox 7 */
+#define RML8 0x0100 /* RX Message Lost In Mailbox 8 */
+#define RML9 0x0200 /* RX Message Lost In Mailbox 9 */
+#define RML10 0x0400 /* RX Message Lost In Mailbox 10 */
+#define RML11 0x0800 /* RX Message Lost In Mailbox 11 */
+#define RML12 0x1000 /* RX Message Lost In Mailbox 12 */
+#define RML13 0x2000 /* RX Message Lost In Mailbox 13 */
+#define RML14 0x4000 /* RX Message Lost In Mailbox 14 */
+#define RML15 0x8000 /* RX Message Lost In Mailbox 15 */
+
+/* CAN_RML2 Masks */
+#define RML16 0x0001 /* RX Message Lost In Mailbox 16 */
+#define RML17 0x0002 /* RX Message Lost In Mailbox 17 */
+#define RML18 0x0004 /* RX Message Lost In Mailbox 18 */
+#define RML19 0x0008 /* RX Message Lost In Mailbox 19 */
+#define RML20 0x0010 /* RX Message Lost In Mailbox 20 */
+#define RML21 0x0020 /* RX Message Lost In Mailbox 21 */
+#define RML22 0x0040 /* RX Message Lost In Mailbox 22 */
+#define RML23 0x0080 /* RX Message Lost In Mailbox 23 */
+#define RML24 0x0100 /* RX Message Lost In Mailbox 24 */
+#define RML25 0x0200 /* RX Message Lost In Mailbox 25 */
+#define RML26 0x0400 /* RX Message Lost In Mailbox 26 */
+#define RML27 0x0800 /* RX Message Lost In Mailbox 27 */
+#define RML28 0x1000 /* RX Message Lost In Mailbox 28 */
+#define RML29 0x2000 /* RX Message Lost In Mailbox 29 */
+#define RML30 0x4000 /* RX Message Lost In Mailbox 30 */
+#define RML31 0x8000 /* RX Message Lost In Mailbox 31 */
+
+/* CAN_OPSS1 Masks */
+#define OPSS0 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0 */
+#define OPSS1 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1 */
+#define OPSS2 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2 */
+#define OPSS3 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3 */
+#define OPSS4 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4 */
+#define OPSS5 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5 */
+#define OPSS6 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6 */
+#define OPSS7 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7 */
+#define OPSS8 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8 */
+#define OPSS9 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9 */
+#define OPSS10 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10 */
+#define OPSS11 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11 */
+#define OPSS12 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12 */
+#define OPSS13 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13 */
+#define OPSS14 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14 */
+#define OPSS15 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15 */
+
+/* CAN_OPSS2 Masks */
+#define OPSS16 0x0001 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16 */
+#define OPSS17 0x0002 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17 */
+#define OPSS18 0x0004 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18 */
+#define OPSS19 0x0008 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19 */
+#define OPSS20 0x0010 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20 */
+#define OPSS21 0x0020 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21 */
+#define OPSS22 0x0040 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22 */
+#define OPSS23 0x0080 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23 */
+#define OPSS24 0x0100 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24 */
+#define OPSS25 0x0200 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25 */
+#define OPSS26 0x0400 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26 */
+#define OPSS27 0x0800 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27 */
+#define OPSS28 0x1000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28 */
+#define OPSS29 0x2000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29 */
+#define OPSS30 0x4000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30 */
+#define OPSS31 0x8000 /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31 */
+
+/* CAN_TRR1 Masks */
+#define TRR0 0x0001 /* Deny But Don't Lock Access To Mailbox 0 */
+#define TRR1 0x0002 /* Deny But Don't Lock Access To Mailbox 1 */
+#define TRR2 0x0004 /* Deny But Don't Lock Access To Mailbox 2 */
+#define TRR3 0x0008 /* Deny But Don't Lock Access To Mailbox 3 */
+#define TRR4 0x0010 /* Deny But Don't Lock Access To Mailbox 4 */
+#define TRR5 0x0020 /* Deny But Don't Lock Access To Mailbox 5 */
+#define TRR6 0x0040 /* Deny But Don't Lock Access To Mailbox 6 */
+#define TRR7 0x0080 /* Deny But Don't Lock Access To Mailbox 7 */
+#define TRR8 0x0100 /* Deny But Don't Lock Access To Mailbox 8 */
+#define TRR9 0x0200 /* Deny But Don't Lock Access To Mailbox 9 */
+#define TRR10 0x0400 /* Deny But Don't Lock Access To Mailbox 10 */
+#define TRR11 0x0800 /* Deny But Don't Lock Access To Mailbox 11 */
+#define TRR12 0x1000 /* Deny But Don't Lock Access To Mailbox 12 */
+#define TRR13 0x2000 /* Deny But Don't Lock Access To Mailbox 13 */
+#define TRR14 0x4000 /* Deny But Don't Lock Access To Mailbox 14 */
+#define TRR15 0x8000 /* Deny But Don't Lock Access To Mailbox 15 */
+
+/* CAN_TRR2 Masks */
+#define TRR16 0x0001 /* Deny But Don't Lock Access To Mailbox 16 */
+#define TRR17 0x0002 /* Deny But Don't Lock Access To Mailbox 17 */
+#define TRR18 0x0004 /* Deny But Don't Lock Access To Mailbox 18 */
+#define TRR19 0x0008 /* Deny But Don't Lock Access To Mailbox 19 */
+#define TRR20 0x0010 /* Deny But Don't Lock Access To Mailbox 20 */
+#define TRR21 0x0020 /* Deny But Don't Lock Access To Mailbox 21 */
+#define TRR22 0x0040 /* Deny But Don't Lock Access To Mailbox 22 */
+#define TRR23 0x0080 /* Deny But Don't Lock Access To Mailbox 23 */
+#define TRR24 0x0100 /* Deny But Don't Lock Access To Mailbox 24 */
+#define TRR25 0x0200 /* Deny But Don't Lock Access To Mailbox 25 */
+#define TRR26 0x0400 /* Deny But Don't Lock Access To Mailbox 26 */
+#define TRR27 0x0800 /* Deny But Don't Lock Access To Mailbox 27 */
+#define TRR28 0x1000 /* Deny But Don't Lock Access To Mailbox 28 */
+#define TRR29 0x2000 /* Deny But Don't Lock Access To Mailbox 29 */
+#define TRR30 0x4000 /* Deny But Don't Lock Access To Mailbox 30 */
+#define TRR31 0x8000 /* Deny But Don't Lock Access To Mailbox 31 */
+
+/* CAN_TRS1 Masks */
+#define TRS0 0x0001 /* Remote Frame Request For Mailbox 0 */
+#define TRS1 0x0002 /* Remote Frame Request For Mailbox 1 */
+#define TRS2 0x0004 /* Remote Frame Request For Mailbox 2 */
+#define TRS3 0x0008 /* Remote Frame Request For Mailbox 3 */
+#define TRS4 0x0010 /* Remote Frame Request For Mailbox 4 */
+#define TRS5 0x0020 /* Remote Frame Request For Mailbox 5 */
+#define TRS6 0x0040 /* Remote Frame Request For Mailbox 6 */
+#define TRS7 0x0080 /* Remote Frame Request For Mailbox 7 */
+#define TRS8 0x0100 /* Remote Frame Request For Mailbox 8 */
+#define TRS9 0x0200 /* Remote Frame Request For Mailbox 9 */
+#define TRS10 0x0400 /* Remote Frame Request For Mailbox 10 */
+#define TRS11 0x0800 /* Remote Frame Request For Mailbox 11 */
+#define TRS12 0x1000 /* Remote Frame Request For Mailbox 12 */
+#define TRS13 0x2000 /* Remote Frame Request For Mailbox 13 */
+#define TRS14 0x4000 /* Remote Frame Request For Mailbox 14 */
+#define TRS15 0x8000 /* Remote Frame Request For Mailbox 15 */
+
+/* CAN_TRS2 Masks */
+#define TRS16 0x0001 /* Remote Frame Request For Mailbox 16 */
+#define TRS17 0x0002 /* Remote Frame Request For Mailbox 17 */
+#define TRS18 0x0004 /* Remote Frame Request For Mailbox 18 */
+#define TRS19 0x0008 /* Remote Frame Request For Mailbox 19 */
+#define TRS20 0x0010 /* Remote Frame Request For Mailbox 20 */
+#define TRS21 0x0020 /* Remote Frame Request For Mailbox 21 */
+#define TRS22 0x0040 /* Remote Frame Request For Mailbox 22 */
+#define TRS23 0x0080 /* Remote Frame Request For Mailbox 23 */
+#define TRS24 0x0100 /* Remote Frame Request For Mailbox 24 */
+#define TRS25 0x0200 /* Remote Frame Request For Mailbox 25 */
+#define TRS26 0x0400 /* Remote Frame Request For Mailbox 26 */
+#define TRS27 0x0800 /* Remote Frame Request For Mailbox 27 */
+#define TRS28 0x1000 /* Remote Frame Request For Mailbox 28 */
+#define TRS29 0x2000 /* Remote Frame Request For Mailbox 29 */
+#define TRS30 0x4000 /* Remote Frame Request For Mailbox 30 */
+#define TRS31 0x8000 /* Remote Frame Request For Mailbox 31 */
+
+/* CAN_AA1 Masks */
+#define AA0 0x0001 /* Aborted Message In Mailbox 0 */
+#define AA1 0x0002 /* Aborted Message In Mailbox 1 */
+#define AA2 0x0004 /* Aborted Message In Mailbox 2 */
+#define AA3 0x0008 /* Aborted Message In Mailbox 3 */
+#define AA4 0x0010 /* Aborted Message In Mailbox 4 */
+#define AA5 0x0020 /* Aborted Message In Mailbox 5 */
+#define AA6 0x0040 /* Aborted Message In Mailbox 6 */
+#define AA7 0x0080 /* Aborted Message In Mailbox 7 */
+#define AA8 0x0100 /* Aborted Message In Mailbox 8 */
+#define AA9 0x0200 /* Aborted Message In Mailbox 9 */
+#define AA10 0x0400 /* Aborted Message In Mailbox 10 */
+#define AA11 0x0800 /* Aborted Message In Mailbox 11 */
+#define AA12 0x1000 /* Aborted Message In Mailbox 12 */
+#define AA13 0x2000 /* Aborted Message In Mailbox 13 */
+#define AA14 0x4000 /* Aborted Message In Mailbox 14 */
+#define AA15 0x8000 /* Aborted Message In Mailbox 15 */
+
+/* CAN_AA2 Masks */
+#define AA16 0x0001 /* Aborted Message In Mailbox 16 */
+#define AA17 0x0002 /* Aborted Message In Mailbox 17 */
+#define AA18 0x0004 /* Aborted Message In Mailbox 18 */
+#define AA19 0x0008 /* Aborted Message In Mailbox 19 */
+#define AA20 0x0010 /* Aborted Message In Mailbox 20 */
+#define AA21 0x0020 /* Aborted Message In Mailbox 21 */
+#define AA22 0x0040 /* Aborted Message In Mailbox 22 */
+#define AA23 0x0080 /* Aborted Message In Mailbox 23 */
+#define AA24 0x0100 /* Aborted Message In Mailbox 24 */
+#define AA25 0x0200 /* Aborted Message In Mailbox 25 */
+#define AA26 0x0400 /* Aborted Message In Mailbox 26 */
+#define AA27 0x0800 /* Aborted Message In Mailbox 27 */
+#define AA28 0x1000 /* Aborted Message In Mailbox 28 */
+#define AA29 0x2000 /* Aborted Message In Mailbox 29 */
+#define AA30 0x4000 /* Aborted Message In Mailbox 30 */
+#define AA31 0x8000 /* Aborted Message In Mailbox 31 */
+
+/* CAN_TA1 Masks */
+#define TA0 0x0001 /* Transmit Successful From Mailbox 0 */
+#define TA1 0x0002 /* Transmit Successful From Mailbox 1 */
+#define TA2 0x0004 /* Transmit Successful From Mailbox 2 */
+#define TA3 0x0008 /* Transmit Successful From Mailbox 3 */
+#define TA4 0x0010 /* Transmit Successful From Mailbox 4 */
+#define TA5 0x0020 /* Transmit Successful From Mailbox 5 */
+#define TA6 0x0040 /* Transmit Successful From Mailbox 6 */
+#define TA7 0x0080 /* Transmit Successful From Mailbox 7 */
+#define TA8 0x0100 /* Transmit Successful From Mailbox 8 */
+#define TA9 0x0200 /* Transmit Successful From Mailbox 9 */
+#define TA10 0x0400 /* Transmit Successful From Mailbox 10 */
+#define TA11 0x0800 /* Transmit Successful From Mailbox 11 */
+#define TA12 0x1000 /* Transmit Successful From Mailbox 12 */
+#define TA13 0x2000 /* Transmit Successful From Mailbox 13 */
+#define TA14 0x4000 /* Transmit Successful From Mailbox 14 */
+#define TA15 0x8000 /* Transmit Successful From Mailbox 15 */
+
+/* CAN_TA2 Masks */
+#define TA16 0x0001 /* Transmit Successful From Mailbox 16 */
+#define TA17 0x0002 /* Transmit Successful From Mailbox 17 */
+#define TA18 0x0004 /* Transmit Successful From Mailbox 18 */
+#define TA19 0x0008 /* Transmit Successful From Mailbox 19 */
+#define TA20 0x0010 /* Transmit Successful From Mailbox 20 */
+#define TA21 0x0020 /* Transmit Successful From Mailbox 21 */
+#define TA22 0x0040 /* Transmit Successful From Mailbox 22 */
+#define TA23 0x0080 /* Transmit Successful From Mailbox 23 */
+#define TA24 0x0100 /* Transmit Successful From Mailbox 24 */
+#define TA25 0x0200 /* Transmit Successful From Mailbox 25 */
+#define TA26 0x0400 /* Transmit Successful From Mailbox 26 */
+#define TA27 0x0800 /* Transmit Successful From Mailbox 27 */
+#define TA28 0x1000 /* Transmit Successful From Mailbox 28 */
+#define TA29 0x2000 /* Transmit Successful From Mailbox 29 */
+#define TA30 0x4000 /* Transmit Successful From Mailbox 30 */
+#define TA31 0x8000 /* Transmit Successful From Mailbox 31 */
+
+/* CAN_MBTD Masks */
+#define TDPTR 0x001F /* Mailbox To Temporarily Disable */
+#define TDA 0x0040 /* Temporary Disable Acknowledge */
+#define TDR 0x0080 /* Temporary Disable Request */
+
+/* CAN_RFH1 Masks */
+#define RFH0 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 0 */
+#define RFH1 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 1 */
+#define RFH2 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 2 */
+#define RFH3 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 3 */
+#define RFH4 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 4 */
+#define RFH5 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 5 */
+#define RFH6 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 6 */
+#define RFH7 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 7 */
+#define RFH8 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 8 */
+#define RFH9 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 9 */
+#define RFH10 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 10 */
+#define RFH11 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 11 */
+#define RFH12 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 12 */
+#define RFH13 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 13 */
+#define RFH14 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 14 */
+#define RFH15 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 15 */
+
+/* CAN_RFH2 Masks */
+#define RFH16 0x0001 /* Enable Automatic Remote Frame Handling For Mailbox 16 */
+#define RFH17 0x0002 /* Enable Automatic Remote Frame Handling For Mailbox 17 */
+#define RFH18 0x0004 /* Enable Automatic Remote Frame Handling For Mailbox 18 */
+#define RFH19 0x0008 /* Enable Automatic Remote Frame Handling For Mailbox 19 */
+#define RFH20 0x0010 /* Enable Automatic Remote Frame Handling For Mailbox 20 */
+#define RFH21 0x0020 /* Enable Automatic Remote Frame Handling For Mailbox 21 */
+#define RFH22 0x0040 /* Enable Automatic Remote Frame Handling For Mailbox 22 */
+#define RFH23 0x0080 /* Enable Automatic Remote Frame Handling For Mailbox 23 */
+#define RFH24 0x0100 /* Enable Automatic Remote Frame Handling For Mailbox 24 */
+#define RFH25 0x0200 /* Enable Automatic Remote Frame Handling For Mailbox 25 */
+#define RFH26 0x0400 /* Enable Automatic Remote Frame Handling For Mailbox 26 */
+#define RFH27 0x0800 /* Enable Automatic Remote Frame Handling For Mailbox 27 */
+#define RFH28 0x1000 /* Enable Automatic Remote Frame Handling For Mailbox 28 */
+#define RFH29 0x2000 /* Enable Automatic Remote Frame Handling For Mailbox 29 */
+#define RFH30 0x4000 /* Enable Automatic Remote Frame Handling For Mailbox 30 */
+#define RFH31 0x8000 /* Enable Automatic Remote Frame Handling For Mailbox 31 */
+
+/* CAN_MBTIF1 Masks */
+#define MBTIF0 0x0001 /* TX Interrupt Active In Mailbox 0 */
+#define MBTIF1 0x0002 /* TX Interrupt Active In Mailbox 1 */
+#define MBTIF2 0x0004 /* TX Interrupt Active In Mailbox 2 */
+#define MBTIF3 0x0008 /* TX Interrupt Active In Mailbox 3 */
+#define MBTIF4 0x0010 /* TX Interrupt Active In Mailbox 4 */
+#define MBTIF5 0x0020 /* TX Interrupt Active In Mailbox 5 */
+#define MBTIF6 0x0040 /* TX Interrupt Active In Mailbox 6 */
+#define MBTIF7 0x0080 /* TX Interrupt Active In Mailbox 7 */
+#define MBTIF8 0x0100 /* TX Interrupt Active In Mailbox 8 */
+#define MBTIF9 0x0200 /* TX Interrupt Active In Mailbox 9 */
+#define MBTIF10 0x0400 /* TX Interrupt Active In Mailbox 10 */
+#define MBTIF11 0x0800 /* TX Interrupt Active In Mailbox 11 */
+#define MBTIF12 0x1000 /* TX Interrupt Active In Mailbox 12 */
+#define MBTIF13 0x2000 /* TX Interrupt Active In Mailbox 13 */
+#define MBTIF14 0x4000 /* TX Interrupt Active In Mailbox 14 */
+#define MBTIF15 0x8000 /* TX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBTIF2 Masks */
+#define MBTIF16 0x0001 /* TX Interrupt Active In Mailbox 16 */
+#define MBTIF17 0x0002 /* TX Interrupt Active In Mailbox 17 */
+#define MBTIF18 0x0004 /* TX Interrupt Active In Mailbox 18 */
+#define MBTIF19 0x0008 /* TX Interrupt Active In Mailbox 19 */
+#define MBTIF20 0x0010 /* TX Interrupt Active In Mailbox 20 */
+#define MBTIF21 0x0020 /* TX Interrupt Active In Mailbox 21 */
+#define MBTIF22 0x0040 /* TX Interrupt Active In Mailbox 22 */
+#define MBTIF23 0x0080 /* TX Interrupt Active In Mailbox 23 */
+#define MBTIF24 0x0100 /* TX Interrupt Active In Mailbox 24 */
+#define MBTIF25 0x0200 /* TX Interrupt Active In Mailbox 25 */
+#define MBTIF26 0x0400 /* TX Interrupt Active In Mailbox 26 */
+#define MBTIF27 0x0800 /* TX Interrupt Active In Mailbox 27 */
+#define MBTIF28 0x1000 /* TX Interrupt Active In Mailbox 28 */
+#define MBTIF29 0x2000 /* TX Interrupt Active In Mailbox 29 */
+#define MBTIF30 0x4000 /* TX Interrupt Active In Mailbox 30 */
+#define MBTIF31 0x8000 /* TX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBRIF1 Masks */
+#define MBRIF0 0x0001 /* RX Interrupt Active In Mailbox 0 */
+#define MBRIF1 0x0002 /* RX Interrupt Active In Mailbox 1 */
+#define MBRIF2 0x0004 /* RX Interrupt Active In Mailbox 2 */
+#define MBRIF3 0x0008 /* RX Interrupt Active In Mailbox 3 */
+#define MBRIF4 0x0010 /* RX Interrupt Active In Mailbox 4 */
+#define MBRIF5 0x0020 /* RX Interrupt Active In Mailbox 5 */
+#define MBRIF6 0x0040 /* RX Interrupt Active In Mailbox 6 */
+#define MBRIF7 0x0080 /* RX Interrupt Active In Mailbox 7 */
+#define MBRIF8 0x0100 /* RX Interrupt Active In Mailbox 8 */
+#define MBRIF9 0x0200 /* RX Interrupt Active In Mailbox 9 */
+#define MBRIF10 0x0400 /* RX Interrupt Active In Mailbox 10 */
+#define MBRIF11 0x0800 /* RX Interrupt Active In Mailbox 11 */
+#define MBRIF12 0x1000 /* RX Interrupt Active In Mailbox 12 */
+#define MBRIF13 0x2000 /* RX Interrupt Active In Mailbox 13 */
+#define MBRIF14 0x4000 /* RX Interrupt Active In Mailbox 14 */
+#define MBRIF15 0x8000 /* RX Interrupt Active In Mailbox 15 */
+
+/* CAN_MBRIF2 Masks */
+#define MBRIF16 0x0001 /* RX Interrupt Active In Mailbox 16 */
+#define MBRIF17 0x0002 /* RX Interrupt Active In Mailbox 17 */
+#define MBRIF18 0x0004 /* RX Interrupt Active In Mailbox 18 */
+#define MBRIF19 0x0008 /* RX Interrupt Active In Mailbox 19 */
+#define MBRIF20 0x0010 /* RX Interrupt Active In Mailbox 20 */
+#define MBRIF21 0x0020 /* RX Interrupt Active In Mailbox 21 */
+#define MBRIF22 0x0040 /* RX Interrupt Active In Mailbox 22 */
+#define MBRIF23 0x0080 /* RX Interrupt Active In Mailbox 23 */
+#define MBRIF24 0x0100 /* RX Interrupt Active In Mailbox 24 */
+#define MBRIF25 0x0200 /* RX Interrupt Active In Mailbox 25 */
+#define MBRIF26 0x0400 /* RX Interrupt Active In Mailbox 26 */
+#define MBRIF27 0x0800 /* RX Interrupt Active In Mailbox 27 */
+#define MBRIF28 0x1000 /* RX Interrupt Active In Mailbox 28 */
+#define MBRIF29 0x2000 /* RX Interrupt Active In Mailbox 29 */
+#define MBRIF30 0x4000 /* RX Interrupt Active In Mailbox 30 */
+#define MBRIF31 0x8000 /* RX Interrupt Active In Mailbox 31 */
+
+/* CAN_MBIM1 Masks */
+#define MBIM0 0x0001 /* Enable Interrupt For Mailbox 0 */
+#define MBIM1 0x0002 /* Enable Interrupt For Mailbox 1 */
+#define MBIM2 0x0004 /* Enable Interrupt For Mailbox 2 */
+#define MBIM3 0x0008 /* Enable Interrupt For Mailbox 3 */
+#define MBIM4 0x0010 /* Enable Interrupt For Mailbox 4 */
+#define MBIM5 0x0020 /* Enable Interrupt For Mailbox 5 */
+#define MBIM6 0x0040 /* Enable Interrupt For Mailbox 6 */
+#define MBIM7 0x0080 /* Enable Interrupt For Mailbox 7 */
+#define MBIM8 0x0100 /* Enable Interrupt For Mailbox 8 */
+#define MBIM9 0x0200 /* Enable Interrupt For Mailbox 9 */
+#define MBIM10 0x0400 /* Enable Interrupt For Mailbox 10 */
+#define MBIM11 0x0800 /* Enable Interrupt For Mailbox 11 */
+#define MBIM12 0x1000 /* Enable Interrupt For Mailbox 12 */
+#define MBIM13 0x2000 /* Enable Interrupt For Mailbox 13 */
+#define MBIM14 0x4000 /* Enable Interrupt For Mailbox 14 */
+#define MBIM15 0x8000 /* Enable Interrupt For Mailbox 15 */
+
+/* CAN_MBIM2 Masks */
+#define MBIM16 0x0001 /* Enable Interrupt For Mailbox 16 */
+#define MBIM17 0x0002 /* Enable Interrupt For Mailbox 17 */
+#define MBIM18 0x0004 /* Enable Interrupt For Mailbox 18 */
+#define MBIM19 0x0008 /* Enable Interrupt For Mailbox 19 */
+#define MBIM20 0x0010 /* Enable Interrupt For Mailbox 20 */
+#define MBIM21 0x0020 /* Enable Interrupt For Mailbox 21 */
+#define MBIM22 0x0040 /* Enable Interrupt For Mailbox 22 */
+#define MBIM23 0x0080 /* Enable Interrupt For Mailbox 23 */
+#define MBIM24 0x0100 /* Enable Interrupt For Mailbox 24 */
+#define MBIM25 0x0200 /* Enable Interrupt For Mailbox 25 */
+#define MBIM26 0x0400 /* Enable Interrupt For Mailbox 26 */
+#define MBIM27 0x0800 /* Enable Interrupt For Mailbox 27 */
+#define MBIM28 0x1000 /* Enable Interrupt For Mailbox 28 */
+#define MBIM29 0x2000 /* Enable Interrupt For Mailbox 29 */
+#define MBIM30 0x4000 /* Enable Interrupt For Mailbox 30 */
+#define MBIM31 0x8000 /* Enable Interrupt For Mailbox 31 */
+
+/* CAN_GIM Masks */
+#define EWTIM 0x0001 /* Enable TX Error Count Interrupt */
+#define EWRIM 0x0002 /* Enable RX Error Count Interrupt */
+#define EPIM 0x0004 /* Enable Error-Passive Mode Interrupt */
+#define BOIM 0x0008 /* Enable Bus Off Interrupt */
+#define WUIM 0x0010 /* Enable Wake-Up Interrupt */
+#define UIAIM 0x0020 /* Enable Access To Unimplemented Address Interrupt */
+#define AAIM 0x0040 /* Enable Abort Acknowledge Interrupt */
+#define RMLIM 0x0080 /* Enable RX Message Lost Interrupt */
+#define UCEIM 0x0100 /* Enable Universal Counter Overflow Interrupt */
+#define EXTIM 0x0200 /* Enable External Trigger Output Interrupt */
+#define ADIM 0x0400 /* Enable Access Denied Interrupt */
+
+/* CAN_GIS Masks */
+#define EWTIS 0x0001 /* TX Error Count IRQ Status */
+#define EWRIS 0x0002 /* RX Error Count IRQ Status */
+#define EPIS 0x0004 /* Error-Passive Mode IRQ Status */
+#define BOIS 0x0008 /* Bus Off IRQ Status */
+#define WUIS 0x0010 /* Wake-Up IRQ Status */
+#define UIAIS 0x0020 /* Access To Unimplemented Address IRQ Status */
+#define AAIS 0x0040 /* Abort Acknowledge IRQ Status */
+#define RMLIS 0x0080 /* RX Message Lost IRQ Status */
+#define UCEIS 0x0100 /* Universal Counter Overflow IRQ Status */
+#define EXTIS 0x0200 /* External Trigger Output IRQ Status */
+#define ADIS 0x0400 /* Access Denied IRQ Status */
+
+/* CAN_GIF Masks */
+#define EWTIF 0x0001 /* TX Error Count IRQ Flag */
+#define EWRIF 0x0002 /* RX Error Count IRQ Flag */
+#define EPIF 0x0004 /* Error-Passive Mode IRQ Flag */
+#define BOIF 0x0008 /* Bus Off IRQ Flag */
+#define WUIF 0x0010 /* Wake-Up IRQ Flag */
+#define UIAIF 0x0020 /* Access To Unimplemented Address IRQ Flag */
+#define AAIF 0x0040 /* Abort Acknowledge IRQ Flag */
+#define RMLIF 0x0080 /* RX Message Lost IRQ Flag */
+#define UCEIF 0x0100 /* Universal Counter Overflow IRQ Flag */
+#define EXTIF 0x0200 /* External Trigger Output IRQ Flag */
+#define ADIF 0x0400 /* Access Denied IRQ Flag */
+
+/* CAN_UCCNF Masks */
+#define UCCNF 0x000F /* Universal Counter Mode */
+#define UC_STAMP 0x0001 /* Timestamp Mode */
+#define UC_WDOG 0x0002 /* Watchdog Mode */
+#define UC_AUTOTX 0x0003 /* Auto-Transmit Mode */
+#define UC_ERROR 0x0006 /* CAN Error Frame Count */
+#define UC_OVER 0x0007 /* CAN Overload Frame Count */
+#define UC_LOST 0x0008 /* Arbitration Lost During TX Count */
+#define UC_AA 0x0009 /* TX Abort Count */
+#define UC_TA 0x000A /* TX Successful Count */
+#define UC_REJECT 0x000B /* RX Message Rejected Count */
+#define UC_RML 0x000C /* RX Message Lost Count */
+#define UC_RX 0x000D /* Total Successful RX Messages Count */
+#define UC_RMP 0x000E /* Successful RX W/Matching ID Count */
+#define UC_ALL 0x000F /* Correct Message On CAN Bus Line Count */
+#define UCRC 0x0020 /* Universal Counter Reload/Clear */
+#define UCCT 0x0040 /* Universal Counter CAN Trigger */
+#define UCE 0x0080 /* Universal Counter Enable */
+
+/* CAN_ESR Masks */
+#define ACKE 0x0004 /* Acknowledge Error */
+#define SER 0x0008 /* Stuff Error */
+#define CRCE 0x0010 /* CRC Error */
+#define SA0 0x0020 /* Stuck At Dominant Error */
+#define BEF 0x0040 /* Bit Error Flag */
+#define FER 0x0080 /* Form Error Flag */
+
+/* CAN_EWR Masks */
+#define EWLREC 0x00FF /* RX Error Count Limit (For EWRIS) */
+#define EWLTEC 0xFF00 /* TX Error Count Limit (For EWTIS) */
+
+
+
+#endif /* _DEF_BF539_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF541.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation for the ADSP-BF541 peripherals.
+**
+**/
+#ifndef _DEF_BF541_H
+#define _DEF_BF541_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/** ADSP-BF541 is a non-existent processor -- no additional #defines **/
+
+#define CHIPID 0xffc00014
+
+#endif /* _DEF_BF541_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF542.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF542_H
+#define _DEF_BF542_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
+
+/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include <defBF54x_base.h>
+
+/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
+
+/* ATAPI Registers */
+
+#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
+#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
+
+/* SDH Registers */
+
+#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
+#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
+#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
+#define SDH_COMMAND 0xffc0390c /* SDH Command */
+#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
+#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
+#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
+#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
+#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
+#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
+#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
+#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
+#define SDH_STATUS 0xffc03934 /* SDH Status */
+#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
+#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
+#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
+#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
+#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
+#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
+#define SDH_CFG 0xffc039c8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
+#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
+#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
+#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
+#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
+#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
+#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
+#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
+#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
+
+/* USB Control Registers */
+
+#define USB_FADDR 0xffc03c00 /* Function address register */
+#define USB_POWER 0xffc03c04 /* Power management register */
+#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
+#define USB_FRAME 0xffc03c20 /* USB frame number */
+#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+
+/* USB Endpoint 1 Control Registers */
+
+#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+
+/* USB Endpoint 2 Control Registers */
+
+#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+
+/* USB Endpoint 3 Control Registers */
+
+#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+
+/* USB Endpoint 4 Control Registers */
+
+#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+
+/* USB Endpoint 5 Control Registers */
+
+#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+
+/* USB Endpoint 6 Control Registers */
+
+#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+
+/* USB Endpoint 7 Control Registers */
+
+#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
+#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
+#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
+#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
+#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
+#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
+#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
+#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
+#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Keypad Registers */
+
+#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
+
+
+/* ********************************************************** */
+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
+/* and MULTI BIT READ MACROS */
+/* ********************************************************** */
+
+/* Bit masks for KPAD_CTL */
+
+#define KPAD_EN 0x1 /* Keypad Enable */
+#define nKPAD_EN 0x0
+#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
+#define nKPAD_IRQMODE 0x0 /* Interrupt Disabled */
+#define KPAD_IRQMODE_SK 0x2 /* Single key (single row, single column) press interrupt enable */
+#define KPAD_IRQMODE_MK 0x4 /* Single key press multiple key press interrupt enable */
+
+#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
+#define KPAD_COLEN 0xe000 /* Column Enable Width */
+
+#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
+#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+
+/* Bit masks for KPAD_PRESCALE */
+
+#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
+
+#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale) Key Prescale Value (5:0) */
+
+/* Bit masks for KPAD_MSEL */
+
+#define DBON_SCALE 0xff /* Debounce Scale Value */
+#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
+
+/* Bit masks for KPAD_ROWCOL */
+
+#define KPAD_ROW 0xff /* Rows Pressed */
+#define KPAD_COL 0xff00 /* Columns Pressed */
+
+#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale) Debounce Delay Multiplier Select [7:0] */
+#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale) Column Driver Period Multiplier Select [15:8] */
+
+/* Bit masks for KPAD_STAT */
+
+#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
+#define nKPAD_IRQ 0x0
+#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
+#define KPAD_PRESSED 0x8 /* Key press current status */
+#define nKPAD_PRESSED 0x0
+#define KPAD_NO_KEY 0x0 /* No Keypress Status*/
+#define KPAD_SINGLE_KEY 0x2 /* Single Keypress Status */
+#define KPAD_MKSROWCOL 0x4 /* Multiple Keypress in the same row or column Status */
+#define KPAD_MKMROWCOL 0x6 /* Multiple Keypress in the same multiple rows and multiple columns Status */
+
+/* Bit masks for KPAD_SOFTEVAL */
+
+#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
+#define nKPAD_SOFTEVAL_E 0x0
+
+/* Bit masks for SDH_COMMAND */
+
+#define CMD_IDX 0x3f /* Command Index */
+#define CMD_RSP 0x40 /* Response */
+#define nCMD_RSP 0x0
+#define CMD_L_RSP 0x80 /* Long Response */
+#define nCMD_L_RSP 0x0
+#define CMD_INT_E 0x100 /* Command Interrupt */
+#define nCMD_INT_E 0x0
+#define CMD_PEND_E 0x200 /* Command Pending */
+#define nCMD_PEND_E 0x0
+#define CMD_E 0x400 /* Command Enable */
+#define nCMD_E 0x0
+
+/* Bit masks for SDH_PWR_CTL */
+
+#define PWR_ON 0x3 /* Power On */
+#if 0
+#define TBD 0x3c /* TBD */
+#endif
+#define SD_CMD_OD 0x40 /* Open Drain Output */
+#define nSD_CMD_OD 0x0
+#define ROD_CTL 0x80 /* Rod Control */
+#define nROD_CTL 0x0
+
+/* Bit masks for SDH_CLK_CTL */
+
+#define CLKDIV 0xff /* MC_CLK Divisor */
+#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
+#define nCLK_E 0x0
+#define PWR_SV_E 0x200 /* Power Save Enable */
+#define nPWR_SV_E 0x0
+#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
+#define nCLKDIV_BYPASS 0x0
+#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
+#define nWIDE_BUS 0x0
+
+/* Bit masks for SDH_RESP_CMD */
+
+#define RESP_CMD 0x3f /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+
+#define DTX_E 0x1 /* Data Transfer Enable */
+#define nDTX_E 0x0
+#define DTX_DIR 0x2 /* Data Transfer Direction */
+#define nDTX_DIR 0x0
+#define DTX_MODE 0x4 /* Data Transfer Mode */
+#define nDTX_MODE 0x0
+#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
+#define nDTX_DMA_E 0x0
+#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+
+#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
+#define nCMD_CRC_FAIL 0x0
+#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
+#define nDAT_CRC_FAIL 0x0
+#define CMD_TIMEOUT 0x4 /* CMD Time Out */
+#define nCMD_TIMEOUT 0x0
+#define DAT_TIMEOUT 0x8 /* Data Time Out */
+#define nDAT_TIMEOUT 0x0
+#define TX_UNDERRUN 0x10 /* Transmit Underrun */
+#define nTX_UNDERRUN 0x0
+#define RX_OVERRUN 0x20 /* Receive Overrun */
+#define nRX_OVERRUN 0x0
+#define CMD_RESP_END 0x40 /* CMD Response End */
+#define nCMD_RESP_END 0x0
+#define CMD_SENT 0x80 /* CMD Sent */
+#define nCMD_SENT 0x0
+#define DAT_END 0x100 /* Data End */
+#define nDAT_END 0x0
+#define START_BIT_ERR 0x200 /* Start Bit Error */
+#define nSTART_BIT_ERR 0x0
+#define DAT_BLK_END 0x400 /* Data Block End */
+#define nDAT_BLK_END 0x0
+#define CMD_ACT 0x800 /* CMD Active */
+#define nCMD_ACT 0x0
+#define TX_ACT 0x1000 /* Transmit Active */
+#define nTX_ACT 0x0
+#define RX_ACT 0x2000 /* Receive Active */
+#define nRX_ACT 0x0
+#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
+#define nTX_FIFO_STAT 0x0
+#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
+#define nRX_FIFO_STAT 0x0
+#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
+#define nTX_FIFO_FULL 0x0
+#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
+#define nRX_FIFO_FULL 0x0
+#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
+#define nTX_FIFO_ZERO 0x0
+#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
+#define nRX_DAT_ZERO 0x0
+#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
+#define nTX_DAT_RDY 0x0
+#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
+#define nRX_FIFO_RDY 0x0
+
+/* Bit masks for SDH_STATUS_CLR */
+
+#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
+#define nCMD_CRC_FAIL_STAT 0x0
+#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
+#define nDAT_CRC_FAIL_STAT 0x0
+#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
+#define nCMD_TIMEOUT_STAT 0x0
+#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
+#define nDAT_TIMEOUT_STAT 0x0
+#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
+#define nTX_UNDERRUN_STAT 0x0
+#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
+#define nRX_OVERRUN_STAT 0x0
+#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
+#define nCMD_RESP_END_STAT 0x0
+#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
+#define nCMD_SENT_STAT 0x0
+#define DAT_END_STAT 0x100 /* Data End Status */
+#define nDAT_END_STAT 0x0
+#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
+#define nSTART_BIT_ERR_STAT 0x0
+#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
+#define nDAT_BLK_END_STAT 0x0
+
+/* Bit masks for SDH_MASK0 */
+
+#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
+#define nCMD_CRC_FAIL_MASK 0x0
+#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
+#define nDAT_CRC_FAIL_MASK 0x0
+#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
+#define nCMD_TIMEOUT_MASK 0x0
+#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
+#define nDAT_TIMEOUT_MASK 0x0
+#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
+#define nTX_UNDERRUN_MASK 0x0
+#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
+#define nRX_OVERRUN_MASK 0x0
+#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
+#define nCMD_RESP_END_MASK 0x0
+#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
+#define nCMD_SENT_MASK 0x0
+#define DAT_END_MASK 0x100 /* Data End Mask */
+#define nDAT_END_MASK 0x0
+#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
+#define nSTART_BIT_ERR_MASK 0x0
+#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
+#define nDAT_BLK_END_MASK 0x0
+#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
+#define nCMD_ACT_MASK 0x0
+#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
+#define nTX_ACT_MASK 0x0
+#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
+#define nRX_ACT_MASK 0x0
+#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
+#define nTX_FIFO_STAT_MASK 0x0
+#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
+#define nRX_FIFO_STAT_MASK 0x0
+#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
+#define nTX_FIFO_FULL_MASK 0x0
+#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
+#define nRX_FIFO_FULL_MASK 0x0
+#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
+#define nTX_FIFO_ZERO_MASK 0x0
+#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
+#define nRX_DAT_ZERO_MASK 0x0
+#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
+#define nTX_DAT_RDY_MASK 0x0
+#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
+#define nRX_FIFO_RDY_MASK 0x0
+
+/* Bit masks for SDH_FIFO_CNT */
+
+#define FIFO_COUNT 0x7fff /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+
+#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
+#define nSDIO_INT_DET 0x0
+#define SD_CARD_DET 0x10 /* SD Card Detect */
+#define nSD_CARD_DET 0x0
+
+/* Bit masks for SDH_E_MASK */
+
+#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
+#define nSDIO_MSK 0x0
+#define SCD_MSK 0x40 /* Mask Card Detect */
+#define nSCD_MSK 0x0
+
+/* Bit masks for SDH_CFG */
+
+#define CLKS_EN 0x1 /* Clocks Enable */
+#define nCLKS_EN 0x0
+#define SD4E 0x4 /* SDIO 4-Bit Enable */
+#define nSD4E 0x0
+#define MWE 0x8 /* Moving Window Enable */
+#define nMWE 0x0
+#define SD_RST 0x10 /* SDMMC Reset */
+#define nSD_RST 0x0
+#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
+#define nPUP_SDDAT 0x0
+#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
+#define nPUP_SDDAT3 0x0
+#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
+#define nPD_SDDAT3 0x0
+
+/* Bit masks for SDH_RD_WAIT_EN */
+
+#define RWR 0x1 /* Read Wait Request */
+#define nRWR 0x0
+
+/* Bit masks for ATAPI_CONTROL */
+
+#define PIO_START 0x1 /* Start PIO/Reg Op */
+#define nPIO_START 0x0
+#define MULTI_START 0x2 /* Start Multi-DMA Op */
+#define nMULTI_START 0x0
+#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
+#define nULTRA_START 0x0
+#define XFER_DIR 0x8 /* Transfer Direction */
+#define nXFER_DIR 0x0
+#define IORDY_EN 0x10 /* IORDY Enable */
+#define nIORDY_EN 0x0
+#define FIFO_FLUSH 0x20 /* Flush FIFOs */
+#define nFIFO_FLUSH 0x0
+#define SOFT_RST 0x40 /* Soft Reset */
+#define nSOFT_RST 0x0
+#define DEV_RST 0x80 /* Device Reset */
+#define nDEV_RST 0x0
+#define TFRCNT_RST 0x100 /* Trans Count Reset */
+#define nTFRCNT_RST 0x0
+#define END_ON_TERM 0x200 /* End/Terminate Select */
+#define nEND_ON_TERM 0x0
+#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
+#define nPIO_USE_DMA 0x0
+#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+
+#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
+#define nPIO_XFER_ON 0x0
+#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
+#define nMULTI_XFER_ON 0x0
+#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
+#define nULTRA_XFER_ON 0x0
+#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+
+#define DEV_ADDR 0x1f /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+
+#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
+#define nATAPI_DEV_INT_MASK 0x0
+#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
+#define nPIO_DONE_MASK 0x0
+#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
+#define nMULTI_DONE_MASK 0x0
+#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
+#define nUDMAIN_DONE_MASK 0x0
+#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
+#define nUDMAOUT_DONE_MASK 0x0
+#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
+#define nHOST_TERM_XFER_MASK 0x0
+#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
+#define nMULTI_TERM_MASK 0x0
+#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define nUDMAIN_TERM_MASK 0x0
+#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
+#define nUDMAOUT_TERM_MASK 0x0
+
+/* Bit masks for ATAPI_INT_STATUS */
+
+#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
+#define nATAPI_DEV_INT 0x0
+#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
+#define nPIO_DONE_INT 0x0
+#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
+#define nMULTI_DONE_INT 0x0
+#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
+#define nUDMAIN_DONE_INT 0x0
+#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
+#define nUDMAOUT_DONE_INT 0x0
+#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
+#define nHOST_TERM_XFER_INT 0x0
+#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
+#define nMULTI_TERM_INT 0x0
+#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define nUDMAIN_TERM_INT 0x0
+#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
+#define nUDMAOUT_TERM_INT 0x0
+
+/* Bit masks for ATAPI_LINE_STATUS */
+
+#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
+#define nATAPI_INTR 0x0
+#define ATAPI_DASP 0x2 /* Device dasp to host line status */
+#define nATAPI_DASP 0x0
+#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
+#define nATAPI_CS0N 0x0
+#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
+#define nATAPI_CS1N 0x0
+#define ATAPI_ADDR 0x70 /* ATAPI address line status */
+#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
+#define nATAPI_DMAREQ 0x0
+#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
+#define nATAPI_DMAACKN 0x0
+#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
+#define nATAPI_DIOWN 0x0
+#define ATAPI_DIORN 0x400 /* ATAPI read line status */
+#define nATAPI_DIORN 0x0
+#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
+#define nATAPI_IORDY 0x0
+
+/* Bit masks for ATAPI_SM_STATE */
+
+#define PIO_CSTATE 0xf /* PIO mode state machine current state */
+#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
+#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
+#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+
+#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
+#define nATAPI_HOST_TERM 0x0
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+
+#define T2_REG 0xff /* End of cycle time for register access transfers */
+#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+
+#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
+#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
+#define T4_REG 0xf000 /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+
+#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+
+#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
+#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+
+#define TKW 0xff /* Selects DIOW negated pulsewidth */
+#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+
+#define TH 0xff /* Selects DIOW data hold */
+#define TEOC 0xff00 /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+
+#define TACK 0xff /* Selects setup and hold times for TACK */
+#define TENV 0xff00 /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+
+#define TDVS 0xff /* Selects data valid setup time */
+#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+
+#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define TMLI 0xff00 /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+
+#define TZAH 0xff /* Selects minimum delay required for output */
+#define READY_PAUSE 0xff00 /* Selects ready to pause */
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS 0x7f /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
+#define nENABLE_SUSPENDM 0x0
+#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
+#define nSUSPEND_MODE 0x0
+#define RESUME_MODE 0x4 /* DMA Mode */
+#define nRESUME_MODE 0x0
+#define RESET 0x8 /* Reset indicator */
+#define nRESET 0x0
+#define HS_MODE 0x10 /* High Speed mode indicator */
+#define nHS_MODE 0x0
+#define HS_ENABLE 0x20 /* high Speed Enable */
+#define nHS_ENABLE 0x0
+#define SOFT_CONN 0x40 /* Soft connect */
+#define nSOFT_CONN 0x0
+#define ISO_UPDATE 0x80 /* Isochronous update */
+#define nISO_UPDATE 0x0
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
+#define nEP0_TX 0x0
+#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
+#define nEP1_TX 0x0
+#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
+#define nEP2_TX 0x0
+#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
+#define nEP3_TX 0x0
+#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
+#define nEP4_TX 0x0
+#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
+#define nEP5_TX 0x0
+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
+#define nEP6_TX 0x0
+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
+#define nEP7_TX 0x0
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
+#define nEP1_RX 0x0
+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
+#define nEP2_RX 0x0
+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
+#define nEP3_RX 0x0
+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
+#define nEP4_RX 0x0
+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
+#define nEP5_RX 0x0
+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
+#define nEP6_RX 0x0
+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
+#define nEP7_RX 0x0
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
+#define nEP0_TX_E 0x0
+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
+#define nEP1_TX_E 0x0
+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
+#define nEP2_TX_E 0x0
+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
+#define nEP3_TX_E 0x0
+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
+#define nEP4_TX_E 0x0
+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
+#define nEP5_TX_E 0x0
+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
+#define nEP6_TX_E 0x0
+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
+#define nEP7_TX_E 0x0
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
+#define nEP1_RX_E 0x0
+#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
+#define nEP2_RX_E 0x0
+#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
+#define nEP3_RX_E 0x0
+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
+#define nEP4_RX_E 0x0
+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
+#define nEP5_RX_E 0x0
+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
+#define nEP6_RX_E 0x0
+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
+#define nEP7_RX_E 0x0
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B 0x1 /* Suspend indicator */
+#define nSUSPEND_B 0x0
+#define RESUME_B 0x2 /* Resume indicator */
+#define nRESUME_B 0x0
+#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
+#define nRESET_OR_BABLE_B 0x0
+#define SOF_B 0x8 /* Start of frame */
+#define nSOF_B 0x0
+#define CONN_B 0x10 /* Connection indicator */
+#define nCONN_B 0x0
+#define DISCON_B 0x20 /* Disconnect indicator */
+#define nDISCON_B 0x0
+#define SESSION_REQ_B 0x40 /* Session Request */
+#define nSESSION_REQ_B 0x0
+#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
+#define nVBUS_ERROR_B 0x0
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
+#define nSUSPEND_BE 0x0
+#define RESUME_BE 0x2 /* Resume indicator int enable */
+#define nRESUME_BE 0x0
+#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
+#define nRESET_OR_BABLE_BE 0x0
+#define SOF_BE 0x8 /* Start of frame int enable */
+#define nSOF_BE 0x0
+#define CONN_BE 0x10 /* Connection indicator int enable */
+#define nCONN_BE 0x0
+#define DISCON_BE 0x20 /* Disconnect indicator int enable */
+#define nDISCON_BE 0x0
+#define SESSION_REQ_BE 0x40 /* Session Request int enable */
+#define nSESSION_REQ_BE 0x0
+#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
+#define nVBUS_ERROR_BE 0x0
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER 0x7ff /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT 0xf /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA 0x1 /* enables USB module */
+#define nGLOBAL_ENA 0x0
+#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
+#define nEP1_TX_ENA 0x0
+#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
+#define nEP2_TX_ENA 0x0
+#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
+#define nEP3_TX_ENA 0x0
+#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
+#define nEP4_TX_ENA 0x0
+#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
+#define nEP5_TX_ENA 0x0
+#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
+#define nEP6_TX_ENA 0x0
+#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
+#define nEP7_TX_ENA 0x0
+#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
+#define nEP1_RX_ENA 0x0
+#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
+#define nEP2_RX_ENA 0x0
+#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
+#define nEP3_RX_ENA 0x0
+#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
+#define nEP4_RX_ENA 0x0
+#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
+#define nEP5_RX_ENA 0x0
+#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
+#define nEP6_RX_ENA 0x0
+#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
+#define nEP7_RX_ENA 0x0
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION 0x1 /* session indicator */
+#define nSESSION 0x0
+#define HOST_REQ 0x2 /* Host negotiation request */
+#define nHOST_REQ 0x0
+#define HOST_MODE 0x4 /* indicates USBDRC is a host */
+#define nHOST_MODE 0x0
+#define VBUS0 0x8 /* Vbus level indicator[0] */
+#define nVBUS0 0x0
+#define VBUS1 0x10 /* Vbus level indicator[1] */
+#define nVBUS1 0x0
+#define LSDEV 0x20 /* Low-speed indicator */
+#define nLSDEV 0x0
+#define FSDEV 0x40 /* Full or High-speed indicator */
+#define nFSDEV 0x0
+#define B_DEVICE 0x80 /* A' or 'B' device indicator */
+#define nB_DEVICE 0x0
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
+#define nDRIVE_VBUS_ON 0x0
+#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
+#define nDRIVE_VBUS_OFF 0x0
+#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
+#define nCHRG_VBUS_START 0x0
+#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
+#define nCHRG_VBUS_END 0x0
+#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
+#define nDISCHRG_VBUS_START 0x0
+#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
+#define nDISCHRG_VBUS_END 0x0
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
+#define nDRIVE_VBUS_ON_ENA 0x0
+#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
+#define nDRIVE_VBUS_OFF_ENA 0x0
+#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
+#define nCHRG_VBUS_START_ENA 0x0
+#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
+#define nCHRG_VBUS_END_ENA 0x0
+#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
+#define nDISCHRG_VBUS_START_ENA 0x0
+#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
+#define nDISCHRG_VBUS_END_ENA 0x0
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY 0x1 /* data packet receive indicator */
+#define nRXPKTRDY 0x0
+#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
+#define nTXPKTRDY 0x0
+#define STALL_SENT 0x4 /* STALL handshake sent */
+#define nSTALL_SENT 0x0
+#define DATAEND 0x8 /* Data end indicator */
+#define nDATAEND 0x0
+#define SETUPEND 0x10 /* Setup end */
+#define nSETUPEND 0x0
+#define SENDSTALL 0x20 /* Send STALL handshake */
+#define nSENDSTALL 0x0
+#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
+#define nSERVICED_RXPKTRDY 0x0
+#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
+#define nSERVICED_SETUPEND 0x0
+#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
+#define nFLUSHFIFO 0x0
+#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
+#define nSTALL_RECEIVED_H 0x0
+#define SETUPPKT_H 0x8 /* send Setup token host mode */
+#define nSETUPPKT_H 0x0
+#define ERROR_H 0x10 /* timeout error indicator host mode */
+#define nERROR_H 0x0
+#define REQPKT_H 0x20 /* Request an IN transaction host mode */
+#define nREQPKT_H 0x0
+#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
+#define nSTATUSPKT_H 0x0
+#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
+#define nNAK_TIMEOUT_H 0x0
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
+#define nTXPKTRDY_T 0x0
+#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
+#define nFIFO_NOT_EMPTY_T 0x0
+#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
+#define nUNDERRUN_T 0x0
+#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
+#define nFLUSHFIFO_T 0x0
+#define STALL_SEND_T 0x10 /* issue a Stall handshake */
+#define nSTALL_SEND_T 0x0
+#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
+#define nSTALL_SENT_T 0x0
+#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_T 0x0
+#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
+#define nINCOMPTX_T 0x0
+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_T 0x0
+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
+#define nFORCE_DATATOGGLE_T 0x0
+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_T 0x0
+#define ISO_T 0x4000 /* enable Isochronous transfers */
+#define nISO_T 0x0
+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOSET_T 0x0
+#define ERROR_TH 0x4 /* error condition host mode */
+#define nERROR_TH 0x0
+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_TH 0x0
+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
+#define nNAK_TIMEOUT_TH 0x0
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
+#define nRXPKTRDY_R 0x0
+#define FIFO_FULL_R 0x2 /* FIFO not empty */
+#define nFIFO_FULL_R 0x0
+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
+#define nOVERRUN_R 0x0
+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
+#define nDATAERROR_R 0x0
+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
+#define nFLUSHFIFO_R 0x0
+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
+#define nSTALL_SEND_R 0x0
+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
+#define nSTALL_SENT_R 0x0
+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_R 0x0
+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
+#define nINCOMPRX_R 0x0
+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_R 0x0
+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
+#define nDISNYET_R 0x0
+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_R 0x0
+#define ISO_R 0x4000 /* enable Isochronous transfers */
+#define nISO_R 0x0
+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOCLEAR_R 0x0
+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
+#define nERROR_RH 0x0
+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
+#define nREQPKT_RH 0x0
+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_RH 0x0
+#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
+#define nINCOMPRX_RH 0x0
+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
+#define nDMAREQMODE_RH 0x0
+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
+#define nAUTOREQ_RH 0x0
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T 0xf /* EP number */
+#define PROTOCOL_T 0xc /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R 0xf /* EP number */
+#define PROTOCOL_R 0xc /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
+#define nDMA0_INT 0x0
+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
+#define nDMA1_INT 0x0
+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
+#define nDMA2_INT 0x0
+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
+#define nDMA3_INT 0x0
+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
+#define nDMA4_INT 0x0
+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
+#define nDMA5_INT 0x0
+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
+#define nDMA6_INT 0x0
+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
+#define nDMA7_INT 0x0
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA 0x1 /* DMA enable */
+#define nDMA_ENA 0x0
+#define DIRECTION 0x2 /* direction of DMA transfer */
+#define nDIRECTION 0x0
+#define MODE 0x4 /* DMA Bus error */
+#define nMODE 0x0
+#define INT_ENA 0x8 /* Interrupt enable */
+#define nINT_ENA 0x0
+#define EPNUM 0xf0 /* EP number */
+#define BUSERROR 0x100 /* DMA Bus error */
+#define nBUSERROR 0x0
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+
+/* ******************************************* */
+/* MULTI BIT MACRO ENUMERATIONS */
+/* ******************************************* */
+
+
+#endif /* _DEF_BF542_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF544.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF544_H
+#define _DEF_BF544_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
+
+/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include <defBF54x_base.h>
+
+/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
+
+/* Timer Registers */
+
+#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
+#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
+#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
+
+/* Timer Group of 3 Registers */
+
+#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
+
+/* EPPI0 Registers */
+
+#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
+#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
+#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
+#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
+#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
+#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
+#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
+#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
+#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
+#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+
+/* CAN Controller 1 Clock/Interrupt/Counter Registers */
+
+#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
+#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
+#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
+#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
+#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
+#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
+#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
+#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
+#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
+#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
+#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
+#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
+#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
+#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
+#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
+#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
+#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
+#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
+#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
+#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
+#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
+#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
+#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
+#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
+#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
+#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
+#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
+#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
+#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
+#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
+#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
+#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
+#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
+#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
+#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
+#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
+#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
+#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
+#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
+#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
+#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
+#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
+#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
+#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
+#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
+#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
+
+/* HOST Port Registers */
+
+#define HOST_CONTROL 0xffc03a00 /* HOSTDP Control Register */
+#define HOST_STATUS 0xffc03a04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT 0xffc03a08 /* HOSTDP Acknowledge Mode Timeout Register */
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
+#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
+#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
+
+/* ********************************************************** */
+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
+/* and MULTI BIT READ MACROS */
+/* ********************************************************** */
+
+/* Bit masks for PIXC_CTL */
+
+#define PIXC_EN 0x1 /* Pixel Compositor Enable */
+#define nPIXC_EN 0x0
+#define OVR_A_EN 0x2 /* Overlay A Enable */
+#define nOVR_A_EN 0x0
+#define OVR_B_EN 0x4 /* Overlay B Enable */
+#define nOVR_B_EN 0x0
+#define IMG_FORM 0x8 /* Image Data Format */
+#define nIMG_FORM 0x0
+#define OVR_FORM 0x10 /* Overlay Data Format */
+#define nOVR_FORM 0x0
+#define OUT_FORM 0x20 /* Output Data Format */
+#define nOUT_FORM 0x0
+#define UDS_MOD 0x40 /* Resampling Mode */
+#define nUDS_MOD 0x0
+#define TC_EN 0x80 /* Transparent Color Enable */
+#define nTC_EN 0x0
+#define IMG_STAT 0x300 /* Image FIFO Status */
+#define OVR_STAT 0xc00 /* Overlay FIFO Status */
+#define WM_LVL 0x3000 /* FIFO Watermark Level */
+
+/* Bit masks for PIXC_AHSTART */
+
+#define A_HSTART 0xfff /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_AHEND */
+
+#define A_HEND 0xfff /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_AVSTART */
+
+#define A_VSTART 0x3ff /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_AVEND */
+
+#define A_VEND 0x3ff /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_ATRANSP */
+
+#define A_TRANSP 0xf /* Transparency Value */
+
+/* Bit masks for PIXC_BHSTART */
+
+#define B_HSTART 0xfff /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_BHEND */
+
+#define B_HEND 0xfff /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_BVSTART */
+
+#define B_VSTART 0x3ff /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_BVEND */
+
+#define B_VEND 0x3ff /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_BTRANSP */
+
+#define B_TRANSP 0xf /* Transparency Value */
+
+/* Bit masks for PIXC_INTRSTAT */
+
+#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
+#define nOVR_INT_EN 0x0
+#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
+#define nFRM_INT_EN 0x0
+#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
+#define nOVR_INT_STAT 0x0
+#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
+#define nFRM_INT_STAT 0x0
+
+/* Bit masks for PIXC_RYCON */
+
+#define A11 0x3ff /* A11 in the Coefficient Matrix */
+#define A12 0xffc00 /* A12 in the Coefficient Matrix */
+#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
+#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nRY_MULT4 0x0
+
+/* Bit masks for PIXC_GUCON */
+
+#define A21 0x3ff /* A21 in the Coefficient Matrix */
+#define A22 0xffc00 /* A22 in the Coefficient Matrix */
+#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
+#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nGU_MULT4 0x0
+
+/* Bit masks for PIXC_BVCON */
+
+#define A31 0x3ff /* A31 in the Coefficient Matrix */
+#define A32 0xffc00 /* A32 in the Coefficient Matrix */
+#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
+#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nBV_MULT4 0x0
+
+/* Bit masks for PIXC_CCBIAS */
+
+#define A14 0x3ff /* A14 in the Bias Vector */
+#define A24 0xffc00 /* A24 in the Bias Vector */
+#define A34 0x3ff00000 /* A34 in the Bias Vector */
+
+/* Bit masks for PIXC_TC */
+
+#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
+#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
+#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
+
+/* Bit masks for HOST_CONTROL */
+
+#define HOSTDP_EN 0x1 /* HOSTDP Enable */
+#define nHOSTDP_EN 0x0
+#define HOSTDP_END 0x2 /* Host Endianess */
+#define nHOSTDP_END 0x0
+#define HOSTDP_DATA_SIZE 0x4 /* Data Size */
+#define nHOSTDP_DATA_SIZE 0x0
+#define HOSTDP_RST 0x8 /* HOSTDP Reset */
+#define nHOSTDP_RST 0x0
+#define HRDY_OVR 0x20 /* HRDY Override */
+#define nHRDY_OVR 0x0
+#define INT_MODE 0x40 /* Interrupt Mode */
+#define nINT_MODE 0x0
+#define BT_EN 0x80 /* Bus Timeout Enable */
+#define nBT_EN 0x0
+#define EHW 0x100 /* Enable Host Write */
+#define nEHW 0x0
+#define EHR 0x200 /* Enable Host Read */
+#define nEHR 0x0
+#define BDR 0x400 /* Burst DMA Requests */
+#define nBDR 0x0
+
+/* Bit masks for HOST_STATUS */
+
+#define DMA_RDY 0x1 /* DMA Ready */
+#define nDMA_RDY 0x0
+#define FIFOFULL 0x2 /* FIFO Full */
+#define nFIFOFULL 0x0
+#define FIFOEMPTY 0x4 /* FIFO Empty */
+#define nFIFOEMPTY 0x0
+#define DMA_CMPLT 0x8 /* DMA Complete */
+#define nDMA_CMPLT 0x0
+#define HSHK 0x10 /* Host Handshake */
+#define nHSHK 0x0
+#define HOSTDP_TOUT 0x20 /* HOSTDP Timeout */
+#define nHOSTDP_TOUT 0x0
+#define HIRQ 0x40 /* Host Interrupt Request */
+#define nHIRQ 0x0
+#define ALLOW_CNFG 0x80 /* Allow New Configuration */
+#define nALLOW_CNFG 0x0
+#define DMA_DIR 0x100 /* DMA Direction */
+#define nDMA_DIR 0x0
+#define BTE 0x200 /* Bus Timeout Enabled */
+#define nBTE 0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define COUNT_TIMEOUT 0x7ff /* HOSTDP Timeout count */
+
+/* Bit masks for TIMER_ENABLE1 */
+
+#define TIMEN8 0x1 /* Timer 8 Enable */
+#define nTIMEN8 0x0
+#define TIMEN9 0x2 /* Timer 9 Enable */
+#define nTIMEN9 0x0
+#define TIMEN10 0x4 /* Timer 10 Enable */
+#define nTIMEN10 0x0
+
+/* Bit masks for TIMER_DISABLE1 */
+
+#define TIMDIS8 0x1 /* Timer 8 Disable */
+#define nTIMDIS8 0x0
+#define TIMDIS9 0x2 /* Timer 9 Disable */
+#define nTIMDIS9 0x0
+#define TIMDIS10 0x4 /* Timer 10 Disable */
+#define nTIMDIS10 0x0
+
+/* Bit masks for TIMER_STATUS1 */
+
+#define TIMIL8 0x1 /* Timer 8 Interrupt */
+#define nTIMIL8 0x0
+#define TIMIL9 0x2 /* Timer 9 Interrupt */
+#define nTIMIL9 0x0
+#define TIMIL10 0x4 /* Timer 10 Interrupt */
+#define nTIMIL10 0x0
+#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
+#define nTOVF_ERR8 0x0
+#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
+#define nTOVF_ERR9 0x0
+#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
+#define nTOVF_ERR10 0x0
+#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
+#define nTRUN8 0x0
+#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
+#define nTRUN9 0x0
+#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
+#define nTRUN10 0x0
+
+/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
+
+/* ******************************************* */
+/* MULTI BIT MACRO ENUMERATIONS */
+/* ******************************************* */
+
+#endif /* _DEF_BF544_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF547.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF547_H
+#define _DEF_BF547_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF547 */
+
+/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include <defBF54x_base.h>
+
+/* The following are the #defines needed by ADSP-BF547 that are not in the common header */
+
+/* Timer Registers */
+
+#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
+#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
+#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
+
+/* Timer Group of 3 Registers */
+
+#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
+
+/* SPORT0 Registers */
+
+#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
+#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
+#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
+#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
+#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
+#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
+#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
+#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
+
+/* EPPI0 Registers */
+
+#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
+
+/* UART2 Registers */
+
+#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
+#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
+#define UART2_GCTL 0xffc02108 /* Global Control Register */
+#define UART2_LCR 0xffc0210c /* Line Control Register */
+#define UART2_MCR 0xffc02110 /* Modem Control Register */
+#define UART2_LSR 0xffc02114 /* Line Status Register */
+#define UART2_MSR 0xffc02118 /* Modem Status Register */
+#define UART2_SCR 0xffc0211c /* Scratch Register */
+#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
+#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
+#define UART2_THR 0xffc02128 /* Transmit Hold Register */
+#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
+#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
+
+/* SPI2 Registers */
+
+#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
+#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
+#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
+#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
+#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
+
+
+/* ATAPI Registers */
+
+#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
+#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
+
+/* SDH Registers */
+
+#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
+#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
+#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
+#define SDH_COMMAND 0xffc0390c /* SDH Command */
+#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
+#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
+#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
+#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
+#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
+#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
+#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
+#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
+#define SDH_STATUS 0xffc03934 /* SDH Status */
+#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
+#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
+#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
+#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
+#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
+#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
+#define SDH_CFG 0xffc039c8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
+#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
+#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
+#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
+#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
+#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
+#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
+#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
+#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
+
+/* HOST Port Registers */
+
+#define HOST_CONTROL 0xffc03a00 /* HOSTDP Control Register */
+#define HOST_STATUS 0xffc03a04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT 0xffc03a08 /* HOSTDP Acknowledge Mode Timeout Register */
+
+/* USB Control Registers */
+
+#define USB_FADDR 0xffc03c00 /* Function address register */
+#define USB_POWER 0xffc03c04 /* Power management register */
+#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
+#define USB_FRAME 0xffc03c20 /* USB frame number */
+#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+
+/* USB Endpoint 1 Control Registers */
+
+#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+
+/* USB Endpoint 2 Control Registers */
+
+#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+
+/* USB Endpoint 3 Control Registers */
+
+#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+
+/* USB Endpoint 4 Control Registers */
+
+#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+
+/* USB Endpoint 5 Control Registers */
+
+#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+
+/* USB Endpoint 6 Control Registers */
+
+#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+
+/* USB Endpoint 7 Control Registers */
+
+#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
+#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
+#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
+#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
+#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
+#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
+#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
+#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
+#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Keypad Registers */
+
+#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
+#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
+#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
+
+/* ********************************************************** */
+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
+/* and MULTI BIT READ MACROS */
+/* ********************************************************** */
+
+/* Bit masks for PIXC_CTL */
+
+#define PIXC_EN 0x1 /* Pixel Compositor Enable */
+#define nPIXC_EN 0x0
+#define OVR_A_EN 0x2 /* Overlay A Enable */
+#define nOVR_A_EN 0x0
+#define OVR_B_EN 0x4 /* Overlay B Enable */
+#define nOVR_B_EN 0x0
+#define IMG_FORM 0x8 /* Image Data Format */
+#define nIMG_FORM 0x0
+#define OVR_FORM 0x10 /* Overlay Data Format */
+#define nOVR_FORM 0x0
+#define OUT_FORM 0x20 /* Output Data Format */
+#define nOUT_FORM 0x0
+#define UDS_MOD 0x40 /* Resampling Mode */
+#define nUDS_MOD 0x0
+#define TC_EN 0x80 /* Transparent Color Enable */
+#define nTC_EN 0x0
+#define IMG_STAT 0x300 /* Image FIFO Status */
+#define OVR_STAT 0xc00 /* Overlay FIFO Status */
+#define WM_LVL 0x3000 /* FIFO Watermark Level */
+
+/* Bit masks for PIXC_AHSTART */
+
+#define A_HSTART 0xfff /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_AHEND */
+
+#define A_HEND 0xfff /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_AVSTART */
+
+#define A_VSTART 0x3ff /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_AVEND */
+
+#define A_VEND 0x3ff /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_ATRANSP */
+
+#define A_TRANSP 0xf /* Transparency Value */
+
+/* Bit masks for PIXC_BHSTART */
+
+#define B_HSTART 0xfff /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_BHEND */
+
+#define B_HEND 0xfff /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_BVSTART */
+
+#define B_VSTART 0x3ff /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_BVEND */
+
+#define B_VEND 0x3ff /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_BTRANSP */
+
+#define B_TRANSP 0xf /* Transparency Value */
+
+/* Bit masks for PIXC_INTRSTAT */
+
+#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
+#define nOVR_INT_EN 0x0
+#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
+#define nFRM_INT_EN 0x0
+#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
+#define nOVR_INT_STAT 0x0
+#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
+#define nFRM_INT_STAT 0x0
+
+/* Bit masks for PIXC_RYCON */
+
+#define A11 0x3ff /* A11 in the Coefficient Matrix */
+#define A12 0xffc00 /* A12 in the Coefficient Matrix */
+#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
+#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nRY_MULT4 0x0
+
+/* Bit masks for PIXC_GUCON */
+
+#define A21 0x3ff /* A21 in the Coefficient Matrix */
+#define A22 0xffc00 /* A22 in the Coefficient Matrix */
+#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
+#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nGU_MULT4 0x0
+
+/* Bit masks for PIXC_BVCON */
+
+#define A31 0x3ff /* A31 in the Coefficient Matrix */
+#define A32 0xffc00 /* A32 in the Coefficient Matrix */
+#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
+#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nBV_MULT4 0x0
+
+/* Bit masks for PIXC_CCBIAS */
+
+#define A14 0x3ff /* A14 in the Bias Vector */
+#define A24 0xffc00 /* A24 in the Bias Vector */
+#define A34 0x3ff00000 /* A34 in the Bias Vector */
+
+/* Bit masks for PIXC_TC */
+
+#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
+#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
+#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
+
+/* Bit masks for HOST_CONTROL */
+
+#define HOSTDP_EN 0x1 /* HOSTDP Enable */
+#define nHOSTDP_EN 0x0
+#define HOSTDP_END 0x2 /* Host Endianess */
+#define nHOSTDP_END 0x0
+#define HOSTDP_DATA_SIZE 0x4 /* Data Size */
+#define nHOSTDP_DATA_SIZE 0x0
+#define HOSTDP_RST 0x8 /* HOSTDP Reset */
+#define nHOSTDP_RST 0x0
+#define HRDY_OVR 0x20 /* HRDY Override */
+#define nHRDY_OVR 0x0
+#define INT_MODE 0x40 /* Interrupt Mode */
+#define nINT_MODE 0x0
+#define BT_EN 0x80 /* Bus Timeout Enable */
+#define nBT_EN 0x0
+#define EHW 0x100 /* Enable Host Write */
+#define nEHW 0x0
+#define EHR 0x200 /* Enable Host Read */
+#define nEHR 0x0
+#define BDR 0x400 /* Burst DMA Requests */
+#define nBDR 0x0
+
+/* Bit masks for HOST_STATUS */
+
+#define DMA_RDY 0x1 /* DMA Ready */
+#define nDMA_RDY 0x0
+#define FIFOFULL 0x2 /* FIFO Full */
+#define nFIFOFULL 0x0
+#define FIFOEMPTY 0x4 /* FIFO Empty */
+#define nFIFOEMPTY 0x0
+#define DMA_CMPLT 0x8 /* DMA Complete */
+#define nDMA_CMPLT 0x0
+#define HSHK 0x10 /* Host Handshake */
+#define nHSHK 0x0
+#define HOSTDP_TOUT 0x20 /* HOSTDP Timeout */
+#define nHOSTDP_TOUT 0x0
+#define HIRQ 0x40 /* Host Interrupt Request */
+#define nHIRQ 0x0
+#define ALLOW_CNFG 0x80 /* Allow New Configuration */
+#define nALLOW_CNFG 0x0
+#define DMA_DIR 0x100 /* DMA Direction */
+#define nDMA_DIR 0x0
+#define BTE 0x200 /* Bus Timeout Enabled */
+#define nBTE 0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define COUNT_TIMEOUT 0x7ff /* HOSTDP Timeout count */
+
+/* Bit masks for KPAD_CTL */
+
+#define KPAD_EN 0x1 /* Keypad Enable */
+#define nKPAD_EN 0x0
+#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
+#define nKPAD_IRQMODE 0x0 /* Interrupt Disabled */
+#define KPAD_IRQMODE_SK 0x2 /* Single key (single row, single column) press interrupt enable */
+#define KPAD_IRQMODE_MK 0x4 /* Single key press multiple key press interrupt enable */
+
+#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
+#define KPAD_COLEN 0xe000 /* Column Enable Width */
+
+#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
+#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+
+
+/* Bit masks for KPAD_PRESCALE */
+
+#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
+
+#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+
+
+/* Bit masks for KPAD_MSEL */
+
+#define DBON_SCALE 0xff /* Debounce Scale Value */
+#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
+
+#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
+#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+
+
+/* Bit masks for KPAD_ROWCOL */
+
+#define KPAD_ROW 0xff /* Rows Pressed */
+#define KPAD_COL 0xff00 /* Columns Pressed */
+
+/* Bit masks for KPAD_STAT */
+
+#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
+#define nKPAD_IRQ 0x0
+#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
+#define KPAD_PRESSED 0x8 /* Key press current status */
+#define nKPAD_PRESSED 0x0
+#define KPAD_NO_KEY 0x0 /* No Keypress Status*/
+#define KPAD_SINGLE_KEY 0x2 /* Single Keypress Status */
+#define KPAD_MKSROWCOL 0x4 /* Multiple Keypress in the same row or column Status */
+#define KPAD_MKMROWCOL 0x6 /* Multiple Keypress in the same multiple rows and multiple columns Status */
+
+/* Bit masks for KPAD_SOFTEVAL */
+
+#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
+#define nKPAD_SOFTEVAL_E 0x0
+
+/* Bit masks for SDH_COMMAND */
+
+#define CMD_IDX 0x3f /* Command Index */
+#define CMD_RSP 0x40 /* Response */
+#define nCMD_RSP 0x0
+#define CMD_L_RSP 0x80 /* Long Response */
+#define nCMD_L_RSP 0x0
+#define CMD_INT_E 0x100 /* Command Interrupt */
+#define nCMD_INT_E 0x0
+#define CMD_PEND_E 0x200 /* Command Pending */
+#define nCMD_PEND_E 0x0
+#define CMD_E 0x400 /* Command Enable */
+#define nCMD_E 0x0
+
+/* Bit masks for SDH_PWR_CTL */
+
+#define PWR_ON 0x3 /* Power On */
+#if 0
+#define TBD 0x3c /* TBD */
+#endif
+#define SD_CMD_OD 0x40 /* Open Drain Output */
+#define nSD_CMD_OD 0x0
+#define ROD_CTL 0x80 /* Rod Control */
+#define nROD_CTL 0x0
+
+/* Bit masks for SDH_CLK_CTL */
+
+#define CLKDIV 0xff /* MC_CLK Divisor */
+#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
+#define nCLK_E 0x0
+#define PWR_SV_E 0x200 /* Power Save Enable */
+#define nPWR_SV_E 0x0
+#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
+#define nCLKDIV_BYPASS 0x0
+#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
+#define nWIDE_BUS 0x0
+
+/* Bit masks for SDH_RESP_CMD */
+
+#define RESP_CMD 0x3f /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+
+#define DTX_E 0x1 /* Data Transfer Enable */
+#define nDTX_E 0x0
+#define DTX_DIR 0x2 /* Data Transfer Direction */
+#define nDTX_DIR 0x0
+#define DTX_MODE 0x4 /* Data Transfer Mode */
+#define nDTX_MODE 0x0
+#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
+#define nDTX_DMA_E 0x0
+#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+
+#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
+#define nCMD_CRC_FAIL 0x0
+#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
+#define nDAT_CRC_FAIL 0x0
+#define CMD_TIMEOUT 0x4 /* CMD Time Out */
+#define nCMD_TIMEOUT 0x0
+#define DAT_TIMEOUT 0x8 /* Data Time Out */
+#define nDAT_TIMEOUT 0x0
+#define TX_UNDERRUN 0x10 /* Transmit Underrun */
+#define nTX_UNDERRUN 0x0
+#define RX_OVERRUN 0x20 /* Receive Overrun */
+#define nRX_OVERRUN 0x0
+#define CMD_RESP_END 0x40 /* CMD Response End */
+#define nCMD_RESP_END 0x0
+#define CMD_SENT 0x80 /* CMD Sent */
+#define nCMD_SENT 0x0
+#define DAT_END 0x100 /* Data End */
+#define nDAT_END 0x0
+#define START_BIT_ERR 0x200 /* Start Bit Error */
+#define nSTART_BIT_ERR 0x0
+#define DAT_BLK_END 0x400 /* Data Block End */
+#define nDAT_BLK_END 0x0
+#define CMD_ACT 0x800 /* CMD Active */
+#define nCMD_ACT 0x0
+#define TX_ACT 0x1000 /* Transmit Active */
+#define nTX_ACT 0x0
+#define RX_ACT 0x2000 /* Receive Active */
+#define nRX_ACT 0x0
+#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
+#define nTX_FIFO_STAT 0x0
+#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
+#define nRX_FIFO_STAT 0x0
+#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
+#define nTX_FIFO_FULL 0x0
+#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
+#define nRX_FIFO_FULL 0x0
+#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
+#define nTX_FIFO_ZERO 0x0
+#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
+#define nRX_DAT_ZERO 0x0
+#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
+#define nTX_DAT_RDY 0x0
+#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
+#define nRX_FIFO_RDY 0x0
+
+/* Bit masks for SDH_STATUS_CLR */
+
+#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
+#define nCMD_CRC_FAIL_STAT 0x0
+#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
+#define nDAT_CRC_FAIL_STAT 0x0
+#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
+#define nCMD_TIMEOUT_STAT 0x0
+#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
+#define nDAT_TIMEOUT_STAT 0x0
+#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
+#define nTX_UNDERRUN_STAT 0x0
+#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
+#define nRX_OVERRUN_STAT 0x0
+#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
+#define nCMD_RESP_END_STAT 0x0
+#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
+#define nCMD_SENT_STAT 0x0
+#define DAT_END_STAT 0x100 /* Data End Status */
+#define nDAT_END_STAT 0x0
+#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
+#define nSTART_BIT_ERR_STAT 0x0
+#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
+#define nDAT_BLK_END_STAT 0x0
+
+/* Bit masks for SDH_MASK0 */
+
+#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
+#define nCMD_CRC_FAIL_MASK 0x0
+#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
+#define nDAT_CRC_FAIL_MASK 0x0
+#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
+#define nCMD_TIMEOUT_MASK 0x0
+#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
+#define nDAT_TIMEOUT_MASK 0x0
+#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
+#define nTX_UNDERRUN_MASK 0x0
+#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
+#define nRX_OVERRUN_MASK 0x0
+#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
+#define nCMD_RESP_END_MASK 0x0
+#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
+#define nCMD_SENT_MASK 0x0
+#define DAT_END_MASK 0x100 /* Data End Mask */
+#define nDAT_END_MASK 0x0
+#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
+#define nSTART_BIT_ERR_MASK 0x0
+#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
+#define nDAT_BLK_END_MASK 0x0
+#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
+#define nCMD_ACT_MASK 0x0
+#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
+#define nTX_ACT_MASK 0x0
+#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
+#define nRX_ACT_MASK 0x0
+#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
+#define nTX_FIFO_STAT_MASK 0x0
+#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
+#define nRX_FIFO_STAT_MASK 0x0
+#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
+#define nTX_FIFO_FULL_MASK 0x0
+#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
+#define nRX_FIFO_FULL_MASK 0x0
+#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
+#define nTX_FIFO_ZERO_MASK 0x0
+#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
+#define nRX_DAT_ZERO_MASK 0x0
+#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
+#define nTX_DAT_RDY_MASK 0x0
+#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
+#define nRX_FIFO_RDY_MASK 0x0
+
+/* Bit masks for SDH_FIFO_CNT */
+
+#define FIFO_COUNT 0x7fff /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+
+#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
+#define nSDIO_INT_DET 0x0
+#define SD_CARD_DET 0x10 /* SD Card Detect */
+#define nSD_CARD_DET 0x0
+
+/* Bit masks for SDH_E_MASK */
+
+#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
+#define nSDIO_MSK 0x0
+#define SCD_MSK 0x40 /* Mask Card Detect */
+#define nSCD_MSK 0x0
+
+/* Bit masks for SDH_CFG */
+
+#define CLKS_EN 0x1 /* Clocks Enable */
+#define nCLKS_EN 0x0
+#define SD4E 0x4 /* SDIO 4-Bit Enable */
+#define nSD4E 0x0
+#define MWE 0x8 /* Moving Window Enable */
+#define nMWE 0x0
+#define SD_RST 0x10 /* SDMMC Reset */
+#define nSD_RST 0x0
+#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
+#define nPUP_SDDAT 0x0
+#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
+#define nPUP_SDDAT3 0x0
+#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
+#define nPD_SDDAT3 0x0
+
+/* Bit masks for SDH_RD_WAIT_EN */
+
+#define RWR 0x1 /* Read Wait Request */
+#define nRWR 0x0
+
+/* Bit masks for ATAPI_CONTROL */
+
+#define PIO_START 0x1 /* Start PIO/Reg Op */
+#define nPIO_START 0x0
+#define MULTI_START 0x2 /* Start Multi-DMA Op */
+#define nMULTI_START 0x0
+#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
+#define nULTRA_START 0x0
+#define XFER_DIR 0x8 /* Transfer Direction */
+#define nXFER_DIR 0x0
+#define IORDY_EN 0x10 /* IORDY Enable */
+#define nIORDY_EN 0x0
+#define FIFO_FLUSH 0x20 /* Flush FIFOs */
+#define nFIFO_FLUSH 0x0
+#define SOFT_RST 0x40 /* Soft Reset */
+#define nSOFT_RST 0x0
+#define DEV_RST 0x80 /* Device Reset */
+#define nDEV_RST 0x0
+#define TFRCNT_RST 0x100 /* Trans Count Reset */
+#define nTFRCNT_RST 0x0
+#define END_ON_TERM 0x200 /* End/Terminate Select */
+#define nEND_ON_TERM 0x0
+#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
+#define nPIO_USE_DMA 0x0
+#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+
+#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
+#define nPIO_XFER_ON 0x0
+#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
+#define nMULTI_XFER_ON 0x0
+#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
+#define nULTRA_XFER_ON 0x0
+#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+
+#define DEV_ADDR 0x1f /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+
+#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
+#define nATAPI_DEV_INT_MASK 0x0
+#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
+#define nPIO_DONE_MASK 0x0
+#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
+#define nMULTI_DONE_MASK 0x0
+#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
+#define nUDMAIN_DONE_MASK 0x0
+#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
+#define nUDMAOUT_DONE_MASK 0x0
+#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
+#define nHOST_TERM_XFER_MASK 0x0
+#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
+#define nMULTI_TERM_MASK 0x0
+#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define nUDMAIN_TERM_MASK 0x0
+#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
+#define nUDMAOUT_TERM_MASK 0x0
+
+/* Bit masks for ATAPI_INT_STATUS */
+
+#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
+#define nATAPI_DEV_INT 0x0
+#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
+#define nPIO_DONE_INT 0x0
+#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
+#define nMULTI_DONE_INT 0x0
+#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
+#define nUDMAIN_DONE_INT 0x0
+#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
+#define nUDMAOUT_DONE_INT 0x0
+#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
+#define nHOST_TERM_XFER_INT 0x0
+#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
+#define nMULTI_TERM_INT 0x0
+#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define nUDMAIN_TERM_INT 0x0
+#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
+#define nUDMAOUT_TERM_INT 0x0
+
+/* Bit masks for ATAPI_LINE_STATUS */
+
+#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
+#define nATAPI_INTR 0x0
+#define ATAPI_DASP 0x2 /* Device dasp to host line status */
+#define nATAPI_DASP 0x0
+#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
+#define nATAPI_CS0N 0x0
+#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
+#define nATAPI_CS1N 0x0
+#define ATAPI_ADDR 0x70 /* ATAPI address line status */
+#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
+#define nATAPI_DMAREQ 0x0
+#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
+#define nATAPI_DMAACKN 0x0
+#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
+#define nATAPI_DIOWN 0x0
+#define ATAPI_DIORN 0x400 /* ATAPI read line status */
+#define nATAPI_DIORN 0x0
+#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
+#define nATAPI_IORDY 0x0
+
+/* Bit masks for ATAPI_SM_STATE */
+
+#define PIO_CSTATE 0xf /* PIO mode state machine current state */
+#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
+#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
+#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+
+#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
+#define nATAPI_HOST_TERM 0x0
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+
+#define T2_REG 0xff /* End of cycle time for register access transfers */
+#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+
+#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
+#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
+#define T4_REG 0xf000 /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+
+#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+
+#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
+#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+
+#define TKW 0xff /* Selects DIOW negated pulsewidth */
+#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+
+#define TH 0xff /* Selects DIOW data hold */
+#define TEOC 0xff00 /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+
+#define TACK 0xff /* Selects setup and hold times for TACK */
+#define TENV 0xff00 /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+
+#define TDVS 0xff /* Selects data valid setup time */
+#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+
+#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define TMLI 0xff00 /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+
+#define TZAH 0xff /* Selects minimum delay required for output */
+#define READY_PAUSE 0xff00 /* Selects ready to pause */
+
+/* Bit masks for TIMER_ENABLE1 */
+
+#define TIMEN8 0x1 /* Timer 8 Enable */
+#define nTIMEN8 0x0
+#define TIMEN9 0x2 /* Timer 9 Enable */
+#define nTIMEN9 0x0
+#define TIMEN10 0x4 /* Timer 10 Enable */
+#define nTIMEN10 0x0
+
+/* Bit masks for TIMER_DISABLE1 */
+
+#define TIMDIS8 0x1 /* Timer 8 Disable */
+#define nTIMDIS8 0x0
+#define TIMDIS9 0x2 /* Timer 9 Disable */
+#define nTIMDIS9 0x0
+#define TIMDIS10 0x4 /* Timer 10 Disable */
+#define nTIMDIS10 0x0
+
+/* Bit masks for TIMER_STATUS1 */
+
+#define TIMIL8 0x1 /* Timer 8 Interrupt */
+#define nTIMIL8 0x0
+#define TIMIL9 0x2 /* Timer 9 Interrupt */
+#define nTIMIL9 0x0
+#define TIMIL10 0x4 /* Timer 10 Interrupt */
+#define nTIMIL10 0x0
+#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
+#define nTOVF_ERR8 0x0
+#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
+#define nTOVF_ERR9 0x0
+#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
+#define nTOVF_ERR10 0x0
+#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
+#define nTRUN8 0x0
+#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
+#define nTRUN9 0x0
+#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
+#define nTRUN10 0x0
+
+/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS 0x7f /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
+#define nENABLE_SUSPENDM 0x0
+#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
+#define nSUSPEND_MODE 0x0
+#define RESUME_MODE 0x4 /* DMA Mode */
+#define nRESUME_MODE 0x0
+#define RESET 0x8 /* Reset indicator */
+#define nRESET 0x0
+#define HS_MODE 0x10 /* High Speed mode indicator */
+#define nHS_MODE 0x0
+#define HS_ENABLE 0x20 /* high Speed Enable */
+#define nHS_ENABLE 0x0
+#define SOFT_CONN 0x40 /* Soft connect */
+#define nSOFT_CONN 0x0
+#define ISO_UPDATE 0x80 /* Isochronous update */
+#define nISO_UPDATE 0x0
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
+#define nEP0_TX 0x0
+#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
+#define nEP1_TX 0x0
+#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
+#define nEP2_TX 0x0
+#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
+#define nEP3_TX 0x0
+#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
+#define nEP4_TX 0x0
+#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
+#define nEP5_TX 0x0
+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
+#define nEP6_TX 0x0
+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
+#define nEP7_TX 0x0
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
+#define nEP1_RX 0x0
+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
+#define nEP2_RX 0x0
+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
+#define nEP3_RX 0x0
+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
+#define nEP4_RX 0x0
+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
+#define nEP5_RX 0x0
+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
+#define nEP6_RX 0x0
+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
+#define nEP7_RX 0x0
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
+#define nEP0_TX_E 0x0
+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
+#define nEP1_TX_E 0x0
+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
+#define nEP2_TX_E 0x0
+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
+#define nEP3_TX_E 0x0
+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
+#define nEP4_TX_E 0x0
+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
+#define nEP5_TX_E 0x0
+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
+#define nEP6_TX_E 0x0
+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
+#define nEP7_TX_E 0x0
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
+#define nEP1_RX_E 0x0
+#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
+#define nEP2_RX_E 0x0
+#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
+#define nEP3_RX_E 0x0
+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
+#define nEP4_RX_E 0x0
+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
+#define nEP5_RX_E 0x0
+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
+#define nEP6_RX_E 0x0
+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
+#define nEP7_RX_E 0x0
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B 0x1 /* Suspend indicator */
+#define nSUSPEND_B 0x0
+#define RESUME_B 0x2 /* Resume indicator */
+#define nRESUME_B 0x0
+#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
+#define nRESET_OR_BABLE_B 0x0
+#define SOF_B 0x8 /* Start of frame */
+#define nSOF_B 0x0
+#define CONN_B 0x10 /* Connection indicator */
+#define nCONN_B 0x0
+#define DISCON_B 0x20 /* Disconnect indicator */
+#define nDISCON_B 0x0
+#define SESSION_REQ_B 0x40 /* Session Request */
+#define nSESSION_REQ_B 0x0
+#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
+#define nVBUS_ERROR_B 0x0
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
+#define nSUSPEND_BE 0x0
+#define RESUME_BE 0x2 /* Resume indicator int enable */
+#define nRESUME_BE 0x0
+#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
+#define nRESET_OR_BABLE_BE 0x0
+#define SOF_BE 0x8 /* Start of frame int enable */
+#define nSOF_BE 0x0
+#define CONN_BE 0x10 /* Connection indicator int enable */
+#define nCONN_BE 0x0
+#define DISCON_BE 0x20 /* Disconnect indicator int enable */
+#define nDISCON_BE 0x0
+#define SESSION_REQ_BE 0x40 /* Session Request int enable */
+#define nSESSION_REQ_BE 0x0
+#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
+#define nVBUS_ERROR_BE 0x0
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER 0x7ff /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT 0xf /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA 0x1 /* enables USB module */
+#define nGLOBAL_ENA 0x0
+#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
+#define nEP1_TX_ENA 0x0
+#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
+#define nEP2_TX_ENA 0x0
+#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
+#define nEP3_TX_ENA 0x0
+#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
+#define nEP4_TX_ENA 0x0
+#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
+#define nEP5_TX_ENA 0x0
+#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
+#define nEP6_TX_ENA 0x0
+#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
+#define nEP7_TX_ENA 0x0
+#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
+#define nEP1_RX_ENA 0x0
+#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
+#define nEP2_RX_ENA 0x0
+#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
+#define nEP3_RX_ENA 0x0
+#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
+#define nEP4_RX_ENA 0x0
+#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
+#define nEP5_RX_ENA 0x0
+#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
+#define nEP6_RX_ENA 0x0
+#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
+#define nEP7_RX_ENA 0x0
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION 0x1 /* session indicator */
+#define nSESSION 0x0
+#define HOST_REQ 0x2 /* Host negotiation request */
+#define nHOST_REQ 0x0
+#define HOST_MODE 0x4 /* indicates USBDRC is a host */
+#define nHOST_MODE 0x0
+#define VBUS0 0x8 /* Vbus level indicator[0] */
+#define nVBUS0 0x0
+#define VBUS1 0x10 /* Vbus level indicator[1] */
+#define nVBUS1 0x0
+#define LSDEV 0x20 /* Low-speed indicator */
+#define nLSDEV 0x0
+#define FSDEV 0x40 /* Full or High-speed indicator */
+#define nFSDEV 0x0
+#define B_DEVICE 0x80 /* A' or 'B' device indicator */
+#define nB_DEVICE 0x0
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
+#define nDRIVE_VBUS_ON 0x0
+#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
+#define nDRIVE_VBUS_OFF 0x0
+#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
+#define nCHRG_VBUS_START 0x0
+#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
+#define nCHRG_VBUS_END 0x0
+#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
+#define nDISCHRG_VBUS_START 0x0
+#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
+#define nDISCHRG_VBUS_END 0x0
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
+#define nDRIVE_VBUS_ON_ENA 0x0
+#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
+#define nDRIVE_VBUS_OFF_ENA 0x0
+#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
+#define nCHRG_VBUS_START_ENA 0x0
+#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
+#define nCHRG_VBUS_END_ENA 0x0
+#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
+#define nDISCHRG_VBUS_START_ENA 0x0
+#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
+#define nDISCHRG_VBUS_END_ENA 0x0
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY 0x1 /* data packet receive indicator */
+#define nRXPKTRDY 0x0
+#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
+#define nTXPKTRDY 0x0
+#define STALL_SENT 0x4 /* STALL handshake sent */
+#define nSTALL_SENT 0x0
+#define DATAEND 0x8 /* Data end indicator */
+#define nDATAEND 0x0
+#define SETUPEND 0x10 /* Setup end */
+#define nSETUPEND 0x0
+#define SENDSTALL 0x20 /* Send STALL handshake */
+#define nSENDSTALL 0x0
+#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
+#define nSERVICED_RXPKTRDY 0x0
+#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
+#define nSERVICED_SETUPEND 0x0
+#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
+#define nFLUSHFIFO 0x0
+#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
+#define nSTALL_RECEIVED_H 0x0
+#define SETUPPKT_H 0x8 /* send Setup token host mode */
+#define nSETUPPKT_H 0x0
+#define ERROR_H 0x10 /* timeout error indicator host mode */
+#define nERROR_H 0x0
+#define REQPKT_H 0x20 /* Request an IN transaction host mode */
+#define nREQPKT_H 0x0
+#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
+#define nSTATUSPKT_H 0x0
+#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
+#define nNAK_TIMEOUT_H 0x0
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
+#define nTXPKTRDY_T 0x0
+#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
+#define nFIFO_NOT_EMPTY_T 0x0
+#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
+#define nUNDERRUN_T 0x0
+#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
+#define nFLUSHFIFO_T 0x0
+#define STALL_SEND_T 0x10 /* issue a Stall handshake */
+#define nSTALL_SEND_T 0x0
+#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
+#define nSTALL_SENT_T 0x0
+#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_T 0x0
+#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
+#define nINCOMPTX_T 0x0
+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_T 0x0
+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
+#define nFORCE_DATATOGGLE_T 0x0
+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_T 0x0
+#define ISO_T 0x4000 /* enable Isochronous transfers */
+#define nISO_T 0x0
+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOSET_T 0x0
+#define ERROR_TH 0x4 /* error condition host mode */
+#define nERROR_TH 0x0
+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_TH 0x0
+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
+#define nNAK_TIMEOUT_TH 0x0
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
+#define nRXPKTRDY_R 0x0
+#define FIFO_FULL_R 0x2 /* FIFO not empty */
+#define nFIFO_FULL_R 0x0
+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
+#define nOVERRUN_R 0x0
+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
+#define nDATAERROR_R 0x0
+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
+#define nFLUSHFIFO_R 0x0
+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
+#define nSTALL_SEND_R 0x0
+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
+#define nSTALL_SENT_R 0x0
+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_R 0x0
+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
+#define nINCOMPRX_R 0x0
+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_R 0x0
+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
+#define nDISNYET_R 0x0
+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_R 0x0
+#define ISO_R 0x4000 /* enable Isochronous transfers */
+#define nISO_R 0x0
+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOCLEAR_R 0x0
+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
+#define nERROR_RH 0x0
+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
+#define nREQPKT_RH 0x0
+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_RH 0x0
+#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
+#define nINCOMPRX_RH 0x0
+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
+#define nDMAREQMODE_RH 0x0
+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
+#define nAUTOREQ_RH 0x0
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T 0xf /* EP number */
+#define PROTOCOL_T 0xc /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R 0xf /* EP number */
+#define PROTOCOL_R 0xc /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
+#define nDMA0_INT 0x0
+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
+#define nDMA1_INT 0x0
+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
+#define nDMA2_INT 0x0
+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
+#define nDMA3_INT 0x0
+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
+#define nDMA4_INT 0x0
+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
+#define nDMA5_INT 0x0
+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
+#define nDMA6_INT 0x0
+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
+#define nDMA7_INT 0x0
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA 0x1 /* DMA enable */
+#define nDMA_ENA 0x0
+#define DIRECTION 0x2 /* direction of DMA transfer */
+#define nDIRECTION 0x0
+#define MODE 0x4 /* DMA Bus error */
+#define nMODE 0x0
+#define INT_ENA 0x8 /* Interrupt enable */
+#define nINT_ENA 0x0
+#define EPNUM 0xf0 /* EP number */
+#define BUSERROR 0x100 /* DMA Bus error */
+#define nBUSERROR 0x0
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* ******************************************* */
+/* MULTI BIT MACRO ENUMERATIONS */
+/* ******************************************* */
+
+
+#endif /* _DEF_BF547_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF548.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF548_H
+#define _DEF_BF548_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
+
+/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include <defBF54x_base.h>
+
+/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
+
+/* Timer Registers */
+
+#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
+#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
+#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
+
+/* Timer Group of 3 Registers */
+
+#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
+
+/* SPORT0 Registers */
+
+#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
+#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
+#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
+#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
+#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
+#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
+#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
+#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
+
+/* EPPI0 Registers */
+
+#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
+
+/* UART2 Registers */
+
+#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
+#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
+#define UART2_GCTL 0xffc02108 /* Global Control Register */
+#define UART2_LCR 0xffc0210c /* Line Control Register */
+#define UART2_MCR 0xffc02110 /* Modem Control Register */
+#define UART2_LSR 0xffc02114 /* Line Status Register */
+#define UART2_MSR 0xffc02118 /* Modem Status Register */
+#define UART2_SCR 0xffc0211c /* Scratch Register */
+#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
+#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
+#define UART2_THR 0xffc02128 /* Transmit Hold Register */
+#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
+#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
+
+/* SPI2 Registers */
+
+#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
+#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
+#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
+#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
+#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
+#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
+#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
+#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
+#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
+#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
+#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
+#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
+#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+
+/* CAN Controller 1 Clock/Interrupt/Counter Registers */
+
+#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
+#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
+#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
+#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
+#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
+#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
+#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
+#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
+#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
+#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
+#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
+#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
+#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
+#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
+#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
+#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
+#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
+#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
+#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
+#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
+#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
+#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
+#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
+#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
+#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
+#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
+#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
+#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
+#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
+#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
+#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
+#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
+#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
+#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
+#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
+#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
+#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
+#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
+#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
+#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
+#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
+#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
+#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
+#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
+#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
+#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
+
+/* ATAPI Registers */
+
+#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
+#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
+
+/* SDH Registers */
+
+#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
+#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
+#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
+#define SDH_COMMAND 0xffc0390c /* SDH Command */
+#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
+#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
+#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
+#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
+#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
+#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
+#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
+#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
+#define SDH_STATUS 0xffc03934 /* SDH Status */
+#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
+#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
+#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
+#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
+#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
+#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
+#define SDH_CFG 0xffc039c8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
+#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
+#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
+#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
+#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
+#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
+#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
+#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
+#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
+
+/* HOST Port Registers */
+
+#define HOST_CONTROL 0xffc03a00 /* HOSTDP Control Register */
+#define HOST_STATUS 0xffc03a04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT 0xffc03a08 /* HOSTDP Acknowledge Mode Timeout Register */
+
+/* USB Control Registers */
+
+#define USB_FADDR 0xffc03c00 /* Function address register */
+#define USB_POWER 0xffc03c04 /* Power management register */
+#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
+#define USB_FRAME 0xffc03c20 /* USB frame number */
+#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+
+/* USB Endpoint 1 Control Registers */
+
+#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+
+/* USB Endpoint 2 Control Registers */
+
+#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+
+/* USB Endpoint 3 Control Registers */
+
+#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+
+/* USB Endpoint 4 Control Registers */
+
+#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+
+/* USB Endpoint 5 Control Registers */
+
+#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+
+/* USB Endpoint 6 Control Registers */
+
+#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+
+/* USB Endpoint 7 Control Registers */
+
+#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
+#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
+#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
+#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
+#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
+#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
+#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
+#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
+#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Keypad Registers */
+
+#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
+#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
+#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
+
+/* ********************************************************** */
+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
+/* and MULTI BIT READ MACROS */
+/* ********************************************************** */
+
+/* Bit masks for PIXC_CTL */
+
+#define PIXC_EN 0x1 /* Pixel Compositor Enable */
+#define nPIXC_EN 0x0
+#define OVR_A_EN 0x2 /* Overlay A Enable */
+#define nOVR_A_EN 0x0
+#define OVR_B_EN 0x4 /* Overlay B Enable */
+#define nOVR_B_EN 0x0
+#define IMG_FORM 0x8 /* Image Data Format */
+#define nIMG_FORM 0x0
+#define OVR_FORM 0x10 /* Overlay Data Format */
+#define nOVR_FORM 0x0
+#define OUT_FORM 0x20 /* Output Data Format */
+#define nOUT_FORM 0x0
+#define UDS_MOD 0x40 /* Resampling Mode */
+#define nUDS_MOD 0x0
+#define TC_EN 0x80 /* Transparent Color Enable */
+#define nTC_EN 0x0
+#define IMG_STAT 0x300 /* Image FIFO Status */
+#define OVR_STAT 0xc00 /* Overlay FIFO Status */
+#define WM_LVL 0x3000 /* FIFO Watermark Level */
+
+/* Bit masks for PIXC_AHSTART */
+
+#define A_HSTART 0xfff /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_AHEND */
+
+#define A_HEND 0xfff /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_AVSTART */
+
+#define A_VSTART 0x3ff /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_AVEND */
+
+#define A_VEND 0x3ff /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_ATRANSP */
+
+#define A_TRANSP 0xf /* Transparency Value */
+
+/* Bit masks for PIXC_BHSTART */
+
+#define B_HSTART 0xfff /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_BHEND */
+
+#define B_HEND 0xfff /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_BVSTART */
+
+#define B_VSTART 0x3ff /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_BVEND */
+
+#define B_VEND 0x3ff /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_BTRANSP */
+
+#define B_TRANSP 0xf /* Transparency Value */
+
+/* Bit masks for PIXC_INTRSTAT */
+
+#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
+#define nOVR_INT_EN 0x0
+#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
+#define nFRM_INT_EN 0x0
+#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
+#define nOVR_INT_STAT 0x0
+#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
+#define nFRM_INT_STAT 0x0
+
+/* Bit masks for PIXC_RYCON */
+
+#define A11 0x3ff /* A11 in the Coefficient Matrix */
+#define A12 0xffc00 /* A12 in the Coefficient Matrix */
+#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
+#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nRY_MULT4 0x0
+
+/* Bit masks for PIXC_GUCON */
+
+#define A21 0x3ff /* A21 in the Coefficient Matrix */
+#define A22 0xffc00 /* A22 in the Coefficient Matrix */
+#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
+#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nGU_MULT4 0x0
+
+/* Bit masks for PIXC_BVCON */
+
+#define A31 0x3ff /* A31 in the Coefficient Matrix */
+#define A32 0xffc00 /* A32 in the Coefficient Matrix */
+#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
+#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nBV_MULT4 0x0
+
+/* Bit masks for PIXC_CCBIAS */
+
+#define A14 0x3ff /* A14 in the Bias Vector */
+#define A24 0xffc00 /* A24 in the Bias Vector */
+#define A34 0x3ff00000 /* A34 in the Bias Vector */
+
+/* Bit masks for PIXC_TC */
+
+#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
+#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
+#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
+
+/* Bit masks for HOST_CONTROL */
+
+#define HOSTDP_EN 0x1 /* HOSTDP Enable */
+#define nHOSTDP_EN 0x0
+#define HOSTDP_END 0x2 /* Host Endianess */
+#define nHOSTDP_END 0x0
+#define HOSTDP_DATA_SIZE 0x4 /* Data Size */
+#define nHOSTDP_DATA_SIZE 0x0
+#define HOSTDP_RST 0x8 /* HOSTDP Reset */
+#define nHOSTDP_RST 0x0
+#define HRDY_OVR 0x20 /* HRDY Override */
+#define nHRDY_OVR 0x0
+#define INT_MODE 0x40 /* Interrupt Mode */
+#define nINT_MODE 0x0
+#define BT_EN 0x80 /* Bus Timeout Enable */
+#define nBT_EN 0x0
+#define EHW 0x100 /* Enable Host Write */
+#define nEHW 0x0
+#define EHR 0x200 /* Enable Host Read */
+#define nEHR 0x0
+#define BDR 0x400 /* Burst DMA Requests */
+#define nBDR 0x0
+
+/* Bit masks for HOST_STATUS */
+
+#define DMA_RDY 0x1 /* DMA Ready */
+#define nDMA_RDY 0x0
+#define FIFOFULL 0x2 /* FIFO Full */
+#define nFIFOFULL 0x0
+#define FIFOEMPTY 0x4 /* FIFO Empty */
+#define nFIFOEMPTY 0x0
+#define DMA_CMPLT 0x8 /* DMA Complete */
+#define nDMA_CMPLT 0x0
+#define HSHK 0x10 /* Host Handshake */
+#define nHSHK 0x0
+#define HOSTDP_TOUT 0x20 /* HOSTDP Timeout */
+#define nHOSTDP_TOUT 0x0
+#define HIRQ 0x40 /* Host Interrupt Request */
+#define nHIRQ 0x0
+#define ALLOW_CNFG 0x80 /* Allow New Configuration */
+#define nALLOW_CNFG 0x0
+#define DMA_DIR 0x100 /* DMA Direction */
+#define nDMA_DIR 0x0
+#define BTE 0x200 /* Bus Timeout Enabled */
+#define nBTE 0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define COUNT_TIMEOUT 0x7ff /* HOSTDP Timeout count */
+
+/* Bit masks for KPAD_CTL */
+
+#define KPAD_EN 0x1 /* Keypad Enable */
+#define nKPAD_EN 0x0
+#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
+#define nKPAD_IRQMODE 0x0 /* Interrupt Disabled */
+#define KPAD_IRQMODE_SK 0x2 /* Single key (single row, single column) press interrupt enable */
+#define KPAD_IRQMODE_MK 0x4 /* Single key press multiple key press interrupt enable */
+
+#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
+#define KPAD_COLEN 0xe000 /* Column Enable Width */
+
+#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
+#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+
+
+/* Bit masks for KPAD_PRESCALE */
+
+#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
+
+#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+
+
+/* Bit masks for KPAD_MSEL */
+
+#define DBON_SCALE 0xff /* Debounce Scale Value */
+#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
+
+#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
+#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+
+
+/* Bit masks for KPAD_ROWCOL */
+
+#define KPAD_ROW 0xff /* Rows Pressed */
+#define KPAD_COL 0xff00 /* Columns Pressed */
+
+/* Bit masks for KPAD_STAT */
+
+#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
+#define nKPAD_IRQ 0x0
+#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
+#define KPAD_PRESSED 0x8 /* Key press current status */
+#define nKPAD_PRESSED 0x0
+
+/* Bit masks for KPAD_SOFTEVAL */
+
+#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
+#define nKPAD_SOFTEVAL_E 0x0
+#define KPAD_NO_KEY 0x0 /* No Keypress Status*/
+#define KPAD_SINGLE_KEY 0x2 /* Single Keypress Status */
+#define KPAD_MKSROWCOL 0x4 /* Multiple Keypress in the same row or column Status */
+#define KPAD_MKMROWCOL 0x6 /* Multiple Keypress in the same multiple rows and multiple columns Status */
+
+/* Bit masks for SDH_COMMAND */
+
+#define CMD_IDX 0x3f /* Command Index */
+#define CMD_RSP 0x40 /* Response */
+#define nCMD_RSP 0x0
+#define CMD_L_RSP 0x80 /* Long Response */
+#define nCMD_L_RSP 0x0
+#define CMD_INT_E 0x100 /* Command Interrupt */
+#define nCMD_INT_E 0x0
+#define CMD_PEND_E 0x200 /* Command Pending */
+#define nCMD_PEND_E 0x0
+#define CMD_E 0x400 /* Command Enable */
+#define nCMD_E 0x0
+
+/* Bit masks for SDH_PWR_CTL */
+
+#define PWR_ON 0x3 /* Power On */
+#if 0
+#define TBD 0x3c /* TBD */
+#endif
+#define SD_CMD_OD 0x40 /* Open Drain Output */
+#define nSD_CMD_OD 0x0
+#define ROD_CTL 0x80 /* Rod Control */
+#define nROD_CTL 0x0
+
+/* Bit masks for SDH_CLK_CTL */
+
+#define CLKDIV 0xff /* MC_CLK Divisor */
+#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
+#define nCLK_E 0x0
+#define PWR_SV_E 0x200 /* Power Save Enable */
+#define nPWR_SV_E 0x0
+#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
+#define nCLKDIV_BYPASS 0x0
+#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
+#define nWIDE_BUS 0x0
+
+/* Bit masks for SDH_RESP_CMD */
+
+#define RESP_CMD 0x3f /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+
+#define DTX_E 0x1 /* Data Transfer Enable */
+#define nDTX_E 0x0
+#define DTX_DIR 0x2 /* Data Transfer Direction */
+#define nDTX_DIR 0x0
+#define DTX_MODE 0x4 /* Data Transfer Mode */
+#define nDTX_MODE 0x0
+#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
+#define nDTX_DMA_E 0x0
+#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+
+#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
+#define nCMD_CRC_FAIL 0x0
+#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
+#define nDAT_CRC_FAIL 0x0
+#define CMD_TIMEOUT 0x4 /* CMD Time Out */
+#define nCMD_TIMEOUT 0x0
+#define DAT_TIMEOUT 0x8 /* Data Time Out */
+#define nDAT_TIMEOUT 0x0
+#define TX_UNDERRUN 0x10 /* Transmit Underrun */
+#define nTX_UNDERRUN 0x0
+#define RX_OVERRUN 0x20 /* Receive Overrun */
+#define nRX_OVERRUN 0x0
+#define CMD_RESP_END 0x40 /* CMD Response End */
+#define nCMD_RESP_END 0x0
+#define CMD_SENT 0x80 /* CMD Sent */
+#define nCMD_SENT 0x0
+#define DAT_END 0x100 /* Data End */
+#define nDAT_END 0x0
+#define START_BIT_ERR 0x200 /* Start Bit Error */
+#define nSTART_BIT_ERR 0x0
+#define DAT_BLK_END 0x400 /* Data Block End */
+#define nDAT_BLK_END 0x0
+#define CMD_ACT 0x800 /* CMD Active */
+#define nCMD_ACT 0x0
+#define TX_ACT 0x1000 /* Transmit Active */
+#define nTX_ACT 0x0
+#define RX_ACT 0x2000 /* Receive Active */
+#define nRX_ACT 0x0
+#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
+#define nTX_FIFO_STAT 0x0
+#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
+#define nRX_FIFO_STAT 0x0
+#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
+#define nTX_FIFO_FULL 0x0
+#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
+#define nRX_FIFO_FULL 0x0
+#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
+#define nTX_FIFO_ZERO 0x0
+#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
+#define nRX_DAT_ZERO 0x0
+#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
+#define nTX_DAT_RDY 0x0
+#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
+#define nRX_FIFO_RDY 0x0
+
+/* Bit masks for SDH_STATUS_CLR */
+
+#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
+#define nCMD_CRC_FAIL_STAT 0x0
+#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
+#define nDAT_CRC_FAIL_STAT 0x0
+#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
+#define nCMD_TIMEOUT_STAT 0x0
+#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
+#define nDAT_TIMEOUT_STAT 0x0
+#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
+#define nTX_UNDERRUN_STAT 0x0
+#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
+#define nRX_OVERRUN_STAT 0x0
+#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
+#define nCMD_RESP_END_STAT 0x0
+#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
+#define nCMD_SENT_STAT 0x0
+#define DAT_END_STAT 0x100 /* Data End Status */
+#define nDAT_END_STAT 0x0
+#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
+#define nSTART_BIT_ERR_STAT 0x0
+#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
+#define nDAT_BLK_END_STAT 0x0
+
+/* Bit masks for SDH_MASK0 */
+
+#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
+#define nCMD_CRC_FAIL_MASK 0x0
+#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
+#define nDAT_CRC_FAIL_MASK 0x0
+#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
+#define nCMD_TIMEOUT_MASK 0x0
+#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
+#define nDAT_TIMEOUT_MASK 0x0
+#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
+#define nTX_UNDERRUN_MASK 0x0
+#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
+#define nRX_OVERRUN_MASK 0x0
+#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
+#define nCMD_RESP_END_MASK 0x0
+#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
+#define nCMD_SENT_MASK 0x0
+#define DAT_END_MASK 0x100 /* Data End Mask */
+#define nDAT_END_MASK 0x0
+#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
+#define nSTART_BIT_ERR_MASK 0x0
+#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
+#define nDAT_BLK_END_MASK 0x0
+#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
+#define nCMD_ACT_MASK 0x0
+#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
+#define nTX_ACT_MASK 0x0
+#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
+#define nRX_ACT_MASK 0x0
+#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
+#define nTX_FIFO_STAT_MASK 0x0
+#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
+#define nRX_FIFO_STAT_MASK 0x0
+#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
+#define nTX_FIFO_FULL_MASK 0x0
+#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
+#define nRX_FIFO_FULL_MASK 0x0
+#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
+#define nTX_FIFO_ZERO_MASK 0x0
+#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
+#define nRX_DAT_ZERO_MASK 0x0
+#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
+#define nTX_DAT_RDY_MASK 0x0
+#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
+#define nRX_FIFO_RDY_MASK 0x0
+
+/* Bit masks for SDH_FIFO_CNT */
+
+#define FIFO_COUNT 0x7fff /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+
+#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
+#define nSDIO_INT_DET 0x0
+#define SD_CARD_DET 0x10 /* SD Card Detect */
+#define nSD_CARD_DET 0x0
+
+/* Bit masks for SDH_E_MASK */
+
+#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
+#define nSDIO_MSK 0x0
+#define SCD_MSK 0x40 /* Mask Card Detect */
+#define nSCD_MSK 0x0
+
+/* Bit masks for SDH_CFG */
+
+#define CLKS_EN 0x1 /* Clocks Enable */
+#define nCLKS_EN 0x0
+#define SD4E 0x4 /* SDIO 4-Bit Enable */
+#define nSD4E 0x0
+#define MWE 0x8 /* Moving Window Enable */
+#define nMWE 0x0
+#define SD_RST 0x10 /* SDMMC Reset */
+#define nSD_RST 0x0
+#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
+#define nPUP_SDDAT 0x0
+#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
+#define nPUP_SDDAT3 0x0
+#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
+#define nPD_SDDAT3 0x0
+
+/* Bit masks for SDH_RD_WAIT_EN */
+
+#define RWR 0x1 /* Read Wait Request */
+#define nRWR 0x0
+
+/* Bit masks for ATAPI_CONTROL */
+
+#define PIO_START 0x1 /* Start PIO/Reg Op */
+#define nPIO_START 0x0
+#define MULTI_START 0x2 /* Start Multi-DMA Op */
+#define nMULTI_START 0x0
+#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
+#define nULTRA_START 0x0
+#define XFER_DIR 0x8 /* Transfer Direction */
+#define nXFER_DIR 0x0
+#define IORDY_EN 0x10 /* IORDY Enable */
+#define nIORDY_EN 0x0
+#define FIFO_FLUSH 0x20 /* Flush FIFOs */
+#define nFIFO_FLUSH 0x0
+#define SOFT_RST 0x40 /* Soft Reset */
+#define nSOFT_RST 0x0
+#define DEV_RST 0x80 /* Device Reset */
+#define nDEV_RST 0x0
+#define TFRCNT_RST 0x100 /* Trans Count Reset */
+#define nTFRCNT_RST 0x0
+#define END_ON_TERM 0x200 /* End/Terminate Select */
+#define nEND_ON_TERM 0x0
+#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
+#define nPIO_USE_DMA 0x0
+#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+
+#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
+#define nPIO_XFER_ON 0x0
+#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
+#define nMULTI_XFER_ON 0x0
+#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
+#define nULTRA_XFER_ON 0x0
+#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+
+#define DEV_ADDR 0x1f /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+
+#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
+#define nATAPI_DEV_INT_MASK 0x0
+#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
+#define nPIO_DONE_MASK 0x0
+#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
+#define nMULTI_DONE_MASK 0x0
+#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
+#define nUDMAIN_DONE_MASK 0x0
+#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
+#define nUDMAOUT_DONE_MASK 0x0
+#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
+#define nHOST_TERM_XFER_MASK 0x0
+#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
+#define nMULTI_TERM_MASK 0x0
+#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define nUDMAIN_TERM_MASK 0x0
+#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
+#define nUDMAOUT_TERM_MASK 0x0
+
+/* Bit masks for ATAPI_INT_STATUS */
+
+#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
+#define nATAPI_DEV_INT 0x0
+#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
+#define nPIO_DONE_INT 0x0
+#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
+#define nMULTI_DONE_INT 0x0
+#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
+#define nUDMAIN_DONE_INT 0x0
+#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
+#define nUDMAOUT_DONE_INT 0x0
+#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
+#define nHOST_TERM_XFER_INT 0x0
+#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
+#define nMULTI_TERM_INT 0x0
+#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define nUDMAIN_TERM_INT 0x0
+#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
+#define nUDMAOUT_TERM_INT 0x0
+
+/* Bit masks for ATAPI_LINE_STATUS */
+
+#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
+#define nATAPI_INTR 0x0
+#define ATAPI_DASP 0x2 /* Device dasp to host line status */
+#define nATAPI_DASP 0x0
+#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
+#define nATAPI_CS0N 0x0
+#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
+#define nATAPI_CS1N 0x0
+#define ATAPI_ADDR 0x70 /* ATAPI address line status */
+#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
+#define nATAPI_DMAREQ 0x0
+#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
+#define nATAPI_DMAACKN 0x0
+#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
+#define nATAPI_DIOWN 0x0
+#define ATAPI_DIORN 0x400 /* ATAPI read line status */
+#define nATAPI_DIORN 0x0
+#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
+#define nATAPI_IORDY 0x0
+
+/* Bit masks for ATAPI_SM_STATE */
+
+#define PIO_CSTATE 0xf /* PIO mode state machine current state */
+#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
+#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
+#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+
+#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
+#define nATAPI_HOST_TERM 0x0
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+
+#define T2_REG 0xff /* End of cycle time for register access transfers */
+#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+
+#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
+#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
+#define T4_REG 0xf000 /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+
+#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+
+#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
+#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+
+#define TKW 0xff /* Selects DIOW negated pulsewidth */
+#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+
+#define TH 0xff /* Selects DIOW data hold */
+#define TEOC 0xff00 /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+
+#define TACK 0xff /* Selects setup and hold times for TACK */
+#define TENV 0xff00 /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+
+#define TDVS 0xff /* Selects data valid setup time */
+#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+
+#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define TMLI 0xff00 /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+
+#define TZAH 0xff /* Selects minimum delay required for output */
+#define READY_PAUSE 0xff00 /* Selects ready to pause */
+
+/* Bit masks for TIMER_ENABLE1 */
+
+#define TIMEN8 0x1 /* Timer 8 Enable */
+#define nTIMEN8 0x0
+#define TIMEN9 0x2 /* Timer 9 Enable */
+#define nTIMEN9 0x0
+#define TIMEN10 0x4 /* Timer 10 Enable */
+#define nTIMEN10 0x0
+
+/* Bit masks for TIMER_DISABLE1 */
+
+#define TIMDIS8 0x1 /* Timer 8 Disable */
+#define nTIMDIS8 0x0
+#define TIMDIS9 0x2 /* Timer 9 Disable */
+#define nTIMDIS9 0x0
+#define TIMDIS10 0x4 /* Timer 10 Disable */
+#define nTIMDIS10 0x0
+
+/* Bit masks for TIMER_STATUS1 */
+
+#define TIMIL8 0x1 /* Timer 8 Interrupt */
+#define nTIMIL8 0x0
+#define TIMIL9 0x2 /* Timer 9 Interrupt */
+#define nTIMIL9 0x0
+#define TIMIL10 0x4 /* Timer 10 Interrupt */
+#define nTIMIL10 0x0
+#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
+#define nTOVF_ERR8 0x0
+#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
+#define nTOVF_ERR9 0x0
+#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
+#define nTOVF_ERR10 0x0
+#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
+#define nTRUN8 0x0
+#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
+#define nTRUN9 0x0
+#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
+#define nTRUN10 0x0
+
+/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS 0x7f /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
+#define nENABLE_SUSPENDM 0x0
+#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
+#define nSUSPEND_MODE 0x0
+#define RESUME_MODE 0x4 /* DMA Mode */
+#define nRESUME_MODE 0x0
+#define RESET 0x8 /* Reset indicator */
+#define nRESET 0x0
+#define HS_MODE 0x10 /* High Speed mode indicator */
+#define nHS_MODE 0x0
+#define HS_ENABLE 0x20 /* high Speed Enable */
+#define nHS_ENABLE 0x0
+#define SOFT_CONN 0x40 /* Soft connect */
+#define nSOFT_CONN 0x0
+#define ISO_UPDATE 0x80 /* Isochronous update */
+#define nISO_UPDATE 0x0
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
+#define nEP0_TX 0x0
+#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
+#define nEP1_TX 0x0
+#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
+#define nEP2_TX 0x0
+#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
+#define nEP3_TX 0x0
+#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
+#define nEP4_TX 0x0
+#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
+#define nEP5_TX 0x0
+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
+#define nEP6_TX 0x0
+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
+#define nEP7_TX 0x0
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
+#define nEP1_RX 0x0
+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
+#define nEP2_RX 0x0
+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
+#define nEP3_RX 0x0
+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
+#define nEP4_RX 0x0
+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
+#define nEP5_RX 0x0
+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
+#define nEP6_RX 0x0
+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
+#define nEP7_RX 0x0
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
+#define nEP0_TX_E 0x0
+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
+#define nEP1_TX_E 0x0
+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
+#define nEP2_TX_E 0x0
+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
+#define nEP3_TX_E 0x0
+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
+#define nEP4_TX_E 0x0
+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
+#define nEP5_TX_E 0x0
+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
+#define nEP6_TX_E 0x0
+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
+#define nEP7_TX_E 0x0
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
+#define nEP1_RX_E 0x0
+#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
+#define nEP2_RX_E 0x0
+#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
+#define nEP3_RX_E 0x0
+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
+#define nEP4_RX_E 0x0
+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
+#define nEP5_RX_E 0x0
+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
+#define nEP6_RX_E 0x0
+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
+#define nEP7_RX_E 0x0
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B 0x1 /* Suspend indicator */
+#define nSUSPEND_B 0x0
+#define RESUME_B 0x2 /* Resume indicator */
+#define nRESUME_B 0x0
+#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
+#define nRESET_OR_BABLE_B 0x0
+#define SOF_B 0x8 /* Start of frame */
+#define nSOF_B 0x0
+#define CONN_B 0x10 /* Connection indicator */
+#define nCONN_B 0x0
+#define DISCON_B 0x20 /* Disconnect indicator */
+#define nDISCON_B 0x0
+#define SESSION_REQ_B 0x40 /* Session Request */
+#define nSESSION_REQ_B 0x0
+#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
+#define nVBUS_ERROR_B 0x0
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
+#define nSUSPEND_BE 0x0
+#define RESUME_BE 0x2 /* Resume indicator int enable */
+#define nRESUME_BE 0x0
+#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
+#define nRESET_OR_BABLE_BE 0x0
+#define SOF_BE 0x8 /* Start of frame int enable */
+#define nSOF_BE 0x0
+#define CONN_BE 0x10 /* Connection indicator int enable */
+#define nCONN_BE 0x0
+#define DISCON_BE 0x20 /* Disconnect indicator int enable */
+#define nDISCON_BE 0x0
+#define SESSION_REQ_BE 0x40 /* Session Request int enable */
+#define nSESSION_REQ_BE 0x0
+#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
+#define nVBUS_ERROR_BE 0x0
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER 0x7ff /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT 0xf /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA 0x1 /* enables USB module */
+#define nGLOBAL_ENA 0x0
+#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
+#define nEP1_TX_ENA 0x0
+#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
+#define nEP2_TX_ENA 0x0
+#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
+#define nEP3_TX_ENA 0x0
+#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
+#define nEP4_TX_ENA 0x0
+#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
+#define nEP5_TX_ENA 0x0
+#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
+#define nEP6_TX_ENA 0x0
+#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
+#define nEP7_TX_ENA 0x0
+#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
+#define nEP1_RX_ENA 0x0
+#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
+#define nEP2_RX_ENA 0x0
+#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
+#define nEP3_RX_ENA 0x0
+#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
+#define nEP4_RX_ENA 0x0
+#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
+#define nEP5_RX_ENA 0x0
+#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
+#define nEP6_RX_ENA 0x0
+#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
+#define nEP7_RX_ENA 0x0
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION 0x1 /* session indicator */
+#define nSESSION 0x0
+#define HOST_REQ 0x2 /* Host negotiation request */
+#define nHOST_REQ 0x0
+#define HOST_MODE 0x4 /* indicates USBDRC is a host */
+#define nHOST_MODE 0x0
+#define VBUS0 0x8 /* Vbus level indicator[0] */
+#define nVBUS0 0x0
+#define VBUS1 0x10 /* Vbus level indicator[1] */
+#define nVBUS1 0x0
+#define LSDEV 0x20 /* Low-speed indicator */
+#define nLSDEV 0x0
+#define FSDEV 0x40 /* Full or High-speed indicator */
+#define nFSDEV 0x0
+#define B_DEVICE 0x80 /* A' or 'B' device indicator */
+#define nB_DEVICE 0x0
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
+#define nDRIVE_VBUS_ON 0x0
+#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
+#define nDRIVE_VBUS_OFF 0x0
+#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
+#define nCHRG_VBUS_START 0x0
+#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
+#define nCHRG_VBUS_END 0x0
+#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
+#define nDISCHRG_VBUS_START 0x0
+#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
+#define nDISCHRG_VBUS_END 0x0
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
+#define nDRIVE_VBUS_ON_ENA 0x0
+#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
+#define nDRIVE_VBUS_OFF_ENA 0x0
+#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
+#define nCHRG_VBUS_START_ENA 0x0
+#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
+#define nCHRG_VBUS_END_ENA 0x0
+#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
+#define nDISCHRG_VBUS_START_ENA 0x0
+#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
+#define nDISCHRG_VBUS_END_ENA 0x0
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY 0x1 /* data packet receive indicator */
+#define nRXPKTRDY 0x0
+#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
+#define nTXPKTRDY 0x0
+#define STALL_SENT 0x4 /* STALL handshake sent */
+#define nSTALL_SENT 0x0
+#define DATAEND 0x8 /* Data end indicator */
+#define nDATAEND 0x0
+#define SETUPEND 0x10 /* Setup end */
+#define nSETUPEND 0x0
+#define SENDSTALL 0x20 /* Send STALL handshake */
+#define nSENDSTALL 0x0
+#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
+#define nSERVICED_RXPKTRDY 0x0
+#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
+#define nSERVICED_SETUPEND 0x0
+#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
+#define nFLUSHFIFO 0x0
+#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
+#define nSTALL_RECEIVED_H 0x0
+#define SETUPPKT_H 0x8 /* send Setup token host mode */
+#define nSETUPPKT_H 0x0
+#define ERROR_H 0x10 /* timeout error indicator host mode */
+#define nERROR_H 0x0
+#define REQPKT_H 0x20 /* Request an IN transaction host mode */
+#define nREQPKT_H 0x0
+#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
+#define nSTATUSPKT_H 0x0
+#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
+#define nNAK_TIMEOUT_H 0x0
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
+#define nTXPKTRDY_T 0x0
+#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
+#define nFIFO_NOT_EMPTY_T 0x0
+#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
+#define nUNDERRUN_T 0x0
+#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
+#define nFLUSHFIFO_T 0x0
+#define STALL_SEND_T 0x10 /* issue a Stall handshake */
+#define nSTALL_SEND_T 0x0
+#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
+#define nSTALL_SENT_T 0x0
+#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_T 0x0
+#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
+#define nINCOMPTX_T 0x0
+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_T 0x0
+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
+#define nFORCE_DATATOGGLE_T 0x0
+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_T 0x0
+#define ISO_T 0x4000 /* enable Isochronous transfers */
+#define nISO_T 0x0
+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOSET_T 0x0
+#define ERROR_TH 0x4 /* error condition host mode */
+#define nERROR_TH 0x0
+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_TH 0x0
+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
+#define nNAK_TIMEOUT_TH 0x0
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
+#define nRXPKTRDY_R 0x0
+#define FIFO_FULL_R 0x2 /* FIFO not empty */
+#define nFIFO_FULL_R 0x0
+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
+#define nOVERRUN_R 0x0
+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
+#define nDATAERROR_R 0x0
+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
+#define nFLUSHFIFO_R 0x0
+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
+#define nSTALL_SEND_R 0x0
+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
+#define nSTALL_SENT_R 0x0
+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_R 0x0
+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
+#define nINCOMPRX_R 0x0
+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_R 0x0
+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
+#define nDISNYET_R 0x0
+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_R 0x0
+#define ISO_R 0x4000 /* enable Isochronous transfers */
+#define nISO_R 0x0
+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOCLEAR_R 0x0
+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
+#define nERROR_RH 0x0
+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
+#define nREQPKT_RH 0x0
+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_RH 0x0
+#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
+#define nINCOMPRX_RH 0x0
+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
+#define nDMAREQMODE_RH 0x0
+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
+#define nAUTOREQ_RH 0x0
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T 0xf /* EP number */
+#define PROTOCOL_T 0xc /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R 0xf /* EP number */
+#define PROTOCOL_R 0xc /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
+#define nDMA0_INT 0x0
+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
+#define nDMA1_INT 0x0
+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
+#define nDMA2_INT 0x0
+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
+#define nDMA3_INT 0x0
+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
+#define nDMA4_INT 0x0
+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
+#define nDMA5_INT 0x0
+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
+#define nDMA6_INT 0x0
+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
+#define nDMA7_INT 0x0
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA 0x1 /* DMA enable */
+#define nDMA_ENA 0x0
+#define DIRECTION 0x2 /* direction of DMA transfer */
+#define nDIRECTION 0x0
+#define MODE 0x4 /* DMA Bus error */
+#define nMODE 0x0
+#define INT_ENA 0x8 /* Interrupt enable */
+#define nINT_ENA 0x0
+#define EPNUM 0xf0 /* EP number */
+#define BUSERROR 0x100 /* DMA Bus error */
+#define nBUSERROR 0x0
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* ******************************************* */
+/* MULTI BIT MACRO ENUMERATIONS */
+/* ******************************************* */
+
+
+#endif /* _DEF_BF548_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF549.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for register-access and bit-manipulation.
+**
+**/
+#ifndef _DEF_BF549_H
+#define _DEF_BF549_H
+
+/* Include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
+
+/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include <defBF54x_base.h>
+
+/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
+
+/* Timer Registers */
+
+#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
+#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
+#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
+
+/* Timer Group of 3 Registers */
+
+#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
+
+/* SPORT0 Registers */
+
+#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
+#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
+#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
+#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
+#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
+#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
+#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
+#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
+
+/* EPPI0 Registers */
+
+#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
+
+/* UART2 Registers */
+
+#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
+#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
+#define UART2_GCTL 0xffc02108 /* Global Control Register */
+#define UART2_LCR 0xffc0210c /* Line Control Register */
+#define UART2_MCR 0xffc02110 /* Modem Control Register */
+#define UART2_LSR 0xffc02114 /* Line Status Register */
+#define UART2_MSR 0xffc02118 /* Modem Status Register */
+#define UART2_SCR 0xffc0211c /* Scratch Register */
+#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
+#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
+#define UART2_THR 0xffc02128 /* Transmit Hold Register */
+#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
+#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTL 0xffc02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTL 0xffc02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTL 0xffc02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
+
+/* SPI2 Registers */
+
+#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
+#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
+#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
+#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
+#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
+
+/* MXVR Registers */
+
+#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */
+#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */
+#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */
+#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */
+#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */
+#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */
+#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */
+#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */
+#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */
+#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */
+#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */
+#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */
+#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */
+#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */
+
+/* MXVR Allocation Table Registers */
+
+#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */
+#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */
+#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */
+#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */
+#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */
+#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */
+#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */
+#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */
+#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */
+#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */
+#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */
+#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */
+#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */
+#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */
+#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */
+
+/* MXVR Channel Assign Registers */
+
+#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
+#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */
+#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
+#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
+#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
+#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */
+#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
+#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
+
+/* MXVR DMA0 Registers */
+
+#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */
+#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */
+#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */
+#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */
+#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */
+
+/* MXVR DMA1 Registers */
+
+#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */
+#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */
+#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */
+#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */
+#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */
+
+/* MXVR DMA2 Registers */
+
+#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */
+#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */
+#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */
+#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */
+#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */
+
+/* MXVR DMA3 Registers */
+
+#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */
+#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */
+#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */
+#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */
+#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */
+
+/* MXVR DMA4 Registers */
+
+#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */
+#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */
+#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */
+#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */
+#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */
+
+/* MXVR DMA5 Registers */
+
+#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */
+#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */
+#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */
+#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */
+#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */
+
+/* MXVR DMA6 Registers */
+
+#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */
+#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
+#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */
+#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */
+#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */
+
+/* MXVR DMA7 Registers */
+
+#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */
+#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */
+#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */
+#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */
+#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */
+
+/* MXVR Asynch Packet Registers */
+
+#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */
+#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */
+#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */
+#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */
+#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */
+
+/* MXVR Control Message Registers */
+
+#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */
+#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */
+#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */
+#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */
+#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */
+
+/* MXVR Remote Read Registers */
+
+#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */
+#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */
+
+/* MXVR Pattern Data Registers */
+
+#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */
+#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */
+#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */
+#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */
+
+/* MXVR Frame Counter Registers */
+
+#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */
+#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */
+
+/* MXVR Routing Table Registers */
+
+#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */
+#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */
+#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */
+#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */
+#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */
+#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */
+#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */
+#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */
+#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */
+#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */
+#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */
+#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */
+#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */
+#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */
+#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */
+
+/* MXVR Counter-Clock-Control Registers */
+
+#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */
+#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */
+#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */
+#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */
+#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
+#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
+
+/* CAN Controller 1 Config 1 Registers */
+
+#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
+#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
+#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
+#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
+#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
+#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
+#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
+#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
+#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
+#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
+#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
+
+/* CAN Controller 1 Config 2 Registers */
+
+#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
+#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
+#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
+#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
+#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
+#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
+#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
+#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
+#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
+#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
+#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
+
+/* CAN Controller 1 Clock/Interrupt/Counter Registers */
+
+#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
+#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
+#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
+#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
+#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
+#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
+#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
+#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
+#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
+#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
+#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
+#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
+#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
+#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
+#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
+#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
+#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
+#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
+#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
+#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
+#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
+#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
+#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
+#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
+#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
+#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
+#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
+#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
+#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
+#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
+#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
+#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
+#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
+#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
+#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
+#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
+#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
+#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
+#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
+#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
+#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
+#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
+#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
+#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
+#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
+#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
+#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Acceptance Registers */
+
+#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
+#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
+#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
+#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
+#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
+#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
+#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
+#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
+#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
+#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
+#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
+#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
+#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
+#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
+#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
+#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
+#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
+#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
+#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
+#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
+#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
+#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
+#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
+#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
+#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
+#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
+#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
+#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
+#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
+#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
+#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
+#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
+#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
+#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
+#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
+#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
+#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
+#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
+#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
+#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
+#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
+#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
+#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
+#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
+#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
+#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
+#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
+#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
+#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
+#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
+#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
+#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
+#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
+#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
+#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
+#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
+#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
+#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
+#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
+#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
+#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
+#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
+#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
+#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
+#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
+#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
+#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
+#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
+#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
+#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
+#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
+#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
+#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
+#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
+#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
+#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
+#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
+#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
+#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
+#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
+#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
+#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
+#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
+#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
+#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
+#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
+#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
+#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
+#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
+#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
+#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
+#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
+#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
+#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
+#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
+#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
+#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
+#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
+#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
+#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
+#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
+#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
+#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
+#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
+#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
+#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
+#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
+#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
+#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
+#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
+#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
+#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
+#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
+#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
+#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
+#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
+#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
+#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
+#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
+#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
+#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
+#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
+#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
+#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
+#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
+#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
+#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
+#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
+#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
+#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
+#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
+#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
+#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
+#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
+#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
+#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
+#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
+#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
+#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
+#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
+#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
+#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
+#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
+#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
+#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
+#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
+#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
+#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
+#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
+#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
+#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
+#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
+#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
+#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
+#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
+#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
+#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
+#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
+#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
+
+/* CAN Controller 1 Mailbox Data Registers */
+
+#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
+#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
+#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
+#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
+#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
+#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
+#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
+#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
+#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
+#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
+#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
+#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
+#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
+#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
+#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
+#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
+#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
+#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
+#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
+#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
+#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
+#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
+#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
+#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
+#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
+#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
+#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
+#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
+#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
+#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
+#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
+#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
+#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
+#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
+#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
+#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
+#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
+#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
+#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
+#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
+#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
+#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
+#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
+#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
+#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
+#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
+#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
+#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
+#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
+#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
+#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
+#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
+#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
+#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
+#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
+#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
+#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
+#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
+#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
+#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
+#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
+#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
+#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
+#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
+#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
+#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
+#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
+#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
+#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
+#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
+#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
+#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
+#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
+#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
+#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
+#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
+#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
+#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
+#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
+#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
+#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
+#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
+#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
+#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
+#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
+#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
+#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
+#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
+#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
+#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
+#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
+#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
+#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
+#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
+#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
+#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
+#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
+#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
+#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
+#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
+#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
+#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
+#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
+#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
+#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
+#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
+#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
+#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
+#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
+#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
+#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
+#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
+#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
+#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
+#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
+#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
+#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
+#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
+#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
+#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
+#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
+#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
+#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
+#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
+#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
+#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
+#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
+#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
+
+/* ATAPI Registers */
+
+#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
+#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
+
+/* SDH Registers */
+
+#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
+#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
+#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
+#define SDH_COMMAND 0xffc0390c /* SDH Command */
+#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
+#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
+#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
+#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
+#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
+#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
+#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
+#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
+#define SDH_STATUS 0xffc03934 /* SDH Status */
+#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
+#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
+#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
+#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
+#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
+#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
+#define SDH_CFG 0xffc039c8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
+#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
+#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
+#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
+#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
+#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
+#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
+#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
+#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
+
+/* HOST Port Registers */
+
+#define HOST_CONTROL 0xffc03a00 /* HOSTDP Control Register */
+#define HOST_STATUS 0xffc03a04 /* HOSTDP Status Register */
+#define HOST_TIMEOUT 0xffc03a08 /* HOSTDP Acknowledge Mode Timeout Register */
+
+/* USB Control Registers */
+
+#define USB_FADDR 0xffc03c00 /* Function address register */
+#define USB_POWER 0xffc03c04 /* Power management register */
+#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
+#define USB_FRAME 0xffc03c20 /* USB frame number */
+#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+
+/* USB Endpoint 1 Control Registers */
+
+#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+
+/* USB Endpoint 2 Control Registers */
+
+#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+
+/* USB Endpoint 3 Control Registers */
+
+#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+
+/* USB Endpoint 4 Control Registers */
+
+#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+
+/* USB Endpoint 5 Control Registers */
+
+#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+
+/* USB Endpoint 6 Control Registers */
+
+#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+
+/* USB Endpoint 7 Control Registers */
+
+#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
+#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
+#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
+#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
+#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
+#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
+#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
+#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
+#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Keypad Registers */
+
+#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
+#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
+#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
+
+/* ********************************************************** */
+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
+/* and MULTI BIT READ MACROS */
+/* ********************************************************** */
+
+/* Bit masks for PIXC_CTL */
+
+#define PIXC_EN 0x1 /* Pixel Compositor Enable */
+#define nPIXC_EN 0x0
+#define OVR_A_EN 0x2 /* Overlay A Enable */
+#define nOVR_A_EN 0x0
+#define OVR_B_EN 0x4 /* Overlay B Enable */
+#define nOVR_B_EN 0x0
+#define IMG_FORM 0x8 /* Image Data Format */
+#define nIMG_FORM 0x0
+#define OVR_FORM 0x10 /* Overlay Data Format */
+#define nOVR_FORM 0x0
+#define OUT_FORM 0x20 /* Output Data Format */
+#define nOUT_FORM 0x0
+#define UDS_MOD 0x40 /* Resampling Mode */
+#define nUDS_MOD 0x0
+#define TC_EN 0x80 /* Transparent Color Enable */
+#define nTC_EN 0x0
+#define IMG_STAT 0x300 /* Image FIFO Status */
+#define OVR_STAT 0xc00 /* Overlay FIFO Status */
+#define WM_LVL 0x3000 /* FIFO Watermark Level */
+
+/* Bit masks for PIXC_AHSTART */
+
+#define A_HSTART 0xfff /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_AHEND */
+
+#define A_HEND 0xfff /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_AVSTART */
+
+#define A_VSTART 0x3ff /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_AVEND */
+
+#define A_VEND 0x3ff /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_ATRANSP */
+
+#define A_TRANSP 0xf /* Transparency Value */
+
+/* Bit masks for PIXC_BHSTART */
+
+#define B_HSTART 0xfff /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_BHEND */
+
+#define B_HEND 0xfff /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_BVSTART */
+
+#define B_VSTART 0x3ff /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_BVEND */
+
+#define B_VEND 0x3ff /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_BTRANSP */
+
+#define B_TRANSP 0xf /* Transparency Value */
+
+/* Bit masks for PIXC_INTRSTAT */
+
+#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
+#define nOVR_INT_EN 0x0
+#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
+#define nFRM_INT_EN 0x0
+#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
+#define nOVR_INT_STAT 0x0
+#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
+#define nFRM_INT_STAT 0x0
+
+/* Bit masks for PIXC_RYCON */
+
+#define A11 0x3ff /* A11 in the Coefficient Matrix */
+#define A12 0xffc00 /* A12 in the Coefficient Matrix */
+#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
+#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nRY_MULT4 0x0
+
+/* Bit masks for PIXC_GUCON */
+
+#define A21 0x3ff /* A21 in the Coefficient Matrix */
+#define A22 0xffc00 /* A22 in the Coefficient Matrix */
+#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
+#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nGU_MULT4 0x0
+
+/* Bit masks for PIXC_BVCON */
+
+#define A31 0x3ff /* A31 in the Coefficient Matrix */
+#define A32 0xffc00 /* A32 in the Coefficient Matrix */
+#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
+#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
+#define nBV_MULT4 0x0
+
+/* Bit masks for PIXC_CCBIAS */
+
+#define A14 0x3ff /* A14 in the Bias Vector */
+#define A24 0xffc00 /* A24 in the Bias Vector */
+#define A34 0x3ff00000 /* A34 in the Bias Vector */
+
+/* Bit masks for PIXC_TC */
+
+#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
+#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
+#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
+
+/* Bit masks for HOST_CONTROL */
+
+#define HOSTDP_EN 0x1 /* HOSTDP Enable */
+#define nHOSTDP_EN 0x0
+#define HOSTDP_END 0x2 /* Host Endianess */
+#define nHOSTDP_END 0x0
+#define HOSTDP_DATA_SIZE 0x4 /* Data Size */
+#define nHOSTDP_DATA_SIZE 0x0
+#define HOSTDP_RST 0x8 /* HOSTDP Reset */
+#define nHOSTDP_RST 0x0
+#define HRDY_OVR 0x20 /* HRDY Override */
+#define nHRDY_OVR 0x0
+#define INT_MODE 0x40 /* Interrupt Mode */
+#define nINT_MODE 0x0
+#define BT_EN 0x80 /* Bus Timeout Enable */
+#define nBT_EN 0x0
+#define EHW 0x100 /* Enable Host Write */
+#define nEHW 0x0
+#define EHR 0x200 /* Enable Host Read */
+#define nEHR 0x0
+#define BDR 0x400 /* Burst DMA Requests */
+#define nBDR 0x0
+
+/* Bit masks for HOST_STATUS */
+
+#define DMA_RDY 0x1 /* DMA Ready */
+#define nDMA_RDY 0x0
+#define FIFOFULL 0x2 /* FIFO Full */
+#define nFIFOFULL 0x0
+#define FIFOEMPTY 0x4 /* FIFO Empty */
+#define nFIFOEMPTY 0x0
+#define DMA_CMPLT 0x8 /* DMA Complete */
+#define nDMA_CMPLT 0x0
+#define HSHK 0x10 /* Host Handshake */
+#define nHSHK 0x0
+#define HOSTDP_TOUT 0x20 /* HOSTDP Timeout */
+#define nHOSTDP_TOUT 0x0
+#define HIRQ 0x40 /* Host Interrupt Request */
+#define nHIRQ 0x0
+#define ALLOW_CNFG 0x80 /* Allow New Configuration */
+#define nALLOW_CNFG 0x0
+#define DMA_DIR 0x100 /* DMA Direction */
+#define nDMA_DIR 0x0
+#define BTE 0x200 /* Bus Timeout Enabled */
+#define nBTE 0x0
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define COUNT_TIMEOUT 0x7ff /* HOSTDP Timeout count */
+
+/* Bit masks for MXVR_CONFIG */
+
+#define MXVREN 0x1 /* MXVR Enable */
+#define nMXVREN 0x0
+#define MMSM 0x2 /* MXVR Master/Slave Mode Select */
+#define nMMSM 0x0
+#define ACTIVE 0x4 /* Active Mode */
+#define nACTIVE 0x0
+#define SDELAY 0x8 /* Synchronous Data Delay */
+#define nSDELAY 0x0
+#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */
+#define nNCMRXEN 0x0
+#define RWRRXEN 0x20 /* Remote Write Receive Enable */
+#define nRWRRXEN 0x0
+#define MTXEN 0x40 /* MXVR Transmit Data Enable */
+#define nMTXEN 0x0
+#define MTXONB 0x80 /* MXVR Phy Transmitter On */
+#define nMTXONB 0x0
+#define EPARITY 0x100 /* Even Parity Select */
+#define nEPARITY 0x0
+#define MSB 0x1e00 /* Master Synchronous Boundary */
+#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */
+#define nAPRXEN 0x0
+#define WAKEUP 0x4000 /* Wake-Up */
+#define nWAKEUP 0x0
+#define LMECH 0x8000 /* Lock Mechanism Select */
+#define nLMECH 0x0
+
+/* Bit masks for MXVR_STATE_0 */
+
+#define NACT 0x1 /* Network Activity */
+#define nNACT 0x0
+#define SBLOCK 0x2 /* Super Block Lock */
+#define nSBLOCK 0x0
+#define FMPLLST 0xc /* Frequency Multiply PLL SM State */
+#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */
+#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */
+#define nAPBSY 0x0
+#define APARB 0x200 /* Asynchronous Packet Arbitrating */
+#define nAPARB 0x0
+#define APTX 0x400 /* Asynchronous Packet Transmitting */
+#define nAPTX 0x0
+#define APRX 0x800 /* Receiving Asynchronous Packet */
+#define nAPRX 0x0
+#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */
+#define nCMBSY 0x0
+#define CMARB 0x2000 /* Control Message Arbitrating */
+#define nCMARB 0x0
+#define CMTX 0x4000 /* Control Message Transmitting */
+#define nCMTX 0x0
+#define CMRX 0x8000 /* Receiving Control Message */
+#define nCMRX 0x0
+#define MRXONB 0x10000 /* MRXONB Pin State */
+#define nMRXONB 0x0
+#define RGSIP 0x20000 /* Remote Get Source In Progress */
+#define nRGSIP 0x0
+#define DALIP 0x40000 /* Resource Deallocate In Progress */
+#define nDALIP 0x0
+#define ALIP 0x80000 /* Resource Allocate In Progress */
+#define nALIP 0x0
+#define RRDIP 0x100000 /* Remote Read In Progress */
+#define nRRDIP 0x0
+#define RWRIP 0x200000 /* Remote Write In Progress */
+#define nRWRIP 0x0
+#define FLOCK 0x400000 /* Frame Lock */
+#define nFLOCK 0x0
+#define BLOCK 0x800000 /* Block Lock */
+#define nBLOCK 0x0
+#define RSB 0xf000000 /* Received Synchronous Boundary */
+#define DERRNUM 0xf0000000 /* DMA Error Channel Number */
+
+/* Bit masks for MXVR_STATE_1 */
+
+#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */
+#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */
+#define APCONT 0x100 /* Asynchronous Packet Continuation */
+#define nAPCONT 0x0
+#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */
+#define DMAACTIVE0 0x10000 /* DMA0 Active */
+#define nDMAACTIVE0 0x0
+#define DMAACTIVE1 0x20000 /* DMA1 Active */
+#define nDMAACTIVE1 0x0
+#define DMAACTIVE2 0x40000 /* DMA2 Active */
+#define nDMAACTIVE2 0x0
+#define DMAACTIVE3 0x80000 /* DMA3 Active */
+#define nDMAACTIVE3 0x0
+#define DMAACTIVE4 0x100000 /* DMA4 Active */
+#define nDMAACTIVE4 0x0
+#define DMAACTIVE5 0x200000 /* DMA5 Active */
+#define nDMAACTIVE5 0x0
+#define DMAACTIVE6 0x400000 /* DMA6 Active */
+#define nDMAACTIVE6 0x0
+#define DMAACTIVE7 0x800000 /* DMA7 Active */
+#define nDMAACTIVE7 0x0
+#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */
+#define nDMAPMEN0 0x0
+#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */
+#define nDMAPMEN1 0x0
+#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */
+#define nDMAPMEN2 0x0
+#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */
+#define nDMAPMEN3 0x0
+#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */
+#define nDMAPMEN4 0x0
+#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */
+#define nDMAPMEN5 0x0
+#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */
+#define nDMAPMEN6 0x0
+#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */
+#define nDMAPMEN7 0x0
+
+/* Bit masks for MXVR_INT_STAT_0 */
+
+#define NI2A 0x1 /* Network Inactive to Active */
+#define nNI2A 0x0
+#define NA2I 0x2 /* Network Active to Inactive */
+#define nNA2I 0x0
+#define SBU2L 0x4 /* Super Block Unlock to Lock */
+#define nSBU2L 0x0
+#define SBL2U 0x8 /* Super Block Lock to Unlock */
+#define nSBL2U 0x0
+#define PRU 0x10 /* Position Register Updated */
+#define nPRU 0x0
+#define MPRU 0x20 /* Maximum Position Register Updated */
+#define nMPRU 0x0
+#define DRU 0x40 /* Delay Register Updated */
+#define nDRU 0x0
+#define MDRU 0x80 /* Maximum Delay Register Updated */
+#define nMDRU 0x0
+#define SBU 0x100 /* Synchronous Boundary Updated */
+#define nSBU 0x0
+#define ATU 0x200 /* Allocation Table Updated */
+#define nATU 0x0
+#define FCZ0 0x400 /* Frame Counter 0 Zero */
+#define nFCZ0 0x0
+#define FCZ1 0x800 /* Frame Counter 1 Zero */
+#define nFCZ1 0x0
+#define PERR 0x1000 /* Parity Error */
+#define nPERR 0x0
+#define MH2L 0x2000 /* MRXONB High to Low */
+#define nMH2L 0x0
+#define ML2H 0x4000 /* MRXONB Low to High */
+#define nML2H 0x0
+#define WUP 0x8000 /* Wake-Up Preamble Received */
+#define nWUP 0x0
+#define FU2L 0x10000 /* Frame Unlock to Lock */
+#define nFU2L 0x0
+#define FL2U 0x20000 /* Frame Lock to Unlock */
+#define nFL2U 0x0
+#define BU2L 0x40000 /* Block Unlock to Lock */
+#define nBU2L 0x0
+#define BL2U 0x80000 /* Block Lock to Unlock */
+#define nBL2U 0x0
+#define OBERR 0x100000 /* DMA Out of Bounds Error */
+#define nOBERR 0x0
+#define PFL 0x200000 /* PLL Frequency Locked */
+#define nPFL 0x0
+#define SCZ 0x400000 /* System Clock Counter Zero */
+#define nSCZ 0x0
+#define FERR 0x800000 /* FIFO Error */
+#define nFERR 0x0
+#define CMR 0x1000000 /* Control Message Received */
+#define nCMR 0x0
+#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */
+#define nCMROF 0x0
+#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */
+#define nCMTS 0x0
+#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */
+#define nCMTC 0x0
+#define RWRC 0x10000000 /* Remote Write Control Message Completed */
+#define nRWRC 0x0
+#define BCZ 0x20000000 /* Block Counter Zero */
+#define nBCZ 0x0
+#define BMERR 0x40000000 /* Biphase Mark Coding Error */
+#define nBMERR 0x0
+#define DERR 0x80000000 /* DMA Error */
+#define nDERR 0x0
+
+/* Bit masks for MXVR_INT_STAT_1 */
+
+#define HDONE0 0x1 /* DMA0 Half Done */
+#define nHDONE0 0x0
+#define DONE0 0x2 /* DMA0 Done */
+#define nDONE0 0x0
+#define APR 0x4 /* Asynchronous Packet Received */
+#define nAPR 0x0
+#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */
+#define nAPROF 0x0
+#define HDONE1 0x10 /* DMA1 Half Done */
+#define nHDONE1 0x0
+#define DONE1 0x20 /* DMA1 Done */
+#define nDONE1 0x0
+#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */
+#define nAPTS 0x0
+#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
+#define nAPTC 0x0
+#define HDONE2 0x100 /* DMA2 Half Done */
+#define nHDONE2 0x0
+#define DONE2 0x200 /* DMA2 Done */
+#define nDONE2 0x0
+#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */
+#define nAPRCE 0x0
+#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */
+#define nAPRPE 0x0
+#define HDONE3 0x1000 /* DMA3 Half Done */
+#define nHDONE3 0x0
+#define DONE3 0x2000 /* DMA3 Done */
+#define nDONE3 0x0
+#define HDONE4 0x10000 /* DMA4 Half Done */
+#define nHDONE4 0x0
+#define DONE4 0x20000 /* DMA4 Done */
+#define nDONE4 0x0
+#define HDONE5 0x100000 /* DMA5 Half Done */
+#define nHDONE5 0x0
+#define DONE5 0x200000 /* DMA5 Done */
+#define nDONE5 0x0
+#define HDONE6 0x1000000 /* DMA6 Half Done */
+#define nHDONE6 0x0
+#define DONE6 0x2000000 /* DMA6 Done */
+#define nDONE6 0x0
+#define HDONE7 0x10000000 /* DMA7 Half Done */
+#define nHDONE7 0x0
+#define DONE7 0x20000000 /* DMA7 Done */
+#define nDONE7 0x0
+
+/* Bit masks for MXVR_INT_EN_0 */
+
+#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */
+#define nNI2AEN 0x0
+#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */
+#define nNA2IEN 0x0
+#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */
+#define nSBU2LEN 0x0
+#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */
+#define nSBL2UEN 0x0
+#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */
+#define nPRUEN 0x0
+#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */
+#define nMPRUEN 0x0
+#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */
+#define nDRUEN 0x0
+#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */
+#define nMDRUEN 0x0
+#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */
+#define nSBUEN 0x0
+#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */
+#define nATUEN 0x0
+#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */
+#define nFCZ0EN 0x0
+#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */
+#define nFCZ1EN 0x0
+#define PERREN 0x1000 /* Parity Error Interrupt Enable */
+#define nPERREN 0x0
+#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */
+#define nMH2LEN 0x0
+#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */
+#define nML2HEN 0x0
+#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */
+#define nWUPEN 0x0
+#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */
+#define nFU2LEN 0x0
+#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */
+#define nFL2UEN 0x0
+#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */
+#define nBU2LEN 0x0
+#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */
+#define nBL2UEN 0x0
+#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */
+#define nOBERREN 0x0
+#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */
+#define nPFLEN 0x0
+#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */
+#define nSCZEN 0x0
+#define FERREN 0x800000 /* FIFO Error Interrupt Enable */
+#define nFERREN 0x0
+#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */
+#define nCMREN 0x0
+#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */
+#define nCMROFEN 0x0
+#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
+#define nCMTSEN 0x0
+#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
+#define nCMTCEN 0x0
+#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
+#define nRWRCEN 0x0
+#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */
+#define nBCZEN 0x0
+#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
+#define nBMERREN 0x0
+#define DERREN 0x80000000 /* DMA Error Interrupt Enable */
+#define nDERREN 0x0
+
+/* Bit masks for MXVR_INT_EN_1 */
+
+#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */
+#define nHDONEEN0 0x0
+#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */
+#define nDONEEN0 0x0
+#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */
+#define nAPREN 0x0
+#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
+#define nAPROFEN 0x0
+#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */
+#define nHDONEEN1 0x0
+#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */
+#define nDONEEN1 0x0
+#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
+#define nAPTSEN 0x0
+#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
+#define nAPTCEN 0x0
+#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */
+#define nHDONEEN2 0x0
+#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */
+#define nDONEEN2 0x0
+#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */
+#define nAPRCEEN 0x0
+#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */
+#define nAPRPEEN 0x0
+#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */
+#define nHDONEEN3 0x0
+#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */
+#define nDONEEN3 0x0
+#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */
+#define nHDONEEN4 0x0
+#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */
+#define nDONEEN4 0x0
+#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */
+#define nHDONEEN5 0x0
+#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */
+#define nDONEEN5 0x0
+#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */
+#define nHDONEEN6 0x0
+#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */
+#define nDONEEN6 0x0
+#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */
+#define nHDONEEN7 0x0
+#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */
+#define nDONEEN7 0x0
+
+/* Bit masks for MXVR_POSITION */
+
+#define POSITION 0x3f /* Node Position */
+#define PVALID 0x8000 /* Node Position Valid */
+#define nPVALID 0x0
+
+/* Bit masks for MXVR_MAX_POSITION */
+
+#define MPOSITION 0x3f /* Maximum Node Position */
+#define MPVALID 0x8000 /* Maximum Node Position Valid */
+#define nMPVALID 0x0
+
+/* Bit masks for MXVR_DELAY */
+
+#define DELAY 0x3f /* Node Frame Delay */
+#define DVALID 0x8000 /* Node Frame Delay Valid */
+#define nDVALID 0x0
+
+/* Bit masks for MXVR_MAX_DELAY */
+
+#define MDELAY 0x3f /* Maximum Node Frame Delay */
+#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */
+#define nMDVALID 0x0
+
+/* Bit masks for MXVR_LADDR */
+
+#define LADDR 0xffff /* Logical Address */
+#define LVALID 0x80000000 /* Logical Address Valid */
+#define nLVALID 0x0
+
+/* Bit masks for MXVR_GADDR */
+
+#define GADDRL 0xff /* Group Address Lower Byte */
+#define GVALID 0x8000 /* Group Address Valid */
+#define nGVALID 0x0
+
+/* Bit masks for MXVR_AADDR */
+
+#define AADDR 0xffff /* Alternate Address */
+#define AVALID 0x80000000 /* Alternate Address Valid */
+#define nAVALID 0x0
+
+/* Bit masks for MXVR_ALLOC_0 */
+
+#define CL0 0x7f /* Channel 0 Connection Label */
+#define CIU0 0x80 /* Channel 0 In Use */
+#define nCIU0 0x0
+#define CL1 0x7f00 /* Channel 0 Connection Label */
+#define CIU1 0x8000 /* Channel 0 In Use */
+#define nCIU1 0x0
+#define CL2 0x7f0000 /* Channel 0 Connection Label */
+#define CIU2 0x800000 /* Channel 0 In Use */
+#define nCIU2 0x0
+#define CL3 0x7f000000 /* Channel 0 Connection Label */
+#define CIU3 0x80000000 /* Channel 0 In Use */
+#define nCIU3 0x0
+
+/* Bit masks for MXVR_ALLOC_1 */
+
+#define CL4 0x7f /* Channel 4 Connection Label */
+#define CIU4 0x80 /* Channel 4 In Use */
+#define nCIU4 0x0
+#define CL5 0x7f00 /* Channel 5 Connection Label */
+#define CIU5 0x8000 /* Channel 5 In Use */
+#define nCIU5 0x0
+#define CL6 0x7f0000 /* Channel 6 Connection Label */
+#define CIU6 0x800000 /* Channel 6 In Use */
+#define nCIU6 0x0
+#define CL7 0x7f000000 /* Channel 7 Connection Label */
+#define CIU7 0x80000000 /* Channel 7 In Use */
+#define nCIU7 0x0
+
+/* Bit masks for MXVR_ALLOC_2 */
+
+#define CL8 0x7f /* Channel 8 Connection Label */
+#define CIU8 0x80 /* Channel 8 In Use */
+#define nCIU8 0x0
+#define CL9 0x7f00 /* Channel 9 Connection Label */
+#define CIU9 0x8000 /* Channel 9 In Use */
+#define nCIU9 0x0
+#define CL10 0x7f0000 /* Channel 10 Connection Label */
+#define CIU10 0x800000 /* Channel 10 In Use */
+#define nCIU10 0x0
+#define CL11 0x7f000000 /* Channel 11 Connection Label */
+#define CIU11 0x80000000 /* Channel 11 In Use */
+#define nCIU11 0x0
+
+/* Bit masks for MXVR_ALLOC_3 */
+
+#define CL12 0x7f /* Channel 12 Connection Label */
+#define CIU12 0x80 /* Channel 12 In Use */
+#define nCIU12 0x0
+#define CL13 0x7f00 /* Channel 13 Connection Label */
+#define CIU13 0x8000 /* Channel 13 In Use */
+#define nCIU13 0x0
+#define CL14 0x7f0000 /* Channel 14 Connection Label */
+#define CIU14 0x800000 /* Channel 14 In Use */
+#define nCIU14 0x0
+#define CL15 0x7f000000 /* Channel 15 Connection Label */
+#define CIU15 0x80000000 /* Channel 15 In Use */
+#define nCIU15 0x0
+
+/* Bit masks for MXVR_ALLOC_4 */
+
+#define CL16 0x7f /* Channel 16 Connection Label */
+#define CIU16 0x80 /* Channel 16 In Use */
+#define nCIU16 0x0
+#define CL17 0x7f00 /* Channel 17 Connection Label */
+#define CIU17 0x8000 /* Channel 17 In Use */
+#define nCIU17 0x0
+#define CL18 0x7f0000 /* Channel 18 Connection Label */
+#define CIU18 0x800000 /* Channel 18 In Use */
+#define nCIU18 0x0
+#define CL19 0x7f000000 /* Channel 19 Connection Label */
+#define CIU19 0x80000000 /* Channel 19 In Use */
+#define nCIU19 0x0
+
+/* Bit masks for MXVR_ALLOC_5 */
+
+#define CL20 0x7f /* Channel 20 Connection Label */
+#define CIU20 0x80 /* Channel 20 In Use */
+#define nCIU20 0x0
+#define CL21 0x7f00 /* Channel 21 Connection Label */
+#define CIU21 0x8000 /* Channel 21 In Use */
+#define nCIU21 0x0
+#define CL22 0x7f0000 /* Channel 22 Connection Label */
+#define CIU22 0x800000 /* Channel 22 In Use */
+#define nCIU22 0x0
+#define CL23 0x7f000000 /* Channel 23 Connection Label */
+#define CIU23 0x80000000 /* Channel 23 In Use */
+#define nCIU23 0x0
+
+/* Bit masks for MXVR_ALLOC_6 */
+
+#define CL24 0x7f /* Channel 24 Connection Label */
+#define CIU24 0x80 /* Channel 24 In Use */
+#define nCIU24 0x0
+#define CL25 0x7f00 /* Channel 25 Connection Label */
+#define CIU25 0x8000 /* Channel 25 In Use */
+#define nCIU25 0x0
+#define CL26 0x7f0000 /* Channel 26 Connection Label */
+#define CIU26 0x800000 /* Channel 26 In Use */
+#define nCIU26 0x0
+#define CL27 0x7f000000 /* Channel 27 Connection Label */
+#define CIU27 0x80000000 /* Channel 27 In Use */
+#define nCIU27 0x0
+
+/* Bit masks for MXVR_ALLOC_7 */
+
+#define CL28 0x7f /* Channel 28 Connection Label */
+#define CIU28 0x80 /* Channel 28 In Use */
+#define nCIU28 0x0
+#define CL29 0x7f00 /* Channel 29 Connection Label */
+#define CIU29 0x8000 /* Channel 29 In Use */
+#define nCIU29 0x0
+#define CL30 0x7f0000 /* Channel 30 Connection Label */
+#define CIU30 0x800000 /* Channel 30 In Use */
+#define nCIU30 0x0
+#define CL31 0x7f000000 /* Channel 31 Connection Label */
+#define CIU31 0x80000000 /* Channel 31 In Use */
+#define nCIU31 0x0
+
+/* Bit masks for MXVR_ALLOC_8 */
+
+#define CL32 0x7f /* Channel 32 Connection Label */
+#define CIU32 0x80 /* Channel 32 In Use */
+#define nCIU32 0x0
+#define CL33 0x7f00 /* Channel 33 Connection Label */
+#define CIU33 0x8000 /* Channel 33 In Use */
+#define nCIU33 0x0
+#define CL34 0x7f0000 /* Channel 34 Connection Label */
+#define CIU34 0x800000 /* Channel 34 In Use */
+#define nCIU34 0x0
+#define CL35 0x7f000000 /* Channel 35 Connection Label */
+#define CIU35 0x80000000 /* Channel 35 In Use */
+#define nCIU35 0x0
+
+/* Bit masks for MXVR_ALLOC_9 */
+
+#define CL36 0x7f /* Channel 36 Connection Label */
+#define CIU36 0x80 /* Channel 36 In Use */
+#define nCIU36 0x0
+#define CL37 0x7f00 /* Channel 37 Connection Label */
+#define CIU37 0x8000 /* Channel 37 In Use */
+#define nCIU37 0x0
+#define CL38 0x7f0000 /* Channel 38 Connection Label */
+#define CIU38 0x800000 /* Channel 38 In Use */
+#define nCIU38 0x0
+#define CL39 0x7f000000 /* Channel 39 Connection Label */
+#define CIU39 0x80000000 /* Channel 39 In Use */
+#define nCIU39 0x0
+
+/* Bit masks for MXVR_ALLOC_10 */
+
+#define CL40 0x7f /* Channel 40 Connection Label */
+#define CIU40 0x80 /* Channel 40 In Use */
+#define nCIU40 0x0
+#define CL41 0x7f00 /* Channel 41 Connection Label */
+#define CIU41 0x8000 /* Channel 41 In Use */
+#define nCIU41 0x0
+#define CL42 0x7f0000 /* Channel 42 Connection Label */
+#define CIU42 0x800000 /* Channel 42 In Use */
+#define nCIU42 0x0
+#define CL43 0x7f000000 /* Channel 43 Connection Label */
+#define CIU43 0x80000000 /* Channel 43 In Use */
+#define nCIU43 0x0
+
+/* Bit masks for MXVR_ALLOC_11 */
+
+#define CL44 0x7f /* Channel 44 Connection Label */
+#define CIU44 0x80 /* Channel 44 In Use */
+#define nCIU44 0x0
+#define CL45 0x7f00 /* Channel 45 Connection Label */
+#define CIU45 0x8000 /* Channel 45 In Use */
+#define nCIU45 0x0
+#define CL46 0x7f0000 /* Channel 46 Connection Label */
+#define CIU46 0x800000 /* Channel 46 In Use */
+#define nCIU46 0x0
+#define CL47 0x7f000000 /* Channel 47 Connection Label */
+#define CIU47 0x80000000 /* Channel 47 In Use */
+#define nCIU47 0x0
+
+/* Bit masks for MXVR_ALLOC_12 */
+
+#define CL48 0x7f /* Channel 48 Connection Label */
+#define CIU48 0x80 /* Channel 48 In Use */
+#define nCIU48 0x0
+#define CL49 0x7f00 /* Channel 49 Connection Label */
+#define CIU49 0x8000 /* Channel 49 In Use */
+#define nCIU49 0x0
+#define CL50 0x7f0000 /* Channel 50 Connection Label */
+#define CIU50 0x800000 /* Channel 50 In Use */
+#define nCIU50 0x0
+#define CL51 0x7f000000 /* Channel 51 Connection Label */
+#define CIU51 0x80000000 /* Channel 51 In Use */
+#define nCIU51 0x0
+
+/* Bit masks for MXVR_ALLOC_13 */
+
+#define CL52 0x7f /* Channel 52 Connection Label */
+#define CIU52 0x80 /* Channel 52 In Use */
+#define nCIU52 0x0
+#define CL53 0x7f00 /* Channel 53 Connection Label */
+#define CIU53 0x8000 /* Channel 53 In Use */
+#define nCIU53 0x0
+#define CL54 0x7f0000 /* Channel 54 Connection Label */
+#define CIU54 0x800000 /* Channel 54 In Use */
+#define nCIU54 0x0
+#define CL55 0x7f000000 /* Channel 55 Connection Label */
+#define CIU55 0x80000000 /* Channel 55 In Use */
+#define nCIU55 0x0
+
+/* Bit masks for MXVR_ALLOC_14 */
+
+#define CL56 0x7f /* Channel 56 Connection Label */
+#define CIU56 0x80 /* Channel 56 In Use */
+#define nCIU56 0x0
+#define CL57 0x7f00 /* Channel 57 Connection Label */
+#define CIU57 0x8000 /* Channel 57 In Use */
+#define nCIU57 0x0
+#define CL58 0x7f0000 /* Channel 58 Connection Label */
+#define CIU58 0x800000 /* Channel 58 In Use */
+#define nCIU58 0x0
+#define CL59 0x7f000000 /* Channel 59 Connection Label */
+#define CIU59 0x80000000 /* Channel 59 In Use */
+#define nCIU59 0x0
+
+/* MXVR_SYNC_LCHAN_0 Masks */
+
+#define LCHANPC0 0x0000000Flu
+#define LCHANPC1 0x000000F0lu
+#define LCHANPC2 0x00000F00lu
+#define LCHANPC3 0x0000F000lu
+#define LCHANPC4 0x000F0000lu
+#define LCHANPC5 0x00F00000lu
+#define LCHANPC6 0x0F000000lu
+#define LCHANPC7 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_1 Masks */
+
+#define LCHANPC8 0x0000000Flu
+#define LCHANPC9 0x000000F0lu
+#define LCHANPC10 0x00000F00lu
+#define LCHANPC11 0x0000F000lu
+#define LCHANPC12 0x000F0000lu
+#define LCHANPC13 0x00F00000lu
+#define LCHANPC14 0x0F000000lu
+#define LCHANPC15 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_2 Masks */
+
+#define LCHANPC16 0x0000000Flu
+#define LCHANPC17 0x000000F0lu
+#define LCHANPC18 0x00000F00lu
+#define LCHANPC19 0x0000F000lu
+#define LCHANPC20 0x000F0000lu
+#define LCHANPC21 0x00F00000lu
+#define LCHANPC22 0x0F000000lu
+#define LCHANPC23 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_3 Masks */
+
+#define LCHANPC24 0x0000000Flu
+#define LCHANPC25 0x000000F0lu
+#define LCHANPC26 0x00000F00lu
+#define LCHANPC27 0x0000F000lu
+#define LCHANPC28 0x000F0000lu
+#define LCHANPC29 0x00F00000lu
+#define LCHANPC30 0x0F000000lu
+#define LCHANPC31 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_4 Masks */
+
+#define LCHANPC32 0x0000000Flu
+#define LCHANPC33 0x000000F0lu
+#define LCHANPC34 0x00000F00lu
+#define LCHANPC35 0x0000F000lu
+#define LCHANPC36 0x000F0000lu
+#define LCHANPC37 0x00F00000lu
+#define LCHANPC38 0x0F000000lu
+#define LCHANPC39 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_5 Masks */
+
+#define LCHANPC40 0x0000000Flu
+#define LCHANPC41 0x000000F0lu
+#define LCHANPC42 0x00000F00lu
+#define LCHANPC43 0x0000F000lu
+#define LCHANPC44 0x000F0000lu
+#define LCHANPC45 0x00F00000lu
+#define LCHANPC46 0x0F000000lu
+#define LCHANPC47 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_6 Masks */
+
+#define LCHANPC48 0x0000000Flu
+#define LCHANPC49 0x000000F0lu
+#define LCHANPC50 0x00000F00lu
+#define LCHANPC51 0x0000F000lu
+#define LCHANPC52 0x000F0000lu
+#define LCHANPC53 0x00F00000lu
+#define LCHANPC54 0x0F000000lu
+#define LCHANPC55 0xF0000000lu
+
+
+/* MXVR_SYNC_LCHAN_7 Masks */
+
+#define LCHANPC56 0x0000000Flu
+#define LCHANPC57 0x000000F0lu
+#define LCHANPC58 0x00000F00lu
+#define LCHANPC59 0x0000F000lu
+
+/* Bit masks for MXVR_DMAx_CONFIG */
+
+#define MDMAEN 0x1 /* DMA Channel Enable */
+#define nMDMAEN 0x0
+#define DD 0x2 /* DMA Channel Direction */
+#define nDD 0x0
+#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
+#define nBY4SWAPEN 0x0
+#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
+#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
+#define nBITSWAPEN 0x0
+#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */
+#define nBY2SWAPEN 0x0
+#define MFLOW 0x7000 /* DMA Channel Operation Flow */
+#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */
+#define nFIXEDPM 0x0
+#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */
+#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */
+#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */
+
+/* Bit masks for MXVR_AP_CTL */
+
+#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */
+#define nSTARTAP 0x0
+#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */
+#define nCANCELAP 0x0
+#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */
+#define nRESETAP 0x0
+#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */
+#define nAPRBE0 0x0
+#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */
+#define nAPRBE1 0x0
+
+/* Bit masks for MXVR_APRB_START_ADDR */
+
+#define APRB_START_ADDR 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */
+
+/* Bit masks for MXVR_APRB_CURR_ADDR */
+
+#define APRB_CURR_ADDR 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
+
+/* Bit masks for MXVR_APTB_START_ADDR */
+
+#define APTB_START_ADDR 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */
+
+/* Bit masks for MXVR_APTB_CURR_ADDR */
+
+#define APTB_CURR_ADDR 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
+
+/* Bit masks for MXVR_CM_CTL */
+
+#define STARTCM 0x1 /* Start Control Message Transmission */
+#define nSTARTCM 0x0
+#define CANCELCM 0x2 /* Cancel Control Message Transmission */
+#define nCANCELCM 0x0
+#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */
+#define nCMRBE0 0x0
+#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */
+#define nCMRBE1 0x0
+#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */
+#define nCMRBE2 0x0
+#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */
+#define nCMRBE3 0x0
+#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */
+#define nCMRBE4 0x0
+#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */
+#define nCMRBE5 0x0
+#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */
+#define nCMRBE6 0x0
+#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */
+#define nCMRBE7 0x0
+#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */
+#define nCMRBE8 0x0
+#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */
+#define nCMRBE9 0x0
+#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */
+#define nCMRBE10 0x0
+#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */
+#define nCMRBE11 0x0
+#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */
+#define nCMRBE12 0x0
+#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */
+#define nCMRBE13 0x0
+#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */
+#define nCMRBE14 0x0
+#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */
+#define nCMRBE15 0x0
+
+/* Bit masks for MXVR_CMRB_START_ADDR */
+
+#define CMRB_START_ADDR 0x1fffffe /* Control Message Receive Buffer Start Address */
+
+/* Bit masks for MXVR_CMRB_CURR_ADDR */
+
+#define CMRB_CURR_ADDR 0xffffffff /* Control Message Receive Buffer Current Address */
+
+/* Bit masks for MXVR_CMTB_START_ADDR */
+
+#define CMTB_START_ADDR 0x1fffffe /* Control Message Transmit Buffer Start Address */
+
+/* Bit masks for MXVR_CMTB_CURR_ADDR */
+
+#define CMTB_CURR_ADDR 0xffffffff /* Control Message Transmit Buffer Current Address */
+
+/* Bit masks for MXVR_RRDB_START_ADDR */
+
+#define RRDB_START_ADDR 0x1fffffe /* Remote Read Buffer Start Address */
+
+/* Bit masks for MXVR_RRDB_CURR_ADDR */
+
+#define RRDB_CURR_ADDR 0xffffffff /* Remote Read Buffer Current Address */
+
+/* Bit masks for MXVR_PAT_DATAx */
+
+#define MATCH_DATA_0 0xff /* Pattern Match Data Byte 0 */
+#define MATCH_DATA_1 0xff00 /* Pattern Match Data Byte 1 */
+#define MATCH_DATA_2 0xff0000 /* Pattern Match Data Byte 2 */
+#define MATCH_DATA_3 0xff000000 /* Pattern Match Data Byte 3 */
+
+/* Bit masks for MXVR_PAT_EN_0 */
+
+#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
+#define nMATCH_EN_0_0 0x0
+#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
+#define nMATCH_EN_0_1 0x0
+#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
+#define nMATCH_EN_0_2 0x0
+#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
+#define nMATCH_EN_0_3 0x0
+#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
+#define nMATCH_EN_0_4 0x0
+#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
+#define nMATCH_EN_0_5 0x0
+#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
+#define nMATCH_EN_0_6 0x0
+#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
+#define nMATCH_EN_0_7 0x0
+#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
+#define nMATCH_EN_1_0 0x0
+#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
+#define nMATCH_EN_1_1 0x0
+#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
+#define nMATCH_EN_1_2 0x0
+#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
+#define nMATCH_EN_1_3 0x0
+#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
+#define nMATCH_EN_1_4 0x0
+#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
+#define nMATCH_EN_1_5 0x0
+#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
+#define nMATCH_EN_1_6 0x0
+#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
+#define nMATCH_EN_1_7 0x0
+#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
+#define nMATCH_EN_2_0 0x0
+#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
+#define nMATCH_EN_2_1 0x0
+#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
+#define nMATCH_EN_2_2 0x0
+#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
+#define nMATCH_EN_2_3 0x0
+#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
+#define nMATCH_EN_2_4 0x0
+#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
+#define nMATCH_EN_2_5 0x0
+#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
+#define nMATCH_EN_2_6 0x0
+#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
+#define nMATCH_EN_2_7 0x0
+#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
+#define nMATCH_EN_3_0 0x0
+#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
+#define nMATCH_EN_3_1 0x0
+#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
+#define nMATCH_EN_3_2 0x0
+#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
+#define nMATCH_EN_3_3 0x0
+#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
+#define nMATCH_EN_3_4 0x0
+#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
+#define nMATCH_EN_3_5 0x0
+#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
+#define nMATCH_EN_3_6 0x0
+#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
+#define nMATCH_EN_3_7 0x0
+
+/* Bit masks for MXVR_PAT_EN_1 */
+
+#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
+#define nMATCH_EN_0_0 0x0
+#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
+#define nMATCH_EN_0_1 0x0
+#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
+#define nMATCH_EN_0_2 0x0
+#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
+#define nMATCH_EN_0_3 0x0
+#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
+#define nMATCH_EN_0_4 0x0
+#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
+#define nMATCH_EN_0_5 0x0
+#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
+#define nMATCH_EN_0_6 0x0
+#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
+#define nMATCH_EN_0_7 0x0
+#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
+#define nMATCH_EN_1_0 0x0
+#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
+#define nMATCH_EN_1_1 0x0
+#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
+#define nMATCH_EN_1_2 0x0
+#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
+#define nMATCH_EN_1_3 0x0
+#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
+#define nMATCH_EN_1_4 0x0
+#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
+#define nMATCH_EN_1_5 0x0
+#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
+#define nMATCH_EN_1_6 0x0
+#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
+#define nMATCH_EN_1_7 0x0
+#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
+#define nMATCH_EN_2_0 0x0
+#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
+#define nMATCH_EN_2_1 0x0
+#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
+#define nMATCH_EN_2_2 0x0
+#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
+#define nMATCH_EN_2_3 0x0
+#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
+#define nMATCH_EN_2_4 0x0
+#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
+#define nMATCH_EN_2_5 0x0
+#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
+#define nMATCH_EN_2_6 0x0
+#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
+#define nMATCH_EN_2_7 0x0
+#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
+#define nMATCH_EN_3_0 0x0
+#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
+#define nMATCH_EN_3_1 0x0
+#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
+#define nMATCH_EN_3_2 0x0
+#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
+#define nMATCH_EN_3_3 0x0
+#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
+#define nMATCH_EN_3_4 0x0
+#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
+#define nMATCH_EN_3_5 0x0
+#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
+#define nMATCH_EN_3_6 0x0
+#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
+#define nMATCH_EN_3_7 0x0
+
+/* Bit masks for MXVR_FRAME_CNT_0 */
+
+#define FCNT 0xffff /* Frame Count */
+
+/* Bit masks for MXVR_FRAME_CNT_1 */
+
+#define FCNT 0xffff /* Frame Count */
+
+/* Bit masks for MXVR_ROUTING_0 */
+
+#define TX_CH0 0x3f /* Transmit Channel 0 */
+#define MUTE_CH0 0x80 /* Mute Channel 0 */
+#define nMUTE_CH0 0x0
+#define TX_CH1 0x3f00 /* Transmit Channel 0 */
+#define MUTE_CH1 0x8000 /* Mute Channel 0 */
+#define nMUTE_CH1 0x0
+#define TX_CH2 0x3f0000 /* Transmit Channel 0 */
+#define MUTE_CH2 0x800000 /* Mute Channel 0 */
+#define nMUTE_CH2 0x0
+#define TX_CH3 0x3f000000 /* Transmit Channel 0 */
+#define MUTE_CH3 0x80000000 /* Mute Channel 0 */
+#define nMUTE_CH3 0x0
+
+/* Bit masks for MXVR_ROUTING_1 */
+
+#define TX_CH4 0x3f /* Transmit Channel 4 */
+#define MUTE_CH4 0x80 /* Mute Channel 4 */
+#define nMUTE_CH4 0x0
+#define TX_CH5 0x3f00 /* Transmit Channel 5 */
+#define MUTE_CH5 0x8000 /* Mute Channel 5 */
+#define nMUTE_CH5 0x0
+#define TX_CH6 0x3f0000 /* Transmit Channel 6 */
+#define MUTE_CH6 0x800000 /* Mute Channel 6 */
+#define nMUTE_CH6 0x0
+#define TX_CH7 0x3f000000 /* Transmit Channel 7 */
+#define MUTE_CH7 0x80000000 /* Mute Channel 7 */
+#define nMUTE_CH7 0x0
+
+/* Bit masks for MXVR_ROUTING_2 */
+
+#define TX_CH8 0x3f /* Transmit Channel 8 */
+#define MUTE_CH8 0x80 /* Mute Channel 8 */
+#define nMUTE_CH8 0x0
+#define TX_CH9 0x3f00 /* Transmit Channel 9 */
+#define MUTE_CH9 0x8000 /* Mute Channel 9 */
+#define nMUTE_CH9 0x0
+#define TX_CH10 0x3f0000 /* Transmit Channel 10 */
+#define MUTE_CH10 0x800000 /* Mute Channel 10 */
+#define nMUTE_CH10 0x0
+#define TX_CH11 0x3f000000 /* Transmit Channel 11 */
+#define MUTE_CH11 0x80000000 /* Mute Channel 11 */
+#define nMUTE_CH11 0x0
+
+/* Bit masks for MXVR_ROUTING_3 */
+
+#define TX_CH12 0x3f /* Transmit Channel 12 */
+#define MUTE_CH12 0x80 /* Mute Channel 12 */
+#define nMUTE_CH12 0x0
+#define TX_CH13 0x3f00 /* Transmit Channel 13 */
+#define MUTE_CH13 0x8000 /* Mute Channel 13 */
+#define nMUTE_CH13 0x0
+#define TX_CH14 0x3f0000 /* Transmit Channel 14 */
+#define MUTE_CH14 0x800000 /* Mute Channel 14 */
+#define nMUTE_CH14 0x0
+#define TX_CH15 0x3f000000 /* Transmit Channel 15 */
+#define MUTE_CH15 0x80000000 /* Mute Channel 15 */
+#define nMUTE_CH15 0x0
+
+/* Bit masks for MXVR_ROUTING_4 */
+
+#define TX_CH16 0x3f /* Transmit Channel 16 */
+#define MUTE_CH16 0x80 /* Mute Channel 16 */
+#define nMUTE_CH16 0x0
+#define TX_CH17 0x3f00 /* Transmit Channel 17 */
+#define MUTE_CH17 0x8000 /* Mute Channel 17 */
+#define nMUTE_CH17 0x0
+#define TX_CH18 0x3f0000 /* Transmit Channel 18 */
+#define MUTE_CH18 0x800000 /* Mute Channel 18 */
+#define nMUTE_CH18 0x0
+#define TX_CH19 0x3f000000 /* Transmit Channel 19 */
+#define MUTE_CH19 0x80000000 /* Mute Channel 19 */
+#define nMUTE_CH19 0x0
+
+/* Bit masks for MXVR_ROUTING_5 */
+
+#define TX_CH20 0x3f /* Transmit Channel 20 */
+#define MUTE_CH20 0x80 /* Mute Channel 20 */
+#define nMUTE_CH20 0x0
+#define TX_CH21 0x3f00 /* Transmit Channel 21 */
+#define MUTE_CH21 0x8000 /* Mute Channel 21 */
+#define nMUTE_CH21 0x0
+#define TX_CH22 0x3f0000 /* Transmit Channel 22 */
+#define MUTE_CH22 0x800000 /* Mute Channel 22 */
+#define nMUTE_CH22 0x0
+#define TX_CH23 0x3f000000 /* Transmit Channel 23 */
+#define MUTE_CH23 0x80000000 /* Mute Channel 23 */
+#define nMUTE_CH23 0x0
+
+/* Bit masks for MXVR_ROUTING_6 */
+
+#define TX_CH24 0x3f /* Transmit Channel 24 */
+#define MUTE_CH24 0x80 /* Mute Channel 24 */
+#define nMUTE_CH24 0x0
+#define TX_CH25 0x3f00 /* Transmit Channel 25 */
+#define MUTE_CH25 0x8000 /* Mute Channel 25 */
+#define nMUTE_CH25 0x0
+#define TX_CH26 0x3f0000 /* Transmit Channel 26 */
+#define MUTE_CH26 0x800000 /* Mute Channel 26 */
+#define nMUTE_CH26 0x0
+#define TX_CH27 0x3f000000 /* Transmit Channel 27 */
+#define MUTE_CH27 0x80000000 /* Mute Channel 27 */
+#define nMUTE_CH27 0x0
+
+/* Bit masks for MXVR_ROUTING_7 */
+
+#define TX_CH28 0x3f /* Transmit Channel 28 */
+#define MUTE_CH28 0x80 /* Mute Channel 28 */
+#define nMUTE_CH28 0x0
+#define TX_CH29 0x3f00 /* Transmit Channel 29 */
+#define MUTE_CH29 0x8000 /* Mute Channel 29 */
+#define nMUTE_CH29 0x0
+#define TX_CH30 0x3f0000 /* Transmit Channel 30 */
+#define MUTE_CH30 0x800000 /* Mute Channel 30 */
+#define nMUTE_CH30 0x0
+#define TX_CH31 0x3f000000 /* Transmit Channel 31 */
+#define MUTE_CH31 0x80000000 /* Mute Channel 31 */
+#define nMUTE_CH31 0x0
+
+/* Bit masks for MXVR_ROUTING_8 */
+
+#define TX_CH32 0x3f /* Transmit Channel 32 */
+#define MUTE_CH32 0x80 /* Mute Channel 32 */
+#define nMUTE_CH32 0x0
+#define TX_CH33 0x3f00 /* Transmit Channel 33 */
+#define MUTE_CH33 0x8000 /* Mute Channel 33 */
+#define nMUTE_CH33 0x0
+#define TX_CH34 0x3f0000 /* Transmit Channel 34 */
+#define MUTE_CH34 0x800000 /* Mute Channel 34 */
+#define nMUTE_CH34 0x0
+#define TX_CH35 0x3f000000 /* Transmit Channel 35 */
+#define MUTE_CH35 0x80000000 /* Mute Channel 35 */
+#define nMUTE_CH35 0x0
+
+/* Bit masks for MXVR_ROUTING_9 */
+
+#define TX_CH36 0x3f /* Transmit Channel 36 */
+#define MUTE_CH36 0x80 /* Mute Channel 36 */
+#define nMUTE_CH36 0x0
+#define TX_CH37 0x3f00 /* Transmit Channel 37 */
+#define MUTE_CH37 0x8000 /* Mute Channel 37 */
+#define nMUTE_CH37 0x0
+#define TX_CH38 0x3f0000 /* Transmit Channel 38 */
+#define MUTE_CH38 0x800000 /* Mute Channel 38 */
+#define nMUTE_CH38 0x0
+#define TX_CH39 0x3f000000 /* Transmit Channel 39 */
+#define MUTE_CH39 0x80000000 /* Mute Channel 39 */
+#define nMUTE_CH39 0x0
+
+/* Bit masks for MXVR_ROUTING_10 */
+
+#define TX_CH40 0x3f /* Transmit Channel 40 */
+#define MUTE_CH40 0x80 /* Mute Channel 40 */
+#define nMUTE_CH40 0x0
+#define TX_CH41 0x3f00 /* Transmit Channel 41 */
+#define MUTE_CH41 0x8000 /* Mute Channel 41 */
+#define nMUTE_CH41 0x0
+#define TX_CH42 0x3f0000 /* Transmit Channel 42 */
+#define MUTE_CH42 0x800000 /* Mute Channel 42 */
+#define nMUTE_CH42 0x0
+#define TX_CH43 0x3f000000 /* Transmit Channel 43 */
+#define MUTE_CH43 0x80000000 /* Mute Channel 43 */
+#define nMUTE_CH43 0x0
+
+/* Bit masks for MXVR_ROUTING_11 */
+
+#define TX_CH44 0x3f /* Transmit Channel 44 */
+#define MUTE_CH44 0x80 /* Mute Channel 44 */
+#define nMUTE_CH44 0x0
+#define TX_CH45 0x3f00 /* Transmit Channel 45 */
+#define MUTE_CH45 0x8000 /* Mute Channel 45 */
+#define nMUTE_CH45 0x0
+#define TX_CH46 0x3f0000 /* Transmit Channel 46 */
+#define MUTE_CH46 0x800000 /* Mute Channel 46 */
+#define nMUTE_CH46 0x0
+#define TX_CH47 0x3f000000 /* Transmit Channel 47 */
+#define MUTE_CH47 0x80000000 /* Mute Channel 47 */
+#define nMUTE_CH47 0x0
+
+/* Bit masks for MXVR_ROUTING_12 */
+
+#define TX_CH48 0x3f /* Transmit Channel 48 */
+#define MUTE_CH48 0x80 /* Mute Channel 48 */
+#define nMUTE_CH48 0x0
+#define TX_CH49 0x3f00 /* Transmit Channel 49 */
+#define MUTE_CH49 0x8000 /* Mute Channel 49 */
+#define nMUTE_CH49 0x0
+#define TX_CH50 0x3f0000 /* Transmit Channel 50 */
+#define MUTE_CH50 0x800000 /* Mute Channel 50 */
+#define nMUTE_CH50 0x0
+#define TX_CH51 0x3f000000 /* Transmit Channel 51 */
+#define MUTE_CH51 0x80000000 /* Mute Channel 51 */
+#define nMUTE_CH51 0x0
+
+/* Bit masks for MXVR_ROUTING_13 */
+
+#define TX_CH52 0x3f /* Transmit Channel 52 */
+#define MUTE_CH52 0x80 /* Mute Channel 52 */
+#define nMUTE_CH52 0x0
+#define TX_CH53 0x3f00 /* Transmit Channel 53 */
+#define MUTE_CH53 0x8000 /* Mute Channel 53 */
+#define nMUTE_CH53 0x0
+#define TX_CH54 0x3f0000 /* Transmit Channel 54 */
+#define MUTE_CH54 0x800000 /* Mute Channel 54 */
+#define nMUTE_CH54 0x0
+#define TX_CH55 0x3f000000 /* Transmit Channel 55 */
+#define MUTE_CH55 0x80000000 /* Mute Channel 55 */
+#define nMUTE_CH55 0x0
+
+/* Bit masks for MXVR_ROUTING_14 */
+
+#define TX_CH56 0x3f /* Transmit Channel 56 */
+#define MUTE_CH56 0x80 /* Mute Channel 56 */
+#define nMUTE_CH56 0x0
+#define TX_CH57 0x3f00 /* Transmit Channel 57 */
+#define MUTE_CH57 0x8000 /* Mute Channel 57 */
+#define nMUTE_CH57 0x0
+#define TX_CH58 0x3f0000 /* Transmit Channel 58 */
+#define MUTE_CH58 0x800000 /* Mute Channel 58 */
+#define nMUTE_CH58 0x0
+#define TX_CH59 0x3f000000 /* Transmit Channel 59 */
+#define MUTE_CH59 0x80000000 /* Mute Channel 59 */
+#define nMUTE_CH59 0x0
+
+/* Bit masks for MXVR_BLOCK_CNT */
+
+#define BCNT 0xffff /* Block Count */
+
+/* Bit masks for MXVR_CLK_CTL */
+
+#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */
+#define nMXTALCEN 0x0
+#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */
+#define nMXTALFEN 0x0
+#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */
+#define CLKX3SEL 0x80 /* Clock Generation Source Select */
+#define nCLKX3SEL 0x0
+#define MMCLKEN 0x100 /* Master Clock Enable */
+#define nMMCLKEN 0x0
+#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */
+#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */
+#define MBCLKEN 0x10000 /* Bit Clock Enable */
+#define nMBCLKEN 0x0
+#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */
+#define INVRX 0x800000 /* Invert Receive Data */
+#define nINVRX 0x0
+#define MFSEN 0x1000000 /* Frame Sync Enable */
+#define nMFSEN 0x0
+#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */
+#define MFSSEL 0x60000000 /* Frame Sync Select */
+#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */
+#define nMFSSYNC 0x0
+
+/* Bit masks for MXVR_CDRPLL_CTL */
+
+#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */
+#define nCDRSMEN 0x0
+#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */
+#define nCDRRSTB 0x0
+#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */
+#define nCDRSVCO 0x0
+#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */
+#define nCDRMODE 0x0
+#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */
+#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */
+#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */
+#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */
+#define nCDRSHPEN 0x0
+#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
+
+/* Bit masks for MXVR_FMPLL_CTL */
+
+#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */
+#define nFMSMEN 0x0
+#define FMRSTB 0x2 /* MXVR FMPLL Reset */
+#define nFMRSTB 0x0
+#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */
+#define nFMSVCO 0x0
+#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */
+#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */
+#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */
+
+/* Bit masks for MXVR_PIN_CTL */
+
+#define MTXONBOD 0x1 /* MTXONB Open Drain Select */
+#define nMTXONBOD 0x0
+#define MTXONBG 0x2 /* MTXONB Gates MTX Select */
+#define nMTXONBG 0x0
+#define MFSOE 0x10 /* MFS Output Enable */
+#define nMFSOE 0x0
+#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */
+#define nMFSGPSEL 0x0
+#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */
+#define nMFSGPDAT 0x0
+
+/* Bit masks for MXVR_SCLK_CNT */
+
+#define SCNT 0xffff /* System Clock Count */
+
+/* Bit masks for KPAD_CTL */
+
+#define KPAD_EN 0x1 /* Keypad Enable */
+#define nKPAD_EN 0x0
+#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
+#define nKPAD_IRQMODE 0x0 /* Interrupt Disabled */
+#define KPAD_IRQMODE_SK 0x2 /* Single key (single row, single column) press interrupt enable */
+#define KPAD_IRQMODE_MK 0x4 /* Single key press multiple key press interrupt enable */
+#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
+#define KPAD_COLEN 0xe000 /* Column Enable Width */
+
+
+#define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
+#define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
+
+/* Bit masks for KPAD_PRESCALE */
+
+#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
+
+#define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale). Key Prescale Value (5:0) */
+
+
+/* Bit masks for KPAD_MSEL */
+
+#define DBON_SCALE 0xff /* Debounce Scale Value */
+#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
+
+#define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale). Debounce Delay Multiplier Select [7:0] */
+#define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale). Column Driver Period Multiplier Select [15:8] */
+
+
+/* Bit masks for KPAD_ROWCOL */
+
+#define KPAD_ROW 0xff /* Rows Pressed */
+#define KPAD_COL 0xff00 /* Columns Pressed */
+
+/* Bit masks for KPAD_STAT */
+
+#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
+#define nKPAD_IRQ 0x0
+#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
+#define KPAD_PRESSED 0x8 /* Key press current status */
+#define nKPAD_PRESSED 0x0
+#define KPAD_NO_KEY 0x0 /* No Keypress Status*/
+#define KPAD_SINGLE_KEY 0x2 /* Single Keypress Status */
+#define KPAD_MKSROWCOL 0x4 /* Multiple Keypress in the same row or column Status */
+#define KPAD_MKMROWCOL 0x6 /* Multiple Keypress in the same multiple rows and multiple columns Status */
+
+/* Bit masks for KPAD_SOFTEVAL */
+
+#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
+#define nKPAD_SOFTEVAL_E 0x0
+
+/* Bit masks for SDH_COMMAND */
+
+#define CMD_IDX 0x3f /* Command Index */
+#define CMD_RSP 0x40 /* Response */
+#define nCMD_RSP 0x0
+#define CMD_L_RSP 0x80 /* Long Response */
+#define nCMD_L_RSP 0x0
+#define CMD_INT_E 0x100 /* Command Interrupt */
+#define nCMD_INT_E 0x0
+#define CMD_PEND_E 0x200 /* Command Pending */
+#define nCMD_PEND_E 0x0
+#define CMD_E 0x400 /* Command Enable */
+#define nCMD_E 0x0
+
+/* Bit masks for SDH_PWR_CTL */
+
+#define PWR_ON 0x3 /* Power On */
+#if 0
+#define TBD 0x3c /* TBD */
+#endif
+#define SD_CMD_OD 0x40 /* Open Drain Output */
+#define nSD_CMD_OD 0x0
+#define ROD_CTL 0x80 /* Rod Control */
+#define nROD_CTL 0x0
+
+/* Bit masks for SDH_CLK_CTL */
+
+#define CLKDIV 0xff /* MC_CLK Divisor */
+#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
+#define nCLK_E 0x0
+#define PWR_SV_E 0x200 /* Power Save Enable */
+#define nPWR_SV_E 0x0
+#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
+#define nCLKDIV_BYPASS 0x0
+#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
+#define nWIDE_BUS 0x0
+
+/* Bit masks for SDH_RESP_CMD */
+
+#define RESP_CMD 0x3f /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+
+#define DTX_E 0x1 /* Data Transfer Enable */
+#define nDTX_E 0x0
+#define DTX_DIR 0x2 /* Data Transfer Direction */
+#define nDTX_DIR 0x0
+#define DTX_MODE 0x4 /* Data Transfer Mode */
+#define nDTX_MODE 0x0
+#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
+#define nDTX_DMA_E 0x0
+#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+
+#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
+#define nCMD_CRC_FAIL 0x0
+#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
+#define nDAT_CRC_FAIL 0x0
+#define CMD_TIMEOUT 0x4 /* CMD Time Out */
+#define nCMD_TIMEOUT 0x0
+#define DAT_TIMEOUT 0x8 /* Data Time Out */
+#define nDAT_TIMEOUT 0x0
+#define TX_UNDERRUN 0x10 /* Transmit Underrun */
+#define nTX_UNDERRUN 0x0
+#define RX_OVERRUN 0x20 /* Receive Overrun */
+#define nRX_OVERRUN 0x0
+#define CMD_RESP_END 0x40 /* CMD Response End */
+#define nCMD_RESP_END 0x0
+#define CMD_SENT 0x80 /* CMD Sent */
+#define nCMD_SENT 0x0
+#define DAT_END 0x100 /* Data End */
+#define nDAT_END 0x0
+#define START_BIT_ERR 0x200 /* Start Bit Error */
+#define nSTART_BIT_ERR 0x0
+#define DAT_BLK_END 0x400 /* Data Block End */
+#define nDAT_BLK_END 0x0
+#define CMD_ACT 0x800 /* CMD Active */
+#define nCMD_ACT 0x0
+#define TX_ACT 0x1000 /* Transmit Active */
+#define nTX_ACT 0x0
+#define RX_ACT 0x2000 /* Receive Active */
+#define nRX_ACT 0x0
+#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
+#define nTX_FIFO_STAT 0x0
+#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
+#define nRX_FIFO_STAT 0x0
+#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
+#define nTX_FIFO_FULL 0x0
+#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
+#define nRX_FIFO_FULL 0x0
+#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
+#define nTX_FIFO_ZERO 0x0
+#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
+#define nRX_DAT_ZERO 0x0
+#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
+#define nTX_DAT_RDY 0x0
+#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
+#define nRX_FIFO_RDY 0x0
+
+/* Bit masks for SDH_STATUS_CLR */
+
+#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
+#define nCMD_CRC_FAIL_STAT 0x0
+#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
+#define nDAT_CRC_FAIL_STAT 0x0
+#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
+#define nCMD_TIMEOUT_STAT 0x0
+#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
+#define nDAT_TIMEOUT_STAT 0x0
+#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
+#define nTX_UNDERRUN_STAT 0x0
+#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
+#define nRX_OVERRUN_STAT 0x0
+#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
+#define nCMD_RESP_END_STAT 0x0
+#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
+#define nCMD_SENT_STAT 0x0
+#define DAT_END_STAT 0x100 /* Data End Status */
+#define nDAT_END_STAT 0x0
+#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
+#define nSTART_BIT_ERR_STAT 0x0
+#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
+#define nDAT_BLK_END_STAT 0x0
+
+/* Bit masks for SDH_MASK0 */
+
+#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
+#define nCMD_CRC_FAIL_MASK 0x0
+#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
+#define nDAT_CRC_FAIL_MASK 0x0
+#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
+#define nCMD_TIMEOUT_MASK 0x0
+#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
+#define nDAT_TIMEOUT_MASK 0x0
+#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
+#define nTX_UNDERRUN_MASK 0x0
+#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
+#define nRX_OVERRUN_MASK 0x0
+#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
+#define nCMD_RESP_END_MASK 0x0
+#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
+#define nCMD_SENT_MASK 0x0
+#define DAT_END_MASK 0x100 /* Data End Mask */
+#define nDAT_END_MASK 0x0
+#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
+#define nSTART_BIT_ERR_MASK 0x0
+#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
+#define nDAT_BLK_END_MASK 0x0
+#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
+#define nCMD_ACT_MASK 0x0
+#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
+#define nTX_ACT_MASK 0x0
+#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
+#define nRX_ACT_MASK 0x0
+#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
+#define nTX_FIFO_STAT_MASK 0x0
+#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
+#define nRX_FIFO_STAT_MASK 0x0
+#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
+#define nTX_FIFO_FULL_MASK 0x0
+#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
+#define nRX_FIFO_FULL_MASK 0x0
+#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
+#define nTX_FIFO_ZERO_MASK 0x0
+#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
+#define nRX_DAT_ZERO_MASK 0x0
+#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
+#define nTX_DAT_RDY_MASK 0x0
+#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
+#define nRX_FIFO_RDY_MASK 0x0
+
+/* Bit masks for SDH_FIFO_CNT */
+
+#define FIFO_COUNT 0x7fff /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+
+#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
+#define nSDIO_INT_DET 0x0
+#define SD_CARD_DET 0x10 /* SD Card Detect */
+#define nSD_CARD_DET 0x0
+
+/* Bit masks for SDH_E_MASK */
+
+#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
+#define nSDIO_MSK 0x0
+#define SCD_MSK 0x40 /* Mask Card Detect */
+#define nSCD_MSK 0x0
+
+/* Bit masks for SDH_CFG */
+
+#define CLKS_EN 0x1 /* Clocks Enable */
+#define nCLKS_EN 0x0
+#define SD4E 0x4 /* SDIO 4-Bit Enable */
+#define nSD4E 0x0
+#define MWE 0x8 /* Moving Window Enable */
+#define nMWE 0x0
+#define SD_RST 0x10 /* SDMMC Reset */
+#define nSD_RST 0x0
+#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
+#define nPUP_SDDAT 0x0
+#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
+#define nPUP_SDDAT3 0x0
+#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
+#define nPD_SDDAT3 0x0
+
+/* Bit masks for SDH_RD_WAIT_EN */
+
+#define RWR 0x1 /* Read Wait Request */
+#define nRWR 0x0
+
+/* Bit masks for ATAPI_CONTROL */
+
+#define PIO_START 0x1 /* Start PIO/Reg Op */
+#define nPIO_START 0x0
+#define MULTI_START 0x2 /* Start Multi-DMA Op */
+#define nMULTI_START 0x0
+#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
+#define nULTRA_START 0x0
+#define XFER_DIR 0x8 /* Transfer Direction */
+#define nXFER_DIR 0x0
+#define IORDY_EN 0x10 /* IORDY Enable */
+#define nIORDY_EN 0x0
+#define FIFO_FLUSH 0x20 /* Flush FIFOs */
+#define nFIFO_FLUSH 0x0
+#define SOFT_RST 0x40 /* Soft Reset */
+#define nSOFT_RST 0x0
+#define DEV_RST 0x80 /* Device Reset */
+#define nDEV_RST 0x0
+#define TFRCNT_RST 0x100 /* Trans Count Reset */
+#define nTFRCNT_RST 0x0
+#define END_ON_TERM 0x200 /* End/Terminate Select */
+#define nEND_ON_TERM 0x0
+#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
+#define nPIO_USE_DMA 0x0
+#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+
+#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
+#define nPIO_XFER_ON 0x0
+#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
+#define nMULTI_XFER_ON 0x0
+#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
+#define nULTRA_XFER_ON 0x0
+#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+
+#define DEV_ADDR 0x1f /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+
+#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
+#define nATAPI_DEV_INT_MASK 0x0
+#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
+#define nPIO_DONE_MASK 0x0
+#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
+#define nMULTI_DONE_MASK 0x0
+#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
+#define nUDMAIN_DONE_MASK 0x0
+#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
+#define nUDMAOUT_DONE_MASK 0x0
+#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
+#define nHOST_TERM_XFER_MASK 0x0
+#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
+#define nMULTI_TERM_MASK 0x0
+#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define nUDMAIN_TERM_MASK 0x0
+#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
+#define nUDMAOUT_TERM_MASK 0x0
+
+/* Bit masks for ATAPI_INT_STATUS */
+
+#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
+#define nATAPI_DEV_INT 0x0
+#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
+#define nPIO_DONE_INT 0x0
+#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
+#define nMULTI_DONE_INT 0x0
+#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
+#define nUDMAIN_DONE_INT 0x0
+#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
+#define nUDMAOUT_DONE_INT 0x0
+#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
+#define nHOST_TERM_XFER_INT 0x0
+#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
+#define nMULTI_TERM_INT 0x0
+#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define nUDMAIN_TERM_INT 0x0
+#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
+#define nUDMAOUT_TERM_INT 0x0
+
+/* Bit masks for ATAPI_LINE_STATUS */
+
+#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
+#define nATAPI_INTR 0x0
+#define ATAPI_DASP 0x2 /* Device dasp to host line status */
+#define nATAPI_DASP 0x0
+#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
+#define nATAPI_CS0N 0x0
+#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
+#define nATAPI_CS1N 0x0
+#define ATAPI_ADDR 0x70 /* ATAPI address line status */
+#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
+#define nATAPI_DMAREQ 0x0
+#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
+#define nATAPI_DMAACKN 0x0
+#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
+#define nATAPI_DIOWN 0x0
+#define ATAPI_DIORN 0x400 /* ATAPI read line status */
+#define nATAPI_DIORN 0x0
+#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
+#define nATAPI_IORDY 0x0
+
+/* Bit masks for ATAPI_SM_STATE */
+
+#define PIO_CSTATE 0xf /* PIO mode state machine current state */
+#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
+#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
+#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+
+#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
+#define nATAPI_HOST_TERM 0x0
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+
+#define T2_REG 0xff /* End of cycle time for register access transfers */
+#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+
+#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
+#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
+#define T4_REG 0xf000 /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+
+#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+
+#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
+#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+
+#define TKW 0xff /* Selects DIOW negated pulsewidth */
+#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+
+#define TH 0xff /* Selects DIOW data hold */
+#define TEOC 0xff00 /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+
+#define TACK 0xff /* Selects setup and hold times for TACK */
+#define TENV 0xff00 /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+
+#define TDVS 0xff /* Selects data valid setup time */
+#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+
+#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define TMLI 0xff00 /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+
+#define TZAH 0xff /* Selects minimum delay required for output */
+#define READY_PAUSE 0xff00 /* Selects ready to pause */
+
+/* Bit masks for TIMER_ENABLE1 */
+
+#define TIMEN8 0x1 /* Timer 8 Enable */
+#define nTIMEN8 0x0
+#define TIMEN9 0x2 /* Timer 9 Enable */
+#define nTIMEN9 0x0
+#define TIMEN10 0x4 /* Timer 10 Enable */
+#define nTIMEN10 0x0
+
+/* Bit masks for TIMER_DISABLE1 */
+
+#define TIMDIS8 0x1 /* Timer 8 Disable */
+#define nTIMDIS8 0x0
+#define TIMDIS9 0x2 /* Timer 9 Disable */
+#define nTIMDIS9 0x0
+#define TIMDIS10 0x4 /* Timer 10 Disable */
+#define nTIMDIS10 0x0
+
+/* Bit masks for TIMER_STATUS1 */
+
+#define TIMIL8 0x1 /* Timer 8 Interrupt */
+#define nTIMIL8 0x0
+#define TIMIL9 0x2 /* Timer 9 Interrupt */
+#define nTIMIL9 0x0
+#define TIMIL10 0x4 /* Timer 10 Interrupt */
+#define nTIMIL10 0x0
+#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
+#define nTOVF_ERR8 0x0
+#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
+#define nTOVF_ERR9 0x0
+#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
+#define nTOVF_ERR10 0x0
+#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
+#define nTRUN8 0x0
+#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
+#define nTRUN9 0x0
+#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
+#define nTRUN10 0x0
+
+/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS 0x7f /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
+#define nENABLE_SUSPENDM 0x0
+#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
+#define nSUSPEND_MODE 0x0
+#define RESUME_MODE 0x4 /* DMA Mode */
+#define nRESUME_MODE 0x0
+#define RESET 0x8 /* Reset indicator */
+#define nRESET 0x0
+#define HS_MODE 0x10 /* High Speed mode indicator */
+#define nHS_MODE 0x0
+#define HS_ENABLE 0x20 /* high Speed Enable */
+#define nHS_ENABLE 0x0
+#define SOFT_CONN 0x40 /* Soft connect */
+#define nSOFT_CONN 0x0
+#define ISO_UPDATE 0x80 /* Isochronous update */
+#define nISO_UPDATE 0x0
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
+#define nEP0_TX 0x0
+#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
+#define nEP1_TX 0x0
+#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
+#define nEP2_TX 0x0
+#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
+#define nEP3_TX 0x0
+#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
+#define nEP4_TX 0x0
+#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
+#define nEP5_TX 0x0
+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
+#define nEP6_TX 0x0
+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
+#define nEP7_TX 0x0
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
+#define nEP1_RX 0x0
+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
+#define nEP2_RX 0x0
+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
+#define nEP3_RX 0x0
+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
+#define nEP4_RX 0x0
+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
+#define nEP5_RX 0x0
+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
+#define nEP6_RX 0x0
+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
+#define nEP7_RX 0x0
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
+#define nEP0_TX_E 0x0
+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
+#define nEP1_TX_E 0x0
+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
+#define nEP2_TX_E 0x0
+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
+#define nEP3_TX_E 0x0
+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
+#define nEP4_TX_E 0x0
+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
+#define nEP5_TX_E 0x0
+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
+#define nEP6_TX_E 0x0
+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
+#define nEP7_TX_E 0x0
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
+#define nEP1_RX_E 0x0
+#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
+#define nEP2_RX_E 0x0
+#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
+#define nEP3_RX_E 0x0
+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
+#define nEP4_RX_E 0x0
+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
+#define nEP5_RX_E 0x0
+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
+#define nEP6_RX_E 0x0
+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
+#define nEP7_RX_E 0x0
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B 0x1 /* Suspend indicator */
+#define nSUSPEND_B 0x0
+#define RESUME_B 0x2 /* Resume indicator */
+#define nRESUME_B 0x0
+#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
+#define nRESET_OR_BABLE_B 0x0
+#define SOF_B 0x8 /* Start of frame */
+#define nSOF_B 0x0
+#define CONN_B 0x10 /* Connection indicator */
+#define nCONN_B 0x0
+#define DISCON_B 0x20 /* Disconnect indicator */
+#define nDISCON_B 0x0
+#define SESSION_REQ_B 0x40 /* Session Request */
+#define nSESSION_REQ_B 0x0
+#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
+#define nVBUS_ERROR_B 0x0
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
+#define nSUSPEND_BE 0x0
+#define RESUME_BE 0x2 /* Resume indicator int enable */
+#define nRESUME_BE 0x0
+#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
+#define nRESET_OR_BABLE_BE 0x0
+#define SOF_BE 0x8 /* Start of frame int enable */
+#define nSOF_BE 0x0
+#define CONN_BE 0x10 /* Connection indicator int enable */
+#define nCONN_BE 0x0
+#define DISCON_BE 0x20 /* Disconnect indicator int enable */
+#define nDISCON_BE 0x0
+#define SESSION_REQ_BE 0x40 /* Session Request int enable */
+#define nSESSION_REQ_BE 0x0
+#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
+#define nVBUS_ERROR_BE 0x0
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER 0x7ff /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT 0xf /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA 0x1 /* enables USB module */
+#define nGLOBAL_ENA 0x0
+#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
+#define nEP1_TX_ENA 0x0
+#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
+#define nEP2_TX_ENA 0x0
+#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
+#define nEP3_TX_ENA 0x0
+#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
+#define nEP4_TX_ENA 0x0
+#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
+#define nEP5_TX_ENA 0x0
+#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
+#define nEP6_TX_ENA 0x0
+#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
+#define nEP7_TX_ENA 0x0
+#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
+#define nEP1_RX_ENA 0x0
+#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
+#define nEP2_RX_ENA 0x0
+#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
+#define nEP3_RX_ENA 0x0
+#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
+#define nEP4_RX_ENA 0x0
+#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
+#define nEP5_RX_ENA 0x0
+#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
+#define nEP6_RX_ENA 0x0
+#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
+#define nEP7_RX_ENA 0x0
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION 0x1 /* session indicator */
+#define nSESSION 0x0
+#define HOST_REQ 0x2 /* Host negotiation request */
+#define nHOST_REQ 0x0
+#define HOST_MODE 0x4 /* indicates USBDRC is a host */
+#define nHOST_MODE 0x0
+#define VBUS0 0x8 /* Vbus level indicator[0] */
+#define nVBUS0 0x0
+#define VBUS1 0x10 /* Vbus level indicator[1] */
+#define nVBUS1 0x0
+#define LSDEV 0x20 /* Low-speed indicator */
+#define nLSDEV 0x0
+#define FSDEV 0x40 /* Full or High-speed indicator */
+#define nFSDEV 0x0
+#define B_DEVICE 0x80 /* A' or 'B' device indicator */
+#define nB_DEVICE 0x0
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
+#define nDRIVE_VBUS_ON 0x0
+#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
+#define nDRIVE_VBUS_OFF 0x0
+#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
+#define nCHRG_VBUS_START 0x0
+#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
+#define nCHRG_VBUS_END 0x0
+#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
+#define nDISCHRG_VBUS_START 0x0
+#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
+#define nDISCHRG_VBUS_END 0x0
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
+#define nDRIVE_VBUS_ON_ENA 0x0
+#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
+#define nDRIVE_VBUS_OFF_ENA 0x0
+#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
+#define nCHRG_VBUS_START_ENA 0x0
+#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
+#define nCHRG_VBUS_END_ENA 0x0
+#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
+#define nDISCHRG_VBUS_START_ENA 0x0
+#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
+#define nDISCHRG_VBUS_END_ENA 0x0
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY 0x1 /* data packet receive indicator */
+#define nRXPKTRDY 0x0
+#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
+#define nTXPKTRDY 0x0
+#define STALL_SENT 0x4 /* STALL handshake sent */
+#define nSTALL_SENT 0x0
+#define DATAEND 0x8 /* Data end indicator */
+#define nDATAEND 0x0
+#define SETUPEND 0x10 /* Setup end */
+#define nSETUPEND 0x0
+#define SENDSTALL 0x20 /* Send STALL handshake */
+#define nSENDSTALL 0x0
+#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
+#define nSERVICED_RXPKTRDY 0x0
+#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
+#define nSERVICED_SETUPEND 0x0
+#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
+#define nFLUSHFIFO 0x0
+#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
+#define nSTALL_RECEIVED_H 0x0
+#define SETUPPKT_H 0x8 /* send Setup token host mode */
+#define nSETUPPKT_H 0x0
+#define ERROR_H 0x10 /* timeout error indicator host mode */
+#define nERROR_H 0x0
+#define REQPKT_H 0x20 /* Request an IN transaction host mode */
+#define nREQPKT_H 0x0
+#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
+#define nSTATUSPKT_H 0x0
+#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
+#define nNAK_TIMEOUT_H 0x0
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
+#define nTXPKTRDY_T 0x0
+#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
+#define nFIFO_NOT_EMPTY_T 0x0
+#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
+#define nUNDERRUN_T 0x0
+#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
+#define nFLUSHFIFO_T 0x0
+#define STALL_SEND_T 0x10 /* issue a Stall handshake */
+#define nSTALL_SEND_T 0x0
+#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
+#define nSTALL_SENT_T 0x0
+#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_T 0x0
+#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
+#define nINCOMPTX_T 0x0
+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_T 0x0
+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
+#define nFORCE_DATATOGGLE_T 0x0
+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_T 0x0
+#define ISO_T 0x4000 /* enable Isochronous transfers */
+#define nISO_T 0x0
+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOSET_T 0x0
+#define ERROR_TH 0x4 /* error condition host mode */
+#define nERROR_TH 0x0
+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_TH 0x0
+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
+#define nNAK_TIMEOUT_TH 0x0
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
+#define nRXPKTRDY_R 0x0
+#define FIFO_FULL_R 0x2 /* FIFO not empty */
+#define nFIFO_FULL_R 0x0
+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
+#define nOVERRUN_R 0x0
+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
+#define nDATAERROR_R 0x0
+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
+#define nFLUSHFIFO_R 0x0
+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
+#define nSTALL_SEND_R 0x0
+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
+#define nSTALL_SENT_R 0x0
+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
+#define nCLEAR_DATATOGGLE_R 0x0
+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
+#define nINCOMPRX_R 0x0
+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
+#define nDMAREQMODE_R 0x0
+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
+#define nDISNYET_R 0x0
+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
+#define nDMAREQ_ENA_R 0x0
+#define ISO_R 0x4000 /* enable Isochronous transfers */
+#define nISO_R 0x0
+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
+#define nAUTOCLEAR_R 0x0
+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
+#define nERROR_RH 0x0
+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
+#define nREQPKT_RH 0x0
+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
+#define nSTALL_RECEIVED_RH 0x0
+#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
+#define nINCOMPRX_RH 0x0
+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
+#define nDMAREQMODE_RH 0x0
+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
+#define nAUTOREQ_RH 0x0
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T 0xf /* EP number */
+#define PROTOCOL_T 0xc /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R 0xf /* EP number */
+#define PROTOCOL_R 0xc /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
+#define nDMA0_INT 0x0
+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
+#define nDMA1_INT 0x0
+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
+#define nDMA2_INT 0x0
+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
+#define nDMA3_INT 0x0
+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
+#define nDMA4_INT 0x0
+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
+#define nDMA5_INT 0x0
+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
+#define nDMA6_INT 0x0
+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
+#define nDMA7_INT 0x0
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA 0x1 /* DMA enable */
+#define nDMA_ENA 0x0
+#define DIRECTION 0x2 /* direction of DMA transfer */
+#define nDIRECTION 0x0
+#define MODE 0x4 /* DMA Bus error */
+#define nMODE 0x0
+#define INT_ENA 0x8 /* Interrupt enable */
+#define nINT_ENA 0x0
+#define EPNUM 0xf0 /* EP number */
+#define BUSERROR 0x100 /* DMA Bus error */
+#define nBUSERROR 0x0
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* ******************************************* */
+/* MULTI BIT MACRO ENUMERATIONS */
+/* ******************************************* */
+
+/* ************************ */
+/* MXVR Address Offsets */
+/* ************************ */
+
+/* Control Message Receive Buffer (CMRB) Address Offsets */
+
+#define CMRB_STRIDE 0x00000016lu
+
+#define CMRB_DST_OFFSET 0x00000000lu
+#define CMRB_SRC_OFFSET 0x00000002lu
+#define CMRB_DATA_OFFSET 0x00000005lu
+
+/* Control Message Transmit Buffer (CMTB) Address Offsets */
+
+#define CMTB_PRIO_OFFSET 0x00000000lu
+#define CMTB_DST_OFFSET 0x00000002lu
+#define CMTB_SRC_OFFSET 0x00000004lu
+#define CMTB_TYPE_OFFSET 0x00000006lu
+#define CMTB_DATA_OFFSET 0x00000007lu
+
+#define CMTB_ANSWER_OFFSET 0x0000000Alu
+
+#define CMTB_STAT_N_OFFSET 0x00000018lu
+#define CMTB_STAT_A_OFFSET 0x00000016lu
+#define CMTB_STAT_D_OFFSET 0x0000000Elu
+#define CMTB_STAT_R_OFFSET 0x00000014lu
+#define CMTB_STAT_W_OFFSET 0x00000014lu
+#define CMTB_STAT_G_OFFSET 0x00000014lu
+
+/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
+
+#define APRB_STRIDE 0x00000400lu
+
+#define APRB_DST_OFFSET 0x00000000lu
+#define APRB_LEN_OFFSET 0x00000002lu
+#define APRB_SRC_OFFSET 0x00000004lu
+#define APRB_DATA_OFFSET 0x00000006lu
+
+/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
+
+#define APTB_PRIO_OFFSET 0x00000000lu
+#define APTB_DST_OFFSET 0x00000002lu
+#define APTB_LEN_OFFSET 0x00000004lu
+#define APTB_SRC_OFFSET 0x00000006lu
+#define APTB_DATA_OFFSET 0x00000008lu
+
+/* Remote Read Buffer (RRDB) Address Offsets */
+
+#define RRDB_WADDR_OFFSET 0x00000100lu
+#define RRDB_WLEN_OFFSET 0x00000101lu
+
+/* **************** */
+/* MXVR Macros */
+/* **************** */
+
+/* MXVR_CONFIG Macros */
+
+#define SET_MSB(x) ( ( (x) & 0xF ) << 9)
+
+/* MXVR_INT_STAT_1 Macros */
+
+#define DONEX(x) (0x00000002 << (4 * (x)))
+#define HDONEX(x) (0x00000001 << (4 * (x)))
+
+/* MXVR_INT_EN_1 Macros */
+
+#define DONEENX(x) (0x00000002 << (4 * (x)))
+#define HDONEENX(x) (0x00000001 << (4 * (x)))
+
+/* MXVR_CDRPLL_CTL Macros */
+
+#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
+
+/* MXVR_FMPLL_CTL Macros */
+
+#define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24)
+#define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24)
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF549_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** defBF54x_base.h
+**
+** Copyright (C) 2008 Analog Devices, Inc.
+**
+************************************************************************************
+**
+** This include file contains a list of macro "defines" to enable the programmer
+** to use symbolic names for the registers common to the ADSP-BF54x peripherals.
+**
+************************************************************************************
+** System MMR Register Map
+************************************************************************************/
+
+#ifndef _DEF_BF54X_H
+#define _DEF_BF54X_H
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+
+/* ************************************************************** */
+/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
+/* ************************************************************** */
+
+/* PLL Registers */
+
+#define PLL_CTL 0xffc00000 /* PLL Control Register */
+#define PLL_DIV 0xffc00004 /* PLL Divisor Register */
+#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */
+#define PLL_STAT 0xffc0000c /* PLL Status Register */
+#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */
+
+/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
+
+#define CHIPID 0xffc00014
+
+/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
+
+#define SWRST 0xffc00100 /* Software Reset Register */
+#define SYSCR 0xffc00104 /* System Configuration register */
+
+/* SIC Registers */
+
+#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
+#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
+#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
+#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
+#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
+#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
+#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
+#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
+#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
+#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
+#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
+#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
+#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
+#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
+#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
+#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
+#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
+#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
+#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
+#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
+#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
+
+/* Watchdog Timer Registers */
+
+#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */
+#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */
+#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */
+
+/* RTC Registers */
+
+#define RTC_STAT 0xffc00300 /* RTC Status Register */
+#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
+#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
+#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */
+#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */
+#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */
+
+/* UART0 Registers */
+
+#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */
+#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */
+#define UART0_GCTL 0xffc00408 /* Global Control Register */
+#define UART0_LCR 0xffc0040c /* Line Control Register */
+#define UART0_MCR 0xffc00410 /* Modem Control Register */
+#define UART0_LSR 0xffc00414 /* Line Status Register */
+#define UART0_MSR 0xffc00418 /* Modem Status Register */
+#define UART0_SCR 0xffc0041c /* Scratch Register */
+#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
+#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
+#define UART0_THR 0xffc00428 /* Transmit Hold Register */
+#define UART0_RBR 0xffc0042c /* Receive Buffer Register */
+
+/* SPI0 Registers */
+
+#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
+#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
+#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
+#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */
+#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */
+#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */
+#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */
+
+/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
+
+/* Two Wire Interface Registers (TWI0) */
+
+#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
+#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
+#define TWI0_SLAVE_CTL 0xffc00708 /* TWI Slave Mode Control Register */
+#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
+#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
+#define TWI0_MASTER_CTL 0xffc00714 /* TWI Master Mode Control Register */
+#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
+#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
+#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
+#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
+#define TWI0_FIFO_CTL 0xffc00728 /* TWI FIFO Control Register */
+#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
+#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */
+
+/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
+
+/* SPORT1 Registers */
+
+#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */
+#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */
+#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */
+#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */
+#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */
+#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */
+#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */
+#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */
+#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */
+#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */
+#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */
+#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */
+#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */
+#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */
+#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */
+#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */
+
+/* Asynchronous Memory Control Registers */
+
+#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */
+#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */
+#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
+#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
+#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */
+#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */
+
+/* DDR Memory Control Registers */
+
+#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */
+#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */
+#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */
+#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */
+#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */
+#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */
+#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */
+#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */
+
+/* DDR BankRead and Write Count Registers */
+
+#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */
+#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */
+#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */
+#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */
+#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */
+#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */
+#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */
+#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */
+#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */
+#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */
+#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */
+#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */
+#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */
+#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */
+#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */
+#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */
+#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */
+#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */
+#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
+#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */
+#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */
+#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */
+#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */
+#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */
+#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */
+
+/* DMAC0 Registers */
+
+#define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
+#define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
+
+/* DMA Channel 0 Registers */
+
+#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */
+#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */
+#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */
+#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */
+#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */
+#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
+#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */
+
+/* DMA Channel 1 Registers */
+
+#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */
+#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */
+#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */
+#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */
+#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */
+#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
+#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */
+
+/* DMA Channel 2 Registers */
+
+#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */
+#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */
+#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */
+#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */
+#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */
+#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */
+#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */
+
+/* DMA Channel 3 Registers */
+
+#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */
+#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */
+#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */
+#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */
+#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */
+#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */
+#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */
+
+/* DMA Channel 4 Registers */
+
+#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */
+#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */
+#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */
+#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */
+#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */
+#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
+#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */
+
+/* DMA Channel 5 Registers */
+
+#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */
+#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */
+#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */
+#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */
+#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */
+#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
+#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */
+
+/* DMA Channel 6 Registers */
+
+#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */
+#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */
+#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */
+#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */
+#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */
+#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */
+#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */
+
+/* DMA Channel 7 Registers */
+
+#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */
+#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */
+#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */
+#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */
+#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */
+#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */
+#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */
+
+/* DMA Channel 8 Registers */
+
+#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */
+#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */
+#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */
+#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */
+#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */
+#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */
+#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */
+#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */
+#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */
+#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
+#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
+#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */
+#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */
+
+/* DMA Channel 9 Registers */
+
+#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */
+#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */
+#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */
+#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */
+#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */
+#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */
+#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */
+#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */
+#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */
+#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
+#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
+#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */
+#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */
+
+/* DMA Channel 10 Registers */
+
+#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */
+#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */
+#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */
+#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */
+#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */
+#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */
+#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */
+#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */
+#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */
+#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */
+#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */
+#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */
+#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */
+
+/* DMA Channel 11 Registers */
+
+#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */
+#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */
+#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */
+#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */
+#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */
+#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */
+#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */
+#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */
+#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */
+#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */
+#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */
+#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */
+#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */
+
+/* MDMA Stream 0 Registers */
+
+#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
+#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
+#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
+#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
+#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
+#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
+#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
+#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
+#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
+#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
+
+/* MDMA Stream 1 Registers */
+
+#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
+#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
+#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
+#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
+#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
+#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
+#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
+#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
+#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
+#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
+
+/* UART3 Registers */
+
+#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
+#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
+#define UART3_GCTL 0xffc03108 /* Global Control Register */
+#define UART3_LCR 0xffc0310c /* Line Control Register */
+#define UART3_MCR 0xffc03110 /* Modem Control Register */
+#define UART3_LSR 0xffc03114 /* Line Status Register */
+#define UART3_MSR 0xffc03118 /* Modem Status Register */
+#define UART3_SCR 0xffc0311c /* Scratch Register */
+#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
+#define UART3_THR 0xffc03128 /* Transmit Hold Register */
+#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
+
+/* EPPI1 Registers */
+
+#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */
+#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */
+#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */
+#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */
+#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */
+#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */
+#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */
+#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */
+#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */
+#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
+#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
+#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
+#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
+#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */
+
+/* Port Interrupt 0 Registers (32-bit) */
+
+#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
+#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
+#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */
+#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
+#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
+#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
+#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
+#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */
+#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
+#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
+
+/* Port Interrupt 1 Registers (32-bit) */
+
+#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
+#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
+#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */
+#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
+#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
+#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
+#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
+#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */
+#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
+#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
+
+/* Port Interrupt 2 Registers (32-bit) */
+
+#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
+#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
+#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */
+#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
+#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
+#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
+#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
+#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */
+#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
+#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
+
+/* Port Interrupt 3 Registers (32-bit) */
+
+#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
+#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
+#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */
+#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
+#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
+#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
+#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
+#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */
+#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
+#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
+
+/* Port A Registers */
+
+#define PORTA_FER 0xffc014c0 /* Function Enable Register */
+#define PORTA 0xffc014c4 /* GPIO Data Register */
+#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */
+#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */
+#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */
+#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */
+#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */
+#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */
+
+/* Port B Registers */
+
+#define PORTB_FER 0xffc014e0 /* Function Enable Register */
+#define PORTB 0xffc014e4 /* GPIO Data Register */
+#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */
+#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */
+#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */
+#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */
+#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */
+#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */
+
+/* Port C Registers */
+
+#define PORTC_FER 0xffc01500 /* Function Enable Register */
+#define PORTC 0xffc01504 /* GPIO Data Register */
+#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */
+#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */
+#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */
+#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */
+#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */
+#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */
+
+/* Port D Registers */
+
+#define PORTD_FER 0xffc01520 /* Function Enable Register */
+#define PORTD 0xffc01524 /* GPIO Data Register */
+#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */
+#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */
+#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */
+#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */
+#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */
+#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */
+
+/* Port E Registers */
+
+#define PORTE_FER 0xffc01540 /* Function Enable Register */
+#define PORTE 0xffc01544 /* GPIO Data Register */
+#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */
+#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */
+#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */
+#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */
+#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */
+#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */
+
+/* Port F Registers */
+
+#define PORTF_FER 0xffc01560 /* Function Enable Register */
+#define PORTF 0xffc01564 /* GPIO Data Register */
+#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */
+#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */
+#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */
+#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */
+#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */
+#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */
+
+/* Port G Registers */
+
+#define PORTG_FER 0xffc01580 /* Function Enable Register */
+#define PORTG 0xffc01584 /* GPIO Data Register */
+#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */
+#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */
+#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */
+#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */
+#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */
+#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */
+
+/* Port H Registers */
+
+#define PORTH_FER 0xffc015a0 /* Function Enable Register */
+#define PORTH 0xffc015a4 /* GPIO Data Register */
+#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */
+#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */
+#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */
+#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */
+#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */
+#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */
+
+/* Port I Registers */
+
+#define PORTI_FER 0xffc015c0 /* Function Enable Register */
+#define PORTI 0xffc015c4 /* GPIO Data Register */
+#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */
+#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */
+#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */
+#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */
+#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */
+#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */
+
+/* Port J Registers */
+
+#define PORTJ_FER 0xffc015e0 /* Function Enable Register */
+#define PORTJ 0xffc015e4 /* GPIO Data Register */
+#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */
+#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */
+#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */
+#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */
+#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */
+#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */
+
+/* PWM Timer Registers */
+
+#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */
+#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */
+#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */
+#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */
+#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */
+#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */
+#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */
+#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */
+#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */
+#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */
+#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */
+#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */
+#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */
+#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */
+#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */
+#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */
+#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */
+#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */
+#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */
+#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */
+#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */
+#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */
+#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */
+#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */
+#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */
+#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */
+#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */
+#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */
+#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */
+#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */
+#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */
+
+/* Timer Group of 8 */
+
+#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */
+#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */
+#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */
+
+/* DMAC1 Registers */
+
+#define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
+#define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
+
+/* DMA Channel 12 Registers */
+
+#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */
+#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */
+#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */
+#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */
+#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */
+#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */
+#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */
+#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */
+#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */
+#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */
+#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
+#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */
+#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */
+
+/* DMA Channel 13 Registers */
+
+#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */
+#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */
+#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */
+#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */
+#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */
+#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */
+#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */
+#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */
+#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */
+#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */
+#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
+#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */
+#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */
+
+/* DMA Channel 14 Registers */
+
+#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */
+#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */
+#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */
+#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */
+#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */
+#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */
+#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */
+#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */
+#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */
+#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */
+#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */
+#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */
+#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */
+
+/* DMA Channel 15 Registers */
+
+#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */
+#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */
+#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */
+#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */
+#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */
+#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */
+#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */
+#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */
+#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */
+#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */
+#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */
+#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */
+#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */
+
+/* DMA Channel 16 Registers */
+
+#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */
+#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */
+#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */
+#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */
+#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */
+#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */
+#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */
+#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */
+#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */
+#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */
+#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
+#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */
+#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */
+
+/* DMA Channel 17 Registers */
+
+#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */
+#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */
+#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */
+#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */
+#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */
+#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */
+#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */
+#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */
+#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */
+#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */
+#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
+#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */
+#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */
+
+/* DMA Channel 18 Registers */
+
+#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */
+#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */
+#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */
+#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */
+#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */
+#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */
+#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */
+#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */
+#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */
+#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */
+#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */
+#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */
+#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */
+
+/* DMA Channel 19 Registers */
+
+#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */
+#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */
+#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */
+#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */
+#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */
+#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */
+#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */
+#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */
+#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */
+#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */
+#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */
+#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */
+#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */
+
+/* DMA Channel 20 Registers */
+
+#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */
+#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */
+#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */
+#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */
+#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */
+#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */
+#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */
+#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */
+#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */
+#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */
+#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
+#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */
+#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */
+
+/* DMA Channel 21 Registers */
+
+#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */
+#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */
+#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */
+#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */
+#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */
+#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */
+#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */
+#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */
+#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */
+#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */
+#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
+#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */
+#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */
+
+/* DMA Channel 22 Registers */
+
+#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */
+#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */
+#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */
+#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */
+#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */
+#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */
+#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */
+#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */
+#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */
+#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */
+#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */
+#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */
+#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */
+
+/* DMA Channel 23 Registers */
+
+#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */
+#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */
+#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */
+#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */
+#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */
+#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */
+#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */
+#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */
+#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */
+#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */
+#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */
+#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */
+#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */
+
+/* MDMA Stream 2 Registers */
+
+#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
+#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
+#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
+#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
+#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
+#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
+#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
+#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
+#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
+#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
+#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
+#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
+#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
+#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
+#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
+#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
+#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
+#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
+#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
+#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
+#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
+#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
+#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
+#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
+#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
+#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
+
+/* MDMA Stream 3 Registers */
+
+#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
+#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
+#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
+#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
+#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
+#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
+#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
+#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
+#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
+#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
+#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
+#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
+#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
+#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
+#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
+#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
+#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
+#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
+#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
+#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
+#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
+#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
+#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
+#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
+#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
+#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
+
+/* UART1 Registers */
+
+#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */
+#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */
+#define UART1_GCTL 0xffc02008 /* Global Control Register */
+#define UART1_LCR 0xffc0200c /* Line Control Register */
+#define UART1_MCR 0xffc02010 /* Modem Control Register */
+#define UART1_LSR 0xffc02014 /* Line Status Register */
+#define UART1_MSR 0xffc02018 /* Modem Status Register */
+#define UART1_SCR 0xffc0201c /* Scratch Register */
+#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
+#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
+#define UART1_THR 0xffc02028 /* Transmit Hold Register */
+#define UART1_RBR 0xffc0202c /* Receive Buffer Register */
+
+/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
+
+/* SPI1 Registers */
+
+#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
+#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
+#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
+#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */
+#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */
+#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */
+#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */
+
+/* SPORT2 Registers */
+
+#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */
+#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */
+#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */
+#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */
+#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */
+#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */
+#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */
+#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */
+#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */
+#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */
+#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */
+#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */
+#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */
+#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */
+#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */
+#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */
+#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */
+#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */
+#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */
+#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */
+#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */
+#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */
+
+/* SPORT3 Registers */
+
+#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */
+#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */
+#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */
+#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */
+#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */
+#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */
+#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */
+#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */
+#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */
+#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */
+#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */
+#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */
+#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */
+#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */
+#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */
+#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */
+#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */
+#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */
+#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */
+#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */
+#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */
+#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */
+
+/* EPPI2 Registers */
+
+#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */
+#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */
+#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */
+#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */
+#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */
+#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */
+#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */
+#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */
+#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */
+#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
+#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
+#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
+#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
+#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */
+
+/* CAN Controller 0 Config 1 Registers */
+
+#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */
+#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */
+#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */
+#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */
+#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
+#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */
+#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */
+#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */
+#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
+#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
+#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
+#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
+#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
+
+/* CAN Controller 0 Config 2 Registers */
+
+#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */
+#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */
+#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */
+#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */
+#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
+#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */
+#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */
+#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */
+#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
+#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
+#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
+#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
+#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
+
+/* CAN Controller 0 Clock/Interrupt/Counter Registers */
+
+#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
+#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */
+#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */
+#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */
+#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */
+#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */
+#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */
+#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */
+#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */
+#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */
+#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */
+#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
+#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
+#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
+#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
+#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
+
+/* CAN Controller 0 Acceptance Registers */
+
+#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
+#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
+#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
+#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
+#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
+#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
+#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
+#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
+#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
+#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
+#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
+#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
+#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
+#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
+#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
+#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
+#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
+#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
+#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
+#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
+#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
+#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
+#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
+#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
+#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
+#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
+#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
+#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
+#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
+#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
+#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
+#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
+
+/* CAN Controller 0 Acceptance Registers */
+
+#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
+#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
+#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
+#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
+#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
+#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
+#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
+#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
+#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
+#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
+#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
+#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
+#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
+#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
+#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
+#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
+#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
+#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
+#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
+#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
+#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
+#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
+#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
+#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
+#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
+#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
+#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
+#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
+#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
+#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
+#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
+#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
+
+/* CAN Controller 0 Mailbox Data Registers */
+
+#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
+#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
+#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
+#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */
+#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */
+#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
+#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
+#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
+#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
+#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
+#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
+#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */
+#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */
+#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
+#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
+#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
+#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
+#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
+#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
+#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */
+#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */
+#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
+#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
+#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
+#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
+#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
+#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
+#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */
+#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */
+#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
+#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
+#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
+#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
+#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
+#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
+#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */
+#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */
+#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
+#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
+#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
+#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
+#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
+#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
+#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */
+#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */
+#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
+#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
+#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
+#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
+#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
+#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
+#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */
+#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */
+#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
+#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
+#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
+#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
+#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
+#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
+#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */
+#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */
+#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
+#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
+#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
+#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
+#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
+#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
+#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */
+#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */
+#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
+#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
+#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
+#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
+#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
+#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
+#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */
+#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */
+#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
+#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
+#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
+#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
+#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
+#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
+#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */
+#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */
+#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
+#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */
+#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */
+#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
+#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
+#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
+#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */
+#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */
+#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
+#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */
+#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */
+#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
+#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
+#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
+#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */
+#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */
+#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
+#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */
+#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */
+#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
+#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
+#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
+#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */
+#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */
+#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
+#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */
+#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */
+#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
+#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
+#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
+#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */
+#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */
+#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
+#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */
+#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */
+#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
+#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
+#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
+#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */
+#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */
+#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
+#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */
+#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */
+
+/* CAN Controller 0 Mailbox Data Registers */
+
+#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
+#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
+#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
+#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */
+#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */
+#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
+#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */
+#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */
+#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
+#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
+#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
+#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */
+#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */
+#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
+#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */
+#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */
+#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
+#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
+#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
+#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */
+#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */
+#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
+#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */
+#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */
+#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
+#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
+#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
+#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */
+#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */
+#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
+#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */
+#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */
+#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
+#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
+#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
+#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */
+#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */
+#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
+#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */
+#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */
+#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
+#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
+#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
+#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */
+#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */
+#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
+#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */
+#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */
+#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
+#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
+#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
+#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */
+#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */
+#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
+#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */
+#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */
+#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
+#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
+#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
+#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */
+#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */
+#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
+#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */
+#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */
+#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
+#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
+#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
+#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */
+#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */
+#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
+#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */
+#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */
+#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
+#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
+#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
+#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */
+#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */
+#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
+#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */
+#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */
+#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
+#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
+#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
+#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */
+#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */
+#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
+#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */
+#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */
+#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
+#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
+#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
+#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */
+#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */
+#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
+#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */
+#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */
+#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
+#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
+#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
+#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */
+#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */
+#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
+#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */
+#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */
+#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
+#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
+#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
+#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */
+#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */
+#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
+#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */
+#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */
+#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
+#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
+#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
+#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */
+#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */
+#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
+#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */
+#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */
+#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
+#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
+#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
+#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */
+#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */
+#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
+#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */
+#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */
+
+/* UART3 Registers */
+
+#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
+#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
+#define UART3_GCTL 0xffc03108 /* Global Control Register */
+#define UART3_LCR 0xffc0310c /* Line Control Register */
+#define UART3_MCR 0xffc03110 /* Modem Control Register */
+#define UART3_LSR 0xffc03114 /* Line Status Register */
+#define UART3_MSR 0xffc03118 /* Modem Status Register */
+#define UART3_SCR 0xffc0311c /* Scratch Register */
+#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
+#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
+#define UART3_THR 0xffc03128 /* Transmit Hold Register */
+#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
+
+/* NFC Registers */
+
+#define NFC_CTL 0xffc03b00 /* NAND Control Register */
+#define NFC_STAT 0xffc03b04 /* NAND Status Register */
+#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
+#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
+#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */
+#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */
+#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */
+#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */
+#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */
+#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */
+#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */
+#define NFC_READ 0xffc03b2c /* NAND Read Data Register */
+#define NFC_ADDR 0xffc03b40 /* NAND Address Register */
+#define NFC_CMD 0xffc03b44 /* NAND Command Register */
+#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */
+#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */
+
+/* Counter Registers */
+
+#define CNT_CONFIG 0xffc04200 /* Configuration Register */
+#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
+#define CNT_STATUS 0xffc04208 /* Status Register */
+#define CNT_COMMAND 0xffc0420c /* Command Register */
+#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */
+#define CNT_COUNTER 0xffc04214 /* Counter Register */
+#define CNT_MAX 0xffc04218 /* Maximal Count Register */
+#define CNT_MIN 0xffc0421c /* Minimal Count Register */
+
+/* OTP/FUSE Registers */
+
+#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */
+#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */
+#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */
+#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */
+
+/* Security Registers */
+
+#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */
+#define SECURE_CONTROL 0xffc04324 /* Secure Control */
+#define SECURE_STATUS 0xffc04328 /* Secure Status */
+
+/* DMA Peripheral Mux Register */
+
+#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */
+
+/* OTP Read/Write Data Buffer Registers */
+
+#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
+
+/* Handshake MDMA 0 Registers */
+
+#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
+
+/* Handshake MDMA 1 Registers */
+
+#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
+
+/* ********************************************************** */
+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
+/* and MULTI BIT READ MACROS */
+/* ********************************************************** */
+
+/* Bit masks for SIC_IAR0 */
+
+#define IRQ_PLL_WAKEUP 0x1 /* PLL Wakeup */
+#define nIRQ_PLL_WAKEUP 0x0
+
+/* Below is an alternate name that matches the 54x HRM and previous defBF532.h header,
+ above matches previous defBF534.h header */
+#define PLL_WAKEUP_IRQ 0x1 /* PLL Wakeup Interrupt Request */
+#define nPLL_WAKEUP_IRQ 0x0
+
+/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
+
+#define IRQ_DMA0_ERR 0x2 /* DMA Controller 0 Error */
+#define nIRQ_DMA0_ERR 0x0
+#define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */
+#define nIRQ_EPPI0_ERR 0x0
+#define IRQ_SPORT0_ERR 0x8 /* SPORT0 Error */
+#define nIRQ_SPORT0_ERR 0x0
+#define IRQ_SPORT1_ERR 0x10 /* SPORT1 Error */
+#define nIRQ_SPORT1_ERR 0x0
+#define IRQ_SPI0_ERR 0x20 /* SPI0 Error */
+#define nIRQ_SPI0_ERR 0x0
+#define IRQ_UART0_ERR 0x40 /* UART0 Error */
+#define nIRQ_UART0_ERR 0x0
+#define IRQ_RTC 0x80 /* Real-Time Clock */
+#define nIRQ_RTC 0x0
+#define IRQ_DMA12 0x100 /* DMA Channel 12 */
+#define nIRQ_DMA12 0x0
+#define IRQ_DMA0 0x200 /* DMA Channel 0 */
+#define nIRQ_DMA0 0x0
+#define IRQ_DMA1 0x400 /* DMA Channel 1 */
+#define nIRQ_DMA1 0x0
+#define IRQ_DMA2 0x800 /* DMA Channel 2 */
+#define nIRQ_DMA2 0x0
+#define IRQ_DMA3 0x1000 /* DMA Channel 3 */
+#define nIRQ_DMA3 0x0
+#define IRQ_DMA4 0x2000 /* DMA Channel 4 */
+#define nIRQ_DMA4 0x0
+#define IRQ_DMA6 0x4000 /* DMA Channel 6 */
+#define nIRQ_DMA6 0x0
+#define IRQ_DMA7 0x8000 /* DMA Channel 7 */
+#define nIRQ_DMA7 0x0
+#define IRQ_PINT0 0x80000 /* Pin Interrupt 0 */
+#define nIRQ_PINT0 0x0
+#define IRQ_PINT1 0x100000 /* Pin Interrupt 1 */
+#define nIRQ_PINT1 0x0
+#define IRQ_MDMA0 0x200000 /* Memory DMA Stream 0 */
+#define nIRQ_MDMA0 0x0
+#define IRQ_MDMA1 0x400000 /* Memory DMA Stream 1 */
+#define nIRQ_MDMA1 0x0
+#define IRQ_WDOG 0x800000 /* Watchdog Timer */
+#define nIRQ_WDOG 0x0
+#define IRQ_DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
+#define nIRQ_DMA1_ERR 0x0
+#define IRQ_SPORT2_ERR 0x2000000 /* SPORT2 Error */
+#define nIRQ_SPORT2_ERR 0x0
+#define IRQ_SPORT3_ERR 0x4000000 /* SPORT3 Error */
+#define nIRQ_SPORT3_ERR 0x0
+#define IRQ_MXVR_SD 0x8000000 /* MXVR Synchronous Data */
+#define nIRQ_MXVR_SD 0x0
+#define IRQ_SPI1_ERR 0x10000000 /* SPI1 Error */
+#define nIRQ_SPI1_ERR 0x0
+#define IRQ_SPI2_ERR 0x20000000 /* SPI2 Error */
+#define nIRQ_SPI2_ERR 0x0
+#define IRQ_UART1_ERR 0x40000000 /* UART1 Error */
+#define nIRQ_UART1_ERR 0x0
+#define IRQ_UART2_ERR 0x80000000 /* UART2 Error */
+#define nIRQ_UART2_ERR 0x0
+
+/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
+
+#define IRQ_CAN0_ERR 0x1 /* CAN0 Error */
+#define nIRQ_CAN0_ERR 0x0
+#define IRQ_DMA18 0x2 /* DMA Channel 18 */
+#define nIRQ_DMA18 0x0
+#define IRQ_DMA19 0x4 /* DMA Channel 19 */
+#define nIRQ_DMA19 0x0
+#define IRQ_DMA20 0x8 /* DMA Channel 20 */
+#define nIRQ_DMA20 0x0
+#define IRQ_DMA21 0x10 /* DMA Channel 21 */
+#define nIRQ_DMA21 0x0
+#define IRQ_DMA13 0x20 /* DMA Channel 13 */
+#define nIRQ_DMA13 0x0
+#define IRQ_DMA14 0x40 /* DMA Channel 14 */
+#define nIRQ_DMA14 0x0
+#define IRQ_DMA5 0x80 /* DMA Channel 5 */
+#define nIRQ_DMA5 0x0
+#define IRQ_DMA23 0x100 /* DMA Channel 23 */
+#define nIRQ_DMA23 0x0
+#define IRQ_DMA8 0x200 /* DMA Channel 8 */
+#define nIRQ_DMA8 0x0
+#define IRQ_DMA9 0x400 /* DMA Channel 9 */
+#define nIRQ_DMA9 0x0
+#define IRQ_DMA10 0x800 /* DMA Channel 10 */
+#define nIRQ_DMA10 0x0
+#define IRQ_DMA11 0x1000 /* DMA Channel 11 */
+#define nIRQ_DMA11 0x0
+#define IRQ_TWI0 0x2000 /* TWI0 */
+#define nIRQ_TWI0 0x0
+#define IRQ_TWI1 0x4000 /* TWI1 */
+#define nIRQ_TWI1 0x0
+#define IRQ_CAN0_RX 0x8000 /* CAN0 Receive */
+#define nIRQ_CAN0_RX 0x0
+#define IRQ_CAN0_TX 0x10000 /* CAN0 Transmit */
+#define nIRQ_CAN0_TX 0x0
+#define IRQ_MDMA2 0x20000 /* Memory DMA Stream 0 */
+#define nIRQ_MDMA2 0x0
+#define IRQ_MDMA3 0x40000 /* Memory DMA Stream 1 */
+#define nIRQ_MDMA3 0x0
+#define IRQ_MXVR_STAT 0x80000 /* MXVR Status */
+#define nIRQ_MXVR_STAT 0x0
+#define IRQ_MXVR_CM 0x100000 /* MXVR Control Message */
+#define nIRQ_MXVR_CM 0x0
+#define IRQ_MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
+#define nIRQ_MXVR_AP 0x0
+#define IRQ_EPPI1_ERR 0x400000 /* EPPI1 Error */
+#define nIRQ_EPPI1_ERR 0x0
+#define IRQ_EPPI2_ERR 0x800000 /* EPPI2 Error */
+#define nIRQ_EPPI2_ERR 0x0
+#define IRQ_UART3_ERR 0x1000000 /* UART3 Error */
+#define nIRQ_UART3_ERR 0x0
+#define IRQ_HOSTDP_STATUS 0x2000000 /* Host DMA Port Error */
+#define nIRQ_HOSTDP_STATUS 0x0
+#define IRQ_USB_ERR 0x4000000 /* USB Error */
+#define nIRQ_USB_ERR 0x0
+#define IRQ_PIXC_ERR 0x8000000 /* Pixel Compositor Error */
+#define nIRQ_PIXC_ERR 0x0
+#define IRQ_NFC_ERR 0x10000000 /* Nand Flash Controller Error */
+#define nIRQ_NFC_ERR 0x0
+#define IRQ_ATAPI_ERR 0x20000000 /* ATAPI Error */
+#define nIRQ_ATAPI_ERR 0x0
+#define IRQ_CAN1_ERR 0x40000000 /* CAN1 Error */
+#define nIRQ_CAN1_ERR 0x0
+#define IRQ_DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
+#define nIRQ_DMAR0_ERR 0x0
+#define IRQ_DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
+#define nIRQ_DMAR1_ERR 0x0
+#define IRQ_DMAR0 0x80000000 /* DMAR0 Block */
+#define nIRQ_DMAR0 0x0
+#define IRQ_DMAR1 0x80000000 /* DMAR1 Block */
+#define nIRQ_DMAR1 0x0
+
+/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
+
+#define IRQ_DMA15 0x1 /* DMA Channel 15 */
+#define nIRQ_DMA15 0x0
+#define IRQ_DMA16 0x2 /* DMA Channel 16 */
+#define nIRQ_DMA16 0x0
+#define IRQ_DMA17 0x4 /* DMA Channel 17 */
+#define nIRQ_DMA17 0x0
+#define IRQ_DMA22 0x8 /* DMA Channel 22 */
+#define nIRQ_DMA22 0x0
+#define IRQ_CNT 0x10 /* Counter */
+#define nIRQ_CNT 0x0
+#define IRQ_KEY 0x20 /* Keypad */
+#define nIRQ_KEY 0x0
+#define IRQ_CAN1_RX 0x40 /* CAN1 Receive */
+#define nIRQ_CAN1_RX 0x0
+#define IRQ_CAN1_TX 0x80 /* CAN1 Transmit */
+#define nIRQ_CAN1_TX 0x0
+#define IRQ_SDH_MASK0 0x100 /* SDH Mask 0 */
+#define nIRQ_SDH_MASK0 0x0
+#define IRQ_SDH_MASK1 0x200 /* SDH Mask 1 */
+#define nIRQ_SDH_MASK1 0x0
+#define IRQ_USB_EINT 0x400 /* USB Exception */
+#define nIRQ_USB_EINT 0x0
+#define IRQ_USB_INT0 0x800 /* USB Interrupt 0 */
+#define nIRQ_USB_INT0 0x0
+#define IRQ_USB_INT1 0x1000 /* USB Interrupt 1 */
+#define nIRQ_USB_INT1 0x0
+#define IRQ_USB_INT2 0x2000 /* USB Interrupt 2 */
+#define nIRQ_USB_INT2 0x0
+#define IRQ_USB_DMAINT 0x4000 /* USB DMA */
+#define nIRQ_USB_DMAINT 0x0
+#define IRQ_OTP 0x8000 /* OTP Access Complete */
+#define nIRQ_OTP 0x0
+#define IRQ_TIMER0 0x400000 /* Timer 0 */
+#define nIRQ_TIMER0 0x0
+#define IRQ_TIMER1 0x800000 /* Timer 1 */
+#define nIRQ_TIMER1 0x0
+#define IRQ_TIMER2 0x1000000 /* Timer 2 */
+#define nIRQ_TIMER2 0x0
+#define IRQ_TIMER3 0x2000000 /* Timer 3 */
+#define nIRQ_TIMER3 0x0
+#define IRQ_TIMER4 0x4000000 /* Timer 4 */
+#define nIRQ_TIMER4 0x0
+#define IRQ_TIMER5 0x8000000 /* Timer 5 */
+#define nIRQ_TIMER5 0x0
+#define IRQ_TIMER6 0x10000000 /* Timer 6 */
+#define nIRQ_TIMER6 0x0
+#define IRQ_TIMER7 0x20000000 /* Timer 7 */
+#define nIRQ_TIMER7 0x0
+#define IRQ_PINT2 0x40000000 /* Pin Interrupt 2 */
+#define nIRQ_PINT2 0x0
+#define IRQ_PINT3 0x80000000 /* Pin Interrupt 3 */
+#define nIRQ_PINT3 0x0
+
+/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
+
+#define DMAEN 0x1 /* DMA Channel Enable */
+#define nDMAEN 0x0
+#define WNR 0x2 /* DMA Direction */
+#define nWNR 0x0
+#define WDSIZE 0xc /* Transfer Word Size */
+#define DMA2D 0x10 /* DMA Mode */
+#define nDMA2D 0x0
+#define SYNC 0x20 /* Work Unit Transitions */
+#define nSYNC 0x0
+#define DI_SEL 0x40 /* Data Interrupt Timing Select */
+#define nDI_SEL 0x0
+#define DI_EN 0x80 /* Data Interrupt Enable */
+#define nDI_EN 0x0
+#define NDSIZE 0xf00 /* Flex Descriptor Size */
+#define FLOW 0xf000 /* Next Operation */
+
+/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
+
+#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
+#define nDMA_DONE 0x0
+#define DMA_ERR 0x2 /* DMA Error Interrupt Status */
+#define nDMA_ERR 0x0
+#define DFETCH 0x4 /* DMA Descriptor Fetch */
+#define nDFETCH 0x0
+#define DMA_RUN 0x8 /* DMA Channel Running */
+#define nDMA_RUN 0x0
+
+/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
+
+#define CTYPE 0x40 /* DMA Channel Type */
+#define nCTYPE 0x0
+#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
+
+/* Bit masks for DMACx_TCPER */
+
+#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
+#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
+#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
+#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
+
+/* Bit masks for DMACx_TCCNT */
+
+#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
+#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
+#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */
+#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */
+
+/* Bit masks for DMAC1_PERIMUX */
+
+#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
+#define nPMUXSDH 0x0
+
+/* Bit masks for EBIU_AMGCTL */
+
+#define AMCKEN 0x1 /* Async Memory Enable */
+#define nAMCKEN 0x0
+#define AMBEN 0xe /* Async bank enable */
+
+/* EBIU_AMGCTL Masks (AMCKEN) */
+#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
+
+/* EBIU_AMGCTL Masks (AMBEN) */
+#define AMBEN_NONE 0x0000 /* All Banks Disabled */
+#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
+#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
+
+/* Bit masks for EBIU_AMBCTL0 */
+
+#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
+#define nB0RDYEN 0x0
+#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
+#define nB0RDYPOL 0x0
+#define B0TT 0xc /* Bank 0 transition time */
+#define B0ST 0x30 /* Bank 0 Setup time */
+#define B0HT 0xc0 /* Bank 0 Hold time */
+#define B0RAT 0xf00 /* Bank 0 Read access time */
+#define B0WAT 0xf000 /* Bank 0 write access time */
+#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
+#define nB1RDYEN 0x0
+#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
+#define nB1RDYPOL 0x0
+#define B1TT 0xc0000 /* Bank 1 transition time */
+#define B1ST 0x300000 /* Bank 1 Setup time */
+#define B1HT 0xc00000 /* Bank 1 Hold time */
+#define B1RAT 0xf000000 /* Bank 1 Read access time */
+#define B1WAT 0xf0000000 /* Bank 1 write access time */
+
+/* EBIU_AMBCTL0 Macros */
+#define SET_B1WAT(x) (((x)&0xF) << 28) /* B1 Write Access Time = x cycles */
+#define SET_B1RAT(x) (((x)&0xF) << 24) /* B1 Read Access Time = x cycles */
+#define SET_B1HT(x) (((x)&0x3) << 22) /* B1 Hold Time (~Read/Write to ~AOE) = x cycles */
+#define SET_B1ST[x) (((x)&0x3) << 20) /* B1 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B1TT(x) (((x)&0x3) << 18) /* B1 Transition Time (Read to Write) = x cycles */
+
+#define SET_B0WAT(x) (((x)&0xF) << 12) /* B0 Write Access Time = x cycles */
+#define SET_B0RAT(x) (((x)&0xF) << 8) /* B0 Read Access Time = x cycles */
+#define SET_B0HT(x) (((x)&0x3) << 6) /* B0 Hold Time (~Read/Write to ~AOE) = x cycles */
+#define SET_B0ST[x) (((x)&0x3) << 4) /* B0 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B0TT(x) (((x)&0x3) << 2) /* B0 Transition Time (Read to Write) = x cycles */
+
+/* Bit masks for EBIU_AMBCTL1 */
+
+#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
+#define nB2RDYEN 0x0
+#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
+#define nB2RDYPOL 0x0
+#define B2TT 0xc /* Bank 2 transition time */
+#define B2ST 0x30 /* Bank 2 Setup time */
+#define B2HT 0xc0 /* Bank 2 Hold time */
+#define B2RAT 0xf00 /* Bank 2 Read access time */
+#define B2WAT 0xf000 /* Bank 2 write access time */
+#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
+#define nB3RDYEN 0x0
+#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
+#define nB3RDYPOL 0x0
+#define B3TT 0xc0000 /* Bank 3 transition time */
+#define B3ST 0x300000 /* Bank 3 Setup time */
+#define B3HT 0xc00000 /* Bank 3 Hold time */
+#define B3RAT 0xf000000 /* Bank 3 Read access time */
+#define B3WAT 0xf0000000 /* Bank 3 write access time */
+
+/* EBIU_AMBCTL1 Macros */
+#define SET_B3WAT(x) (((x)&0xF) << 28) /* B3 Write Access Time = x cycles */
+#define SET_B3RAT(x) (((x)&0xF) << 24) /* B3 Read Access Time = x cycles */
+#define SET_B3HT(x) (((x)&0x3) << 22) /* B3 Hold Time (~Read/Write to ~AOE) = x cycles */
+#define SET_B3ST[x) (((x)&0x3) << 20) /* B3 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B3TT(x) (((x)&0x3) << 18) /* B3 Transition Time (Read to Write) = x cycles */
+
+#define SET_B2WAT(x) (((x)&0xF) << 12) /* B2 Write Access Time = x cycles */
+#define SET_B2RAT(x) (((x)&0xF) << 8) /* B2 Read Access Time = x cycles */
+#define SET_B2HT(x) (((x)&0x3) << 6) /* B2 Hold Time (~Read/Write to ~AOE) = x cycles */
+#define SET_B2ST[x) (((x)&0x3) << 4) /* B2 Setup Time (AOE to Read/Write) = x cycle */
+#define SET_B2TT(x) (((x)&0x3) << 2) /* B2 Transition Time (Read to Write) = x cycles */
+
+/* Bit masks for EBIU_MBSCTL */
+
+#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
+#define AMSB1CTL 0xc /* Async Memory Bank 1 select */
+#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
+#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
+
+/* Bit masks for EBIU_MODE */
+
+#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
+#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
+#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
+#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
+
+/* Bit masks for EBIU_MODE (BOMODE) */
+#define B0MODE_ASYNC 0x00000000 /* Bank 0 Access Mode - 00 - Asynchronous Mode */
+#define B0MODE_FLASH 0x00000001 /* Bank 0 Access Mode - 01 - Asynchronous Flash Mode */
+#define B0MODE_PAGE 0x00000002 /* Bank 0 Access Mode - 10 - Asynchronous Page Mode */
+#define B0MODE_BURST 0x00000003 /* Bank 0 Access Mode - 11 - Synchronous (Burst) Mode */
+
+/* Bit masks for EBIU_MODE (B1MODE) */
+#define B1MODE_ASYNC 0x00000000 /* Bank 1 Access Mode - 00 - Asynchronous Mode */
+#define B1MODE_FLASH 0x00000004 /* Bank 1 Access Mode - 01 - Asynchronous Flash Mode */
+#define B1MODE_PAGE 0x00000008 /* Bank 1 Access Mode - 10 - Asynchronous Page Mode */
+#define B1MODE_BURST 0x0000000C /* Bank 1 Access Mode - 11 - Synchronous (Burst) Mode */
+
+/* Bit masks for EBIU_MODE (B2MODE) */
+#define B2MODE_ASYNC 0x00000000 /* Bank 2 Access Mode - 00 - Asynchronous Mode */
+#define B2MODE_FLASH 0x00000010 /* Bank 2 Access Mode - 01 - Asynchronous Flash Mode */
+#define B2MODE_PAGE 0x00000020 /* Bank 2 Access Mode - 10 - Asynchronous Page Mode */
+#define B2MODE_BURST 0x00000030 /* Bank 2 Access Mode - 11 - Synchronous (Burst) Mode */
+
+/* Bit masks for EBIU_MODE (B3MODE) */
+#define B3MODE_ASYNC 0x00000000 /* Bank 3 Access Mode - 00 - Asynchronous Mode */
+#define B3MODE_FLASH 0x00000040 /* Bank 3 Access Mode - 01 - Asynchronous Flash Mode */
+#define B3MODE_PAGE 0x00000080 /* Bank 3 Access Mode - 10 - Asynchronous Page Mode */
+#define B3MODE_BURST 0x000000C0 /* Bank 3 Access Mode - 11 - Synchronous (Burst) Mode */
+
+/* Bit masks for EBIU_FCTL */
+
+#define TESTSETLOCK 0x1 /* Test set lock */
+#define nTESTSETLOCK 0x0
+#define BCLK 0x6 /* Burst clock frequency */
+#define PGWS 0x38 /* Page wait states */
+#define PGSZ 0x40 /* Page size */
+#define nPGSZ 0x0
+#define RDDL 0x380 /* Read data delay */
+
+/* Bit masks for EBIU_FCTL (BCLK) */
+#define BCLK2 0x00000002 /* Burst clock frequency: 01 - SCLK/2 */
+#define BCLK3 0x00000004 /* Burst clock frequency: 10 - SCLK/3 */
+#define BCLK4 0x00000006 /* Burst clock frequency: 11 - SCLK/4 */
+
+/* Macros for EBIU_FCTL */
+#define SET_PGWS(x) (((x)&0x7) << 0x3) /* PGWS[5:3] Page Wait States - 000 to 100 - 0 to 4 cycles */
+ /* Burst clock frequency: 00 - Reserved */
+/* Bit masks for EBIU_ARBSTAT */
+
+#define ARBSTAT 0x1 /* Arbitration status */
+#define nARBSTAT 0x0
+#define BGSTAT 0x2 /* Bus grant status */
+#define nBGSTAT 0x0
+
+/* Bit masks for EBIU_DDRCTL0 */
+#define TREFI 0x3fff /* Refresh Interval */
+#define TRFC 0x3c000 /* Auto-refresh command period */
+#define TRP 0x3c0000 /* Pre charge-to-active command period */
+#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
+#define TRC 0x3c000000 /* Active-to-active time */
+
+/* Macros for EBIU_DDRCTL0 */
+#define SET_tRC(x) (((x)&0xF) << 26) /* tRC (Active-to-Active)[29:26] - Number of clock cycles from an active command to next active command (Default: 0x2) */
+#define SET_tRAS(x) (((x)&0xF) << 22) /* tRAS (Minimum Active-to-Precharge time) [3:0] - Number of clock cycles from an ACTIVE command until a PRE-CHARGE command is issued. To obtain this value, one should divide the minimum RAS to pre-charge delay of SDRAM by clock cycle time (Default: 0x6) */
+#define SET_tRP(x) (((x)&0xF) << 18) /* tRP (Precharge-to-Active Command period)[3:0] - Number of clock cycles needed for DDR to recover from a precharge command and ready to accept next active command (Default: 0x3) */
+#define SET_tRFC(x) (((x)&0xF) << 14) /* tRFC[3:0] AUTO-REFRESH Command Period[3:0] - Number of clock cycles needed for DDR to recover from a refresh to be ready for next active command (tRFC/Clock Period) (Default: 0xA) */
+#define SET_tREFI(x) ((x)&0x3FFF) /* tREFI (Refresh Interval)[13:0] - Number of clock cycles from one refresh cycle to next refresh cycle. To obtain this value, divide the DDR refresh period (tREF) by total number of rows to be refreshed. Then divide the result by total time. (Default: 0x0411) */
+
+/* Bit masks for EBIU_DDRCTL1 */
+
+#define TRCD 0xf /* Active-to-Read/write delay */
+#define MRD 0xf0 /* Mode register set to active */
+#define TWR 0x300 /* Write Recovery time */
+#define DDRDATWIDTH 0x3000 /* DDR data width */
+#define EXTBANKS 0xc000 /* External banks */
+#define DDRDEVWIDTH 0x30000 /* DDR device width */
+#define DDRDEVSIZE 0xc0000 /* DDR device size */
+#define TWWTR 0xf0000000 /* Write-to-read delay */
+
+/* Alternate names that match BF54x HRM */
+#define DDR_DATWIDTH 0x3000 /* DDR data width */
+#define DDR_DEVWIDTH 0x30000 /* DDR device width */
+#define DDR_DEVSIZE 0xc0000 /* DDR device size */
+
+/* Masks for EBIU_DDRCTL1 (DDRDATWIDTH) [in HRM: DDR_DATWIDTH] */
+#define DDR_DATAWIDTH 0x00002000 /* DDR_DATWIDTH Total DDR Data Width (16-bit Only) */
+
+/* Masks for EBIU_DDRCTL1 (EXTBANKS) */
+#define CS0 0x00000000 /* EXTBANKS External Banks[15:14] */
+#define CS0_CS1 0x00004000 /* default */
+
+/* Masks for EBIU_DDRCTL1 (DDRDEVWIDTH) [in HRM: DDR_DEVWIDTH] */
+#define DDR_DEVWIDTH_4 0x00000000 /* DDR_DRVWIDTH DDR Device Width[17:16] */
+#define DDR_DEVWIDTH_8 0x00010000
+#define DDR_DEVWIDTH_16 0x00020000 /* default */
+
+/* Masks for EBIU_DDRCTL1 (DDRDEVSIZE) [in HRM: DDR_DEVSIZE] */
+#define DDR_DEVSIZE_512 0x00000000 /* DDR_DEVSIZE DDR Device Size[19:18] */
+#define DDR_DEVSIZE_64 0x00040000
+#define DDR_DEVSIZE_128 0x00080000
+#define DDR_DEVSIZE_256 0x000C0000
+
+/* Macros for EBIU_DDRCTL1 */
+#define SET_tWTR(x) (((x)&0xF) << 28) /* tWTR (Write-to-Read Delay)[3:0] - The Write to read delay (last write data to the next read command) as specified by DDR Data sheet (Default: 0x0001) */
+#define SET_tWR(x) (((x)&0x3) << 8) /* tWR Write Recovery Time[9:8] */
+#define SET_tMRD(x) (((x)&0xF) << 4) /* tMRD Mode register set to active[7:4] */
+#define SET_tRCD(x) ((x)&0xF) /* tRCD ACTIVE-to-READ/WRITE delay[3:0] */
+
+/* Bit masks for EBIU_DDRCTL2 */
+#define BURSTLENGTH 0x7 /* Burst length */
+#define CASLATENCY 0x70 /* CAS latency */
+#define DLLRESET 0x100 /* DLL Reset */
+#define nDLLRESET 0x0
+#define REGE 0x1000 /* Register mode enable */
+#define nREGE 0x0
+
+/* Masks for EBIU_DDRCTL2 (BURSTLENGTH) */
+#define BURSTLENGTH1 0x00000001 /* BURSTLENGTH Burst length[2:0] - 001 : Read Only value is set to a burst length of 2 */
+
+/* Masks for EBIU_DDRCTL2 (CASLATENCY) */
+/* CASLATENCY CAS Latency[6:4] - The number of clock cycles from assertion of read/write signal to SDRAM until first valid data on output from SDRAM. */
+#define CASLATENCY15 0x00000050 /* 101 : 1.5 */
+#define CASLATENCY2 0x00000020 /* 010 : 2 (Default) */
+#define CASLATENCY25 0x00000060 /* 110 : 2.5 */
+#define CASLATENCY3 0x00000030 /* 011 : 3 */
+
+/* Masks for EBIU_DDRCTL2 (DLLRESET) */
+#define DLL 0x00000001 /* 0: Enable DLL */
+#define nDLL 0x0 /* 0: Disable DLL (Default) */
+#define DS 0x00000002 /* Defaults to 1 ( Reduced Strength). This is the ONLY value supported */
+#define nDS 0x0
+
+/* Bit masks for EBIU_DDRCTL3 */
+#define PASR 0x7 /* Partial array self-refresh */
+
+/* Bit masks for EBIU_DDRQUE */
+#define DEB0_PFLEN 0x30 /* Pre fetch length for DEB0 accesses */
+#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
+#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
+#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
+#define DEB0_URGENT 0x4000 /* DEB0 Urgent */
+#define nDEB0_URGENT 0x0
+#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
+#define nDEB1_URGENT 0x0
+#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
+#define nDEB2_URGENT 0x0
+
+/* Bit masks for EBIU_DDRQUE (DEB0_PFLEN) */
+/* DEB0_PFLEN[1:0] - Prefetch Length for DEB0 Accesses. Based on these bits, DQM instructs DDR Controller to perform 2-beat, 4-beat or 8-beat bursts for prefetch read data. */
+#define DEB0_PFLEN0 0x00000000 /* 00 - (Single Access) */
+#define DEB0_PFLEN4 0x00000001 /* 01 - 4 Half-words (Default) */
+#define DEB0_PFLEN8 0x00000002 /* 10 - 8 Half-words */
+#define DEB0_PFLEN16 0x00000003 /* 11 - 16Half-words */
+/* performs, 16 bit read to DDR controller. Second edge is not used. */
+
+/* Bit masks for EBIU_DDRQUE (DEB1_PFLEN) */
+/* DEB1_PFLEN[3:2] - Prefetch Length for DEB0 Accesses. Based on these bits, DQM instructs DDR Controller to perform 2-beat, 4-beat or 8-beat bursts for prefetch read data. */
+#define DEB1_PFLEN0 0x00000000 /* 00 - (Single Access) */
+#define DEB1_PFLEN4 0x00000004 /* 01 - 4 Half-words (Default) */
+#define DEB1_PFLEN8 0x00000008 /* 10 - 8 Half-words */
+#define DEB1_PFLEN16 0x0000000C /* 11 - 16Half-words */
+/* performs, 16 bit read to DDR controller. Second edge is not used. */
+
+/* Bit masks for EBIU_DDRQUE (DEB2_PFLEN) */
+/* DEB2_PFLEN[5:4] - Prefetch Length for DEB0 Accesses. Based on these bits, DQM instructs DDR Controller to perform 2-beat, 4-beat or 8-beat bursts for prefetch read data. */
+#define DEB2_PFLEN0 0x00000000 /* 00 - (Single Access) */
+#define DEB2_PFLEN4 0x00000010 /* 01 - 4 Half-words (Default) */
+#define DEB2_PFLEN8 0x00000020 /* 10 - 8 Half-words */
+#define DEB2_PFLEN16 0x00000030 /* 11 - 16Half-words */
+/* performs, 16 bit read to DDR controller. Second edge is not used. */
+
+/* Bit masks for EBIU_DDRQUE (DEB_ARB_PRIORITY) */
+/* DEB_ARB_PRIORITY[10:8] - Arbitration Priority between all DEB buses for External DDR Memory: */
+#define DEB_ARB_PRIORITY0 0x00000000 /* 000 : DEB0>DEB1>DEB2 */
+#define DEB_ARB_PRIORITY1 0x00000100 /* 001 : DEB1>DEB0>DEB2 (Default) */
+#define DEB_ARB_PRIORITY2 0x00000200 /* 010 : DEB2>DEB0>DEB1 */
+/* In addition the following fixed order of arbitration is maintained:
+1. Core Lock Access
+2. Urgent DMA Access
+3. Core Access
+4. Normal DMA Access
+5. Prefetch Reads */
+
+/* Bit masks for EBIU_ERRMST */
+
+#define DEB1_ERROR 0x1 /* DEB1 Error */
+#define nDEB1_ERROR 0x0
+#define DEB2_ERROR 0x2 /* DEB2 Error */
+#define nDEB2_ERROR 0x0
+#define DEB3_ERROR 0x4 /* DEB3 Error */
+#define nDEB3_ERROR 0x0
+#define CORE_ERROR 0x8 /* Core error */
+#define nCORE_ERROR 0x0
+#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
+#define nDEB_MERROR 0x0
+#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
+#define nDEB2_MERROR 0x0
+#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
+#define nDEB3_MERROR 0x0
+#define CORE_MERROR 0x80 /* Core Error (2nd) */
+#define nCORE_MERROR 0x0
+
+/* Bit masks for EBIU_ERRADD */
+
+#define ERROR_ADDRESS 0xffffffff /* Error Address */
+
+/* Bit masks for EBIU_RSTCTL */
+
+#define DDRSRESET 0x1 /* DDR soft reset */
+#define nDDRSRESET 0x0
+#define PFTCHSRESET 0x4 /* DDR prefetch reset */
+#define nPFTCHSRESET 0x0
+#define SRREQ 0x8 /* Self-refresh request */
+#define nSRREQ 0x0
+#define SRACK 0x10 /* Self-refresh acknowledge */
+#define nSRACK 0x0
+#define MDDRENABLE 0x20 /* Mobile DDR enable */
+#define nMDDRENABLE 0x0
+
+/* Bit masks for EBIU_DDRBRC0 */
+
+#define BRC0 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC1 */
+
+#define BRC1 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC2 */
+
+#define BRC2 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC3 */
+
+#define BRC3 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC4 */
+
+#define BRC4 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC5 */
+
+#define BRC5 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC6 */
+
+#define BRC6 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBRC7 */
+
+#define BRC7 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC0 */
+
+#define BWC0 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC1 */
+
+#define BWC1 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC2 */
+
+#define BWC2 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC3 */
+
+#define BWC3 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC4 */
+
+#define BWC4 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC5 */
+
+#define BWC5 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC6 */
+
+#define BWC6 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRBWC7 */
+
+#define BWC7 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRACCT */
+
+#define ACCT 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRTACT */
+
+#define TECT 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRARCT */
+
+#define ARCT 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRGC0 */
+
+#define GC0 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRGC1 */
+
+#define GC1 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRGC2 */
+
+#define GC2 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRGC3 */
+
+#define GC3 0xffffffff /* Count */
+
+/* Bit masks for EBIU_DDRMCEN */
+
+#define B0WCENABLE 0x1 /* Bank 0 write count enable */
+#define nB0WCENABLE 0x0
+#define B1WCENABLE 0x2 /* Bank 1 write count enable */
+#define nB1WCENABLE 0x0
+#define B2WCENABLE 0x4 /* Bank 2 write count enable */
+#define nB2WCENABLE 0x0
+#define B3WCENABLE 0x8 /* Bank 3 write count enable */
+#define nB3WCENABLE 0x0
+#define B4WCENABLE 0x10 /* Bank 4 write count enable */
+#define nB4WCENABLE 0x0
+#define B5WCENABLE 0x20 /* Bank 5 write count enable */
+#define nB5WCENABLE 0x0
+#define B6WCENABLE 0x40 /* Bank 6 write count enable */
+#define nB6WCENABLE 0x0
+#define B7WCENABLE 0x80 /* Bank 7 write count enable */
+#define nB7WCENABLE 0x0
+#define B0RCENABLE 0x100 /* Bank 0 read count enable */
+#define nB0RCENABLE 0x0
+#define B1RCENABLE 0x200 /* Bank 1 read count enable */
+#define nB1RCENABLE 0x0
+#define B2RCENABLE 0x400 /* Bank 2 read count enable */
+#define nB2RCENABLE 0x0
+#define B3RCENABLE 0x800 /* Bank 3 read count enable */
+#define nB3RCENABLE 0x0
+#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
+#define nB4RCENABLE 0x0
+#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
+#define nB5RCENABLE 0x0
+#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
+#define nB6RCENABLE 0x0
+#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
+#define nB7RCENABLE 0x0
+#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
+#define nROWACTCENABLE 0x0
+#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
+#define nRWTCENABLE 0x0
+#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
+#define nARCENABLE 0x0
+#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
+#define nGC0ENABLE 0x0
+#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
+#define nGC1ENABLE 0x0
+#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
+#define nGC2ENABLE 0x0
+#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
+#define nGC3ENABLE 0x0
+#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
+
+/* Bit masks for EBIU_DDRMCCL */
+
+#define CB0WCOUNT 0x1 /* Clear write count 0 */
+#define nCB0WCOUNT 0x0
+#define CB1WCOUNT 0x2 /* Clear write count 1 */
+#define nCB1WCOUNT 0x0
+#define CB2WCOUNT 0x4 /* Clear write count 2 */
+#define nCB2WCOUNT 0x0
+#define CB3WCOUNT 0x8 /* Clear write count 3 */
+#define nCB3WCOUNT 0x0
+#define CB4WCOUNT 0x10 /* Clear write count 4 */
+#define nCB4WCOUNT 0x0
+#define CB5WCOUNT 0x20 /* Clear write count 5 */
+#define nCB5WCOUNT 0x0
+#define CB6WCOUNT 0x40 /* Clear write count 6 */
+#define nCB6WCOUNT 0x0
+#define CB7WCOUNT 0x80 /* Clear write count 7 */
+#define nCB7WCOUNT 0x0
+#define CBRCOUNT 0x100 /* Clear read count 0 */
+#define nCBRCOUNT 0x0
+#define CB1RCOUNT 0x200 /* Clear read count 1 */
+#define nCB1RCOUNT 0x0
+#define CB2RCOUNT 0x400 /* Clear read count 2 */
+#define nCB2RCOUNT 0x0
+#define CB3RCOUNT 0x800 /* Clear read count 3 */
+#define nCB3RCOUNT 0x0
+#define CB4RCOUNT 0x1000 /* Clear read count 4 */
+#define nCB4RCOUNT 0x0
+#define CB5RCOUNT 0x2000 /* Clear read count 5 */
+#define nCB5RCOUNT 0x0
+#define CB6RCOUNT 0x4000 /* Clear read count 6 */
+#define nCB6RCOUNT 0x0
+#define CB7RCOUNT 0x8000 /* Clear read count 7 */
+#define nCB7RCOUNT 0x0
+#define CRACOUNT 0x10000 /* Clear row activation count */
+#define nCRACOUNT 0x0
+#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
+#define nCRWTACOUNT 0x0
+#define CARCOUNT 0x40000 /* Clear auto-refresh count */
+#define nCARCOUNT 0x0
+#define CG0COUNT 0x100000 /* Clear grant count 0 */
+#define nCG0COUNT 0x0
+#define CG1COUNT 0x200000 /* Clear grant count 1 */
+#define nCG1COUNT 0x0
+#define CG2COUNT 0x400000 /* Clear grant count 2 */
+#define nCG2COUNT 0x0
+#define CG3COUNT 0x800000 /* Clear grant count 3 */
+#define nCG3COUNT 0x0
+
+/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
+
+#define Px0 0x1 /* GPIO 0 */
+#define nPx0 0x0
+#define Px1 0x2 /* GPIO 1 */
+#define nPx1 0x0
+#define Px2 0x4 /* GPIO 2 */
+#define nPx2 0x0
+#define Px3 0x8 /* GPIO 3 */
+#define nPx3 0x0
+#define Px4 0x10 /* GPIO 4 */
+#define nPx4 0x0
+#define Px5 0x20 /* GPIO 5 */
+#define nPx5 0x0
+#define Px6 0x40 /* GPIO 6 */
+#define nPx6 0x0
+#define Px7 0x80 /* GPIO 7 */
+#define nPx7 0x0
+#define Px8 0x100 /* GPIO 8 */
+#define nPx8 0x0
+#define Px9 0x200 /* GPIO 9 */
+#define nPx9 0x0
+#define Px10 0x400 /* GPIO 10 */
+#define nPx10 0x0
+#define Px11 0x800 /* GPIO 11 */
+#define nPx11 0x0
+#define Px12 0x1000 /* GPIO 12 */
+#define nPx12 0x0
+#define Px13 0x2000 /* GPIO 13 */
+#define nPx13 0x0
+#define Px14 0x4000 /* GPIO 14 */
+#define nPx14 0x0
+#define Px15 0x8000 /* GPIO 15 */
+#define nPx15 0x0
+
+/* Bit masks for PORTA_MUX - PORTJ_MUX */
+
+#define PxM0 0x3 /* GPIO Mux 0 */
+#define PxM1 0xc /* GPIO Mux 1 */
+#define PxM2 0x30 /* GPIO Mux 2 */
+#define PxM3 0xc0 /* GPIO Mux 3 */
+#define PxM4 0x300 /* GPIO Mux 4 */
+#define PxM5 0xc00 /* GPIO Mux 5 */
+#define PxM6 0x3000 /* GPIO Mux 6 */
+#define PxM7 0xc000 /* GPIO Mux 7 */
+#define PxM8 0x30000 /* GPIO Mux 8 */
+#define PxM9 0xc0000 /* GPIO Mux 9 */
+#define PxM10 0x300000 /* GPIO Mux 10 */
+#define PxM11 0xc00000 /* GPIO Mux 11 */
+#define PxM12 0x3000000 /* GPIO Mux 12 */
+#define PxM13 0xc000000 /* GPIO Mux 13 */
+#define PxM14 0x30000000 /* GPIO Mux 14 */
+#define PxM15 0xc0000000 /* GPIO Mux 15 */
+
+
+/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
+
+#define IB0 0x1 /* Interrupt Bit 0 */
+#define nIB0 0x0
+#define IB1 0x2 /* Interrupt Bit 1 */
+#define nIB1 0x0
+#define IB2 0x4 /* Interrupt Bit 2 */
+#define nIB2 0x0
+#define IB3 0x8 /* Interrupt Bit 3 */
+#define nIB3 0x0
+#define IB4 0x10 /* Interrupt Bit 4 */
+#define nIB4 0x0
+#define IB5 0x20 /* Interrupt Bit 5 */
+#define nIB5 0x0
+#define IB6 0x40 /* Interrupt Bit 6 */
+#define nIB6 0x0
+#define IB7 0x80 /* Interrupt Bit 7 */
+#define nIB7 0x0
+#define IB8 0x100 /* Interrupt Bit 8 */
+#define nIB8 0x0
+#define IB9 0x200 /* Interrupt Bit 9 */
+#define nIB9 0x0
+#define IB10 0x400 /* Interrupt Bit 10 */
+#define nIB10 0x0
+#define IB11 0x800 /* Interrupt Bit 11 */
+#define nIB11 0x0
+#define IB12 0x1000 /* Interrupt Bit 12 */
+#define nIB12 0x0
+#define IB13 0x2000 /* Interrupt Bit 13 */
+#define nIB13 0x0
+#define IB14 0x4000 /* Interrupt Bit 14 */
+#define nIB14 0x0
+#define IB15 0x8000 /* Interrupt Bit 15 */
+#define nIB15 0x0
+
+/* Bit masks for TIMERx_CONFIG */
+
+#define TMODE 0x3 /* Timer Mode */
+#define PULSE_HI 0x4 /* Pulse Polarity */
+#define nPULSE_HI 0x0
+#define PERIOD_CNT 0x8 /* Period Count */
+#define nPERIOD_CNT 0x0
+#define IRQ_ENA 0x10 /* Interrupt Request Enable */
+#define nIRQ_ENA 0x0
+#define TIN_SEL 0x20 /* Timer Input Select */
+#define nTIN_SEL 0x0
+#define OUT_DIS 0x40 /* Output Pad Disable */
+#define nOUT_DIS 0x0
+#define CLK_SEL 0x80 /* Timer Clock Select */
+#define nCLK_SEL 0x0
+#define TOGGLE_HI 0x100 /* Toggle Mode */
+#define nTOGGLE_HI 0x0
+#define EMU_RUN 0x200 /* Emulation Behavior Select */
+#define nEMU_RUN 0x0
+#define ERR_TYP 0xc000 /* Error Type */
+
+/* Bit masks for TIMER_ENABLE0 */
+
+#define TIMEN0 0x1 /* Timer 0 Enable */
+#define nTIMEN0 0x0
+#define TIMEN1 0x2 /* Timer 1 Enable */
+#define nTIMEN1 0x0
+#define TIMEN2 0x4 /* Timer 2 Enable */
+#define nTIMEN2 0x0
+#define TIMEN3 0x8 /* Timer 3 Enable */
+#define nTIMEN3 0x0
+#define TIMEN4 0x10 /* Timer 4 Enable */
+#define nTIMEN4 0x0
+#define TIMEN5 0x20 /* Timer 5 Enable */
+#define nTIMEN5 0x0
+#define TIMEN6 0x40 /* Timer 6 Enable */
+#define nTIMEN6 0x0
+#define TIMEN7 0x80 /* Timer 7 Enable */
+#define nTIMEN7 0x0
+
+/* Bit masks for TIMER_DISABLE0 */
+
+#define TIMDIS0 0x1 /* Timer 0 Disable */
+#define nTIMDIS0 0x0
+#define TIMDIS1 0x2 /* Timer 1 Disable */
+#define nTIMDIS1 0x0
+#define TIMDIS2 0x4 /* Timer 2 Disable */
+#define nTIMDIS2 0x0
+#define TIMDIS3 0x8 /* Timer 3 Disable */
+#define nTIMDIS3 0x0
+#define TIMDIS4 0x10 /* Timer 4 Disable */
+#define nTIMDIS4 0x0
+#define TIMDIS5 0x20 /* Timer 5 Disable */
+#define nTIMDIS5 0x0
+#define TIMDIS6 0x40 /* Timer 6 Disable */
+#define nTIMDIS6 0x0
+#define TIMDIS7 0x80 /* Timer 7 Disable */
+#define nTIMDIS7 0x0
+
+/* Bit masks for TIMER_STATUS0 */
+
+#define TIMIL0 0x1 /* Timer 0 Interrupt */
+#define nTIMIL0 0x0
+#define TIMIL1 0x2 /* Timer 1 Interrupt */
+#define nTIMIL1 0x0
+#define TIMIL2 0x4 /* Timer 2 Interrupt */
+#define nTIMIL2 0x0
+#define TIMIL3 0x8 /* Timer 3 Interrupt */
+#define nTIMIL3 0x0
+#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
+#define nTOVF_ERR0 0x0
+#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
+#define nTOVF_ERR1 0x0
+#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
+#define nTOVF_ERR2 0x0
+#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
+#define nTOVF_ERR3 0x0
+#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
+#define nTRUN0 0x0
+#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
+#define nTRUN1 0x0
+#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
+#define nTRUN2 0x0
+#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
+#define nTRUN3 0x0
+#define TIMIL4 0x10000 /* Timer 4 Interrupt */
+#define nTIMIL4 0x0
+#define TIMIL5 0x20000 /* Timer 5 Interrupt */
+#define nTIMIL5 0x0
+#define TIMIL6 0x40000 /* Timer 6 Interrupt */
+#define nTIMIL6 0x0
+#define TIMIL7 0x80000 /* Timer 7 Interrupt */
+#define nTIMIL7 0x0
+#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
+#define nTOVF_ERR4 0x0
+#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
+#define nTOVF_ERR5 0x0
+#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
+#define nTOVF_ERR6 0x0
+#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
+#define nTOVF_ERR7 0x0
+#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
+#define nTRUN4 0x0
+#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
+#define nTRUN5 0x0
+#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
+#define nTRUN6 0x0
+#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
+#define nTRUN7 0x0
+
+/* Bit masks for WDOG_CTL */
+
+#define WDEV 0x6 /* Watchdog Event */
+#define WDEN 0xff0 /* Watchdog Enable */
+#define WDRO 0x8000 /* Watchdog Rolled Over */
+#define nWDRO 0x0
+
+/* Bit masks for CNT_CONFIG */
+
+#define CNTE 0x1 /* Counter Enable */
+#define nCNTE 0x0
+#define DEBE 0x2 /* Debounce Enable */
+#define nDEBE 0x0
+#define CDGINV 0x10 /* CDG Pin Polarity Invert */
+#define nCDGINV 0x0
+#define CUDINV 0x20 /* CUD Pin Polarity Invert */
+#define nCUDINV 0x0
+#define CZMINV 0x40 /* CZM Pin Polarity Invert */
+#define nCZMINV 0x0
+#define CNTMODE 0x700 /* Counter Operating Mode */
+#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
+#define nZMZC 0x0
+#define BNDMODE 0x3000 /* Boundary register Mode */
+#define INPDIS 0x8000 /* CUG and CDG Input Disable */
+#define nINPDIS 0x0
+
+/* Bit masks for CNT_IMASK */
+
+#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
+#define nICIE 0x0
+#define UCIE 0x2 /* Up count Interrupt Enable */
+#define nUCIE 0x0
+#define DCIE 0x4 /* Down count Interrupt Enable */
+#define nDCIE 0x0
+#define MINCIE 0x8 /* Min Count Interrupt Enable */
+#define nMINCIE 0x0
+#define MAXCIE 0x10 /* Max Count Interrupt Enable */
+#define nMAXCIE 0x0
+#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
+#define nCOV31IE 0x0
+#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
+#define nCOV15IE 0x0
+#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
+#define nCZEROIE 0x0
+#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
+#define nCZMIE 0x0
+#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
+#define nCZMEIE 0x0
+#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
+#define nCZMZIE 0x0
+
+/* Bit masks for CNT_STATUS */
+
+#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
+#define nICII 0x0
+#define UCII 0x2 /* Up count Interrupt Identifier */
+#define nUCII 0x0
+#define DCII 0x4 /* Down count Interrupt Identifier */
+#define nDCII 0x0
+#define MINCII 0x8 /* Min Count Interrupt Identifier */
+#define nMINCII 0x0
+#define MAXCII 0x10 /* Max Count Interrupt Identifier */
+#define nMAXCII 0x0
+#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
+#define nCOV31II 0x0
+#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
+#define nCOV15II 0x0
+#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
+#define nCZEROII 0x0
+#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
+#define nCZMII 0x0
+#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
+#define nCZMEII 0x0
+#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
+#define nCZMZII 0x0
+
+/* Bit masks for CNT_COMMAND */
+
+#define W1LCNT 0xf /* Load Counter Register */
+#define W1LMIN 0xf0 /* Load Min Register */
+#define W1LMAX 0xf00 /* Load Max Register */
+#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
+#define nW1ZMONCE 0x0
+
+/* Bit masks for CNT_DEBOUNCE */
+
+#define DPRESCALE 0xf /* Load Counter Register */
+
+/* Bit masks for RTC_STAT */
+
+#define SECONDS 0x3f /* Seconds */
+#define MINUTES 0xfc0 /* Minutes */
+#define HOURS 0x1f000 /* Hours */
+#define DAY_COUNTER 0xfffe0000 /* Day Counter */
+
+/* Bit masks for RTC_ICTL */
+
+#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */
+#define nSTOPWATCH_INTERRUPT_ENABLE 0x0
+#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */
+#define nALARM_INTERRUPT_ENABLE 0x0
+#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */
+#define nSECONDS_INTERRUPT_ENABLE 0x0
+#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */
+#define nMINUTES_INTERRUPT_ENABLE 0x0
+#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */
+#define nHOURS_INTERRUPT_ENABLE 0x0
+#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */
+#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x0
+#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */
+#define nDAY_ALARM_INTERRUPT_ENABLE 0x0
+#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */
+#define nWRITE_COMPLETE_INTERRUPT_ENABLE 0x0
+
+/* Bit masks for RTC_ISTAT */
+
+#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */
+#define nSTOPWATCH_EVENT_FLAG 0x0
+#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */
+#define nALARM_EVENT_FLAG 0x0
+#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */
+#define nSECONDS_EVENT_FLAG 0x0
+#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */
+#define nMINUTES_EVENT_FLAG 0x0
+#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */
+#define nHOURS_EVENT_FLAG 0x0
+#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */
+#define nTWENTY_FOUR_HOURS_EVENT_FLAG 0x0
+#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */
+#define nDAY_ALARM_EVENT_FLAG 0x0
+#define WRITE_PENDING_STATUS 0x4000 /* Write Pending Status */
+#define nWRITE_PENDING_STATUS 0x0
+#define WRITE_COMPLETE 0x8000 /* Write Complete */
+#define nWRITE_COMPLETE 0x0
+
+/* Bit masks for RTC_SWCNT */
+
+#define STOPWATCH_COUNT 0xffff /* Stopwatch Count */
+
+/* Bit masks for RTC_ALARM */
+
+#define SECONDS 0x3f /* Seconds */
+#define MINUTES 0xfc0 /* Minutes */
+#define HOURS 0x1f000 /* Hours */
+#define DAY 0xfffe0000 /* Day */
+
+/* Bit masks for RTC_PREN */
+
+#define PREN 0x1 /* Prescaler Enable */
+#define nPREN 0x0
+
+/* Bit masks for OTP_CONTROL */
+
+#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
+#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
+#define nFIEN 0x0
+#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
+#define nFTESTDEC 0x0
+#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
+#define nFWRTEST 0x0
+#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
+#define nFRDEN 0x0
+#define FWREN 0x8000 /* OTP/Fuse Write Enable */
+#define nFWREN 0x0
+
+/* Bit masks for OTP_BEN */
+
+#define FBEN 0xffff /* OTP/Fuse Byte Enable */
+
+/* Bit masks for OTP_STATUS */
+
+#define FCOMP 0x1 /* OTP/Fuse Access Complete */
+#define nFCOMP 0x0
+#define FERROR 0x2 /* OTP/Fuse Access Error */
+#define nFERROR 0x0
+#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
+#define nMMRGLOAD 0x0
+#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
+#define nMMRGLOCK 0x0
+#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
+#define nFPGMEN 0x0
+
+/* Bit masks for OTP_TIMING */
+
+#define USECDIV 0xff /* Micro Second Divider */
+#define READACC 0x7f00 /* Read Access Time */
+#define CPUMPRL 0x38000 /* Charge Pump Release Time */
+#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
+#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
+#define PGMTIME 0xff000000 /* Program Time */
+
+/* Bit masks for SECURE_SYSSWT */
+
+#define EMUDABL 0x1 /* Emulation Disable. */
+#define nEMUDABL 0x0
+#define RSTDABL 0x2 /* Reset Disable */
+#define nRSTDABL 0x0
+#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
+#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
+#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
+#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
+#define nDMA0OVR 0x0
+#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
+#define nDMA1OVR 0x0
+#define EMUOVR 0x4000 /* Emulation Override */
+#define nEMUOVR 0x0
+#define OTPSEN 0x8000 /* OTP Secrets Enable. */
+#define nOTPSEN 0x0
+#define L2DABL 0x70000 /* L2 Memory Disable. */
+
+/* Bit masks for SECURE_CONTROL */
+
+#define SECURE0 0x1 /* SECURE 0 */
+#define nSECURE0 0x0
+#define SECURE1 0x2 /* SECURE 1 */
+#define nSECURE1 0x0
+#define SECURE2 0x4 /* SECURE 2 */
+#define nSECURE2 0x0
+#define SECURE3 0x8 /* SECURE 3 */
+#define nSECURE3 0x0
+
+/* Bit masks for SECURE_STATUS */
+
+#define SECMODE 0x3 /* Secured Mode Control State */
+#define NMI 0x4 /* Non Maskable Interrupt */
+#define nNMI 0x0
+#define AFVALID 0x8 /* Authentication Firmware Valid */
+#define nAFVALID 0x0
+#define AFEXIT 0x10 /* Authentication Firmware Exit */
+#define nAFEXIT 0x0
+#define SECSTAT 0xe0 /* Secure Status */
+
+/* Bit masks for PLL_DIV */
+
+#define CSEL 0x30 /* Core Select */
+#define SSEL 0xf /* System Select */
+
+/* PLL_DIV Masks (CSEL) */
+#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
+#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
+#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
+#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
+
+/* PLL_DIV Macros */
+#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
+
+/* Bit masks for PLL_CTL */
+
+#define MSEL 0x7e00 /* Multiplier Select */
+#define BYPASS 0x100 /* PLL Bypass Enable */
+#define nBYPASS 0x0
+#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
+#define nOUTPUT_DELAY 0x0
+#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
+#define nINPUT_DELAY 0x0
+#define PDWN 0x20 /* Power Down */
+#define nPDWN 0x0
+#define STOPCK 0x8 /* Stop Clock */
+#define nSTOPCK 0x0
+#define PLL_OFF 0x2 /* Disable PLL */
+#define nPLL_OFF 0x0
+#define DF 0x1 /* Divide Frequency */
+#define nDF 0x0
+
+/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
+#define SET_MSEL(x) (((x)&0x3F) << 9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
+
+/* Bit masks for PLL_STAT */
+
+#define PLL_LOCKED 0x20 /* PLL Locked Status */
+#define nPLL_LOCKED 0x0
+#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
+#define nACTIVE_PLLDISABLED 0x0
+#define FULL_ON 0x2 /* Full-On Mode */
+#define nFULL_ON 0x0
+#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
+#define nACTIVE_PLLENABLED 0x0
+#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
+#define nRTCWS 0x0
+#define CANWS 0x800 /* CAN Wake-Up Status */
+#define nCANWS 0x0
+#define USBWS 0x2000 /* USB Wake-Up Status */
+#define nUSBWS 0x0
+#define KPADWS 0x4000 /* Keypad Wake-Up Status */
+#define nKPADWS 0x0
+#define ROTWS 0x8000 /* Rotary Wake-Up Status */
+#define nROTWS 0x0
+#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
+#define nGPWS 0x0
+
+/* Bit masks for VR_CTL */
+
+#define FREQ 0x3 /* Regulator Switching Frequency */
+#define GAIN 0xc /* Voltage Output Level Gain */
+#define VLEV 0xf0 /* Internal Voltage Level */
+#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
+#define nSCKELOW 0x0
+#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
+#define nWAKE 0x0
+#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
+#define nCANWE 0x0
+#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
+#define nGPWE 0x0
+#define USBWE 0x800 /* USB Wake-Up Enable */
+#define nUSBWE 0x0
+#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
+#define nKPADWE 0x0
+#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
+#define nROTWE 0x0
+#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
+#define nCLKBUFOE 0x0
+
+/* VR_CTL Masks (FREQ) */
+#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
+#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
+#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
+
+/* VR_CTL Masks (GAIN) */
+
+#define GAIN_5 0x0000 /* GAIN = 5 */
+#define GAIN_10 0x0004 /* GAIN = 10 */
+#define GAIN_20 0x0008 /* GAIN = 20 */
+#define GAIN_50 0x000C /* GAIN = 50 */
+
+/* VR_CTL Masks (VLEV) */
+
+#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
+
+/* Bit masks for NFC_CTL */
+
+#define WR_DLY 0xf /* Write Strobe Delay */
+#define RD_DLY 0xf0 /* Read Strobe Delay */
+#define NWIDTH 0x100 /* NAND Data Width */
+#define nNWIDTH 0x0
+#define PG_SIZE 0x200 /* Page Size */
+#define nPG_SIZE 0x0
+
+/* Bit masks for NFC_STAT */
+
+#define NBUSY 0x1 /* Not Busy */
+#define nNBUSY 0x0
+#define WB_FULL 0x2 /* Write Buffer Full */
+#define nWB_FULL 0x0
+#define PG_WR_STAT 0x4 /* Page Write Pending */
+#define nPG_WR_STAT 0x0
+#define PG_RD_STAT 0x8 /* Page Read Pending */
+#define nPG_RD_STAT 0x0
+#define WB_EMPTY 0x10 /* Write Buffer Empty */
+#define nWB_EMPTY 0x0
+
+/* Bit masks for NFC_IRQSTAT */
+
+#define NBUSYIRQ 0x1 /* Not Busy IRQ */
+#define nNBUSYIRQ 0x0
+#define WB_OVF 0x2 /* Write Buffer Overflow */
+#define nWB_OVF 0x0
+#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
+#define nWB_EDGE 0x0
+#define RD_RDY 0x8 /* Read Data Ready */
+#define nRD_RDY 0x0
+#define WR_DONE 0x10 /* Page Write Done */
+#define nWR_DONE 0x0
+
+/* Bit masks for NFC_IRQMASK */
+
+#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
+#define nMASK_BUSYIRQ 0x0
+#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
+#define nMASK_WBOVF 0x0
+#define MASK_WBEDGE 0x4 /* Mask Write Buffer Edge Detect */
+#define nMASK_WBEDGE 0x0
+#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
+#define nMASK_RDRDY 0x0
+#define MASK_WRDONE 0x10 /* Mask Write Done */
+#define nMASK_WRDONE 0x0
+
+/* Bit masks for NFC_RST */
+
+#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
+#define nECC_RST 0x0
+
+/* Bit masks for NFC_PGCTL */
+
+#define PG_RD_START 0x1 /* Page Read Start */
+#define nPG_RD_START 0x0
+#define PG_WR_START 0x2 /* Page Write Start */
+#define nPG_WR_START 0x0
+
+/* Bit masks for NFC_ECC0 */
+
+#define ECC0 0x7ff /* Parity Calculation Result0 */
+
+/* Bit masks for NFC_ECC1 */
+
+#define ECC1 0x7ff /* Parity Calculation Result1 */
+
+/* Bit masks for NFC_ECC2 */
+
+#define ECC2 0x7ff /* Parity Calculation Result2 */
+
+/* Bit masks for NFC_ECC3 */
+
+#define ECC3 0x7ff /* Parity Calculation Result3 */
+
+/* Bit masks for NFC_COUNT */
+
+#define ECCCNT 0x3ff /* Transfer Count */
+
+/* Bit masks for CAN0_CONTROL */
+
+#define SRS 0x1 /* Software Reset */
+#define nSRS 0x0
+#define DNM 0x2 /* DeviceNet Mode */
+#define nDNM 0x0
+#define ABO 0x4 /* Auto Bus On */
+#define nABO 0x0
+#define WBA 0x10 /* Wakeup On CAN Bus Activity */
+#define nWBA 0x0
+#define SMR 0x20 /* Sleep Mode Request */
+#define nSMR 0x0
+#define CSR 0x40 /* CAN Suspend Mode Request */
+#define nCSR 0x0
+#define CCR 0x80 /* CAN Configuration Mode Request */
+#define nCCR 0x0
+
+/* Bit masks for CAN0_STATUS */
+
+#define WT 0x1 /* CAN Transmit Warning Flag */
+#define nWT 0x0
+#define WR 0x2 /* CAN Receive Warning Flag */
+#define nWR 0x0
+#define EP 0x4 /* CAN Error Passive Mode */
+#define nEP 0x0
+#define EBO 0x8 /* CAN Error Bus Off Mode */
+#define nEBO 0x0
+#define CSA 0x40 /* CAN Suspend Mode Acknowledge */
+#define nCSA 0x0
+#define CCA 0x80 /* CAN Configuration Mode Acknowledge */
+#define nCCA 0x0
+#define MBPTR 0x1f00 /* Mailbox Pointer */
+#define TRM 0x4000 /* Transmit Mode Status */
+#define nTRM 0x0
+#define REC 0x8000 /* Receive Mode Status */
+#define nREC 0x0
+
+/* Bit masks for CAN0_DEBUG */
+
+#define DEC 0x1 /* Disable Transmit/Receive Error Counters */
+#define nDEC 0x0
+#define DRI 0x2 /* Disable CANRX Input Pin */
+#define nDRI 0x0
+#define DTO 0x4 /* Disable CANTX Output Pin */
+#define nDTO 0x0
+#define DIL 0x8 /* Disable Internal Loop */
+#define nDIL 0x0
+#define MAA 0x10 /* Mode Auto-Acknowledge */
+#define nMAA 0x0
+#define MRB 0x20 /* Mode Read Back */
+#define nMRB 0x0
+#define CDE 0x8000 /* CAN Debug Mode Enable */
+#define nCDE 0x0
+
+/* Bit masks for CAN0_CLOCK */
+
+#define BRP 0x3ff /* CAN Bit Rate Prescaler */
+
+/* Bit masks for CAN0_TIMING */
+
+#define SJW 0x300 /* Synchronization Jump Width */
+#define SAM 0x80 /* Sampling */
+#define nSAM 0x0
+#define TSEG2 0x70 /* Time Segment 2 */
+#define TSEG1 0xf /* Time Segment 1 */
+
+/* Bit masks for CAN0_INTR */
+
+#define CANRX 0x80 /* Serial Input From Transceiver */
+#define nCANRX 0x0
+#define CANTX 0x40 /* Serial Output To Transceiver */
+#define nCANTX 0x0
+#define SMACK 0x8 /* Sleep Mode Acknowledge */
+#define nSMACK 0x0
+#define GIRQ 0x4 /* Global Interrupt Request Status */
+#define nGIRQ 0x0
+#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */
+#define nMBTIRQ 0x0
+#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */
+#define nMBRIRQ 0x0
+
+/* Bit masks for CAN0_GIM */
+
+#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */
+#define nEWTIM 0x0
+#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */
+#define nEWRIM 0x0
+#define EPIM 0x4 /* Error Passive Interrupt Mask */
+#define nEPIM 0x0
+#define BOIM 0x8 /* Bus Off Interrupt Mask */
+#define nBOIM 0x0
+#define WUIM 0x10 /* Wakeup Interrupt Mask */
+#define nWUIM 0x0
+#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */
+#define nUIAIM 0x0
+#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */
+#define nAAIM 0x0
+#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */
+#define nRMLIM 0x0
+#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */
+#define nUCEIM 0x0
+#define ADIM 0x400 /* Access Denied Interrupt Mask */
+#define nADIM 0x0
+
+/* Bit masks for CAN0_GIS */
+
+#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */
+#define nEWTIS 0x0
+#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */
+#define nEWRIS 0x0
+#define EPIS 0x4 /* Error Passive Interrupt Status */
+#define nEPIS 0x0
+#define BOIS 0x8 /* Bus Off Interrupt Status */
+#define nBOIS 0x0
+#define WUIS 0x10 /* Wakeup Interrupt Status */
+#define nWUIS 0x0
+#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */
+#define nUIAIS 0x0
+#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */
+#define nAAIS 0x0
+#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */
+#define nRMLIS 0x0
+#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */
+#define nUCEIS 0x0
+#define ADIS 0x400 /* Access Denied Interrupt Status */
+#define nADIS 0x0
+
+/* Bit masks for CAN0_GIF */
+
+#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */
+#define nEWTIF 0x0
+#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */
+#define nEWRIF 0x0
+#define EPIF 0x4 /* Error Passive Interrupt Flag */
+#define nEPIF 0x0
+#define BOIF 0x8 /* Bus Off Interrupt Flag */
+#define nBOIF 0x0
+#define WUIF 0x10 /* Wakeup Interrupt Flag */
+#define nWUIF 0x0
+#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */
+#define nUIAIF 0x0
+#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */
+#define nAAIF 0x0
+#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */
+#define nRMLIF 0x0
+#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */
+#define nUCEIF 0x0
+#define ADIF 0x400 /* Access Denied Interrupt Flag */
+#define nADIF 0x0
+
+/* Bit masks for CAN0_MBTD */
+
+#define TDR 0x80 /* Temporary Disable Request */
+#define nTDR 0x0
+#define TDA 0x40 /* Temporary Disable Acknowledge */
+#define nTDA 0x0
+#define TDPTR 0x1f /* Temporary Disable Pointer */
+
+/* Bit masks for CAN0_UCCNF */
+
+#define UCCNF 0xf /* Universal Counter Configuration */
+#define UCRC 0x20 /* Universal Counter Reload/Clear */
+#define nUCRC 0x0
+#define UCCT 0x40 /* Universal Counter CAN Trigger */
+#define nUCCT 0x0
+#define UCE 0x80 /* Universal Counter Enable */
+#define nUCE 0x0
+
+/* Bit masks for CAN0_UCCNT */
+
+#define UCCNT 0xffff /* Universal Counter Count Value */
+
+/* Bit masks for CAN0_UCRC */
+
+#define UCVAL 0xffff /* Universal Counter Reload/Capture Value */
+
+/* Bit masks for CAN0_CEC */
+
+#define RXECNT 0xff /* Receive Error Counter */
+#define TXECNT 0xff00 /* Transmit Error Counter */
+
+/* Bit masks for CAN0_ESR */
+
+#define FER 0x80 /* Form Error */
+#define nFER 0x0
+#define BEF 0x40 /* Bit Error Flag */
+#define nBEF 0x0
+#define SA0 0x20 /* Stuck At Dominant */
+#define nSA0 0x0
+#define CRCE 0x10 /* CRC Error */
+#define nCRCE 0x0
+#define SER 0x8 /* Stuff Bit Error */
+#define nSER 0x0
+#define ACKE 0x4 /* Acknowledge Error */
+#define nACKE 0x0
+
+/* Bit masks for CAN0_EWR */
+
+#define EWLTEC 0xff00 /* Transmit Error Warning Limit */
+#define EWLREC 0xff /* Receive Error Warning Limit */
+
+/* Bit masks for CAN0_AMxx_H */
+
+#define FDF 0x8000 /* Filter On Data Field */
+#define nFDF 0x0
+#define FMD 0x4000 /* Full Mask Data */
+#define nFMD 0x0
+#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */
+#define nAMIDE 0x0
+#define BASEID 0x1ffc /* Base Identifier */
+#define EXTID_HI 0x3 /* Extended Identifier High Bits */
+
+/* Bit masks for CAN0_AMxx_L */
+
+#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
+#define DFM 0xffff /* Data Field Mask */
+
+/* Bit masks for CAN0_MBxx_ID1 */
+
+#define AME 0x8000 /* Acceptance Mask Enable */
+#define nAME 0x0
+#define RTR 0x4000 /* Remote Transmission Request */
+#define nRTR 0x0
+#define IDE 0x2000 /* Identifier Extension */
+#define nIDE 0x0
+#define BASEID 0x1ffc /* Base Identifier */
+#define EXTID_HI 0x3 /* Extended Identifier High Bits */
+
+/* Bit masks for CAN0_MBxx_ID0 */
+
+#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
+#define DFM 0xffff /* Data Field Mask */
+
+/* Bit masks for CAN0_MBxx_TIMESTAMP */
+
+#define TSV 0xffff /* Time Stamp Value */
+
+/* Bit masks for CAN0_MBxx_LENGTH */
+
+#define DLC 0xf /* Data Length Code */
+
+/* Bit masks for CAN0_MBxx_DATA3 */
+
+#define CAN_BYTE0 0xff00 /* Data Field Byte 0 */
+#define CAN_BYTE1 0xff /* Data Field Byte 1 */
+
+/* Bit masks for CAN0_MBxx_DATA2 */
+
+#define CAN_BYTE2 0xff00 /* Data Field Byte 2 */
+#define CAN_BYTE3 0xff /* Data Field Byte 3 */
+
+/* Bit masks for CAN0_MBxx_DATA1 */
+
+#define CAN_BYTE4 0xff00 /* Data Field Byte 4 */
+#define CAN_BYTE5 0xff /* Data Field Byte 5 */
+
+/* Bit masks for CAN0_MBxx_DATA0 */
+
+#define CAN_BYTE6 0xff00 /* Data Field Byte 6 */
+#define CAN_BYTE7 0xff /* Data Field Byte 7 */
+
+/* Bit masks for CAN0_MC1 */
+
+#define MC0 0x1 /* Mailbox 0 Enable */
+#define nMC0 0x0
+#define MC1 0x2 /* Mailbox 1 Enable */
+#define nMC1 0x0
+#define MC2 0x4 /* Mailbox 2 Enable */
+#define nMC2 0x0
+#define MC3 0x8 /* Mailbox 3 Enable */
+#define nMC3 0x0
+#define MC4 0x10 /* Mailbox 4 Enable */
+#define nMC4 0x0
+#define MC5 0x20 /* Mailbox 5 Enable */
+#define nMC5 0x0
+#define MC6 0x40 /* Mailbox 6 Enable */
+#define nMC6 0x0
+#define MC7 0x80 /* Mailbox 7 Enable */
+#define nMC7 0x0
+#define MC8 0x100 /* Mailbox 8 Enable */
+#define nMC8 0x0
+#define MC9 0x200 /* Mailbox 9 Enable */
+#define nMC9 0x0
+#define MC10 0x400 /* Mailbox 10 Enable */
+#define nMC10 0x0
+#define MC11 0x800 /* Mailbox 11 Enable */
+#define nMC11 0x0
+#define MC12 0x1000 /* Mailbox 12 Enable */
+#define nMC12 0x0
+#define MC13 0x2000 /* Mailbox 13 Enable */
+#define nMC13 0x0
+#define MC14 0x4000 /* Mailbox 14 Enable */
+#define nMC14 0x0
+#define MC15 0x8000 /* Mailbox 15 Enable */
+#define nMC15 0x0
+
+/* Bit masks for CAN0_MC2 */
+
+#define MC16 0x1 /* Mailbox 16 Enable */
+#define nMC16 0x0
+#define MC17 0x2 /* Mailbox 17 Enable */
+#define nMC17 0x0
+#define MC18 0x4 /* Mailbox 18 Enable */
+#define nMC18 0x0
+#define MC19 0x8 /* Mailbox 19 Enable */
+#define nMC19 0x0
+#define MC20 0x10 /* Mailbox 20 Enable */
+#define nMC20 0x0
+#define MC21 0x20 /* Mailbox 21 Enable */
+#define nMC21 0x0
+#define MC22 0x40 /* Mailbox 22 Enable */
+#define nMC22 0x0
+#define MC23 0x80 /* Mailbox 23 Enable */
+#define nMC23 0x0
+#define MC24 0x100 /* Mailbox 24 Enable */
+#define nMC24 0x0
+#define MC25 0x200 /* Mailbox 25 Enable */
+#define nMC25 0x0
+#define MC26 0x400 /* Mailbox 26 Enable */
+#define nMC26 0x0
+#define MC27 0x800 /* Mailbox 27 Enable */
+#define nMC27 0x0
+#define MC28 0x1000 /* Mailbox 28 Enable */
+#define nMC28 0x0
+#define MC29 0x2000 /* Mailbox 29 Enable */
+#define nMC29 0x0
+#define MC30 0x4000 /* Mailbox 30 Enable */
+#define nMC30 0x0
+#define MC31 0x8000 /* Mailbox 31 Enable */
+#define nMC31 0x0
+
+/* Bit masks for CAN0_MD1 */
+
+#define MD0 0x1 /* Mailbox 0 Receive Enable */
+#define nMD0 0x0
+#define MD1 0x2 /* Mailbox 1 Receive Enable */
+#define nMD1 0x0
+#define MD2 0x4 /* Mailbox 2 Receive Enable */
+#define nMD2 0x0
+#define MD3 0x8 /* Mailbox 3 Receive Enable */
+#define nMD3 0x0
+#define MD4 0x10 /* Mailbox 4 Receive Enable */
+#define nMD4 0x0
+#define MD5 0x20 /* Mailbox 5 Receive Enable */
+#define nMD5 0x0
+#define MD6 0x40 /* Mailbox 6 Receive Enable */
+#define nMD6 0x0
+#define MD7 0x80 /* Mailbox 7 Receive Enable */
+#define nMD7 0x0
+#define MD8 0x100 /* Mailbox 8 Receive Enable */
+#define nMD8 0x0
+#define MD9 0x200 /* Mailbox 9 Receive Enable */
+#define nMD9 0x0
+#define MD10 0x400 /* Mailbox 10 Receive Enable */
+#define nMD10 0x0
+#define MD11 0x800 /* Mailbox 11 Receive Enable */
+#define nMD11 0x0
+#define MD12 0x1000 /* Mailbox 12 Receive Enable */
+#define nMD12 0x0
+#define MD13 0x2000 /* Mailbox 13 Receive Enable */
+#define nMD13 0x0
+#define MD14 0x4000 /* Mailbox 14 Receive Enable */
+#define nMD14 0x0
+#define MD15 0x8000 /* Mailbox 15 Receive Enable */
+#define nMD15 0x0
+
+/* Bit masks for CAN0_MD2 */
+
+#define MD16 0x1 /* Mailbox 16 Receive Enable */
+#define nMD16 0x0
+#define MD17 0x2 /* Mailbox 17 Receive Enable */
+#define nMD17 0x0
+#define MD18 0x4 /* Mailbox 18 Receive Enable */
+#define nMD18 0x0
+#define MD19 0x8 /* Mailbox 19 Receive Enable */
+#define nMD19 0x0
+#define MD20 0x10 /* Mailbox 20 Receive Enable */
+#define nMD20 0x0
+#define MD21 0x20 /* Mailbox 21 Receive Enable */
+#define nMD21 0x0
+#define MD22 0x40 /* Mailbox 22 Receive Enable */
+#define nMD22 0x0
+#define MD23 0x80 /* Mailbox 23 Receive Enable */
+#define nMD23 0x0
+#define MD24 0x100 /* Mailbox 24 Receive Enable */
+#define nMD24 0x0
+#define MD25 0x200 /* Mailbox 25 Receive Enable */
+#define nMD25 0x0
+#define MD26 0x400 /* Mailbox 26 Receive Enable */
+#define nMD26 0x0
+#define MD27 0x800 /* Mailbox 27 Receive Enable */
+#define nMD27 0x0
+#define MD28 0x1000 /* Mailbox 28 Receive Enable */
+#define nMD28 0x0
+#define MD29 0x2000 /* Mailbox 29 Receive Enable */
+#define nMD29 0x0
+#define MD30 0x4000 /* Mailbox 30 Receive Enable */
+#define nMD30 0x0
+#define MD31 0x8000 /* Mailbox 31 Receive Enable */
+#define nMD31 0x0
+
+/* Bit masks for CAN0_RMP1 */
+
+#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */
+#define nRMP0 0x0
+#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */
+#define nRMP1 0x0
+#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
+#define nRMP2 0x0
+#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */
+#define nRMP3 0x0
+#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */
+#define nRMP4 0x0
+#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */
+#define nRMP5 0x0
+#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */
+#define nRMP6 0x0
+#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */
+#define nRMP7 0x0
+#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */
+#define nRMP8 0x0
+#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */
+#define nRMP9 0x0
+#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */
+#define nRMP10 0x0
+#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */
+#define nRMP11 0x0
+#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */
+#define nRMP12 0x0
+#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */
+#define nRMP13 0x0
+#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */
+#define nRMP14 0x0
+#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */
+#define nRMP15 0x0
+
+/* Bit masks for CAN0_RMP2 */
+
+#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */
+#define nRMP16 0x0
+#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */
+#define nRMP17 0x0
+#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
+#define nRMP18 0x0
+#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */
+#define nRMP19 0x0
+#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */
+#define nRMP20 0x0
+#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */
+#define nRMP21 0x0
+#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */
+#define nRMP22 0x0
+#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */
+#define nRMP23 0x0
+#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */
+#define nRMP24 0x0
+#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */
+#define nRMP25 0x0
+#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */
+#define nRMP26 0x0
+#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */
+#define nRMP27 0x0
+#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */
+#define nRMP28 0x0
+#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */
+#define nRMP29 0x0
+#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */
+#define nRMP30 0x0
+#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */
+#define nRMP31 0x0
+
+/* Bit masks for CAN0_RML1 */
+
+#define RML0 0x1 /* Mailbox 0 Receive Message Lost */
+#define nRML0 0x0
+#define RML1 0x2 /* Mailbox 1 Receive Message Lost */
+#define nRML1 0x0
+#define RML2 0x4 /* Mailbox 2 Receive Message Lost */
+#define nRML2 0x0
+#define RML3 0x8 /* Mailbox 3 Receive Message Lost */
+#define nRML3 0x0
+#define RML4 0x10 /* Mailbox 4 Receive Message Lost */
+#define nRML4 0x0
+#define RML5 0x20 /* Mailbox 5 Receive Message Lost */
+#define nRML5 0x0
+#define RML6 0x40 /* Mailbox 6 Receive Message Lost */
+#define nRML6 0x0
+#define RML7 0x80 /* Mailbox 7 Receive Message Lost */
+#define nRML7 0x0
+#define RML8 0x100 /* Mailbox 8 Receive Message Lost */
+#define nRML8 0x0
+#define RML9 0x200 /* Mailbox 9 Receive Message Lost */
+#define nRML9 0x0
+#define RML10 0x400 /* Mailbox 10 Receive Message Lost */
+#define nRML10 0x0
+#define RML11 0x800 /* Mailbox 11 Receive Message Lost */
+#define nRML11 0x0
+#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */
+#define nRML12 0x0
+#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */
+#define nRML13 0x0
+#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */
+#define nRML14 0x0
+#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */
+#define nRML15 0x0
+
+/* Bit masks for CAN0_RML2 */
+
+#define RML16 0x1 /* Mailbox 16 Receive Message Lost */
+#define nRML16 0x0
+#define RML17 0x2 /* Mailbox 17 Receive Message Lost */
+#define nRML17 0x0
+#define RML18 0x4 /* Mailbox 18 Receive Message Lost */
+#define nRML18 0x0
+#define RML19 0x8 /* Mailbox 19 Receive Message Lost */
+#define nRML19 0x0
+#define RML20 0x10 /* Mailbox 20 Receive Message Lost */
+#define nRML20 0x0
+#define RML21 0x20 /* Mailbox 21 Receive Message Lost */
+#define nRML21 0x0
+#define RML22 0x40 /* Mailbox 22 Receive Message Lost */
+#define nRML22 0x0
+#define RML23 0x80 /* Mailbox 23 Receive Message Lost */
+#define nRML23 0x0
+#define RML24 0x100 /* Mailbox 24 Receive Message Lost */
+#define nRML24 0x0
+#define RML25 0x200 /* Mailbox 25 Receive Message Lost */
+#define nRML25 0x0
+#define RML26 0x400 /* Mailbox 26 Receive Message Lost */
+#define nRML26 0x0
+#define RML27 0x800 /* Mailbox 27 Receive Message Lost */
+#define nRML27 0x0
+#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */
+#define nRML28 0x0
+#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */
+#define nRML29 0x0
+#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */
+#define nRML30 0x0
+#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */
+#define nRML31 0x0
+
+/* Bit masks for CAN0_OPSS1 */
+
+#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS0 0x0
+#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS1 0x0
+#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS2 0x0
+#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS3 0x0
+#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS4 0x0
+#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS5 0x0
+#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS6 0x0
+#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS7 0x0
+#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS8 0x0
+#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS9 0x0
+#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS10 0x0
+#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS11 0x0
+#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS12 0x0
+#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS13 0x0
+#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS14 0x0
+#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS15 0x0
+
+/* Bit masks for CAN0_OPSS2 */
+
+#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS16 0x0
+#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS17 0x0
+#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS18 0x0
+#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS19 0x0
+#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS20 0x0
+#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS21 0x0
+#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS22 0x0
+#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS23 0x0
+#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS24 0x0
+#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS25 0x0
+#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS26 0x0
+#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS27 0x0
+#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS28 0x0
+#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS29 0x0
+#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS30 0x0
+#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
+#define nOPSS31 0x0
+
+/* Bit masks for CAN0_TRS1 */
+
+#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */
+#define nTRS0 0x0
+#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */
+#define nTRS1 0x0
+#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
+#define nTRS2 0x0
+#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */
+#define nTRS3 0x0
+#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */
+#define nTRS4 0x0
+#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */
+#define nTRS5 0x0
+#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */
+#define nTRS6 0x0
+#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */
+#define nTRS7 0x0
+#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */
+#define nTRS8 0x0
+#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */
+#define nTRS9 0x0
+#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */
+#define nTRS10 0x0
+#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */
+#define nTRS11 0x0
+#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */
+#define nTRS12 0x0
+#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */
+#define nTRS13 0x0
+#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */
+#define nTRS14 0x0
+#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */
+#define nTRS15 0x0
+
+/* Bit masks for CAN0_TRS2 */
+
+#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */
+#define nTRS16 0x0
+#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */
+#define nTRS17 0x0
+#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
+#define nTRS18 0x0
+#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */
+#define nTRS19 0x0
+#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */
+#define nTRS20 0x0
+#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */
+#define nTRS21 0x0
+#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */
+#define nTRS22 0x0
+#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */
+#define nTRS23 0x0
+#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */
+#define nTRS24 0x0
+#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */
+#define nTRS25 0x0
+#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */
+#define nTRS26 0x0
+#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */
+#define nTRS27 0x0
+#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */
+#define nTRS28 0x0
+#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */
+#define nTRS29 0x0
+#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */
+#define nTRS30 0x0
+#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */
+#define nTRS31 0x0
+
+/* Bit masks for CAN0_TRR1 */
+
+#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */
+#define nTRR0 0x0
+#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */
+#define nTRR1 0x0
+#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
+#define nTRR2 0x0
+#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */
+#define nTRR3 0x0
+#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */
+#define nTRR4 0x0
+#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */
+#define nTRR5 0x0
+#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */
+#define nTRR6 0x0
+#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */
+#define nTRR7 0x0
+#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */
+#define nTRR8 0x0
+#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */
+#define nTRR9 0x0
+#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */
+#define nTRR10 0x0
+#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */
+#define nTRR11 0x0
+#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */
+#define nTRR12 0x0
+#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */
+#define nTRR13 0x0
+#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */
+#define nTRR14 0x0
+#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */
+#define nTRR15 0x0
+
+/* Bit masks for CAN0_TRR2 */
+
+#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */
+#define nTRR16 0x0
+#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */
+#define nTRR17 0x0
+#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
+#define nTRR18 0x0
+#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */
+#define nTRR19 0x0
+#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */
+#define nTRR20 0x0
+#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */
+#define nTRR21 0x0
+#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */
+#define nTRR22 0x0
+#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */
+#define nTRR23 0x0
+#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */
+#define nTRR24 0x0
+#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */
+#define nTRR25 0x0
+#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */
+#define nTRR26 0x0
+#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */
+#define nTRR27 0x0
+#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */
+#define nTRR28 0x0
+#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */
+#define nTRR29 0x0
+#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */
+#define nTRR30 0x0
+#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */
+#define nTRR31 0x0
+
+/* Bit masks for CAN0_AA1 */
+
+#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */
+#define nAA0 0x0
+#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */
+#define nAA1 0x0
+#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
+#define nAA2 0x0
+#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */
+#define nAA3 0x0
+#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */
+#define nAA4 0x0
+#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */
+#define nAA5 0x0
+#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */
+#define nAA6 0x0
+#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */
+#define nAA7 0x0
+#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */
+#define nAA8 0x0
+#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */
+#define nAA9 0x0
+#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */
+#define nAA10 0x0
+#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */
+#define nAA11 0x0
+#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */
+#define nAA12 0x0
+#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */
+#define nAA13 0x0
+#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */
+#define nAA14 0x0
+#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */
+#define nAA15 0x0
+
+/* Bit masks for CAN0_AA2 */
+
+#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */
+#define nAA16 0x0
+#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */
+#define nAA17 0x0
+#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
+#define nAA18 0x0
+#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */
+#define nAA19 0x0
+#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */
+#define nAA20 0x0
+#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */
+#define nAA21 0x0
+#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */
+#define nAA22 0x0
+#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */
+#define nAA23 0x0
+#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */
+#define nAA24 0x0
+#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */
+#define nAA25 0x0
+#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */
+#define nAA26 0x0
+#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */
+#define nAA27 0x0
+#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */
+#define nAA28 0x0
+#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */
+#define nAA29 0x0
+#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */
+#define nAA30 0x0
+#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */
+#define nAA31 0x0
+
+/* Bit masks for CAN0_TA1 */
+
+#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */
+#define nTA0 0x0
+#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */
+#define nTA1 0x0
+#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
+#define nTA2 0x0
+#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */
+#define nTA3 0x0
+#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */
+#define nTA4 0x0
+#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */
+#define nTA5 0x0
+#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */
+#define nTA6 0x0
+#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */
+#define nTA7 0x0
+#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */
+#define nTA8 0x0
+#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */
+#define nTA9 0x0
+#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */
+#define nTA10 0x0
+#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */
+#define nTA11 0x0
+#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */
+#define nTA12 0x0
+#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */
+#define nTA13 0x0
+#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */
+#define nTA14 0x0
+#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */
+#define nTA15 0x0
+
+/* Bit masks for CAN0_TA2 */
+
+#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */
+#define nTA16 0x0
+#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */
+#define nTA17 0x0
+#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
+#define nTA18 0x0
+#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */
+#define nTA19 0x0
+#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */
+#define nTA20 0x0
+#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */
+#define nTA21 0x0
+#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */
+#define nTA22 0x0
+#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */
+#define nTA23 0x0
+#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */
+#define nTA24 0x0
+#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */
+#define nTA25 0x0
+#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */
+#define nTA26 0x0
+#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */
+#define nTA27 0x0
+#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */
+#define nTA28 0x0
+#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */
+#define nTA29 0x0
+#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */
+#define nTA30 0x0
+#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */
+#define nTA31 0x0
+
+/* Bit masks for CAN0_RFH1 */
+
+#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */
+#define nRFH0 0x0
+#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */
+#define nRFH1 0x0
+#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
+#define nRFH2 0x0
+#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */
+#define nRFH3 0x0
+#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */
+#define nRFH4 0x0
+#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */
+#define nRFH5 0x0
+#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */
+#define nRFH6 0x0
+#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */
+#define nRFH7 0x0
+#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */
+#define nRFH8 0x0
+#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */
+#define nRFH9 0x0
+#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */
+#define nRFH10 0x0
+#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */
+#define nRFH11 0x0
+#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */
+#define nRFH12 0x0
+#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */
+#define nRFH13 0x0
+#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */
+#define nRFH14 0x0
+#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */
+#define nRFH15 0x0
+
+/* Bit masks for CAN0_RFH2 */
+
+#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */
+#define nRFH16 0x0
+#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */
+#define nRFH17 0x0
+#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
+#define nRFH18 0x0
+#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */
+#define nRFH19 0x0
+#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */
+#define nRFH20 0x0
+#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */
+#define nRFH21 0x0
+#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */
+#define nRFH22 0x0
+#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */
+#define nRFH23 0x0
+#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */
+#define nRFH24 0x0
+#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */
+#define nRFH25 0x0
+#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */
+#define nRFH26 0x0
+#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */
+#define nRFH27 0x0
+#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */
+#define nRFH28 0x0
+#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */
+#define nRFH29 0x0
+#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */
+#define nRFH30 0x0
+#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */
+#define nRFH31 0x0
+
+/* Bit masks for CAN0_MBIM1 */
+
+#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */
+#define nMBIM0 0x0
+#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */
+#define nMBIM1 0x0
+#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
+#define nMBIM2 0x0
+#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */
+#define nMBIM3 0x0
+#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */
+#define nMBIM4 0x0
+#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */
+#define nMBIM5 0x0
+#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */
+#define nMBIM6 0x0
+#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */
+#define nMBIM7 0x0
+#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */
+#define nMBIM8 0x0
+#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */
+#define nMBIM9 0x0
+#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */
+#define nMBIM10 0x0
+#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */
+#define nMBIM11 0x0
+#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */
+#define nMBIM12 0x0
+#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */
+#define nMBIM13 0x0
+#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */
+#define nMBIM14 0x0
+#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */
+#define nMBIM15 0x0
+
+/* Bit masks for CAN0_MBIM2 */
+
+#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */
+#define nMBIM16 0x0
+#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */
+#define nMBIM17 0x0
+#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
+#define nMBIM18 0x0
+#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */
+#define nMBIM19 0x0
+#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */
+#define nMBIM20 0x0
+#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */
+#define nMBIM21 0x0
+#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */
+#define nMBIM22 0x0
+#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */
+#define nMBIM23 0x0
+#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */
+#define nMBIM24 0x0
+#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */
+#define nMBIM25 0x0
+#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */
+#define nMBIM26 0x0
+#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */
+#define nMBIM27 0x0
+#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */
+#define nMBIM28 0x0
+#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */
+#define nMBIM29 0x0
+#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */
+#define nMBIM30 0x0
+#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */
+#define nMBIM31 0x0
+
+/* Bit masks for CAN0_MBTIF1 */
+
+#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */
+#define nMBTIF0 0x0
+#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */
+#define nMBTIF1 0x0
+#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
+#define nMBTIF2 0x0
+#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */
+#define nMBTIF3 0x0
+#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */
+#define nMBTIF4 0x0
+#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */
+#define nMBTIF5 0x0
+#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */
+#define nMBTIF6 0x0
+#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */
+#define nMBTIF7 0x0
+#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */
+#define nMBTIF8 0x0
+#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */
+#define nMBTIF9 0x0
+#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */
+#define nMBTIF10 0x0
+#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */
+#define nMBTIF11 0x0
+#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */
+#define nMBTIF12 0x0
+#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */
+#define nMBTIF13 0x0
+#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */
+#define nMBTIF14 0x0
+#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */
+#define nMBTIF15 0x0
+
+/* Bit masks for CAN0_MBTIF2 */
+
+#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */
+#define nMBTIF16 0x0
+#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */
+#define nMBTIF17 0x0
+#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
+#define nMBTIF18 0x0
+#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */
+#define nMBTIF19 0x0
+#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */
+#define nMBTIF20 0x0
+#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */
+#define nMBTIF21 0x0
+#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */
+#define nMBTIF22 0x0
+#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */
+#define nMBTIF23 0x0
+#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */
+#define nMBTIF24 0x0
+#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */
+#define nMBTIF25 0x0
+#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */
+#define nMBTIF26 0x0
+#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */
+#define nMBTIF27 0x0
+#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */
+#define nMBTIF28 0x0
+#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */
+#define nMBTIF29 0x0
+#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */
+#define nMBTIF30 0x0
+#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */
+#define nMBTIF31 0x0
+
+/* Bit masks for CAN0_MBRIF1 */
+
+#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */
+#define nMBRIF0 0x0
+#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */
+#define nMBRIF1 0x0
+#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
+#define nMBRIF2 0x0
+#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */
+#define nMBRIF3 0x0
+#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */
+#define nMBRIF4 0x0
+#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */
+#define nMBRIF5 0x0
+#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */
+#define nMBRIF6 0x0
+#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */
+#define nMBRIF7 0x0
+#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */
+#define nMBRIF8 0x0
+#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */
+#define nMBRIF9 0x0
+#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */
+#define nMBRIF10 0x0
+#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */
+#define nMBRIF11 0x0
+#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */
+#define nMBRIF12 0x0
+#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */
+#define nMBRIF13 0x0
+#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */
+#define nMBRIF14 0x0
+#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */
+#define nMBRIF15 0x0
+
+/* Bit masks for CAN0_MBRIF2 */
+
+#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */
+#define nMBRIF16 0x0
+#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */
+#define nMBRIF17 0x0
+#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
+#define nMBRIF18 0x0
+#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */
+#define nMBRIF19 0x0
+#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */
+#define nMBRIF20 0x0
+#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */
+#define nMBRIF21 0x0
+#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */
+#define nMBRIF22 0x0
+#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */
+#define nMBRIF23 0x0
+#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */
+#define nMBRIF24 0x0
+#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */
+#define nMBRIF25 0x0
+#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */
+#define nMBRIF26 0x0
+#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */
+#define nMBRIF27 0x0
+#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */
+#define nMBRIF28 0x0
+#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */
+#define nMBRIF29 0x0
+#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */
+#define nMBRIF30 0x0
+#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */
+#define nMBRIF31 0x0
+
+/* Bit masks for EPPIx_STATUS */
+
+#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
+#define nCFIFO_ERR 0x0
+#define YFIFO_ERR 0x2 /* Luma FIFO Error */
+#define nYFIFO_ERR 0x0
+#define LTERR_OVR 0x4 /* Line Track Overflow */
+#define nLTERR_OVR 0x0
+#define LTERR_UNDR 0x8 /* Line Track Underflow */
+#define nLTERR_UNDR 0x0
+#define FTERR_OVR 0x10 /* Frame Track Overflow */
+#define nFTERR_OVR 0x0
+#define FTERR_UNDR 0x20 /* Frame Track Underflow */
+#define nFTERR_UNDR 0x0
+#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
+#define nERR_NCOR 0x0
+#define DMA1URQ 0x80 /* DMA1 Urgent Request */
+#define nDMA1URQ 0x0
+#define DMA0URQ 0x100 /* DMA0 Urgent Request */
+#define nDMA0URQ 0x0
+#define ERR_DET 0x4000 /* Preamble Error Detected */
+#define nERR_DET 0x0
+#define FLD 0x8000 /* Field */
+#define nFLD 0x0
+
+/* Bit masks for EPPIx_CONTROL */
+
+#define EPPI_EN 0x1 /* Enable */
+#define nEPPI_EN 0x0
+#define EPPI_DIR 0x2 /* Direction */
+#define nEPPI_DIR 0x0
+#define XFR_TYPE 0xc /* Operating Mode */
+#define FS_CFG 0x30 /* Frame Sync Configuration */
+#define FLD_SEL 0x40 /* Field Select/Trigger */
+#define nFLD_SEL 0x0
+#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
+#define nITU_TYPE 0x0
+#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
+#define nBLANKGEN 0x0
+#define ICLKGEN 0x200 /* Internal Clock Generation */
+#define nICLKGEN 0x0
+#define IFSGEN 0x400 /* Internal Frame Sync Generation */
+#define nIFSGEN 0x0
+#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
+#define POLS 0x6000 /* Frame Sync Polarity */
+#define DLEN 0x38000 /* Data Length */
+#define SKIP_EN 0x40000 /* Skip Enable */
+#define nSKIP_EN 0x0
+#define SKIP_EO 0x80000 /* Skip Even or Odd */
+#define nSKIP_EO 0x0
+#define PACKEN 0x100000 /* Packing/Unpacking Enable */
+#define nPACKEN 0x0
+#define SWAPEN 0x200000 /* Swap Enable */
+#define nSWAPEN 0x0
+#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
+#define nSIGN_EXT 0x0
+#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
+#define nSPLT_EVEN_ODD 0x0
+#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
+#define nSUBSPLT_ODD 0x0
+#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
+#define nDMACFG 0x0
+#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
+#define nRGB_FMT_EN 0x0
+#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
+#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
+
+/* Bit masks for EPPIx_FS2W_LVB */
+
+#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */
+#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */
+#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */
+#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
+
+/* Bit masks for EPPIx_FS2W_LAVF */
+
+#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */
+#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
+
+/* Bit masks for EPPIx_CLIP */
+
+#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */
+#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */
+#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
+#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
+
+/* Bit masks for SPIx_BAUD */
+
+#define SPI_BAUD 0xffff /* Baud Rate */
+
+/* Bit masks for SPIx_CTL */
+
+#define SPE 0x4000 /* SPI Enable */
+#define nSPE 0x0
+#define WOM 0x2000 /* Write Open Drain Master */
+#define nWOM 0x0
+#define MSTR 0x1000 /* Master Mode */
+#define nMSTR 0x0
+#define CPOL 0x800 /* Clock Polarity */
+#define nCPOL 0x0
+#define CPHA 0x400 /* Clock Phase */
+#define nCPHA 0x0
+#define LSBF 0x200 /* LSB First */
+#define nLSBF 0x0
+#define SIZE 0x100 /* Size of Words */
+#define nSIZE 0x0
+#define EMISO 0x20 /* Enable MISO Output */
+#define nEMISO 0x0
+#define PSSE 0x10 /* Slave-Select Enable */
+#define nPSSE 0x0
+#define GM 0x8 /* Get More Data */
+#define nGM 0x0
+#define SZ 0x4 /* Send Zero */
+#define nSZ 0x0
+#define TIMOD 0x3 /* Transfer Initiation Mode */
+
+/* Bit masks for SPIx_FLG */
+
+#define FLS1 0x2 /* Slave Select Enable 1 */
+#define nFLS1 0x0
+#define FLS2 0x4 /* Slave Select Enable 2 */
+#define nFLS2 0x0
+#define FLS3 0x8 /* Slave Select Enable 3 */
+#define nFLS3 0x0
+#define FLG1 0x200 /* Slave Select Value 1 */
+#define nFLG1 0x0
+#define FLG2 0x400 /* Slave Select Value 2 */
+#define nFLG2 0x0
+#define FLG3 0x800 /* Slave Select Value 3 */
+#define nFLG3 0x0
+
+/* Bit masks for SPIx_STAT */
+
+#define TXCOL 0x40 /* Transmit Collision Error */
+#define nTXCOL 0x0
+#define RXS 0x20 /* RDBR Data Buffer Status */
+#define nRXS 0x0
+#define RBSY 0x10 /* Receive Error */
+#define nRBSY 0x0
+#define TXS 0x8 /* TDBR Data Buffer Status */
+#define nTXS 0x0
+#define TXE 0x4 /* Transmission Error */
+#define nTXE 0x0
+#define MODF 0x2 /* Mode Fault Error */
+#define nMODF 0x0
+#define SPIF 0x1 /* SPI Finished */
+#define nSPIF 0x0
+
+/* Bit masks for SPIx_TDBR */
+
+#define TDBR 0xffff /* Transmit Data Buffer */
+
+/* Bit masks for SPIx_RDBR */
+
+#define RDBR 0xffff /* Receive Data Buffer */
+
+/* Bit masks for SPIx_SHADOW */
+
+#define SHADOW 0xffff /* RDBR Shadow */
+
+/* ************************************************ */
+/* The TWI bit masks fields are from the ADSP-BF538 */
+/* and they have not been verified as the final */
+/* ones for the Moab processors ... bz 1/19/2007 */
+/* ************************************************ */
+
+/* Bit masks for TWIx_CONTROL */
+
+#define PRESCALE 0x7f /* Prescale Value */
+#define TWI_ENA 0x80 /* TWI Enable */
+#define nTWI_ENA 0x0
+#define SCCB 0x200 /* Serial Camera Control Bus */
+#define nSCCB 0x0
+
+/* Bit maskes for TWIx_CLKDIV */
+
+#define CLKLOW 0xff /* Clock Low */
+#define CLKHI 0xff00 /* Clock High */
+
+/* Bit maskes for TWIx_SLAVE_CTL */
+
+#define SEN 0x1 /* Slave Enable */
+#define nSEN 0x0
+#define STDVAL 0x4 /* Slave Transmit Data Valid */
+#define nSTDVAL 0x0
+#define NAK 0x8 /* Not Acknowledge */
+#define nNAK 0x0
+#define GEN 0x10 /* General Call Enable */
+#define nGEN 0x0
+
+/* Bit maskes for TWIx_SLAVE_ADDR */
+
+#define SADDR 0x7f /* Slave Mode Address */
+
+/* Bit maskes for TWIx_SLAVE_STAT */
+
+#define SDIR 0x1 /* Slave Transfer Direction */
+#define nSDIR 0x0
+#define GCALL 0x2 /* General Call */
+#define nGCALL 0x0
+
+/* Bit maskes for TWIx_MASTER_CTL */
+
+#define MEN 0x1 /* Master Mode Enable */
+#define nMEN 0x0
+#define MDIR 0x4 /* Master Transfer Direction */
+#define nMDIR 0x0
+#define FAST 0x8 /* Fast Mode */
+#define nFAST 0x0
+#define STOP 0x10 /* Issue Stop Condition */
+#define nSTOP 0x0
+#define RSTART 0x20 /* Repeat Start */
+#define nRSTART 0x0
+#define DCNT 0x3fc0 /* Data Transfer Count */
+#define SDAOVR 0x4000 /* Serial Data Override */
+#define nSDAOVR 0x0
+#define SCLOVR 0x8000 /* Serial Clock Override */
+#define nSCLOVR 0x0
+
+/* Bit maskes for TWIx_MASTER_ADDR */
+
+#define MADDR 0x7f /* Master Mode Address */
+
+/* Bit maskes for TWIx_MASTER_STAT */
+
+#define MPROG 0x1 /* Master Transfer in Progress */
+#define nMPROG 0x0
+#define LOSTARB 0x2 /* Lost Arbitration */
+#define nLOSTARB 0x0
+#define ANAK 0x4 /* Address Not Acknowledged */
+#define nANAK 0x0
+#define DNAK 0x8 /* Data Not Acknowledged */
+#define nDNAK 0x0
+#define BUFRDERR 0x10 /* Buffer Read Error */
+#define nBUFRDERR 0x0
+#define BUFWRERR 0x20 /* Buffer Write Error */
+#define nBUFWRERR 0x0
+#define SDASEN 0x40 /* Serial Data Sense */
+#define nSDASEN 0x0
+#define SCLSEN 0x80 /* Serial Clock Sense */
+#define nSCLSEN 0x0
+#define BUSBUSY 0x100 /* Bus Busy */
+#define nBUSBUSY 0x0
+
+/* Bit maskes for TWIx_FIFO_CTL */
+
+#define XMTFLUSH 0x1 /* Transmit Buffer Flush */
+#define nXMTFLUSH 0x0
+#define RCVFLUSH 0x2 /* Receive Buffer Flush */
+#define nRCVFLUSH 0x0
+#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
+#define nXMTINTLEN 0x0
+#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
+#define nRCVINTLEN 0x0
+
+/* Bit maskes for TWIx_FIFO_STAT */
+
+#define XMTSTAT 0x3 /* Transmit FIFO Status */
+#define RCVSTAT 0xc /* Receive FIFO Status */
+
+/* Bit maskes for TWIx_INT_MASK */
+
+#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
+#define nSINITM 0x0
+#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
+#define nSCOMPM 0x0
+#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
+#define nSERRM 0x0
+#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
+#define nSOVFM 0x0
+#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
+#define nMCOMPM 0x0
+#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
+#define nMERRM 0x0
+#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
+#define nXMTSERVM 0x0
+#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
+#define nRCVSERVM 0x0
+
+/* Bit maskes for TWIx_INT_STAT */
+
+#define SINIT 0x1 /* Slave Transfer Initiated */
+#define nSINIT 0x0
+#define SCOMP 0x2 /* Slave Transfer Complete */
+#define nSCOMP 0x0
+#define SERR 0x4 /* Slave Transfer Error */
+#define nSERR 0x0
+#define SOVF 0x8 /* Slave Overflow */
+#define nSOVF 0x0
+#define MCOMP 0x10 /* Master Transfer Complete */
+#define nMCOMP 0x0
+#define MERR 0x20 /* Master Transfer Error */
+#define nMERR 0x0
+#define XMTSERV 0x40 /* Transmit FIFO Service */
+#define nXMTSERV 0x0
+#define RCVSERV 0x80 /* Receive FIFO Service */
+#define nRCVSERV 0x0
+
+/* Bit maskes for TWIx_XMT_DATA8 */
+
+#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
+
+/* Bit maskes for TWIx_XMT_DATA16 */
+
+#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
+
+/* Bit maskes for TWIx_RCV_DATA8 */
+
+#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
+
+/* Bit maskes for TWIx_RCV_DATA16 */
+
+#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
+
+/* Bit masks for SPORTx_TCR1 */
+
+#define TCKFE 0x4000 /* Clock Falling Edge Select */
+#define nTCKFE 0x0
+#define LATFS 0x2000 /* Late Transmit Frame Sync */
+#define nLATFS 0x0
+#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
+#define nLTFS 0x0
+#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
+#define nDITFS 0x0
+#define TFSR 0x400 /* Transmit Frame Sync Required Select */
+#define nTFSR 0x0
+#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
+#define nITFS 0x0
+#define TLSBIT 0x10 /* Transmit Bit Order */
+#define nTLSBIT 0x0
+#define TDTYPE 0xc /* Data Formatting Type Select */
+#define ITCLK 0x2 /* Internal Transmit Clock Select */
+#define nITCLK 0x0
+#define TSPEN 0x1 /* Transmit Enable */
+#define nTSPEN 0x0
+
+/* Bit masks for SPORTx_TCR2 */
+
+#define TRFST 0x400 /* Left/Right Order */
+#define nTRFST 0x0
+#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
+#define nTSFSE 0x0
+#define TXSE 0x100 /* TxSEC Enable */
+#define nTXSE 0x0
+#define SLEN_T 0x1f /* SPORT Word Length */
+
+/* Bit masks for SPORTx_RCR1 */
+
+#define RCKFE 0x4000 /* Clock Falling Edge Select */
+#define nRCKFE 0x0
+#define LARFS 0x2000 /* Late Receive Frame Sync */
+#define nLARFS 0x0
+#define LRFS 0x1000 /* Low Receive Frame Sync Select */
+#define nLRFS 0x0
+#define RFSR 0x400 /* Receive Frame Sync Required Select */
+#define nRFSR 0x0
+#define IRFS 0x200 /* Internal Receive Frame Sync Select */
+#define nIRFS 0x0
+#define RLSBIT 0x10 /* Receive Bit Order */
+#define nRLSBIT 0x0
+#define RDTYPE 0xc /* Data Formatting Type Select */
+#define IRCLK 0x2 /* Internal Receive Clock Select */
+#define nIRCLK 0x0
+#define RSPEN 0x1 /* Receive Enable */
+#define nRSPEN 0x0
+
+/* Bit masks for SPORTx_RCR2 */
+
+#define RRFST 0x400 /* Left/Right Order */
+#define nRRFST 0x0
+#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
+#define nRSFSE 0x0
+#define RXSE 0x100 /* RxSEC Enable */
+#define nRXSE 0x0
+#define SLEN_R 0x1f /* SPORT Word Length */
+
+/* Bit masks for SPORTx_STAT */
+
+#define TXHRE 0x40 /* Transmit Hold Register Empty */
+#define nTXHRE 0x0
+#define TOVF 0x20 /* Sticky Transmit Overflow Status */
+#define nTOVF 0x0
+#define TUVF 0x10 /* Sticky Transmit Underflow Status */
+#define nTUVF 0x0
+#define TXF 0x8 /* Transmit FIFO Full Status */
+#define nTXF 0x0
+#define ROVF 0x4 /* Sticky Receive Overflow Status */
+#define nROVF 0x0
+#define RUVF 0x2 /* Sticky Receive Underflow Status */
+#define nRUVF 0x0
+#define RXNE 0x1 /* Receive FIFO Not Empty Status */
+#define nRXNE 0x0
+
+/* Bit masks for SPORTx_MCMC1 */
+
+#define WSIZE 0xf000 /* Window Size */
+#define WOFF 0x3ff /* Windows Offset */
+
+/* Bit masks for SPORTx_MCMC2 */
+
+#define MFD 0xf000 /* Multi channel Frame Delay */
+#define FSDR 0x80 /* Frame Sync to Data Relationship */
+#define nFSDR 0x0
+#define MCMEM 0x10 /* Multi channel Frame Mode Enable */
+#define nMCMEM 0x0
+#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
+#define nMCDRXPE 0x0
+#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
+#define nMCDTXPE 0x0
+#define MCCRM 0x3 /* 2X Clock Recovery Mode */
+
+/* Bit masks for SPORTx_CHNL */
+
+#define CUR_CHNL 0x3ff /* Current Channel Indicator */
+
+/* Bit masks for UARTx_LCR */
+
+#if 0
+/* conflicts with legacy one in last section */
+#define WLS 0x3 /* Word Length Select */
+#endif
+#define STB 0x4 /* Stop Bits */
+#define nSTB 0x0
+#define PEN 0x8 /* Parity Enable */
+#define nPEN 0x0
+#define EPS 0x10 /* Even Parity Select */
+#define nEPS 0x0
+#define STP 0x20 /* Sticky Parity */
+#define nSTP 0x0
+#define SB 0x40 /* Set Break */
+#define nSB 0x0
+
+/* Bit masks for UARTx_MCR */
+
+#define XOFF 0x1 /* Transmitter Off */
+#define nXOFF 0x0
+#define MRTS 0x2 /* Manual Request To Send */
+#define nMRTS 0x0
+#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
+#define nRFIT 0x0
+#define RFRT 0x8 /* Receive FIFO RTS Threshold */
+#define nRFRT 0x0
+#define LOOP_ENA 0x10 /* Loopback Mode Enable */
+#define nLOOP_ENA 0x0
+#define FCPOL 0x20 /* Flow Control Pin Polarity */
+#define nFCPOL 0x0
+#define ARTS 0x40 /* Automatic Request To Send */
+#define nARTS 0x0
+#define ACTS 0x80 /* Automatic Clear To Send */
+#define nACTS 0x0
+
+/* Bit masks for UARTx_LSR */
+
+#define DR 0x1 /* Data Ready */
+#define nDR 0x0
+#define OE 0x2 /* Overrun Error */
+#define nOE 0x0
+#define PE 0x4 /* Parity Error */
+#define nPE 0x0
+#define FE 0x8 /* Framing Error */
+#define nFE 0x0
+#define BI 0x10 /* Break Interrupt */
+#define nBI 0x0
+#define THRE 0x20 /* THR Empty */
+#define nTHRE 0x0
+#define TEMT 0x40 /* Transmitter Empty */
+#define nTEMT 0x0
+#define TFI 0x80 /* Transmission Finished Indicator */
+#define nTFI 0x0
+
+/* Bit masks for UARTx_MSR */
+
+#define SCTS 0x1 /* Sticky CTS */
+#define nSCTS 0x0
+#define CTS 0x10 /* Clear To Send */
+#define nCTS 0x0
+#define RFCS 0x20 /* Receive FIFO Count Status */
+#define nRFCS 0x0
+
+/* Bit masks for UARTx_IER_SET and UARTx_IER_CLEAR */
+
+#define ERBFI 0x1 /* Enable Receive Buffer Full Interrupt */
+#define nERBFI 0x0
+#define ETBEI 0x2 /* Enable Transmit Buffer Empty Interrupt */
+#define nETBEI 0x0
+#define ELSI 0x4 /* Enable Receive Status Interrupt */
+#define nELSI 0x0
+#define EDSSI 0x8 /* Enable Modem Status Interrupt */
+#define nEDSSI 0x0
+#define EDTPTI 0x10 /* Enable DMA Transmit PIRQ Interrupt */
+#define nEDTPTI 0x0
+#define ETFI 0x20 /* Enable Transmission Finished Interrupt */
+#define nETFI 0x0
+#define ERFCI 0x40 /* Enable Receive FIFO Count Interrupt */
+#define nERFCI 0x0
+
+
+/* Bit masks for UARTx_GCTL */
+
+#define UCEN 0x1 /* UART Enable */
+#define nUCEN 0x0
+#define IREN 0x2 /* IrDA Mode Enable */
+#define nIREN 0x0
+#define TPOLC 0x4 /* IrDA TX Polarity Change */
+#define nTPOLC 0x0
+#define RPOLC 0x8 /* IrDA RX Polarity Change */
+#define nRPOLC 0x0
+#define FPE 0x10 /* Force Parity Error */
+#define nFPE 0x0
+#define FFE 0x20 /* Force Framing Error */
+#define nFFE 0x0
+#define EDBO 0x40 /* Enable Divide-by-One */
+#define nEDBO 0x0
+#define EGLSI 0x80 /* Enable Global LS Interrupt */
+#define nEGLSI 0x0
+
+/* Bit masks for HMDMAx_CONTROL */
+
+#define HMDMAEN 0x1 /* Handshake MDMA Enable */
+#define nHMDMAEN 0x0
+#define REP 0x2 /* Handshake MDMA Request Polarity */
+#define nREP 0x0
+#define UTE 0x8 /* Urgency Threshold Enable */
+#define nUTE 0x0
+#define OIE 0x10 /* Overflow Interrupt Enable */
+#define nOIE 0x0
+#define BDIE 0x20 /* Block Done Interrupt Enable */
+#define nBDIE 0x0
+#define MBDI 0x40 /* Mask Block Done Interrupt */
+#define nMBDI 0x0
+#define DRQ 0x300 /* Handshake MDMA Request Type */
+#define RBC 0x1000 /* Force Reload of BCOUNT */
+#define nRBC 0x0
+#define PS 0x2000 /* Pin Status */
+#define nPS 0x0
+#define OI 0x4000 /* Overflow Interrupt Generated */
+#define nOI 0x0
+#define BDI 0x8000 /* Block Done Interrupt Generated */
+#define nBDI 0x0
+
+/* ******************************************* */
+/* MULTI BIT MACRO ENUMERATIONS */
+/* ******************************************* */
+
+/* BCODE bit field options (SYSCFG register) */
+
+#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
+#define BCODE_FULLBOOT 0x0010 /* always perform full boot */
+#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
+#define BCODE_NOBOOT 0x0030 /* always perform full boot */
+
+/* CNT_COMMAND bit field options */
+
+#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
+#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
+#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
+
+#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
+#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
+#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
+
+#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
+#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
+#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
+
+/* CNT_CONFIG bit field options */
+
+#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
+#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
+#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
+#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
+#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
+
+#define BNDMODE_COMP 0x0000 /* boundary compare mode */
+#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
+#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
+#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
+
+/* TMODE in TIMERx_CONFIG bit field options */
+
+#define PWM_OUT 0x0001
+#define WDTH_CAP 0x0002
+#define EXT_CLK 0x0003
+
+/* UARTx_LCR bit field options */
+
+#define WLS_5 0x0000 /* 5 data bits */
+#define WLS_6 0x0001 /* 6 data bits */
+#define WLS_7 0x0002 /* 7 data bits */
+#define WLS_8 0x0003 /* 8 data bits */
+
+/* PINTx Register Bit Definitions */
+
+#define PIQ0 0x00000001
+#define PIQ1 0x00000002
+#define PIQ2 0x00000004
+#define PIQ3 0x00000008
+
+#define PIQ4 0x00000010
+#define PIQ5 0x00000020
+#define PIQ6 0x00000040
+#define PIQ7 0x00000080
+
+#define PIQ8 0x00000100
+#define PIQ9 0x00000200
+#define PIQ10 0x00000400
+#define PIQ11 0x00000800
+
+#define PIQ12 0x00001000
+#define PIQ13 0x00002000
+#define PIQ14 0x00004000
+#define PIQ15 0x00008000
+
+#define PIQ16 0x00010000
+#define PIQ17 0x00020000
+#define PIQ18 0x00040000
+#define PIQ19 0x00080000
+
+#define PIQ20 0x00100000
+#define PIQ21 0x00200000
+#define PIQ22 0x00400000
+#define PIQ23 0x00800000
+
+#define PIQ24 0x01000000
+#define PIQ25 0x02000000
+#define PIQ26 0x04000000
+#define PIQ27 0x08000000
+
+#define PIQ28 0x10000000
+#define PIQ29 0x20000000
+#define PIQ30 0x40000000
+#define PIQ31 0x80000000
+
+/* PORT A Bit Definitions for the registers
+PORTA, PORTA_SET, PORTA_CLEAR,
+PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
+PORTA_FER registers
+*/
+
+#define PA0 0x0001
+#define PA1 0x0002
+#define PA2 0x0004
+#define PA3 0x0008
+#define PA4 0x0010
+#define PA5 0x0020
+#define PA6 0x0040
+#define PA7 0x0080
+#define PA8 0x0100
+#define PA9 0x0200
+#define PA10 0x0400
+#define PA11 0x0800
+#define PA12 0x1000
+#define PA13 0x2000
+#define PA14 0x4000
+#define PA15 0x8000
+
+/* PORT B Bit Definitions for the registers
+PORTB, PORTB_SET, PORTB_CLEAR,
+PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
+PORTB_FER registers
+*/
+
+#define PB0 0x0001
+#define PB1 0x0002
+#define PB2 0x0004
+#define PB3 0x0008
+#define PB4 0x0010
+#define PB5 0x0020
+#define PB6 0x0040
+#define PB7 0x0080
+#define PB8 0x0100
+#define PB9 0x0200
+#define PB10 0x0400
+#define PB11 0x0800
+#define PB12 0x1000
+#define PB13 0x2000
+#define PB14 0x4000
+
+
+/* PORT C Bit Definitions for the registers
+PORTC, PORTC_SET, PORTC_CLEAR,
+PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
+PORTC_FER registers
+*/
+
+
+#define PC0 0x0001
+#define PC1 0x0002
+#define PC2 0x0004
+#define PC3 0x0008
+#define PC4 0x0010
+#define PC5 0x0020
+#define PC6 0x0040
+#define PC7 0x0080
+#define PC8 0x0100
+#define PC9 0x0200
+#define PC10 0x0400
+#define PC11 0x0800
+#define PC12 0x1000
+#define PC13 0x2000
+
+
+/* PORT D Bit Definitions for the registers
+PORTD, PORTD_SET, PORTD_CLEAR,
+PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
+PORTD_FER registers
+*/
+
+#define PD0 0x0001
+#define PD1 0x0002
+#define PD2 0x0004
+#define PD3 0x0008
+#define PD4 0x0010
+#define PD5 0x0020
+#define PD6 0x0040
+#define PD7 0x0080
+#define PD8 0x0100
+#define PD9 0x0200
+#define PD10 0x0400
+#define PD11 0x0800
+#define PD12 0x1000
+#define PD13 0x2000
+#define PD14 0x4000
+#define PD15 0x8000
+
+/* PORT E Bit Definitions for the registers
+PORTE, PORTE_SET, PORTE_CLEAR,
+PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
+PORTE_FER registers
+*/
+
+
+#define PE0 0x0001
+#define PE1 0x0002
+#define PE2 0x0004
+#define PE3 0x0008
+#define PE4 0x0010
+#define PE5 0x0020
+#define PE6 0x0040
+#define PE7 0x0080
+#define PE8 0x0100
+#define PE9 0x0200
+#define PE10 0x0400
+#define PE11 0x0800
+#define PE12 0x1000
+#define PE13 0x2000
+#define PE14 0x4000
+#define PE15 0x8000
+
+/* PORT F Bit Definitions for the registers
+PORTF, PORTF_SET, PORTF_CLEAR,
+PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
+PORTF_FER registers
+*/
+
+
+#define PF0 0x0001
+#define PF1 0x0002
+#define PF2 0x0004
+#define PF3 0x0008
+#define PF4 0x0010
+#define PF5 0x0020
+#define PF6 0x0040
+#define PF7 0x0080
+#define PF8 0x0100
+#define PF9 0x0200
+#define PF10 0x0400
+#define PF11 0x0800
+#define PF12 0x1000
+#define PF13 0x2000
+#define PF14 0x4000
+#define PF15 0x8000
+
+/* PORT G Bit Definitions for the registers
+PORTG, PORTG_SET, PORTG_CLEAR,
+PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
+PORTG_FER registers
+*/
+
+
+#define PG0 0x0001
+#define PG1 0x0002
+#define PG2 0x0004
+#define PG3 0x0008
+#define PG4 0x0010
+#define PG5 0x0020
+#define PG6 0x0040
+#define PG7 0x0080
+#define PG8 0x0100
+#define PG9 0x0200
+#define PG10 0x0400
+#define PG11 0x0800
+#define PG12 0x1000
+#define PG13 0x2000
+#define PG14 0x4000
+#define PG15 0x8000
+
+/* PORT H Bit Definitions for the registers
+PORTH, PORTH_SET, PORTH_CLEAR,
+PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
+PORTH_FER registers
+*/
+
+
+#define PH0 0x0001
+#define PH1 0x0002
+#define PH2 0x0004
+#define PH3 0x0008
+#define PH4 0x0010
+#define PH5 0x0020
+#define PH6 0x0040
+#define PH7 0x0080
+#define PH8 0x0100
+#define PH9 0x0200
+#define PH10 0x0400
+#define PH11 0x0800
+#define PH12 0x1000
+#define PH13 0x2000
+
+
+/* PORT I Bit Definitions for the registers
+PORTI, PORTI_SET, PORTI_CLEAR,
+PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
+PORTI_FER registers
+*/
+
+
+#define PI0 0x0001
+#define PI1 0x0002
+#define PI2 0x0004
+#define PI3 0x0008
+#define PI4 0x0010
+#define PI5 0x0020
+#define PI6 0x0040
+#define PI7 0x0080
+#define PI8 0x0100
+#define PI9 0x0200
+#define PI10 0x0400
+#define PI11 0x0800
+#define PI12 0x1000
+#define PI13 0x2000
+#define PI14 0x4000
+#define PI15 0x8000
+
+/* PORT J Bit Definitions for the registers
+PORTJ, PORTJ_SET, PORTJ_CLEAR,
+PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
+PORTJ_FER registers
+*/
+
+
+#define PJ0 0x0001
+#define PJ1 0x0002
+#define PJ2 0x0004
+#define PJ3 0x0008
+#define PJ4 0x0010
+#define PJ5 0x0020
+#define PJ6 0x0040
+#define PJ7 0x0080
+#define PJ8 0x0100
+#define PJ9 0x0200
+#define PJ10 0x0400
+#define PJ11 0x0800
+#define PJ12 0x1000
+#define PJ13 0x2000
+
+
+/* Port Muxing Bit Fields for PORTx_MUX Registers */
+
+#define MUX0 0x00000003
+#define MUX0_0 0x00000000
+#define MUX0_1 0x00000001
+#define MUX0_2 0x00000002
+#define MUX0_3 0x00000003
+
+#define MUX1 0x0000000C
+#define MUX1_0 0x00000000
+#define MUX1_1 0x00000004
+#define MUX1_2 0x00000008
+#define MUX1_3 0x0000000C
+
+#define MUX2 0x00000030
+#define MUX2_0 0x00000000
+#define MUX2_1 0x00000010
+#define MUX2_2 0x00000020
+#define MUX2_3 0x00000030
+
+#define MUX3 0x000000C0
+#define MUX3_0 0x00000000
+#define MUX3_1 0x00000040
+#define MUX3_2 0x00000080
+#define MUX3_3 0x000000C0
+
+#define MUX4 0x00000300
+#define MUX4_0 0x00000000
+#define MUX4_1 0x00000100
+#define MUX4_2 0x00000200
+#define MUX4_3 0x00000300
+
+#define MUX5 0x00000C00
+#define MUX5_0 0x00000000
+#define MUX5_1 0x00000400
+#define MUX5_2 0x00000800
+#define MUX5_3 0x00000C00
+
+#define MUX6 0x00003000
+#define MUX6_0 0x00000000
+#define MUX6_1 0x00001000
+#define MUX6_2 0x00002000
+#define MUX6_3 0x00003000
+
+#define MUX7 0x0000C000
+#define MUX7_0 0x00000000
+#define MUX7_1 0x00004000
+#define MUX7_2 0x00008000
+#define MUX7_3 0x0000C000
+
+#define MUX8 0x00030000
+#define MUX8_0 0x00000000
+#define MUX8_1 0x00010000
+#define MUX8_2 0x00020000
+#define MUX8_3 0x00030000
+
+#define MUX9 0x000C0000
+#define MUX9_0 0x00000000
+#define MUX9_1 0x00040000
+#define MUX9_2 0x00080000
+#define MUX9_3 0x000C0000
+
+#define MUX10 0x00300000
+#define MUX10_0 0x00000000
+#define MUX10_1 0x00100000
+#define MUX10_2 0x00200000
+#define MUX10_3 0x00300000
+
+#define MUX11 0x00C00000
+#define MUX11_0 0x00000000
+#define MUX11_1 0x00400000
+#define MUX11_2 0x00800000
+#define MUX11_3 0x00C00000
+
+#define MUX12 0x03000000
+#define MUX12_0 0x00000000
+#define MUX12_1 0x01000000
+#define MUX12_2 0x02000000
+#define MUX12_3 0x03000000
+
+#define MUX13 0x0C000000
+#define MUX13_0 0x00000000
+#define MUX13_1 0x04000000
+#define MUX13_2 0x08000000
+#define MUX13_3 0x0C000000
+
+#define MUX14 0x30000000
+#define MUX14_0 0x00000000
+#define MUX14_1 0x10000000
+#define MUX14_2 0x20000000
+#define MUX14_3 0x30000000
+
+#define MUX15 0xC0000000
+#define MUX15_0 0x00000000
+#define MUX15_1 0x40000000
+#define MUX15_2 0x80000000
+#define MUX15_3 0xC0000000
+
+#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
+ ((((b15)&3) << 30) | \
+ (((b14)&3) << 28) | \
+ (((b13)&3) << 26) | \
+ (((b12)&3) << 24) | \
+ (((b11)&3) << 22) | \
+ (((b10)&3) << 20) | \
+ (((b9) &3) << 18) | \
+ (((b8) &3) << 16) | \
+ (((b7) &3) << 14) | \
+ (((b6) &3) << 12) | \
+ (((b5) &3) << 10) | \
+ (((b4) &3) << 8) | \
+ (((b3) &3) << 6) | \
+ (((b2) &3) << 4) | \
+ (((b1) &3) << 2) | \
+ (((b0) &3)))
+
+/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
+
+#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */
+#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
+#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
+#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */
+#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
+#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
+#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */
+#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
+#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
+#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */
+#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
+#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
+
+/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
+
+#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
+#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
+#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
+#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
+#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
+#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
+#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
+#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
+
+#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
+#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
+#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
+#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
+#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
+#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
+#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
+#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
+
+#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
+#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
+#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
+#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
+#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
+#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
+#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
+#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
+
+#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
+#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
+#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
+#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
+#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
+#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
+#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
+#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
+
+
+/* for legacy compatibility */
+
+#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+#define W1LMAX_MAX W1LMAX_MIN
+#define EBIU_AMCBCTL0 EBIU_AMBCTL0
+#define EBIU_AMCBCTL1 EBIU_AMBCTL1
+#define PINT0_IRQ PINT0_REQUEST
+#define PINT1_IRQ PINT1_REQUEST
+#define PINT2_IRQ PINT2_REQUEST
+#define PINT3_IRQ PINT3_REQUEST
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF54X_H */
+
+
+/*********************************************************************************** */
+/* System MMR Register Bits */
+/******************************************************************************* */
+
+/* ************************** DMA CONTROLLER MASKS ********************************/
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
+#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
+#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
+#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
+#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
+#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
+#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
+#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
+#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
+#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
+#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
+#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
+#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
+#define SET_NDSIZE(x) (((x)&0xF)<<8) /* NDSIZE[3:0] (Flex Descriptor Size)
+ Size of next descriptor
+ 0000 - Required if in Stop or Autobuffer mode
+ 0001 - 1001 - Descriptor size
+ 1010 - 1111 - Reserved */
+#define FLOW_STOP 0x0000 /* Stop Mode */
+#define FLOW_AUTO 0x1000 /* Autobuffer Mode */
+#define FLOW_ARRAY 0x4000 /* Descriptor Array Mode */
+#define FLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
+#define FLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
+
+
+/* ********************* PLL AND RESET MASKS ************************ */
+/* SWRST Mask */
+#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
+#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
+#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
+#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
+#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
+
+/* SYSCR Masks */
+#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
+#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
+
+
+/* ******************************************* */
+/* MULTI BIT MACRO ENUMERATIONS */
+/* ******************************************* */
+
+/* PORT A Bit Definitions for the registers
+PORTA, PORTA_SET, PORTA_CLEAR, PORTA_DIR_SET,
+PORTA_DIR_CLEAR, PORTA_INEN, PORTA_FER */
+
+#define nPA0 0x0
+#define nPA1 0x0
+#define nPA2 0x0
+#define nPA3 0x0
+#define nPA4 0x0
+#define nPA5 0x0
+#define nPA6 0x0
+#define nPA7 0x0
+#define nPA8 0x0
+#define nPA9 0x0
+#define nPA10 0x0
+#define nPA11 0x0
+#define nPA12 0x0
+#define nPA13 0x0
+#define nPA14 0x0
+#define nPA15 0x0
+
+/* PORT B Bit Definitions for the registers
+PORTB, PORTB_SET, PORTB_CLEAR, PORTB_DIR_SET,
+PORTB_DIR_CLEAR, PORTB_INEN, PORTB_FER */
+
+#define nPB0 0x0
+#define nPB1 0x0
+#define nPB2 0x0
+#define nPB3 0x0
+#define nPB4 0x0
+#define nPB5 0x0
+#define nPB6 0x0
+#define nPB7 0x0
+#define nPB8 0x0
+#define nPB9 0x0
+#define nPB10 0x0
+#define nPB11 0x0
+#define nPB12 0x0
+#define nPB13 0x0
+#define nPB14 0x0
+#define nPB15 0x0
+
+/* PORT D Bit Definitions for the registers
+PORTD, PORTD_SET, PORTD_CLEAR, PORTD_DIR_SET,
+PORTD_DIR_CLEAR, PORTD_INEN, PORTD_FER */
+
+#define nPD0 0x0
+#define nPD1 0x0
+#define nPD2 0x0
+#define nPD3 0x0
+#define nPD4 0x0
+#define nPD5 0x0
+#define nPD6 0x0
+#define nPD7 0x0
+#define nPD8 0x0
+#define nPD9 0x0
+#define nPD10 0x0
+#define nPD11 0x0
+#define nPD12 0x0
+#define nPD13 0x0
+#define nPD14 0x0
+#define nPD15 0x0
+
+/* PORT E Bit Definitions for the registers
+PORTE, PORTE_SET, PORTE_CLEAR, PORTE_DIR_SET,
+PORTE_DIR_CLEAR, PORTE_INEN, PORTE_FER */
+
+#define nPE0 0x0
+#define nPE1 0x0
+#define nPE2 0x0
+#define nPE3 0x0
+#define nPE4 0x0
+#define nPE5 0x0
+#define nPE6 0x0
+#define nPE7 0x0
+#define nPE8 0x0
+#define nPE9 0x0
+#define nPE10 0x0
+#define nPE11 0x0
+#define nPE12 0x0
+#define nPE13 0x0
+#define nPE14 0x0
+#define nPE15 0x0
+
+/* PORT F Bit Definitions for the registers
+PORTF, PORTF_SET, PORTF_CLEAR, PORTF_DIR_SET,
+PORTF_DIR_CLEAR, PORTF_INEN, PORTF_FER */
+
+#define nPF0 0x0
+#define nPF1 0x0
+#define nPF2 0x0
+#define nPF3 0x0
+#define nPF4 0x0
+#define nPF5 0x0
+#define nPF6 0x0
+#define nPF7 0x0
+#define nPF8 0x0
+#define nPF9 0x0
+#define nPF10 0x0
+#define nPF11 0x0
+#define nPF12 0x0
+#define nPF13 0x0
+#define nPF14 0x0
+#define nPF15 0x0
+
+/* PORT G Bit Definitions for the registers
+PORTG, PORTG_SET, PORTG_CLEAR, PORTG_DIR_SET,
+PORTG_DIR_CLEAR, PORTG_INEN, PORTG_FER */
+#define nPG0 0x0
+#define nPG1 0x0
+#define nPG2 0x0
+#define nPG3 0x0
+#define nPG4 0x0
+#define nPG5 0x0
+#define nPG6 0x0
+#define nPG7 0x0
+#define nPG8 0x0
+#define nPG9 0x0
+#define nPG10 0x0
+#define nPG11 0x0
+#define nPG12 0x0
+#define nPG13 0x0
+#define nPG14 0x0
+#define nPG15 0x0
+
+/* PORT H Bit Definitions for the registers
+PORTH, PORTH_SET, PORTH_CLEAR, PORTH_DIR_SET,
+PORTH_DIR_CLEAR, PORTH_INEN, PORTH_FER */
+#define nPH0 0x0
+#define nPH1 0x0
+#define nPH2 0x0
+#define nPH3 0x0
+#define nPH4 0x0
+#define nPH5 0x0
+#define nPH6 0x0
+#define nPH7 0x0
+#define nPH8 0x0
+#define nPH9 0x0
+#define nPH10 0x0
+#define nPH11 0x0
+#define nPH12 0x0
+#define nPH13 0x0
+#define nPH14 0x0
+#define nPH15 0x0
+
+/* PORT I Bit Definitions for the registers
+PORTI, PORTI_SET, PORTI_CLEAR, PORTI_DIR_SET,
+PORTI_DIR_CLEAR, PORTI_INEN, PORTI_FER */
+#define nPI0 0x0
+#define nPI1 0x0
+#define nPI2 0x0
+#define nPI3 0x0
+#define nPI4 0x0
+#define nPI5 0x0
+#define nPI6 0x0
+#define nPI7 0x0
+#define nPI8 0x0
+#define nPI9 0x0
+#define nPI10 0x0
+#define nPI11 0x0
+#define nPI12 0x0
+#define nPI13 0x0
+#define nPI14 0x0
+#define nPI15 0x0
+
+/* PORT J Bit Definitions for the registers
+PORTJ, PORTJ_SET, PORTJ_CLEAR, PORTJ_DIR_SET,
+PORTJ_DIR_CLEAR, PORTJ_INEN, PORTJ_FER */
+#define nPJ0 0x0
+#define nPJ1 0x0
+#define nPJ2 0x0
+#define nPJ3 0x0
+#define nPJ4 0x0
+#define nPJ5 0x0
+#define nPJ6 0x0
+#define nPJ7 0x0
+#define nPJ8 0x0
+#define nPJ9 0x0
+#define nPJ10 0x0
+#define nPJ11 0x0
+#define nPJ12 0x0
+#define nPJ13 0x0
+#define nPJ14 0x0
+#define nPJ15 0x0
+
+
+/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
+
+/* SIC_IAR0 Macros */
+#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
+#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
+#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
+#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
+#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
+#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
+#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
+#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
+
+/* SIC_IAR1 Macros */
+#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
+#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
+#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
+#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
+#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
+#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
+#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
+#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
+
+/* SIC_IAR2 Macros */
+#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
+#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
+#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
+#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
+#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
+#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
+#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
+#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
+
+/* SIC_IAR3 Macros */
+#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
+#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
+#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
+#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
+#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
+#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
+#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
+#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
+
+/* SIC_IAR4 Macros */
+#define P32_IVG(x) (((x)&0xF)-7) /* Peripheral #32 assigned IVG #x */
+#define P33_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #33 assigned IVG #x */
+#define P34_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #34 assigned IVG #x */
+#define P35_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #35 assigned IVG #x */
+#define P36_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #36 assigned IVG #x */
+#define P37_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #37 assigned IVG #x */
+#define P38_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #38 assigned IVG #x */
+#define P39_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #39 assigned IVG #x */
+
+/* SIC_IAR4 Macros */
+#define P40_IVG(x) (((x)&0xF)-7) /* Peripheral #40 assigned IVG #x */
+#define P41_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #41 assigned IVG #x */
+#define P42_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #42 assigned IVG #x */
+#define P43_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #43 assigned IVG #x */
+#define P44_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #44 assigned IVG #x */
+#define P45_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #45 assigned IVG #x */
+#define P46_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #46 assigned IVG #x */
+#define P47_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #47 assigned IVG #x */
+
+/* SIC_IAR5 Macros */
+#define P48_IVG(x) (((x)&0xF)-7) /* Peripheral #48 assigned IVG #x */
+#define P49_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #49 assigned IVG #x */
+#define P50_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #50 assigned IVG #x */
+#define P51_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #51 assigned IVG #x */
+#define P52_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #52 assigned IVG #x */
+#define P53_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #53 assigned IVG #x */
+#define P54_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #54 assigned IVG #x */
+#define P55_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #55 assigned IVG #x */
+
+/* SIC_IAR5 Macros */
+#define P56_IVG(x) (((x)&0xF)-7) /* Peripheral #56 assigned IVG #x */
+#define P57_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #57 assigned IVG #x */
+#define P58_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #58 assigned IVG #x */
+#define P59_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #59 assigned IVG #x */
+#define P60_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #60 assigned IVG #x */
+#define P61_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #61 assigned IVG #x */
+#define P62_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #62 assigned IVG #x */
+#define P63_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #63 assigned IVG #x */
+
+/* SIC_IAR6 Macros */
+#define P64_IVG(x) (((x)&0xF)-7) /* Peripheral #64 assigned IVG #x */
+#define P65_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #65 assigned IVG #x */
+#define P66_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #66 assigned IVG #x */
+#define P67_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #67 assigned IVG #x */
+#define P68_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #68 assigned IVG #x */
+#define P69_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #69 assigned IVG #x */
+#define P70_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #70 assigned IVG #x */
+#define P71_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #71 assigned IVG #x */
+
+/* SIC_IAR7 Macros */
+#define P72_IVG(x) (((x)&0xF)-7) /* Peripheral #72 assigned IVG #x */
+#define P73_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #73 assigned IVG #x */
+#define P74_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #74 assigned IVG #x */
+#define P75_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #75 assigned IVG #x */
+#define P76_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #76 assigned IVG #x */
+#define P77_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #77 assigned IVG #x */
+#define P78_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #78 assigned IVG #x */
+#define P79_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #79 assigned IVG #x */
+
+/* SIC_IAR7 Macros */
+#define P72_IVG(x) (((x)&0xF)-7) /* Peripheral #72 assigned IVG #x */
+#define P73_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #73 assigned IVG #x */
+#define P74_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #74 assigned IVG #x */
+#define P75_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #75 assigned IVG #x */
+#define P76_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #76 assigned IVG #x */
+#define P77_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #77 assigned IVG #x */
+#define P78_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #78 assigned IVG #x */
+#define P79_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #79 assigned IVG #x */
+
+/* SIC_IAR8 Macros */
+#define P80_IVG(x) (((x)&0xF)-7) /* Peripheral #80 assigned IVG #x */
+#define P81_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #81 assigned IVG #x */
+#define P82_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #82 assigned IVG #x */
+#define P83_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #83 assigned IVG #x */
+#define P84_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #84 assigned IVG #x */
+#define P85_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #85 assigned IVG #x */
+#define P86_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #86 assigned IVG #x */
+#define P87_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #87 assigned IVG #x */
+
+/* SIC_IAR8 Macros */
+#define P88_IVG(x) (((x)&0xF)-7) /* Peripheral #88 assigned IVG #x */
+#define P89_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #89 assigned IVG #x */
+#define P90_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #90 assigned IVG #x */
+#define P91_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #91 assigned IVG #x */
+#define P92_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #92 assigned IVG #x */
+#define P93_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #93 assigned IVG #x */
+#define P94_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #94 assigned IVG #x */
+#define P95_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #95 assigned IVG #x */
+
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+#define SET_WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#define WDEV_RESET 0x0000 /* generate reset event on roll over */
+#define nWDEV_RESET 0x0
+#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
+#define nWDEV_NMI 0x0
+#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
+#define nWDEV_GPI 0x0
+#define WDEV_NONE 0x0006 /* no event on roll over */
+#define WDDIS 0x0AD0 /* disable watchdog */
+
+/* RTC_SWCNT (RTC stopwatch count) Macros */
+#define SET_SWCNT(x) (x)
+
+/* RTC_PREN Register Masks */
+#define ENABLE_PRESCALE PREN /* Enable prescaler so RTC runs at 1 Hz */
+
+/* RTC_ALARM Macro: z=day, y=hr, x=min, w=sec */
+#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
+
+
+/* ******************************************* */
+/* MULTI BIT MACRO ENUMERATIONS */
+/* ******************************************* */
+
+/* CNT_COMMAND bit field options */
+#define nW1LCNT_ZERO 0x0
+#define nW1LCNT_MIN 0x0
+#define nW1LCNT_MAX 0x0
+
+#define nW1LMIN_ZERO 0x0
+#define nW1LMIN_CNT 0x0
+#define nW1LMIN_MAX 0x0
+
+#define nW1LMAX_ZERO 0x0
+#define nW1LMAX_CNT 0x0
+#define nW1LMAX_MIN 0x0
+
+#define W1ZMONCE 0x1000 /* write on to enable single zero marker. clear CNT_COUNT action (W1A/R) */
+#define nW1ZMONCE 0x0
+
+/* Bit macros for CNT_DEBOUNCE */
+#define SET_DPRESCALE(x) ((x)&0x7) /* 0000: 1x -> 0111: 128x, 1xxx Reserved */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * defBF561.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/* SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */
+
+#ifndef _DEF_BF561_H
+#define _DEF_BF561_H
+
+#if !defined(__ADSPBF561__)
+#warning defBF561.h should only be included for BF561 chip.
+#endif
+/* include all Core registers and bit definitions */
+#include <def_LPBlackfin.h>
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+/*********************************************************************************** */
+/* System MMR Register Map */
+/*********************************************************************************** */
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+
+#define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
+#define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
+#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
+#define CHIPID 0xFFC00014 /* Device ID Register */
+
+/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
+#define SICA_SWRST 0xFFC00100 /* Software Reset register */
+#define SICA_SYSCR 0xFFC00104 /* System Reset Configuration register */
+#define SICA_RVECT 0xFFC00108 /* SIC Reset Vector Address Register */
+#define SICA_IMASK 0xFFC0010C /* SIC Interrupt Mask register 0 - hack to fix old tests */
+#define SICA_IMASK0 0xFFC0010C /* SIC Interrupt Mask register 0 */
+#define SICA_IMASK1 0xFFC00110 /* SIC Interrupt Mask register 1 */
+#define SICA_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */
+#define SICA_IAR1 0xFFC00128 /* SIC Interrupt Assignment Register 1 */
+#define SICA_IAR2 0xFFC0012C /* SIC Interrupt Assignment Register 2 */
+#define SICA_IAR3 0xFFC00130 /* SIC Interrupt Assignment Register 3 */
+#define SICA_IAR4 0xFFC00134 /* SIC Interrupt Assignment Register 4 */
+#define SICA_IAR5 0xFFC00138 /* SIC Interrupt Assignment Register 5 */
+#define SICA_IAR6 0xFFC0013C /* SIC Interrupt Assignment Register 6 */
+#define SICA_IAR7 0xFFC00140 /* SIC Interrupt Assignment Register 7 */
+#define SICA_ISR0 0xFFC00114 /* SIC Interrupt Status register 0 */
+#define SICA_ISR1 0xFFC00118 /* SIC Interrupt Status register 1 */
+#define SICA_IWR0 0xFFC0011C /* SIC Interrupt Wakeup-Enable register 0 */
+#define SICA_IWR1 0xFFC00120 /* SIC Interrupt Wakeup-Enable register 1 */
+
+
+/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
+#define SICB_SWRST 0xFFC01100 /* reserved */
+#define SICB_SYSCR 0xFFC01104 /* reserved */
+#define SICB_RVECT 0xFFC01108 /* SIC Reset Vector Address Register */
+#define SICB_IMASK0 0xFFC0110C /* SIC Interrupt Mask register 0 */
+#define SICB_IMASK1 0xFFC01110 /* SIC Interrupt Mask register 1 */
+#define SICB_IAR0 0xFFC01124 /* SIC Interrupt Assignment Register 0 */
+#define SICB_IAR1 0xFFC01128 /* SIC Interrupt Assignment Register 1 */
+#define SICB_IAR2 0xFFC0112C /* SIC Interrupt Assignment Register 2 */
+#define SICB_IAR3 0xFFC01130 /* SIC Interrupt Assignment Register 3 */
+#define SICB_IAR4 0xFFC01134 /* SIC Interrupt Assignment Register 4 */
+#define SICB_IAR5 0xFFC01138 /* SIC Interrupt Assignment Register 5 */
+#define SICB_IAR6 0xFFC0113C /* SIC Interrupt Assignment Register 6 */
+#define SICB_IAR7 0xFFC01140 /* SIC Interrupt Assignment Register 7 */
+#define SICB_ISR0 0xFFC01114 /* SIC Interrupt Status register 0 */
+#define SICB_ISR1 0xFFC01118 /* SIC Interrupt Status register 1 */
+#define SICB_IWR0 0xFFC0111C /* SIC Interrupt Wakeup-Enable register 0 */
+#define SICB_IWR1 0xFFC01120 /* SIC Interrupt Wakeup-Enable register 1 */
+
+
+/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
+#define WDOGA_CTL 0xFFC00200 /* Watchdog Control register */
+#define WDOGA_CNT 0xFFC00204 /* Watchdog Count register */
+#define WDOGA_STAT 0xFFC00208 /* Watchdog Status register */
+
+
+/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
+#define WDOGB_CTL 0xFFC01200 /* Watchdog Control register */
+#define WDOGB_CNT 0xFFC01204 /* Watchdog Count register */
+#define WDOGB_STAT 0xFFC01208 /* Watchdog Status register */
+
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART_THR 0xFFC00400 /* Transmit Holding register */
+#define UART_RBR 0xFFC00400 /* Receive Buffer register */
+#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
+#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define UART_LCR 0xFFC0040C /* Line Control Register */
+#define UART_MCR 0xFFC00410 /* Modem Control Register */
+#define UART_LSR 0xFFC00414 /* Line Status Register */
+#define UART_MSR 0xFFC00418 /* Modem Status Register */
+#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
+#define UART_GCTL 0xFFC00424 /* Global Control Register */
+
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL 0xFFC00500 /* SPI Control Register */
+#define SPI_FLG 0xFFC00504 /* SPI Flag register */
+#define SPI_STAT 0xFFC00508 /* SPI Status register */
+#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
+#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
+#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
+
+
+/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
+#define TIMER0_CONFIG 0xFFC00600 /* Timer0 Configuration register */
+#define TIMER0_COUNTER 0xFFC00604 /* Timer0 Counter register */
+#define TIMER0_PERIOD 0xFFC00608 /* Timer0 Period register */
+#define TIMER0_WIDTH 0xFFC0060C /* Timer0 Width register */
+
+#define TIMER1_CONFIG 0xFFC00610 /* Timer1 Configuration register */
+#define TIMER1_COUNTER 0xFFC00614 /* Timer1 Counter register */
+#define TIMER1_PERIOD 0xFFC00618 /* Timer1 Period register */
+#define TIMER1_WIDTH 0xFFC0061C /* Timer1 Width register */
+
+#define TIMER2_CONFIG 0xFFC00620 /* Timer2 Configuration register */
+#define TIMER2_COUNTER 0xFFC00624 /* Timer2 Counter register */
+#define TIMER2_PERIOD 0xFFC00628 /* Timer2 Period register */
+#define TIMER2_WIDTH 0xFFC0062C /* Timer2 Width register */
+
+#define TIMER3_CONFIG 0xFFC00630 /* Timer3 Configuration register */
+#define TIMER3_COUNTER 0xFFC00634 /* Timer3 Counter register */
+#define TIMER3_PERIOD 0xFFC00638 /* Timer3 Period register */
+#define TIMER3_WIDTH 0xFFC0063C /* Timer3 Width register */
+
+#define TIMER4_CONFIG 0xFFC00640 /* Timer4 Configuration register */
+#define TIMER4_COUNTER 0xFFC00644 /* Timer4 Counter register */
+#define TIMER4_PERIOD 0xFFC00648 /* Timer4 Period register */
+#define TIMER4_WIDTH 0xFFC0064C /* Timer4 Width register */
+
+#define TIMER5_CONFIG 0xFFC00650 /* Timer5 Configuration register */
+#define TIMER5_COUNTER 0xFFC00654 /* Timer5 Counter register */
+#define TIMER5_PERIOD 0xFFC00658 /* Timer5 Period register */
+#define TIMER5_WIDTH 0xFFC0065C /* Timer5 Width register */
+
+#define TIMER6_CONFIG 0xFFC00660 /* Timer6 Configuration register */
+#define TIMER6_COUNTER 0xFFC00664 /* Timer6 Counter register */
+#define TIMER6_PERIOD 0xFFC00668 /* Timer6 Period register */
+#define TIMER6_WIDTH 0xFFC0066C /* Timer6 Width register */
+
+#define TIMER7_CONFIG 0xFFC00670 /* Timer7 Configuration register */
+#define TIMER7_COUNTER 0xFFC00674 /* Timer7 Counter register */
+#define TIMER7_PERIOD 0xFFC00678 /* Timer7 Period register */
+#define TIMER7_WIDTH 0xFFC0067C /* Timer7 Width register */
+
+#define TMRS8_ENABLE 0xFFC00680 /* Timer Enable Register */
+#define TMRS8_DISABLE 0xFFC00684 /* Timer Disable register */
+#define TMRS8_STATUS 0xFFC00688 /* Timer Status register */
+
+
+/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
+#define TIMER8_CONFIG 0xFFC01600 /* Timer8 Configuration register */
+#define TIMER8_COUNTER 0xFFC01604 /* Timer8 Counter register */
+#define TIMER8_PERIOD 0xFFC01608 /* Timer8 Period register */
+#define TIMER8_WIDTH 0xFFC0160C /* Timer8 Width register */
+
+#define TIMER9_CONFIG 0xFFC01610 /* Timer9 Configuration register */
+#define TIMER9_COUNTER 0xFFC01614 /* Timer9 Counter register */
+#define TIMER9_PERIOD 0xFFC01618 /* Timer9 Period register */
+#define TIMER9_WIDTH 0xFFC0161C /* Timer9 Width register */
+
+#define TIMER10_CONFIG 0xFFC01620 /* Timer10 Configuration register */
+#define TIMER10_COUNTER 0xFFC01624 /* Timer10 Counter register */
+#define TIMER10_PERIOD 0xFFC01628 /* Timer10 Period register */
+#define TIMER10_WIDTH 0xFFC0162C /* Timer10 Width register */
+
+#define TIMER11_CONFIG 0xFFC01630 /* Timer11 Configuration register */
+#define TIMER11_COUNTER 0xFFC01634 /* Timer11 Counter register */
+#define TIMER11_PERIOD 0xFFC01638 /* Timer11 Period register */
+#define TIMER11_WIDTH 0xFFC0163C /* Timer11 Width register */
+
+#define TMRS4_ENABLE 0xFFC01640 /* Timer Enable Register */
+#define TMRS4_DISABLE 0xFFC01644 /* Timer Disable register */
+#define TMRS4_STATUS 0xFFC01648 /* Timer Status register */
+
+
+/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
+#define FIO0_FLAG_D 0xFFC00700 /* Flag Data register */
+#define FIO0_FLAG_C 0xFFC00704 /* Flag Clear register */
+#define FIO0_FLAG_S 0xFFC00708 /* Flag Set register */
+#define FIO0_FLAG_T 0xFFC0070C /* Flag Toggle register */
+#define FIO0_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Data register */
+#define FIO0_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Clear register */
+#define FIO0_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Set register */
+#define FIO0_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Toggle register */
+#define FIO0_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Data register */
+#define FIO0_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Clear register */
+#define FIO0_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Set register */
+#define FIO0_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Toggle register */
+#define FIO0_DIR 0xFFC00730 /* Flag Direction register */
+#define FIO0_POLAR 0xFFC00734 /* Flag Polarity register */
+#define FIO0_EDGE 0xFFC00738 /* Flag Interrupt Sensitivity register */
+#define FIO0_BOTH 0xFFC0073C /* Flag Set on Both Edges register */
+#define FIO0_INEN 0xFFC00740 /* Flag Input Enable register */
+
+
+/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
+#define FIO1_FLAG_D 0xFFC01500 /* Flag Data register (mask used to directly */
+#define FIO1_FLAG_C 0xFFC01504 /* Flag Clear register */
+#define FIO1_FLAG_S 0xFFC01508 /* Flag Set register */
+#define FIO1_FLAG_T 0xFFC0150C /* Flag Toggle register (mask used to */
+#define FIO1_MASKA_D 0xFFC01510 /* Flag Mask Interrupt A Data register */
+#define FIO1_MASKA_C 0xFFC01514 /* Flag Mask Interrupt A Clear register */
+#define FIO1_MASKA_S 0xFFC01518 /* Flag Mask Interrupt A Set register */
+#define FIO1_MASKA_T 0xFFC0151C /* Flag Mask Interrupt A Toggle register */
+#define FIO1_MASKB_D 0xFFC01520 /* Flag Mask Interrupt B Data register */
+#define FIO1_MASKB_C 0xFFC01524 /* Flag Mask Interrupt B Clear register */
+#define FIO1_MASKB_S 0xFFC01528 /* Flag Mask Interrupt B Set register */
+#define FIO1_MASKB_T 0xFFC0152C /* Flag Mask Interrupt B Toggle register */
+#define FIO1_DIR 0xFFC01530 /* Flag Direction register */
+#define FIO1_POLAR 0xFFC01534 /* Flag Polarity register */
+#define FIO1_EDGE 0xFFC01538 /* Flag Interrupt Sensitivity register */
+#define FIO1_BOTH 0xFFC0153C /* Flag Set on Both Edges register */
+#define FIO1_INEN 0xFFC01540 /* Flag Input Enable register */
+
+
+/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
+#define FIO2_FLAG_D 0xFFC01700 /* Flag Data register (mask used to directly */
+#define FIO2_FLAG_C 0xFFC01704 /* Flag Clear register */
+#define FIO2_FLAG_S 0xFFC01708 /* Flag Set register */
+#define FIO2_FLAG_T 0xFFC0170C /* Flag Toggle register (mask used to */
+#define FIO2_MASKA_D 0xFFC01710 /* Flag Mask Interrupt A Data register */
+#define FIO2_MASKA_C 0xFFC01714 /* Flag Mask Interrupt A Clear register */
+#define FIO2_MASKA_S 0xFFC01718 /* Flag Mask Interrupt A Set register */
+#define FIO2_MASKA_T 0xFFC0171C /* Flag Mask Interrupt A Toggle register */
+#define FIO2_MASKB_D 0xFFC01720 /* Flag Mask Interrupt B Data register */
+#define FIO2_MASKB_C 0xFFC01724 /* Flag Mask Interrupt B Clear register */
+#define FIO2_MASKB_S 0xFFC01728 /* Flag Mask Interrupt B Set register */
+#define FIO2_MASKB_T 0xFFC0172C /* Flag Mask Interrupt B Toggle register */
+#define FIO2_DIR 0xFFC01730 /* Flag Direction register */
+#define FIO2_POLAR 0xFFC01734 /* Flag Polarity register */
+#define FIO2_EDGE 0xFFC01738 /* Flag Interrupt Sensitivity register */
+#define FIO2_BOTH 0xFFC0173C /* Flag Set on Both Edges register */
+#define FIO2_INEN 0xFFC01740 /* Flag Input Enable register */
+
+
+/*// SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
+#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
+#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+
+/*// SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
+#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
+#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
+#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+
+/* Asynchronous Memory Controller - External Bus Interface Unit */
+#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
+
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
+#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
+#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
+
+
+/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
+#define PPI0_CONTROL 0xFFC01000 /* PPI0 Control register */
+#define PPI0_STATUS 0xFFC01004 /* PPI0 Status register */
+#define PPI0_COUNT 0xFFC01008 /* PPI0 Transfer Count register */
+#define PPI0_DELAY 0xFFC0100C /* PPI0 Delay Count register */
+#define PPI0_FRAME 0xFFC01010 /* PPI0 Frame Length register */
+
+
+/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
+#define PPI1_CONTROL 0xFFC01300 /* PPI1 Control register */
+#define PPI1_STATUS 0xFFC01304 /* PPI1 Status register */
+#define PPI1_COUNT 0xFFC01308 /* PPI1 Transfer Count register */
+#define PPI1_DELAY 0xFFC0130C /* PPI1 Delay Count register */
+#define PPI1_FRAME 0xFFC01310 /* PPI1 Frame Length register */
+
+
+/*DMA traffic control registers */
+#define DMA1_TC_PER 0xFFC01B0C /* Traffic control periods */
+#define DMA1_TC_CNT 0xFFC01B10 /* Traffic control current counts */
+#define DMA2_TC_PER 0xFFC00B0C /* Traffic control periods */
+#define DMA2_TC_CNT 0xFFC00B10 /* Traffic control current counts */
+
+
+/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
+#define DMA1_0_CONFIG 0xFFC01C08 /* DMA1 Channel 0 Configuration register */
+#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
+#define DMA1_0_START_ADDR 0xFFC01C04 /* DMA1 Channel 0 Start Address */
+#define DMA1_0_X_COUNT 0xFFC01C10 /* DMA1 Channel 0 Inner Loop Count */
+#define DMA1_0_Y_COUNT 0xFFC01C18 /* DMA1 Channel 0 Outer Loop Count */
+#define DMA1_0_X_MODIFY 0xFFC01C14 /* DMA1 Channel 0 Inner Loop Addr Increment */
+#define DMA1_0_Y_MODIFY 0xFFC01C1C /* DMA1 Channel 0 Outer Loop Addr Increment */
+#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
+#define DMA1_0_CURR_ADDR 0xFFC01C24 /* DMA1 Channel 0 Current Address Pointer */
+#define DMA1_0_CURR_X_COUNT 0xFFC01C30 /* DMA1 Channel 0 Current Inner Loop Count */
+#define DMA1_0_CURR_Y_COUNT 0xFFC01C38 /* DMA1 Channel 0 Current Outer Loop Count */
+#define DMA1_0_IRQ_STATUS 0xFFC01C28 /* DMA1 Channel 0 Interrupt/Status Register */
+#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C /* DMA1 Channel 0 Peripheral Map Register */
+
+#define DMA1_1_CONFIG 0xFFC01C48 /* DMA1 Channel 1 Configuration register */
+#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
+#define DMA1_1_START_ADDR 0xFFC01C44 /* DMA1 Channel 1 Start Address */
+#define DMA1_1_X_COUNT 0xFFC01C50 /* DMA1 Channel 1 Inner Loop Count */
+#define DMA1_1_Y_COUNT 0xFFC01C58 /* DMA1 Channel 1 Outer Loop Count */
+#define DMA1_1_X_MODIFY 0xFFC01C54 /* DMA1 Channel 1 Inner Loop Addr Increment */
+#define DMA1_1_Y_MODIFY 0xFFC01C5C /* DMA1 Channel 1 Outer Loop Addr Increment */
+#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
+#define DMA1_1_CURR_ADDR 0xFFC01C64 /* DMA1 Channel 1 Current Address Pointer */
+#define DMA1_1_CURR_X_COUNT 0xFFC01C70 /* DMA1 Channel 1 Current Inner Loop Count */
+#define DMA1_1_CURR_Y_COUNT 0xFFC01C78 /* DMA1 Channel 1 Current Outer Loop Count */
+#define DMA1_1_IRQ_STATUS 0xFFC01C68 /* DMA1 Channel 1 Interrupt/Status Register */
+#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C /* DMA1 Channel 1 Peripheral Map Register */
+
+#define DMA1_2_CONFIG 0xFFC01C88 /* DMA1 Channel 2 Configuration register */
+#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
+#define DMA1_2_START_ADDR 0xFFC01C84 /* DMA1 Channel 2 Start Address */
+#define DMA1_2_X_COUNT 0xFFC01C90 /* DMA1 Channel 2 Inner Loop Count */
+#define DMA1_2_Y_COUNT 0xFFC01C98 /* DMA1 Channel 2 Outer Loop Count */
+#define DMA1_2_X_MODIFY 0xFFC01C94 /* DMA1 Channel 2 Inner Loop Addr Increment */
+#define DMA1_2_Y_MODIFY 0xFFC01C9C /* DMA1 Channel 2 Outer Loop Addr Increment */
+#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
+#define DMA1_2_CURR_ADDR 0xFFC01CA4 /* DMA1 Channel 2 Current Address Pointer */
+#define DMA1_2_CURR_X_COUNT 0xFFC01CB0 /* DMA1 Channel 2 Current Inner Loop Count */
+#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8 /* DMA1 Channel 2 Current Outer Loop Count */
+#define DMA1_2_IRQ_STATUS 0xFFC01CA8 /* DMA1 Channel 2 Interrupt/Status Register */
+#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC /* DMA1 Channel 2 Peripheral Map Register */
+
+#define DMA1_3_CONFIG 0xFFC01CC8 /* DMA1 Channel 3 Configuration register */
+#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
+#define DMA1_3_START_ADDR 0xFFC01CC4 /* DMA1 Channel 3 Start Address */
+#define DMA1_3_X_COUNT 0xFFC01CD0 /* DMA1 Channel 3 Inner Loop Count */
+#define DMA1_3_Y_COUNT 0xFFC01CD8 /* DMA1 Channel 3 Outer Loop Count */
+#define DMA1_3_X_MODIFY 0xFFC01CD4 /* DMA1 Channel 3 Inner Loop Addr Increment */
+#define DMA1_3_Y_MODIFY 0xFFC01CDC /* DMA1 Channel 3 Outer Loop Addr Increment */
+#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
+#define DMA1_3_CURR_ADDR 0xFFC01CE4 /* DMA1 Channel 3 Current Address Pointer */
+#define DMA1_3_CURR_X_COUNT 0xFFC01CF0 /* DMA1 Channel 3 Current Inner Loop Count */
+#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8 /* DMA1 Channel 3 Current Outer Loop Count */
+#define DMA1_3_IRQ_STATUS 0xFFC01CE8 /* DMA1 Channel 3 Interrupt/Status Register */
+#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC /* DMA1 Channel 3 Peripheral Map Register */
+
+#define DMA1_4_CONFIG 0xFFC01D08 /* DMA1 Channel 4 Configuration register */
+#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
+#define DMA1_4_START_ADDR 0xFFC01D04 /* DMA1 Channel 4 Start Address */
+#define DMA1_4_X_COUNT 0xFFC01D10 /* DMA1 Channel 4 Inner Loop Count */
+#define DMA1_4_Y_COUNT 0xFFC01D18 /* DMA1 Channel 4 Outer Loop Count */
+#define DMA1_4_X_MODIFY 0xFFC01D14 /* DMA1 Channel 4 Inner Loop Addr Increment */
+#define DMA1_4_Y_MODIFY 0xFFC01D1C /* DMA1 Channel 4 Outer Loop Addr Increment */
+#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
+#define DMA1_4_CURR_ADDR 0xFFC01D24 /* DMA1 Channel 4 Current Address Pointer */
+#define DMA1_4_CURR_X_COUNT 0xFFC01D30 /* DMA1 Channel 4 Current Inner Loop Count */
+#define DMA1_4_CURR_Y_COUNT 0xFFC01D38 /* DMA1 Channel 4 Current Outer Loop Count */
+#define DMA1_4_IRQ_STATUS 0xFFC01D28 /* DMA1 Channel 4 Interrupt/Status Register */
+#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C /* DMA1 Channel 4 Peripheral Map Register */
+
+#define DMA1_5_CONFIG 0xFFC01D48 /* DMA1 Channel 5 Configuration register */
+#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
+#define DMA1_5_START_ADDR 0xFFC01D44 /* DMA1 Channel 5 Start Address */
+#define DMA1_5_X_COUNT 0xFFC01D50 /* DMA1 Channel 5 Inner Loop Count */
+#define DMA1_5_Y_COUNT 0xFFC01D58 /* DMA1 Channel 5 Outer Loop Count */
+#define DMA1_5_X_MODIFY 0xFFC01D54 /* DMA1 Channel 5 Inner Loop Addr Increment */
+#define DMA1_5_Y_MODIFY 0xFFC01D5C /* DMA1 Channel 5 Outer Loop Addr Increment */
+#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
+#define DMA1_5_CURR_ADDR 0xFFC01D64 /* DMA1 Channel 5 Current Address Pointer */
+#define DMA1_5_CURR_X_COUNT 0xFFC01D70 /* DMA1 Channel 5 Current Inner Loop Count */
+#define DMA1_5_CURR_Y_COUNT 0xFFC01D78 /* DMA1 Channel 5 Current Outer Loop Count */
+#define DMA1_5_IRQ_STATUS 0xFFC01D68 /* DMA1 Channel 5 Interrupt/Status Register */
+#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C /* DMA1 Channel 5 Peripheral Map Register */
+
+#define DMA1_6_CONFIG 0xFFC01D88 /* DMA1 Channel 6 Configuration register */
+#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
+#define DMA1_6_START_ADDR 0xFFC01D84 /* DMA1 Channel 6 Start Address */
+#define DMA1_6_X_COUNT 0xFFC01D90 /* DMA1 Channel 6 Inner Loop Count */
+#define DMA1_6_Y_COUNT 0xFFC01D98 /* DMA1 Channel 6 Outer Loop Count */
+#define DMA1_6_X_MODIFY 0xFFC01D94 /* DMA1 Channel 6 Inner Loop Addr Increment */
+#define DMA1_6_Y_MODIFY 0xFFC01D9C /* DMA1 Channel 6 Outer Loop Addr Increment */
+#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
+#define DMA1_6_CURR_ADDR 0xFFC01DA4 /* DMA1 Channel 6 Current Address Pointer */
+#define DMA1_6_CURR_X_COUNT 0xFFC01DB0 /* DMA1 Channel 6 Current Inner Loop Count */
+#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8 /* DMA1 Channel 6 Current Outer Loop Count */
+#define DMA1_6_IRQ_STATUS 0xFFC01DA8 /* DMA1 Channel 6 Interrupt/Status Register */
+#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC /* DMA1 Channel 6 Peripheral Map Register */
+
+#define DMA1_7_CONFIG 0xFFC01DC8 /* DMA1 Channel 7 Configuration register */
+#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
+#define DMA1_7_START_ADDR 0xFFC01DC4 /* DMA1 Channel 7 Start Address */
+#define DMA1_7_X_COUNT 0xFFC01DD0 /* DMA1 Channel 7 Inner Loop Count */
+#define DMA1_7_Y_COUNT 0xFFC01DD8 /* DMA1 Channel 7 Outer Loop Count */
+#define DMA1_7_X_MODIFY 0xFFC01DD4 /* DMA1 Channel 7 Inner Loop Addr Increment */
+#define DMA1_7_Y_MODIFY 0xFFC01DDC /* DMA1 Channel 7 Outer Loop Addr Increment */
+#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
+#define DMA1_7_CURR_ADDR 0xFFC01DE4 /* DMA1 Channel 7 Current Address Pointer */
+#define DMA1_7_CURR_X_COUNT 0xFFC01DF0 /* DMA1 Channel 7 Current Inner Loop Count */
+#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8 /* DMA1 Channel 7 Current Outer Loop Count */
+#define DMA1_7_IRQ_STATUS 0xFFC01DE8 /* DMA1 Channel 7 Interrupt/Status Register */
+#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC /* DMA1 Channel 7 Peripheral Map Register */
+
+#define DMA1_8_CONFIG 0xFFC01E08 /* DMA1 Channel 8 Configuration register */
+#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
+#define DMA1_8_START_ADDR 0xFFC01E04 /* DMA1 Channel 8 Start Address */
+#define DMA1_8_X_COUNT 0xFFC01E10 /* DMA1 Channel 8 Inner Loop Count */
+#define DMA1_8_Y_COUNT 0xFFC01E18 /* DMA1 Channel 8 Outer Loop Count */
+#define DMA1_8_X_MODIFY 0xFFC01E14 /* DMA1 Channel 8 Inner Loop Addr Increment */
+#define DMA1_8_Y_MODIFY 0xFFC01E1C /* DMA1 Channel 8 Outer Loop Addr Increment */
+#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
+#define DMA1_8_CURR_ADDR 0xFFC01E24 /* DMA1 Channel 8 Current Address Pointer */
+#define DMA1_8_CURR_X_COUNT 0xFFC01E30 /* DMA1 Channel 8 Current Inner Loop Count */
+#define DMA1_8_CURR_Y_COUNT 0xFFC01E38 /* DMA1 Channel 8 Current Outer Loop Count */
+#define DMA1_8_IRQ_STATUS 0xFFC01E28 /* DMA1 Channel 8 Interrupt/Status Register */
+#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C /* DMA1 Channel 8 Peripheral Map Register */
+
+#define DMA1_9_CONFIG 0xFFC01E48 /* DMA1 Channel 9 Configuration register */
+#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
+#define DMA1_9_START_ADDR 0xFFC01E44 /* DMA1 Channel 9 Start Address */
+#define DMA1_9_X_COUNT 0xFFC01E50 /* DMA1 Channel 9 Inner Loop Count */
+#define DMA1_9_Y_COUNT 0xFFC01E58 /* DMA1 Channel 9 Outer Loop Count */
+#define DMA1_9_X_MODIFY 0xFFC01E54 /* DMA1 Channel 9 Inner Loop Addr Increment */
+#define DMA1_9_Y_MODIFY 0xFFC01E5C /* DMA1 Channel 9 Outer Loop Addr Increment */
+#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
+#define DMA1_9_CURR_ADDR 0xFFC01E64 /* DMA1 Channel 9 Current Address Pointer */
+#define DMA1_9_CURR_X_COUNT 0xFFC01E70 /* DMA1 Channel 9 Current Inner Loop Count */
+#define DMA1_9_CURR_Y_COUNT 0xFFC01E78 /* DMA1 Channel 9 Current Outer Loop Count */
+#define DMA1_9_IRQ_STATUS 0xFFC01E68 /* DMA1 Channel 9 Interrupt/Status Register */
+#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C /* DMA1 Channel 9 Peripheral Map Register */
+
+#define DMA1_10_CONFIG 0xFFC01E88 /* DMA1 Channel 10 Configuration register */
+#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80 /* DMA1 Channel 10 Next Descripter Ptr Reg */
+#define DMA1_10_START_ADDR 0xFFC01E84 /* DMA1 Channel 10 Start Address */
+#define DMA1_10_X_COUNT 0xFFC01E90 /* DMA1 Channel 10 Inner Loop Count */
+#define DMA1_10_Y_COUNT 0xFFC01E98 /* DMA1 Channel 10 Outer Loop Count */
+#define DMA1_10_X_MODIFY 0xFFC01E94 /* DMA1 Channel 10 Inner Loop Addr Increment */
+#define DMA1_10_Y_MODIFY 0xFFC01E9C /* DMA1 Channel 10 Outer Loop Addr Increment */
+#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0 /* DMA1 Channel 10 Current Descriptor Pointer */
+#define DMA1_10_CURR_ADDR 0xFFC01EA4 /* DMA1 Channel 10 Current Address Pointer */
+#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
+#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
+#define DMA1_10_IRQ_STATUS 0xFFC01EA8 /* DMA1 Channel 10 Interrupt/Status Register */
+#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC /* DMA1 Channel 10 Peripheral Map Register */
+
+#define DMA1_11_CONFIG 0xFFC01EC8 /* DMA1 Channel 11 Configuration register */
+#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0 /* DMA1 Channel 11 Next Descripter Ptr Reg */
+#define DMA1_11_START_ADDR 0xFFC01EC4 /* DMA1 Channel 11 Start Address */
+#define DMA1_11_X_COUNT 0xFFC01ED0 /* DMA1 Channel 11 Inner Loop Count */
+#define DMA1_11_Y_COUNT 0xFFC01ED8 /* DMA1 Channel 11 Outer Loop Count */
+#define DMA1_11_X_MODIFY 0xFFC01ED4 /* DMA1 Channel 11 Inner Loop Addr Increment */
+#define DMA1_11_Y_MODIFY 0xFFC01EDC /* DMA1 Channel 11 Outer Loop Addr Increment */
+#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0 /* DMA1 Channel 11 Current Descriptor Pointer */
+#define DMA1_11_CURR_ADDR 0xFFC01EE4 /* DMA1 Channel 11 Current Address Pointer */
+#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
+#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
+#define DMA1_11_IRQ_STATUS 0xFFC01EE8 /* DMA1 Channel 11 Interrupt/Status Register */
+#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC /* DMA1 Channel 11 Peripheral Map Register */
+
+/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
+#define MDMA1_D0_CONFIG 0xFFC01F08 /*MemDMA1 Stream 0 Destination Configuration */
+#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00 /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA1_D0_START_ADDR 0xFFC01F04 /*MemDMA1 Stream 0 Destination Start Address */
+#define MDMA1_D0_X_COUNT 0xFFC01F10 /*MemDMA1 Stream 0 Destination Inner-Loop Count */
+#define MDMA1_D0_Y_COUNT 0xFFC01F18 /*MemDMA1 Stream 0 Destination Outer-Loop Count */
+#define MDMA1_D0_X_MODIFY 0xFFC01F14 /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA1_D0_Y_MODIFY 0xFFC01F1C /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20 /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA1_D0_CURR_ADDR 0xFFC01F24 /*MemDMA1 Stream 0 Destination Current Address */
+#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30 /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
+#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38 /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
+#define MDMA1_D0_IRQ_STATUS 0xFFC01F28 /*MemDMA1 Stream 0 Destination Interrupt/Status */
+#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C /*MemDMA1 Stream 0 Destination Peripheral Map */
+
+#define MDMA1_S0_CONFIG 0xFFC01F48 /*MemDMA1 Stream 0 Source Configuration */
+#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40 /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA1_S0_START_ADDR 0xFFC01F44 /*MemDMA1 Stream 0 Source Start Address */
+#define MDMA1_S0_X_COUNT 0xFFC01F50 /*MemDMA1 Stream 0 Source Inner-Loop Count */
+#define MDMA1_S0_Y_COUNT 0xFFC01F58 /*MemDMA1 Stream 0 Source Outer-Loop Count */
+#define MDMA1_S0_X_MODIFY 0xFFC01F54 /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
+#define MDMA1_S0_Y_MODIFY 0xFFC01F5C /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
+#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60 /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA1_S0_CURR_ADDR 0xFFC01F64 /*MemDMA1 Stream 0 Source Current Address */
+#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70 /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
+#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78 /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
+#define MDMA1_S0_IRQ_STATUS 0xFFC01F68 /*MemDMA1 Stream 0 Source Interrupt/Status */
+#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C /*MemDMA1 Stream 0 Source Peripheral Map */
+
+#define MDMA1_D1_CONFIG 0xFFC01F88 /*MemDMA1 Stream 1 Destination Configuration */
+#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80 /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA1_D1_START_ADDR 0xFFC01F84 /*MemDMA1 Stream 1 Destination Start Address */
+#define MDMA1_D1_X_COUNT 0xFFC01F90 /*MemDMA1 Stream 1 Destination Inner-Loop Count */
+#define MDMA1_D1_Y_COUNT 0xFFC01F98 /*MemDMA1 Stream 1 Destination Outer-Loop Count */
+#define MDMA1_D1_X_MODIFY 0xFFC01F94 /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA1_D1_Y_MODIFY 0xFFC01F9C /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0 /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
+#define MDMA1_D1_CURR_ADDR 0xFFC01FA4 /*MemDMA1 Stream 1 Dest Current Address */
+#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0 /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
+#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8 /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
+#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8 /*MemDMA1 Stream 1 Dest Interrupt/Status */
+#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC /*MemDMA1 Stream 1 Dest Peripheral Map */
+
+#define MDMA1_S1_CONFIG 0xFFC01FC8 /*MemDMA1 Stream 1 Source Configuration */
+#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0 /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA1_S1_START_ADDR 0xFFC01FC4 /*MemDMA1 Stream 1 Source Start Address */
+#define MDMA1_S1_X_COUNT 0xFFC01FD0 /*MemDMA1 Stream 1 Source Inner-Loop Count */
+#define MDMA1_S1_Y_COUNT 0xFFC01FD8 /*MemDMA1 Stream 1 Source Outer-Loop Count */
+#define MDMA1_S1_X_MODIFY 0xFFC01FD4 /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
+#define MDMA1_S1_Y_MODIFY 0xFFC01FDC /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0 /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA1_S1_CURR_ADDR 0xFFC01FE4 /*MemDMA1 Stream 1 Source Current Address */
+#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0 /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
+#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8 /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
+#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8 /*MemDMA1 Stream 1 Source Interrupt/Status */
+#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC /*MemDMA1 Stream 1 Source Peripheral Map */
+
+
+/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
+#define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */
+#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
+#define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */
+#define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */
+#define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */
+#define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */
+#define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */
+#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
+#define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */
+#define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */
+#define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */
+#define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */
+#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */
+
+#define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */
+#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
+#define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */
+#define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */
+#define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */
+#define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */
+#define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */
+#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
+#define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */
+#define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */
+#define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */
+#define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */
+#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */
+
+#define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */
+#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
+#define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */
+#define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */
+#define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */
+#define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */
+#define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */
+#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
+#define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */
+#define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */
+#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */
+#define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */
+#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */
+
+#define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */
+#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
+#define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */
+#define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */
+#define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */
+#define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */
+#define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */
+#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
+#define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */
+#define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */
+#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */
+#define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */
+#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */
+
+#define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */
+#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
+#define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */
+#define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */
+#define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */
+#define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */
+#define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */
+#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
+#define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */
+#define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */
+#define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */
+#define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */
+#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */
+
+#define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */
+#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
+#define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */
+#define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */
+#define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */
+#define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */
+#define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */
+#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
+#define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */
+#define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */
+#define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */
+#define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */
+#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */
+
+#define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */
+#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
+#define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */
+#define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */
+#define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */
+#define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */
+#define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */
+#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
+#define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */
+#define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */
+#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */
+#define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */
+#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */
+
+#define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */
+#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
+#define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */
+#define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */
+#define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */
+#define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */
+#define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */
+#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
+#define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */
+#define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */
+#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */
+#define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */
+#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */
+
+#define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */
+#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
+#define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */
+#define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */
+#define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */
+#define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */
+#define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */
+#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
+#define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */
+#define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */
+#define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */
+#define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */
+#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */
+
+#define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */
+#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
+#define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */
+#define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */
+#define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */
+#define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */
+#define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */
+#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
+#define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */
+#define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */
+#define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */
+#define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */
+#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */
+
+#define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */
+#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */
+#define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */
+#define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */
+#define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */
+#define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */
+#define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */
+#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */
+#define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */
+#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
+#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
+#define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */
+#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */
+
+#define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */
+#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */
+#define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */
+#define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */
+#define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */
+#define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */
+#define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */
+#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */
+#define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */
+#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
+#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
+#define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */
+#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */
+
+
+/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
+#define MDMA2_D0_CONFIG 0xFFC00F08 /*MemDMA2 Stream 0 Destination Configuration register */
+#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00 /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA2_D0_START_ADDR 0xFFC00F04 /*MemDMA2 Stream 0 Destination Start Address */
+#define MDMA2_D0_X_COUNT 0xFFC00F10 /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
+#define MDMA2_D0_Y_COUNT 0xFFC00F18 /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
+#define MDMA2_D0_X_MODIFY 0xFFC00F14 /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA2_D0_Y_MODIFY 0xFFC00F1C /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20 /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA2_D0_CURR_ADDR 0xFFC00F24 /*MemDMA2 Stream 0 Destination Current Address */
+#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30 /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
+#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38 /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
+#define MDMA2_D0_IRQ_STATUS 0xFFC00F28 /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
+#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C /*MemDMA2 Stream 0 Destination Peripheral Map register */
+
+#define MDMA2_S0_CONFIG 0xFFC00F48 /*MemDMA2 Stream 0 Source Configuration register */
+#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40 /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA2_S0_START_ADDR 0xFFC00F44 /*MemDMA2 Stream 0 Source Start Address */
+#define MDMA2_S0_X_COUNT 0xFFC00F50 /*MemDMA2 Stream 0 Source Inner-Loop Count register */
+#define MDMA2_S0_Y_COUNT 0xFFC00F58 /*MemDMA2 Stream 0 Source Outer-Loop Count register */
+#define MDMA2_S0_X_MODIFY 0xFFC00F54 /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
+#define MDMA2_S0_Y_MODIFY 0xFFC00F5C /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
+#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60 /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA2_S0_CURR_ADDR 0xFFC00F64 /*MemDMA2 Stream 0 Source Current Address */
+#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70 /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
+#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78 /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
+#define MDMA2_S0_IRQ_STATUS 0xFFC00F68 /*MemDMA2 Stream 0 Source Interrupt/Status Register */
+#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C /*MemDMA2 Stream 0 Source Peripheral Map register */
+
+#define MDMA2_D1_CONFIG 0xFFC00F88 /*MemDMA2 Stream 1 Destination Configuration register */
+#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80 /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA2_D1_START_ADDR 0xFFC00F84 /*MemDMA2 Stream 1 Destination Start Address */
+#define MDMA2_D1_X_COUNT 0xFFC00F90 /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
+#define MDMA2_D1_Y_COUNT 0xFFC00F98 /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
+#define MDMA2_D1_X_MODIFY 0xFFC00F94 /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA2_D1_Y_MODIFY 0xFFC00F9C /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0 /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
+#define MDMA2_D1_CURR_ADDR 0xFFC00FA4 /*MemDMA2 Stream 1 Destination Current Address reg */
+#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0 /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
+#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8 /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
+#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8 /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
+#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC /*MemDMA2 Stream 1 Destination Peripheral Map register */
+
+#define MDMA2_S1_CONFIG 0xFFC00FC8 /*MemDMA2 Stream 1 Source Configuration register */
+#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0 /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA2_S1_START_ADDR 0xFFC00FC4 /*MemDMA2 Stream 1 Source Start Address */
+#define MDMA2_S1_X_COUNT 0xFFC00FD0 /*MemDMA2 Stream 1 Source Inner-Loop Count register */
+#define MDMA2_S1_Y_COUNT 0xFFC00FD8 /*MemDMA2 Stream 1 Source Outer-Loop Count register */
+#define MDMA2_S1_X_MODIFY 0xFFC00FD4 /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
+#define MDMA2_S1_Y_MODIFY 0xFFC00FDC /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0 /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA2_S1_CURR_ADDR 0xFFC00FE4 /*MemDMA2 Stream 1 Source Current Address */
+#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0 /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
+#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8 /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
+#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8 /*MemDMA2 Stream 1 Source Interrupt/Status Register */
+#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC /*MemDMA2 Stream 1 Source Peripheral Map register */
+
+
+
+/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
+#define IMDMA_D0_CONFIG 0xFFC01808 /*IMDMA Stream 0 Destination Configuration */
+#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800 /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
+#define IMDMA_D0_START_ADDR 0xFFC01804 /*IMDMA Stream 0 Destination Start Address */
+#define IMDMA_D0_X_COUNT 0xFFC01810 /*IMDMA Stream 0 Destination Inner-Loop Count */
+#define IMDMA_D0_Y_COUNT 0xFFC01818 /*IMDMA Stream 0 Destination Outer-Loop Count */
+#define IMDMA_D0_X_MODIFY 0xFFC01814 /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
+#define IMDMA_D0_Y_MODIFY 0xFFC0181C /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
+#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820 /*IMDMA Stream 0 Destination Current Descriptor Ptr */
+#define IMDMA_D0_CURR_ADDR 0xFFC01824 /*IMDMA Stream 0 Destination Current Address */
+#define IMDMA_D0_CURR_X_COUNT 0xFFC01830 /*IMDMA Stream 0 Destination Current Inner-Loop Count */
+#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838 /*IMDMA Stream 0 Destination Current Outer-Loop Count */
+#define IMDMA_D0_IRQ_STATUS 0xFFC01828 /*IMDMA Stream 0 Destination Interrupt/Status */
+
+#define IMDMA_S0_CONFIG 0xFFC01848 /*IMDMA Stream 0 Source Configuration */
+#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840 /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
+#define IMDMA_S0_START_ADDR 0xFFC01844 /*IMDMA Stream 0 Source Start Address */
+#define IMDMA_S0_X_COUNT 0xFFC01850 /*IMDMA Stream 0 Source Inner-Loop Count */
+#define IMDMA_S0_Y_COUNT 0xFFC01858 /*IMDMA Stream 0 Source Outer-Loop Count */
+#define IMDMA_S0_X_MODIFY 0xFFC01854 /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
+#define IMDMA_S0_Y_MODIFY 0xFFC0185C /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
+#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860 /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
+#define IMDMA_S0_CURR_ADDR 0xFFC01864 /*IMDMA Stream 0 Source Current Address */
+#define IMDMA_S0_CURR_X_COUNT 0xFFC01870 /*IMDMA Stream 0 Source Current Inner-Loop Count */
+#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878 /*IMDMA Stream 0 Source Current Outer-Loop Count */
+#define IMDMA_S0_IRQ_STATUS 0xFFC01868 /*IMDMA Stream 0 Source Interrupt/Status */
+
+#define IMDMA_D1_CONFIG 0xFFC01888 /*IMDMA Stream 1 Destination Configuration */
+#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880 /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
+#define IMDMA_D1_START_ADDR 0xFFC01884 /*IMDMA Stream 1 Destination Start Address */
+#define IMDMA_D1_X_COUNT 0xFFC01890 /*IMDMA Stream 1 Destination Inner-Loop Count */
+#define IMDMA_D1_Y_COUNT 0xFFC01898 /*IMDMA Stream 1 Destination Outer-Loop Count */
+#define IMDMA_D1_X_MODIFY 0xFFC01894 /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
+#define IMDMA_D1_Y_MODIFY 0xFFC0189C /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
+#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0 /*IMDMA Stream 1 Destination Current Descriptor Ptr */
+#define IMDMA_D1_CURR_ADDR 0xFFC018A4 /*IMDMA Stream 1 Destination Current Address */
+#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0 /*IMDMA Stream 1 Destination Current Inner-Loop Count */
+#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8 /*IMDMA Stream 1 Destination Current Outer-Loop Count */
+#define IMDMA_D1_IRQ_STATUS 0xFFC018A8 /*IMDMA Stream 1 Destination Interrupt/Status */
+
+#define IMDMA_S1_CONFIG 0xFFC018C8 /*IMDMA Stream 1 Source Configuration */
+#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0 /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
+#define IMDMA_S1_START_ADDR 0xFFC018C4 /*IMDMA Stream 1 Source Start Address */
+#define IMDMA_S1_X_COUNT 0xFFC018D0 /*IMDMA Stream 1 Source Inner-Loop Count */
+#define IMDMA_S1_Y_COUNT 0xFFC018D8 /*IMDMA Stream 1 Source Outer-Loop Count */
+#define IMDMA_S1_X_MODIFY 0xFFC018D4 /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
+#define IMDMA_S1_Y_MODIFY 0xFFC018DC /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
+#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0 /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
+#define IMDMA_S1_CURR_ADDR 0xFFC018E4 /*IMDMA Stream 1 Source Current Address */
+#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0 /*IMDMA Stream 1 Source Current Inner-Loop Count */
+#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8 /*IMDMA Stream 1 Source Current Outer-Loop Count */
+#define IMDMA_S1_IRQ_STATUS 0xFFC018E8 /*IMDMA Stream 1 Source Interrupt/Status */
+
+
+
+/*********************************************************************************** */
+/* System MMR Register Bits */
+/******************************************************************************* */
+
+/* ********************* PLL AND RESET MASKS ************************ */
+
+/* PLL_CTL Masks */
+#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
+#define PLL_OFF 0x0002 /* Shut off PLL clocks */
+#define STOPCK_OFF 0x0008 /* Core clock off */
+#define ALT_TIMING 0x0010 /* Enable Alternate PPI Timing (0.5 Silicon And Beyond) */
+#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
+#define BYPASS 0x0100 /* Bypass the PLL */
+
+/* PLL_DIV Masks */
+#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
+
+#define CCLK_DIV1 0x00000000 /* CCLK = VCO / 1 */
+#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
+#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
+#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
+
+/* SWRST Mask */
+#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */
+#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */
+#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */
+#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */
+#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */
+#define SWRST_OCCURRED 0x00008000 /* SWRST Status */
+
+/* VR_CTL Masks */
+#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
+#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
+#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
+
+#define GAIN 0x000C /* Voltage Level Gain */
+#define GAIN_5 0x0000 /* GAIN = 5 */
+#define GAIN_10 0x0004 /* GAIN = 10 */
+#define GAIN_20 0x0008 /* GAIN = 20 */
+#define GAIN_50 0x000C /* GAIN = 50 */
+
+#define VLEV 0x00F0 /* Internal Voltage Level - Only Program Values Within Specifications */
+#define VLEV_085 0x0060 /* VLEV = 0.85 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_090 0x0070 /* VLEV = 0.90 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_095 0x0080 /* VLEV = 0.95 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_100 0x0090 /* VLEV = 1.00 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_105 0x00A0 /* VLEV = 1.05 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_110 0x00B0 /* VLEV = 1.10 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_115 0x00C0 /* VLEV = 1.15 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_120 0x00D0 /* VLEV = 1.20 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_125 0x00E0 /* VLEV = 1.25 V (See Datasheet for Regulator Tolerance) */
+#define VLEV_130 0x00F0 /* VLEV = 1.30 V (See Datasheet for Regulator Tolerance) */
+
+
+/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
+
+/* SICu_IARv Masks */
+/* u = A or B */
+/* v = 0 to 7 */
+/* w = 0 or 1 */
+
+/* Per_number = 0 to 63 */
+/* IVG_number = 7 to 15 */
+#define Peripheral_IVG(Per_number, IVG_number) \
+ ( (IVG_number) -7) << ( ((Per_number)%8) *4) /* Peripheral #Per_number assigned IVG #IVG_number */
+ /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
+ /* r0.h = hi(Peripheral_IVG(62, 10)); */
+
+
+
+/* SICx_IMASKw Masks */
+/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers */
+#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
+#define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
+/* x = pos 0 to 31, for 32-63 use value-32 */
+#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
+
+
+
+/* ********* WATCHDOG TIMER MASKS ******************** */
+
+/* Watchdog Timer WDOG_CTL Register Masks */
+
+#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
+#define WDEV_RESET 0x0000 /* generate reset event on roll over */
+#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
+#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
+#define WDEV_NONE 0x0006 /* no event on roll over */
+#define WDEN 0x0FF0 /* enable watchdog */
+#define WDDIS 0x0AD0 /* disable watchdog */
+#define WDRO 0x8000 /* watchdog rolled over latch */
+
+/* depreciated WDOG_CTL Register Masks for legacy code */
+
+
+#define ICTL WDEV
+#define ENABLE_RESET WDEV_RESET
+#define WDOG_RESET WDEV_RESET
+#define ENABLE_NMI WDEV_NMI
+#define WDOG_NMI WDEV_NMI
+#define ENABLE_GPI WDEV_GPI
+#define WDOG_GPI WDEV_GPI
+#define DISABLE_EVT WDEV_NONE
+#define WDOG_NONE WDEV_NONE
+
+#define TMR_EN WDEN
+#define WDOG_DISABLE WDDIS
+#define TRO WDRO
+
+
+
+/* ***************************** UART CONTROLLER MASKS ********************** */
+
+/* UART_LCR Register */
+
+#define DLAB 0x80
+#define SB 0x40
+#define STP 0x20
+#define EPS 0x10
+#define PEN 0x08
+#define STB 0x04
+#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
+
+#define DLAB_P 0x07
+#define SB_P 0x06
+#define STP_P 0x05
+#define EPS_P 0x04
+#define PEN_P 0x03
+#define STB_P 0x02
+#define WLS_P1 0x01
+#define WLS_P0 0x00
+
+/* UART_MCR Register */
+#define LOOP_ENA 0x10 /* Loopback Mode Enable */
+#define LOOP_ENA_P 0x04
+
+/* UART_LSR Register */
+#define TEMT 0x40
+#define THRE 0x20
+#define BI 0x10
+#define FE 0x08
+#define PE 0x04
+#define OE 0x02
+#define DR 0x01
+
+#define TEMP_P 0x06
+#define THRE_P 0x05
+#define BI_P 0x04
+#define FE_P 0x03
+#define PE_P 0x02
+#define OE_P 0x01
+#define DR_P 0x00
+
+/* UART_IER Register */
+#define ELSI 0x04
+#define ETBEI 0x02
+#define ERBFI 0x01
+
+#define ELSI_P 0x02
+#define ETBEI_P 0x01
+#define ERBFI_P 0x00
+
+/* UART_IIR Register */
+#define STATUS(x) (((x) << 1) & 0x06)
+#define NINT 0x01
+#define STATUS_P1 0x02
+#define STATUS_P0 0x01
+#define NINT_P 0x00
+
+/* UART_GCTL Register */
+#define FFE 0x20
+#define FPE 0x10
+#define RPOLC 0x08
+#define TPOLC 0x04
+#define IREN 0x02
+#define UCEN 0x01
+
+#define FFE_P 0x05
+#define FPE_P 0x04
+#define RPOLC_P 0x03
+#define TPOLC_P 0x02
+#define IREN_P 0x01
+#define UCEN_P 0x00
+
+/* ********** SERIAL PORT MASKS ********************** */
+
+/* SPORTx_TCR1 Masks */
+#define TSPEN 0x0001 /* TX enable */
+#define ITCLK 0x0002 /* Internal TX Clock Select */
+#define TDTYPE 0x000C /* TX Data Formatting Select */
+#define TLSBIT 0x0010 /* TX Bit Order */
+#define ITFS 0x0200 /* Internal TX Frame Sync Select */
+#define TFSR 0x0400 /* TX Frame Sync Required Select */
+#define DITFS 0x0800 /* Data Independent TX Frame Sync Select */
+#define LTFS 0x1000 /* Low TX Frame Sync Select */
+#define LATFS 0x2000 /* Late TX Frame Sync Select */
+#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
+
+/* SPORTx_TCR2 Masks */
+#define SLEN 0x001F /*TX Word Length */
+#define TXSE 0x0100 /*TX Secondary Enable */
+#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
+#define TRFST 0x0400 /*TX Right-First Data Order */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN 0x0001 /* RX enable */
+#define IRCLK 0x0002 /* Internal RX Clock Select */
+#define RDTYPE 0x000C /* RX Data Formatting Select */
+#define RULAW 0x0008 /* u-Law enable */
+#define RALAW 0x000C /* A-Law enable */
+#define RLSBIT 0x0010 /* RX Bit Order */
+#define IRFS 0x0200 /* Internal RX Frame Sync Select */
+#define RFSR 0x0400 /* RX Frame Sync Required Select */
+#define LRFS 0x1000 /* Low RX Frame Sync Select */
+#define LARFS 0x2000 /* Late RX Frame Sync Select */
+#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN 0x001F /*RX Word Length */
+#define RXSE 0x0100 /*RX Secondary Enable */
+#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
+#define RRFST 0x0400 /*Right-First Data Order */
+
+/*SPORTx_STAT Masks */
+#define RXNE 0x0001 /*RX FIFO Not Empty Status */
+#define RUVF 0x0002 /*RX Underflow Status */
+#define ROVF 0x0004 /*RX Overflow Status */
+#define TXF 0x0008 /*TX FIFO Full Status */
+#define TUVF 0x0010 /*TX Underflow Status */
+#define TOVF 0x0020 /*TX Overflow Status */
+#define TXHRE 0x0040 /*TX Hold Register Empty */
+
+/*SPORTx_MCMC1 Masks */
+#define WSIZE 0x0000F000 /*Multichannel Window Size Field */
+#define WOFF 0x000003FF /*Multichannel Window Offset Field */
+
+/*SPORTx_MCMC2 Masks */
+#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
+#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
+#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
+#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
+#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
+#define MFD 0x0000F000 /*Multichannel Frame Delay */
+
+/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
+
+/*// PPI_CONTROL Masks */
+#define PORT_EN 0x00000001 /* PPI Port Enable */
+#define PORT_DIR 0x00000002 /* PPI Port Direction */
+#define XFR_TYPE 0x0000000C /* PPI Transfer Type */
+#define PORT_CFG 0x00000030 /* PPI Port Configuration */
+#define FLD_SEL 0x00000040 /* PPI Active Field Select */
+#define PACK_EN 0x00000080 /* PPI Packing Mode */
+#define DMA32 0x00000100 /* PPI 32-bit DMA Enable */
+#define SKIP_EN 0x00000200 /* PPI Skip Element Enable */
+#define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */
+#define DLENGTH 0x00003800 /* PPI Data Length */
+#define DLEN_8 0x0 /* PPI Data Length mask for DLEN=8 */
+#define DLEN(x) ((((x)-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
+#define POL 0x0000C000 /* PPI Signal Polarities */
+
+
+/*// PPI_STATUS Masks */
+#define FLD 0x00000400 /* Field Indicator */
+#define FT_ERR 0x00000800 /* Frame Track Error */
+#define OVR 0x00001000 /* FIFO Overflow Error */
+#define UNDR 0x00002000 /* FIFO Underrun Error */
+#define ERR_DET 0x00004000 /* Error Detected Indicator */
+#define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */
+
+/* ********** DMA CONTROLLER MASKS *********************8 */
+
+/*//DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
+#define DMAEN 0x00000001 /* Channel Enable */
+#define WNR 0x00000002 /* Channel Direction (W/R*) */
+#define WDSIZE_8 0x00000000 /* Word Size 8 bits */
+#define WDSIZE_16 0x00000004 /* Word Size 16 bits */
+#define WDSIZE_32 0x00000008 /* Word Size 32 bits */
+#define DMA2D 0x00000010 /* 2D/1D* Mode */
+#define RESTART 0x00000020 /* Restart */
+#define DI_SEL 0x00000040 /* Data Interrupt Select */
+#define DI_EN 0x00000080 /* Data Interrupt Enable */
+#define NDSIZE 0x00000900 /* Next Descriptor Size */
+#define FLOW 0x00007000 /* Flow Control */
+
+
+#define DMAEN_P 0 /* Channel Enable */
+#define WNR_P 1 /* Channel Direction (W/R*) */
+#define DMA2D_P 4 /* 2D/1D* Mode */
+#define RESTART_P 5 /* Restart */
+#define DI_SEL_P 6 /* Data Interrupt Select */
+#define DI_EN_P 7 /* Data Interrupt Enable */
+
+/*//DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
+
+#define DMA_DONE 0x00000001 /* DMA Done Indicator */
+#define DMA_ERR 0x00000002 /* DMA Error Indicator */
+#define DFETCH 0x00000004 /* Descriptor Fetch Indicator */
+#define DMA_RUN 0x00000008 /* DMA Running Indicator */
+
+#define DMA_DONE_P 0 /* DMA Done Indicator */
+#define DMA_ERR_P 1 /* DMA Error Indicator */
+#define DFETCH_P 2 /* Descriptor Fetch Indicator */
+#define DMA_RUN_P 3 /* DMA Running Indicator */
+
+/*//DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
+
+#define CTYPE 0x00000040 /* DMA Channel Type Indicator */
+#define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */
+#define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */
+#define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */
+#define PCAPWR 0x00000400 /* DMA Write Operation Indicator */
+#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
+#define PMAP 0x00007000 /* DMA Peripheral Map Field */
+
+/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
+
+/* PWM Timer bit definitions */
+
+/* TIMER_ENABLE Register */
+#define TIMEN0 0x0001
+#define TIMEN1 0x0002
+#define TIMEN2 0x0004
+#define TIMEN3 0x0008
+#define TIMEN4 0x0010
+#define TIMEN5 0x0020
+#define TIMEN6 0x0040
+#define TIMEN7 0x0080
+#define TIMEN8 0x0001
+#define TIMEN9 0x0002
+#define TIMEN10 0x0004
+#define TIMEN11 0x0008
+
+#define TIMEN0_P 0x00
+#define TIMEN1_P 0x01
+#define TIMEN2_P 0x02
+#define TIMEN3_P 0x03
+#define TIMEN4_P 0x04
+#define TIMEN5_P 0x05
+#define TIMEN6_P 0x06
+#define TIMEN7_P 0x07
+#define TIMEN8_P 0x00
+#define TIMEN9_P 0x01
+#define TIMEN10_P 0x02
+#define TIMEN11_P 0x03
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0 0x0001
+#define TIMDIS1 0x0002
+#define TIMDIS2 0x0004
+#define TIMDIS3 0x0008
+#define TIMDIS4 0x0010
+#define TIMDIS5 0x0020
+#define TIMDIS6 0x0040
+#define TIMDIS7 0x0080
+#define TIMDIS8 0x0001
+#define TIMDIS9 0x0002
+#define TIMDIS10 0x0004
+#define TIMDIS11 0x0008
+
+#define TIMDIS0_P 0x00
+#define TIMDIS1_P 0x01
+#define TIMDIS2_P 0x02
+#define TIMDIS3_P 0x03
+#define TIMDIS4_P 0x04
+#define TIMDIS5_P 0x05
+#define TIMDIS6_P 0x06
+#define TIMDIS7_P 0x07
+#define TIMDIS8_P 0x00
+#define TIMDIS9_P 0x01
+#define TIMDIS10_P 0x02
+#define TIMDIS11_P 0x03
+
+/* TIMER_STATUS Register */
+#define TIMIL0 0x00000001
+#define TIMIL1 0x00000002
+#define TIMIL2 0x00000004
+#define TIMIL3 0x00000008
+#define TIMIL4 0x00010000
+#define TIMIL5 0x00020000
+#define TIMIL6 0x00040000
+#define TIMIL7 0x00080000
+#define TIMIL8 0x0001
+#define TIMIL9 0x0002
+#define TIMIL10 0x0004
+#define TIMIL11 0x0008
+#define TOVF_ERR0 0x00000010
+#define TOVF_ERR1 0x00000020
+#define TOVF_ERR2 0x00000040
+#define TOVF_ERR3 0x00000080
+#define TOVF_ERR4 0x00100000
+#define TOVF_ERR5 0x00200000
+#define TOVF_ERR6 0x00400000
+#define TOVF_ERR7 0x00800000
+#define TOVF_ERR8 0x0010
+#define TOVF_ERR9 0x0020
+#define TOVF_ERR10 0x0040
+#define TOVF_ERR11 0x0080
+#define TRUN0 0x00001000
+#define TRUN1 0x00002000
+#define TRUN2 0x00004000
+#define TRUN3 0x00008000
+#define TRUN4 0x10000000
+#define TRUN5 0x20000000
+#define TRUN6 0x40000000
+#define TRUN7 0x80000000
+#define TRUN8 0x1000
+#define TRUN9 0x2000
+#define TRUN10 0x4000
+#define TRUN11 0x8000
+
+#define TIMIL0_P 0x00
+#define TIMIL1_P 0x01
+#define TIMIL2_P 0x02
+#define TIMIL3_P 0x03
+#define TIMIL4_P 0x10
+#define TIMIL5_P 0x11
+#define TIMIL6_P 0x12
+#define TIMIL7_P 0x13
+#define TIMIL8_P 0x00
+#define TIMIL9_P 0x01
+#define TIMIL10_P 0x02
+#define TIMIL11_P 0x03
+#define TOVF_ERR0_P 0x04
+#define TOVF_ERR1_P 0x05
+#define TOVF_ERR2_P 0x06
+#define TOVF_ERR3_P 0x07
+#define TOVF_ERR4_P 0x14
+#define TOVF_ERR5_P 0x15
+#define TOVF_ERR6_P 0x16
+#define TOVF_ERR7_P 0x17
+#define TOVF_ERR8_P 0x04
+#define TOVF_ERR9_P 0x05
+#define TOVF_ERR10_P 0x06
+#define TOVF_ERR11_P 0x07
+#define TRUN0_P 0x0C
+#define TRUN1_P 0x0D
+#define TRUN2_P 0x0E
+#define TRUN3_P 0x0F
+#define TRUN4_P 0x1C
+#define TRUN5_P 0x1D
+#define TRUN6_P 0x1E
+#define TRUN7_P 0x1F
+#define TRUN8_P 0x0C
+#define TRUN9_P 0x0D
+#define TRUN10_P 0x0E
+#define TRUN11_P 0x0F
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#define TOVL_ERR0 TOVF_ERR0
+#define TOVL_ERR1 TOVF_ERR1
+#define TOVL_ERR2 TOVF_ERR2
+#define TOVL_ERR3 TOVF_ERR3
+#define TOVL_ERR4 TOVF_ERR4
+#define TOVL_ERR5 TOVF_ERR5
+#define TOVL_ERR6 TOVF_ERR6
+#define TOVL_ERR7 TOVF_ERR7
+#define TOVL_ERR8 TOVF_ERR8
+#define TOVL_ERR9 TOVF_ERR9
+#define TOVL_ERR10 TOVF_ERR10
+#define TOVL_ERR11 TOVF_ERR11
+#define TOVL_ERR0_P TOVF_ERR0_P
+#define TOVL_ERR1_P TOVF_ERR1_P
+#define TOVL_ERR2_P TOVF_ERR2_P
+#define TOVL_ERR3_P TOVF_ERR3_P
+#define TOVL_ERR4_P TOVF_ERR4_P
+#define TOVL_ERR5_P TOVF_ERR5_P
+#define TOVL_ERR6_P TOVF_ERR6_P
+#define TOVL_ERR7_P TOVF_ERR7_P
+#define TOVL_ERR8_P TOVF_ERR8_P
+#define TOVL_ERR9_P TOVF_ERR9_P
+#define TOVL_ERR10_P TOVF_ERR10_P
+#define TOVL_ERR11_P TOVF_ERR11_P
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT 0x0001
+#define WDTH_CAP 0x0002
+#define EXT_CLK 0x0003
+#define PULSE_HI 0x0004
+#define PERIOD_CNT 0x0008
+#define IRQ_ENA 0x0010
+#define TIN_SEL 0x0020
+#define OUT_DIS 0x0040
+#define CLK_SEL 0x0080
+#define TOGGLE_HI 0x0100
+#define EMU_RUN 0x0200
+#define ERR_TYP(x) (((x) & 0x03) << 14)
+
+#define TMODE_P0 0x00
+#define TMODE_P1 0x01
+#define PULSE_HI_P 0x02
+#define PERIOD_CNT_P 0x03
+#define IRQ_ENA_P 0x04
+#define TIN_SEL_P 0x05
+#define OUT_DIS_P 0x06
+#define CLK_SEL_P 0x07
+#define TOGGLE_HI_P 0x08
+#define EMU_RUN_P 0x09
+#define ERR_TYP_P0 0x0E
+#define ERR_TYP_P1 0x0F
+
+
+/*/ ****************** PROGRAMMABLE FLAG MASKS ********************* */
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
+#define PF0 0x0001
+#define PF1 0x0002
+#define PF2 0x0004
+#define PF3 0x0008
+#define PF4 0x0010
+#define PF5 0x0020
+#define PF6 0x0040
+#define PF7 0x0080
+#define PF8 0x0100
+#define PF9 0x0200
+#define PF10 0x0400
+#define PF11 0x0800
+#define PF12 0x1000
+#define PF13 0x2000
+#define PF14 0x4000
+#define PF15 0x8000
+
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) BIT POSITIONS */
+#define PF0_P 0
+#define PF1_P 1
+#define PF2_P 2
+#define PF3_P 3
+#define PF4_P 4
+#define PF5_P 5
+#define PF6_P 6
+#define PF7_P 7
+#define PF8_P 8
+#define PF9_P 9
+#define PF10_P 10
+#define PF11_P 11
+#define PF12_P 12
+#define PF13_P 13
+#define PF14_P 14
+#define PF15_P 15
+
+/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
+
+/*// SPI_CTL Masks */
+#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
+#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
+#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
+#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
+#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
+#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
+#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
+#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
+#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
+#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
+#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
+#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
+
+/*// SPI_FLG Masks */
+#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/*// SPI_FLG Bit Positions */
+#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/*// SPI_STAT Masks */
+#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
+#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
+#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
+#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
+#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
+#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
+#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
+
+/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
+
+/* AMGCTL Masks */
+#define AMCKEN 0x0001 /* Enable CLKOUT */
+#define AMBEN_B0 0x0002 /* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1 0x0004 /* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2 0x0006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL 0x0008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+#define B0_PEN 0x0010 /* Enable 16-bit packing Bank 0 */
+#define B1_PEN 0x0020 /* Enable 16-bit packing Bank 1 */
+#define B2_PEN 0x0040 /* Enable 16-bit packing Bank 2 */
+#define B3_PEN 0x0080 /* Enable 16-bit packing Bank 3 */
+
+/* AMGCTL Bit Positions */
+#define AMCKEN_P 0x0000 /* Enable CLKOUT */
+#define AMBEN_P0 0x0001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1 0x0002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */
+#define AMBEN_P2 0x0003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+#define B0_PEN_P 0x0004 /* Enable 16-bit packing Bank 0 */
+#define B1_PEN_P 0x0005 /* Enable 16-bit packing Bank 1 */
+#define B2_PEN_P 0x0006 /* Enable 16-bit packing Bank 2 */
+#define B3_PEN_P 0x0007 /* Enable 16-bit packing Bank 3 */
+#define CDPRIO 0x0100 /* DMA has priority over core for for external accesses */
+
+/* AMBCTL0 Masks */
+#define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */
+
+/* AMBCTL1 Masks */
+#define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */
+
+
+/* ********************** SDRAM CONTROLLER MASKS *************************** */
+
+/* EBIU_SDGCTL Masks */
+#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
+#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
+#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
+#define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */
+#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
+#define PFE 0x00000010 /* Enable SDRAM prefetch */
+#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
+#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
+#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
+#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
+#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
+#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
+#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
+#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
+#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
+#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
+#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
+#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
+#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
+#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
+#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
+#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
+#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
+#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
+#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
+#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
+#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
+#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
+#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
+#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
+#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
+#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
+#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
+#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
+#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
+#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
+#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
+#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
+#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
+#define PUPSD 0x00200000 /*Power-up start delay */
+#define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS 0x01000000 /* Start SDRAM self-refresh mode */
+#define EBUFE 0x02000000 /* Enable external buffering timing */
+#define FBBRW 0x04000000 /* Fast back-to-back read write enable */
+#define EMREN 0x10000000 /* Extended mode register enable */
+#define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */
+#define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EB0_E 0x00000001 /* Enable SDRAM external bank 0 */
+#define EB0_SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
+#define EB0_SZ_32 0x00000002 /* SDRAM external bank size = 32MB */
+#define EB0_SZ_64 0x00000004 /* SDRAM external bank size = 64MB */
+#define EB0_SZ_128 0x00000006 /* SDRAM external bank size = 128MB */
+#define EB0_CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EB0_CAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */
+#define EB0_CAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */
+#define EB0_CAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */
+
+#define EB1_E 0x00000100 /* Enable SDRAM external bank 1 */
+#define EB1__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
+#define EB1__SZ_32 0x00000200 /* SDRAM external bank size = 32MB */
+#define EB1__SZ_64 0x00000400 /* SDRAM external bank size = 64MB */
+#define EB1__SZ_128 0x00000600 /* SDRAM external bank size = 128MB */
+#define EB1__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EB1__CAW_9 0x00001000 /* SDRAM external bank column address width = 9 bits */
+#define EB1__CAW_10 0x00002000 /* SDRAM external bank column address width = 9 bits */
+#define EB1__CAW_11 0x00003000 /* SDRAM external bank column address width = 9 bits */
+
+#define EB2__E 0x00010000 /* Enable SDRAM external bank 2 */
+#define EB2__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
+#define EB2__SZ_32 0x00020000 /* SDRAM external bank size = 32MB */
+#define EB2__SZ_64 0x00040000 /* SDRAM external bank size = 64MB */
+#define EB2__SZ_128 0x00060000 /* SDRAM external bank size = 128MB */
+#define EB2__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EB2__CAW_9 0x00100000 /* SDRAM external bank column address width = 9 bits */
+#define EB2__CAW_10 0x00200000 /* SDRAM external bank column address width = 9 bits */
+#define EB2__CAW_11 0x00300000 /* SDRAM external bank column address width = 9 bits */
+
+#define EB3__E 0x01000000 /* Enable SDRAM external bank 3 */
+#define EB3__SZ_16 0x00000000 /* SDRAM external bank size = 16MB */
+#define EB3__SZ_32 0x02000000 /* SDRAM external bank size = 32MB */
+#define EB3__SZ_64 0x04000000 /* SDRAM external bank size = 64MB */
+#define EB3__SZ_128 0x06000000 /* SDRAM external bank size = 128MB */
+#define EB3__CAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */
+#define EB3__CAW_9 0x10000000 /* SDRAM external bank column address width = 9 bits */
+#define EB3__CAW_10 0x20000000 /* SDRAM external bank column address width = 9 bits */
+#define EB3__CAW_11 0x30000000 /* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI 0x00000001 /* SDRAM controller is idle */
+#define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */
+#define SDPUA 0x00000004 /* SDRAM power up active */
+#define SDRS 0x00000008 /* SDRAM is in reset state */
+#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
+#define BGSTAT 0x00000020 /* Bus granted */
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BF561_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * def_LPBlackfin.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
+
+#ifndef _DEF_LPBLACKFIN_H
+#define _DEF_LPBLACKFIN_H
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+
+#if !defined(__ADSPLPBLACKFIN__)
+#warning def_LPBlackfin.h should only be included for 532 compatible chips.
+#endif
+/* ensure macro params bracketed to avoid unexpected evaluations. (GA), MISRA Rule 19.10 */
+#define MK_BMSK_( x ) (1<<(x)) /* Make a bit mask from a bit position */
+
+/*********************************************************************************** */
+/* System Register Bits */
+/*********************************************************************************** */
+
+/*************************************************** */
+/* ASTAT register */
+/*************************************************** */
+
+/* definitions of ASTAT bit positions */
+#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */
+#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */
+#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */
+#define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */
+#define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
+#define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0 */
+#define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */
+#define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1 */
+#define ASTAT_V_P 0x00000018 /* Result of last ALU0 or MAC0 operation overflowed */
+#define ASTAT_V_COPY_P 0x00000003 /* Result of last ALU0 or MAC0 operation overflowed */
+#define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V */
+
+/* ** Masks */
+#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
+#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */
+#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */
+#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */
+#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */
+#define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Overflow Bit */
+#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Overflow Bit */
+
+/*************************************************** */
+/* SEQSTAT register */
+/*************************************************** */
+
+/* ** Bit Positions */
+#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
+#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
+#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
+#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
+#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
+#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
+#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */
+#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
+#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
+#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
+#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
+#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
+#define SEQSTAT_HWERRCAUSE5_P 0x00000013 /* Last hw error cause bit 5 */
+#define SEQSTAT_HWERRCAUSE6_P 0x00000014 /* Last hw error cause bit 6 */
+#define SEQSTAT_HWERRCAUSE7_P 0x00000015 /* Last hw error cause bit 7 */
+/* ** Masks */
+/* Exception cause */
+#define SEQSTAT_EXCAUSE ( MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE5_P ) )
+
+/* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P )
+
+/* Last hw error cause */
+#define SEQSTAT_HWERRCAUSE ( MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) )
+
+/*************************************************** */
+/* SYSCFG register */
+/*************************************************** */
+
+/* ** Bit Positions */
+#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */
+#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
+#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
+
+/* ** Masks */
+#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P ) /* Supervisor single step, when set it forces an exception for each instruction executed */
+#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P ) /* Enable cycle counter (=1) */
+#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P) /* Self Nesting Interrupt Enable */
+/* Backward-compatibility for typos in prior releases */
+#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
+#define SYSCFG_CCCEN SYSCFG_CCEN
+
+/*********************************************************************************** */
+/* Core MMR Register Map */
+/*********************************************************************************** */
+
+/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
+
+
+#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
+#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
+#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
+#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
+
+/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
+
+#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
+#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
+#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
+#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
+#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
+
+/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
+
+#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
+#define IMASK 0xFFE02104 /* Interrupt Mask Register */
+#define IPEND 0xFFE02108 /* Interrupt Pending Register */
+#define ILAT 0xFFE0210C /* Interrupt Latch Register */
+#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
+
+/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
+
+#define TCNTL 0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
+#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
+
+/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
+#define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */
+
+#define DBGSTAT 0xFFE05008 /* Debug Status Register */
+
+
+/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
+
+#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF 0xFFE06100 /* Trace Buffer */
+
+/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
+
+#define WPIACTL 0xFFE07000 /* Watchpoint Instruction Address Control Register */
+#define WPIA0 0xFFE07040 /* Watchpoint Instruction Address Register 0 */
+#define WPIA1 0xFFE07044 /* Watchpoint Instruction Address Register 1 */
+#define WPIA2 0xFFE07048 /* Watchpoint Instruction Address Register 2 */
+#define WPIA3 0xFFE0704C /* Watchpoint Instruction Address Register 3 */
+#define WPIA4 0xFFE07050 /* Watchpoint Instruction Address Register 4 */
+#define WPIA5 0xFFE07054 /* Watchpoint Instruction Address Register 5 */
+#define WPIACNT0 0xFFE07080 /* Watchpoint Instruction Address Count Register 0 */
+#define WPIACNT1 0xFFE07084 /* Watchpoint Instruction Address Count Register 1 */
+#define WPIACNT2 0xFFE07088 /* Watchpoint Instruction Address Count Register 2 */
+#define WPIACNT3 0xFFE0708C /* Watchpoint Instruction Address Count Register 3 */
+#define WPIACNT4 0xFFE07090 /* Watchpoint Instruction Address Count Register 4 */
+#define WPIACNT5 0xFFE07094 /* Watchpoint Instruction Address Count Register 5 */
+#define WPDACTL 0xFFE07100 /* Watchpoint Data Address Control Register */
+#define WPDA0 0xFFE07140 /* Watchpoint Data Address Register 0 */
+#define WPDA1 0xFFE07144 /* Watchpoint Data Address Register 1 */
+#define WPDACNT0 0xFFE07180 /* Watchpoint Data Address Count Value Register 0 */
+#define WPDACNT1 0xFFE07184 /* Watchpoint Data Address Count Value Register 1 */
+#define WPSTAT 0xFFE07200 /* Watchpoint Status Register */
+
+/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
+
+#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */
+#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */
+#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */
+
+
+/*********************************************************************************** */
+/* Core MMR Register Bits */
+/*********************************************************************************** */
+
+/*************************************************** */
+/* EVT registers (ILAT, IMASK, and IPEND). */
+/*************************************************** */
+
+/* ** Bit Positions */
+#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
+#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
+#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
+#define EVT_EVX_P 0x00000003 /* Exception bit position */
+#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
+#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
+#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
+#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
+#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
+#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
+#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
+#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
+#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
+#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
+#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
+#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
+
+/* ** Masks */
+#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
+#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
+#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
+#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
+#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
+#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
+#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
+#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
+#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
+#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
+#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
+#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
+#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
+#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
+#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
+#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
+
+/*************************************************** */
+/* DMEM_CONTROL Register */
+/*************************************************** */
+/* ** Bit Positions */
+#define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */
+#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
+
+#define ENDCPLB_P 0x01 /* Enable DCPLBS */
+#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
+#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
+#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
+#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
+#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
+#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
+#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
+#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
+
+/* ** Masks */
+#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */
+#define ENDCPLB 0x00000002 /* Enable DCPLB */
+#define ASRAM_BSRAM 0x00000000
+#define ACACHE_BSRAM 0x00000008
+#define ACACHE_BCACHE 0x0000000C
+#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
+#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
+#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
+
+/* IMEM_CONTROL Register */
+/* ** Bit Positions */
+#define ENIM_P 0x00 /* Enable L1 Code Memory */
+#define IMCTL_ENIM_P 0x00 /* "" (older define) */
+#define ENICPLB_P 0x01 /* Enable ICPLB */
+#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
+#define IMC_P 0x02 /* Enable */
+#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0_P 0x03 /* Lock Way 0 */
+#define ILOC1_P 0x04 /* Lock Way 1 */
+#define ILOC2_P 0x05 /* Lock Way 2 */
+#define ILOC3_P 0x06 /* Lock Way 3 */
+#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */
+/* ** Masks */
+#define ENIM 0x00000001 /* Enable L1 Code Memory */
+#define ENICPLB 0x00000002 /* Enable ICPLB */
+#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */
+#define ILOC0 0x00000008 /* Lock Way 0 */
+#define ILOC1 0x00000010 /* Lock Way 1 */
+#define ILOC2 0x00000020 /* Lock Way 2 */
+#define ILOC3 0x00000040 /* Lock Way 3 */
+#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */
+
+/* TCNTL Masks */
+#define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */
+#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD 0x00000004 /* Timer auto reload */
+#define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
+
+/* TCNTL Bit Positions */
+#define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */
+#define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD_P 0x00000002 /* Timer auto reload */
+#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
+
+/* DCPLB_DATA and ICPLB_DATA Registers */
+/*** Bit Positions */
+#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */
+/*** Masks */
+#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
+#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
+#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
+#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
+#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
+#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
+#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
+/*** ICPLB_DATA only */
+#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */
+/*** DCPLB_DATA only */
+#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
+#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
+#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
+#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */
+ /* 1= allocate cache lines on write-through writes. */
+#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
+
+
+
+/* ITEST_COMMAND and DTEST_COMMAND Registers */
+/*** Masks */
+#define TEST_READ 0x00000000 /* Read Access */
+#define TEST_WRITE 0x00000002 /* Write Access */
+#define TEST_TAG 0x00000000 /* Access TAG */
+#define TEST_DATA 0x00000004 /* Access DATA */
+#define TEST_DW0 0x00000000 /* Select Double Word 0 */
+#define TEST_DW1 0x00000008 /* Select Double Word 1 */
+#define TEST_DW2 0x00000010 /* Select Double Word 2 */
+#define TEST_DW3 0x00000018 /* Select Double Word 3 */
+#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
+#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
+#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
+#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
+/* ensure macro params bracketed to avoid unexpected evaluations. (GA) MISRA Rule 19.10 */
+#define TEST_SET(x) (((x) << 5) & 0x03E0) /* Set Index 0->31 */
+#define TEST_WAY0 0x00000000 /* Access Way0 */
+#define TEST_WAY1 0x04000000 /* Access Way1 */
+/*** ITEST_COMMAND only */
+#define TEST_WAY2 0x08000000 /* Access Way2 */
+#define TEST_WAY3 0x0C000000 /* Access Way3 */
+/*** DTEST_COMMAND only */
+#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
+#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_LPBLACKFIN_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * defblackfin.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF535 */
+
+#ifndef _DEF_BLACKFIN_H
+#define _DEF_BLACKFIN_H
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_7)
+#endif /* _MISRA_RULES */
+
+
+#if defined(__ADSPLPBLACKFIN__)
+#warning defblackfin.h should only be included for 535 compatible chips.
+#endif
+/* Macro parameters should be enclosed in parantheses to avoid incorrect expression evaluation. MISRA Rule 19.10 */
+#define MK_BMSK_( x ) (1<<(x)) /* Make a bit mask from a bit position */
+
+/*********************************************************************************** */
+/* System Register Bits */
+/*********************************************************************************** */
+
+/*************************************************** */
+/* ASTAT register */
+/*************************************************** */
+
+#if !defined(__ADSPLPBLACKFIN__)
+/* ** Bit Positions */
+#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */
+#define ASTAT_V_COPY_P 0x00000003 /* Result of last DAG operation overflowed */
+#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */
+#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */
+#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */
+
+#else /* !__ADSPLPBLACKFIN__ */
+
+/* definitions of ASTAT bit positions for next revision of BLACKFIN */
+#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */
+#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */
+#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */
+#define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */
+#define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
+#define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0_P */
+#define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */
+#define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1_P */
+#define ASTAT_V_P 0x00000018 /* Result of last op written to data register file. */
+#define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V_P */
+#endif /* !__ADSPLPBLACKFIN__ */
+
+/* ** Masks */
+#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */
+#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */
+#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */
+#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */
+#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */
+
+#if !defined(__ADSPLPBLACKFIN__)
+
+#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */
+#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Result of last DAG operation overflowed */
+
+#else /* !__ADSPLPBLACKFIN__ */
+
+#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
+#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */
+#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */
+#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU1 operation generated a carry */
+#define ASTAT_AV0S MK_BMSK_(ASTAT_AV0S_P) /* Sticky version of ASTAT_AV0_P */
+#define ASTAT_AV1S MK_BMSK_(ASTAT_AV1S_P) /* Sticky version of ASTAT_AV1_P */
+#define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Result of last op written to data register file. */
+#define ASTAT_VS MK_BMSK_(ASTAT_VS_P) /* Sticky version of ASTAT_V_P */
+
+#endif /* !__ADSPLPBLACKFIN__ */
+
+/*************************************************** */
+/* SEQSTAT register */
+/*************************************************** */
+
+/* ** Bit Positions */
+#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
+#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
+#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
+#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
+#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
+#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
+#define SEQSTAT_OMODE0_P 0x0000000A /* Operating mode: 00 user, 01 supervisor, 1x debug */
+#define SEQSTAT_OMODE1_P 0x0000000B /* Operating mode: 00 user, 01 supervisor, 1x debug */
+#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */
+#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
+#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
+#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
+#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
+#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
+
+/* ** Masks */
+/* Exception cause */
+#define SEQSTAT_EXCAUSE ( MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
+ MK_BMSK_(SEQSTAT_EXCAUSE5_P) )
+
+/* Operating mode: 00 user, 01 supervisor, 1x debug */
+#define SEQSTAT_OMODE ( MK_BMSK_(SEQSTAT_OMODE0_P) | \
+ MK_BMSK_(SEQSTAT_OMODE1_P) )
+
+/* Pending idle mode request, set by IDLE instruction */
+#define SEQSTAT_IDLE_REQ MK_BMSK_(SEQSTAT_IDLE_REQ_P)
+
+/* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P)
+
+/* Last hw error cause */
+#define SEQSTAT_HWERRCAUSE ( MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
+ MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) )
+
+/*************************************************** */
+/* SYSCFG register */
+/*************************************************** */
+
+/* ** Bit Positions */
+#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */
+#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
+#define SYSCFG_SNEN_P 0x00000002 /* Enable self-nesting interrupts (=1) */
+
+/* ** Masks */
+#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P) /* Supervisor single step, when set it forces an exception for each instruction executed */
+#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P) /* Enable cycle counter (=1) */
+#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P) /* Enable self-nesting interrupts (=1) */
+/* Backward-compatibility for typos in prior releases */
+#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
+#define SYSCFG_CCCEN SYSCFG_CCEN
+
+
+/*********************************************************************************** */
+/* Core MMR Register Map */
+/*********************************************************************************** */
+
+/* Cache & SRAM Memory */
+#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address (Read Only) */
+#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
+#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
+#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
+#define MMR_TIMEOUT 0xFFE00010 /* Memory-Mapped Register Timeout Register */
+#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
+#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
+#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
+#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
+#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
+#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
+#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
+#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
+#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
+#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
+#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
+#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
+#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
+#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
+#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
+#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
+#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
+#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
+#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
+#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
+#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
+#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
+#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
+#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
+#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
+#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
+#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
+#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
+#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
+#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
+#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
+#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
+#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
+#define DTEST_INDEX 0xFFE00304 /* Data Test Index Register */
+#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
+#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
+#define DTEST_DATA2 0xFFE00408 /* Data Test Data Register */
+#define DTEST_DATA3 0xFFE0040C /* Data Test Data Register */
+#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
+#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
+#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
+#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cache Protection Lookaside Buffer 0 */
+#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cache Protection Lookaside Buffer 1 */
+#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cache Protection Lookaside Buffer 2 */
+#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cache Protection Lookaside Buffer 3 */
+#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cache Protection Lookaside Buffer 4 */
+#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cache Protection Lookaside Buffer 5 */
+#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cache Protection Lookaside Buffer 6 */
+#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cache Protection Lookaside Buffer 7 */
+#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cache Protection Lookaside Buffer 8 */
+#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cache Protection Lookaside Buffer 9 */
+#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cache Protection Lookaside Buffer 10 */
+#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cache Protection Lookaside Buffer 11 */
+#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cache Protection Lookaside Buffer 12 */
+#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cache Protection Lookaside Buffer 13 */
+#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cache Protection Lookaside Buffer 14 */
+#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cache Protection Lookaside Buffer 15 */
+#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
+#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
+#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
+#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
+#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
+#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
+#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
+#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
+#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
+#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
+#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
+#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
+#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
+#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
+#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
+#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
+#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
+#define ITEST_INDEX 0xFFE01304 /* Instruction Test Index Register */
+#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
+#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
+
+/* Event/Interrupt Registers */
+#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
+#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
+#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
+#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
+#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
+#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
+#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
+#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
+#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
+#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
+#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
+#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
+#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
+#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
+#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
+#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
+#define IMASK 0xFFE02104 /* Interrupt Mask Register */
+#define IPEND 0xFFE02108 /* Interrupt Pending Register */
+#define ILAT 0xFFE0210C /* Interrupt Latch Register */
+
+/* Core Timer Registers */
+#define TCNTL 0xFFE03000 /* Core Timer Control Register */
+#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
+#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
+#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
+
+/* Debug/MP/Emulation Registers */
+#define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */
+#define DBGCTL 0xFFE05004 /* Debug Control Register */
+#define DBGSTAT 0xFFE05008 /* Debug Status Register */
+#define EMUDAT 0xFFE0500C /* Emulator Data Register */
+
+/* Trace Buffer Registers */
+#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
+#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
+#define TBUF 0xFFE06100 /* Trace Buffer */
+
+/* Watch Point Control Registers */
+#define WPIACTL 0xFFE07000 /* Instruction Watch Point Control Register */
+#define WPIA0 0xFFE07040 /* Instruction Watch Point Address 0 */
+#define WPIA1 0xFFE07044 /* Instruction Watch Point Address 1 */
+#define WPIA2 0xFFE07048 /* Instruction Watch Point Address 2 */
+#define WPIA3 0xFFE0704C /* Instruction Watch Point Address 3 */
+#define WPIA4 0xFFE07050 /* Instruction Watch Point Address 4 */
+#define WPIA5 0xFFE07054 /* Instruction Watch Point Address 5 */
+#define WPIACNT0 0xFFE07080 /* Instruction Watch Point Counter 0 */
+#define WPIACNT1 0xFFE07084 /* Instruction Watch Point Counter 1 */
+#define WPIACNT2 0xFFE07088 /* Instruction Watch Point Counter 2 */
+#define WPIACNT3 0xFFE0708C /* Instruction Watch Point Counter 3 */
+#define WPIACNT4 0xFFE07090 /* Instruction Watch Point Counter 4 */
+#define WPIACNT5 0xFFE07094 /* Instruction Watch Point Counter 5 */
+#define WPDACTL 0xFFE07100 /* Data Watch Point Control Register */
+#define WPDA0 0xFFE07140 /* Data Watch Point Address 0 */
+#define WPDA1 0xFFE07144 /* Data Watch Point Address 1 */
+#define WPDACNT0 0xFFE07180 /* Data Watch Point Counter 0 */
+#define WPDACNT1 0xFFE07184 /* Data Watch Point Counter 1 */
+#define WPSTAT 0xFFE07200 /* Watch Point Status Register */
+
+/* Performance Monitor Registers */
+#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */
+#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */
+#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */
+
+
+/*********************************************************************************** */
+/* Core MMR Register Bits */
+/*********************************************************************************** */
+
+/*************************************************** */
+/* EVT registers (ILAT, IMASK, and IPEND). */
+/*************************************************** */
+
+/* ** Bit Positions */
+#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
+#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
+#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
+#define EVT_EVX_P 0x00000003 /* Exception bit position */
+#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
+#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
+#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
+#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
+#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
+#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
+#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
+#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
+#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
+#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
+#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
+#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
+
+/* ** Masks */
+#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
+#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
+#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
+#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
+#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
+#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
+#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
+#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
+#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
+#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
+#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
+#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
+#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
+#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
+#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
+#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
+
+/*************************************************** */
+/* DMEM_CONTROL register */
+/*************************************************** */
+/* ** Bit Positions */
+#define ENDM_P 0x00 /* Enable Data Memory L1 */
+#define DMCTL_ENDM_P ENDM_P /* "" (older define) */
+#define ENDCPLB_P 0x01 /* Enable DCPLBS */
+#define DMCTL_ENDCPLB_P ENDCPLB_P /* "" (older define) */
+#define DMC0_P 0x02 /* L1 Data Memory Configure bit 0 */
+#define DMCTL_DMC0_P DMC0_P /* "" (older define) */
+#define DMC1_P 0x03 /* L1 Data Memory Configure bit 1 */
+#define DMCTL_DMC1_P DMC1_P /* "" (older define) */
+
+/* ** Masks */
+#define ENDM MK_BMSK_(DMCTL_ENDM_P) /* Enable Data Memory L1 */
+
+/* Bank A set as SRAM, Bank B set as SRAM */
+#define ASRAM_BSRAM 0x00000000
+
+/* Enable DCPLB */
+#define ENDCPLB MK_BMSK_(DMCTL_ENDCPLB_P)
+
+/* Bank A set as CACHE, Bank B set as SRAM */
+#define ACACHE_BSRAM 0x00000008
+/* Bank A set as CACHE, Bank B set as CACHE */
+#define ACACHE_BCACHE 0x0000000C
+#define DCBS 0x00000010 /* If HIGHBIT is 1, select L1 data memory B */
+ /* If HIGHBIT is 0, select L1 data memory A */
+ /* If LOWBIT is 1, select L1 memory bank B */
+ /* If LOWBIT is 0, select L1 memory bank A */
+
+/* IMEM_CONTROL Masks */
+#define ENIM 0x00000001 /* Enable L1 Code Memory */
+#define ENICPLB 0x00000002 /* Enable ICPLB */
+#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */
+
+/* TCNTL Masks */
+#define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */
+#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD 0x00000004 /* Timer auto reload */
+#define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
+
+/* TCNTL Bit Positions */
+#define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */
+#define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD_P 0x00000002 /* Timer auto reload */
+#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
+
+/* DCPLB_DATA and ICPLB_DATA Masks */
+#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
+#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
+ /* only applies to L1 data memory */
+#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
+#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
+#define CPLB_DA0ACC 0x00000040 /* 0=access allowed from either DAG, 1=access from DAG0 only */
+ /* only applies in L1 data memory controller */
+#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
+ /* only applies in L1 data memory controller */
+#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
+#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
+ /* only applies in L1 data memory controller in cache mode */
+#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
+#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
+#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
+#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
+
+
+/* DCPLB_DATA and ICPLB_DATA Bit Positions */
+#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
+#define CPLB_USER_RD_P 0x00000002 /* */
+
+/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
+#if !defined(__ADSPLPBLACKFIN__)
+#define ASTAT_AC0_P ASTAT_AC0_COPY_P
+#define ASTAT_AC_P ASTAT_AC0_COPY_P
+#define ASTAT_AV0_P ASTAT_V_COPY_P
+#define ASTAT_AC MK_BMSK_(ASTAT_AC0_COPY_P)
+#define ASTAT_AV1 MK_BMSK_(ASTAT_V_COPY_P)
+#endif
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _DEF_BLACKFIN_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+** Include appropriate header file for platform.
+** Copyright (C) 2008 Analog Devices, Inc.
+*/
+
+#ifndef __ADI_PLATFORM_H
+#define __ADI_PLATFORM_H
+
+#ifdef __ASSEMBLY__
+
+#if defined (__ADSPBF531__)
+#include <cdefBF531.h>
+#elif defined (__ADSPBF532__)
+#include <cdefBF532.h>
+#elif defined (__ADSPBF533__)
+#include <cdefBF533.h>
+#elif defined (__ADSPBF534__)
+#include <cdefBF534.h>
+#elif defined (__ADSPBF535__)
+#include <cdefBF535.h>
+#elif defined (__ADSPBF536__)
+#include <cdefBF536.h>
+#elif defined (__ADSPBF537__)
+#include <cdefBF537.h>
+#elif defined (__ADSPBF538__)
+#include <cdefBF538.h>
+#elif defined (__ADSPBF539__)
+#include <cdefBF539.h>
+#elif defined (__ADSPBF561__)
+#include <cdefBF561.h>
+#elif defined (__AD6531__)
+#include <cdefAD6531.h>
+#elif defined (__AD6532__)
+#include <cdefAD6532.h>
+#elif defined (__AD6723__)
+#include <cdefAD6723.h>
+#elif defined (__AD6900__)
+#include <cdefAD6900.h>
+#elif defined (__AD6901__)
+#include <cdefAD6901.h>
+#elif defined (__AD6902__)
+#include <cdefAD6902.h>
+#elif defined (__AD6903__)
+#include <cdefAD6903.h>
+#elif defined (__AD6904__)
+#include <cdefAD6904.h>
+#elif defined (__ADSPBF522__)
+#include <cdefBF522.h>
+#elif defined (__ADSPBF525__)
+#include <cdefBF525.h>
+#elif defined (__ADSPBF527__)
+#include <cdefBF527.h>
+#elif defined (__ADSPBF542__) || defined (__ADSPBF541__)
+#include <cdefBF542.h>
+#elif defined (__ADSPBF544__)
+#include <cdefBF544.h>
+#elif defined (__ADSPBF547__)
+#include <cdefBF547.h>
+#elif defined (__ADSPBF548__)
+#include <cdefBF548.h>
+#elif defined (__ADSPBF549__)
+#include <cdefBF549.h>
+#else
+#error Processor Type Not Supported
+#endif
+
+
+#else
+
+#if defined (__ADSPBF531__)
+#include <defBF531.h>
+#elif defined (__ADSPBF532__)
+#include <defBF532.h>
+#elif defined (__ADSPBF533__)
+#include <defBF533.h>
+#elif defined (__ADSPBF534__)
+#include <defBF534.h>
+#elif defined (__ADSPBF535__)
+#include <defBF535.h>
+#elif defined (__ADSPBF536__)
+#include <defBF536.h>
+#elif defined (__ADSPBF537__)
+#include <defBF537.h>
+#elif defined (__ADSPBF538__)
+#include <defBF538.h>
+#elif defined (__ADSPBF539__)
+#include <defBF539.h>
+#elif defined (__ADSPBF561__)
+#include <defBF561.h>
+#elif defined (__AD6531__)
+#include <defAD6531.h>
+#elif defined (__AD6532__)
+#include <defAD6532.h>
+#elif defined (__AD6723__)
+#include <defAD6723.h>
+#elif defined (__AD6900__)
+#include <defAD6900.h>
+#elif defined (__AD6901__)
+#include <defAD6901.h>
+#elif defined (__AD6902__)
+#include <defAD6902.h>
+#elif defined (__AD6903__)
+#include <defAD6903.h>
+#elif defined (__AD6904__)
+#include <defAD6904.h>
+#elif defined (__ADSPBF522__)
+#include <defBF522.h>
+#elif defined (__ADSPBF525__)
+#include <defBF525.h>
+#elif defined (__ADSPBF527__)
+#include <defBF527.h>
+#elif defined (__ADSPBF542__) || defined (__ADSPBF541__)
+#include <defBF542.h>
+#elif defined (__ADSPBF544__)
+#include <defBF544.h>
+#elif defined (__ADSPBF547__)
+#include <defBF547.h>
+#elif defined (__ADSPBF548__)
+#include <defBF548.h>
+#elif defined (__ADSPBF549__)
+#include <defBF549.h>
+
+#else
+#error Processor Type Not Supported
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __INC_BLACKFIN__ */
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * anomaly_macros_rtl.h : $Revision$
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ * This file defines macros used within the run-time libraries to enable
+ * certain anomaly workarounds for the appropriate chips and silicon
+ * revisions. Certain macros are defined for silicon-revision none - this
+ * is to ensure behaviour is unchanged from libraries supplied with
+ * earlier tools versions, where a small number of anomaly workarounds
+ * were applied in all library flavours. __FORCE_LEGACY_WORKAROUNDS__
+ * is defined in this case.
+ *
+ * This file defines macros for a subset of all anomalies that may impact
+ * the run-time libraries.
+ *
+ ************************************************************************/
+
+
+#if !defined(__SILICON_REVISION__)
+#define __FORCE_LEGACY_WORKAROUNDS__
+#endif
+
+
+/* 05-00-0096 - PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC
+**
+** ADSP-BF531/2/3 - revs 0.0-0.1,
+** ADSP-BF561 - revs 0.0-0.1 (not supported in VDSP++ 4.0)
+**
+*/
+#define WA_05000096 \
+ ((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__) || \
+ defined(__ADSPBF561__)) && \
+ ((defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x1)) || \
+ defined(__FORCE_LEGACY_WORKAROUNDS__)))
+
+
+/* 05-00-0109 - Reserved bits in SYSCFG register not set at power on
+**
+** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
+** ADSP-BF561 - revs 0.0-0.2 (fixed 0.3. 0.0, 0.1 not supported in VDSP++ 4.0)
+**
+** Changes to start code.
+*/
+#define WA_05000109 \
+ ((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__) || \
+ defined(__ADSPBF561__)) && \
+ ((defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
+ defined(__FORCE_LEGACY_WORKAROUNDS__)))
+
+
+/* 05-00-0123 - DTEST_COMMAND initiated memory access may be incorrect if
+** data cache or DMA is active.
+**
+** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3)
+** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0)
+*/
+#define WA_05000123 \
+ ((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__) || \
+ defined(__ADSPBF561__)) && \
+ ((defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
+ defined(__FORCE_LEGACY_WORKAROUNDS__)))
+
+
+/* 05-00-0125 - Erroneous exception when enabling cache
+**
+** ADSP-BF531/2/3 - revs 0.1-0.2 (fixed 0.3)
+** ADSP-BF561 - revs 0.0-0.2 (0.0 and 0.1 not supported in VDSP++ 4.0)
+**
+*/
+#define WA_05000125 \
+ ((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__) || \
+ defined(__ADSPBF561__)) && \
+ ((defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
+ defined(__FORCE_LEGACY_WORKAROUNDS__)))
+
+
+/* 05-00-0137 - DMEM_CONTROL<12> is not set on Reset
+**
+** ADSP-BF531/2/3 - revs 0.0-0.2 (fixed 0.3)
+**
+** Changes to start code.
+**
+*/
+#define WA_05000137 \
+ ((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__)) && \
+ ((defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x2)) || \
+ defined(__FORCE_LEGACY_WORKAROUNDS__)))
+
+
+/* 05-00-0158 - "Boot fails when data cache enabled: Data from a Data Cache
+** fill can be corrupted after or during instruction DMA if certain core
+** stalls exist"
+**
+** Impacted:
+** BF533/3/1 : 0.0-0.4 (fixed 0.5)
+**
+** The workaround we have only works for si-revisions >= 0.3. No workaround for
+** ealier revisions.
+*/
+#define WA_05000158 \
+ ((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__)) && \
+ ((defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || \
+ (__SILICON_REVISION__ >= 0x3 && \
+ __SILICON_REVISION__ < 0x5))) || \
+ defined(__FORCE_LEGACY_WORKAROUNDS__)))
+
+
+/* 05-00-0204 - "Incorrect data read with write-through cache and
+** allocate cache lines on reads only mode.
+**
+** This problem is cache related with high speed clocks. It apparently does
+** not impact BF531 and BF532 because they cannot run at high enough clock
+** to cause the anomaly. We build libs for BF532 though so that means we will
+** need to do the workaround for BF532 and BF531 also.
+**
+** Also the 0.3 to 0.4 revision is not an inflexion for libs BF532 and BF561.
+** This means a RT check may be required to avoid doing the WA for 0.4.
+**
+** Impacted:
+** BF533 - 0.0-0.3 (fixed 0.4)
+** BF534 - 0.0 (fixed 0.1)
+** BF536 - 0.0 (fixed 0.1)
+** BF537 - 0.0 (fixed 0.1)
+** BF538 - 0.0 (fixed 0.1)
+** BF539 - 0.0 (fixed 0.1)
+** BF561 - 0.0-0.3 (fixed 0.4)
+*/
+#if defined(__ADI_LIB_BUILD__)
+# define __BUILDBF53123 1 /* building one single library for BF531/2/3 */
+#else
+# define __BUILDBF53123 0
+#endif
+
+#define WA_05000204 \
+ ((((__BUILDBF53123==1 && \
+ (defined(__ADSPBF531__) || defined(__ADSPBF532__))) || \
+ (defined(__ADSPBF533__) || defined(__ADSPBF561__))) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ <= 0x3))) || \
+ ((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \
+ defined(__ADSPBF537__) || defined(__ADSPBF538__) || \
+ defined(__ADSPBF539__)) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0))))
+
+#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__) || defined(__ADSPBF561__)) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x3)))
+/* check at RT for 0.4 revs when doing 204 workaround */
+# define WA_05000204_CHECK_AVOID_FOR_REV <=3
+#elif ((defined(__ADSPBF534__) || defined(__ADSPBF536__) || \
+ defined(__ADSPBF537__) || defined(__ADSPBF538__) || \
+ defined(__ADSPBF539__)) && \
+ (defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || __SILICON_REVISION__ == 0x0)))
+/* check at RT for 0.4 revs when doing 204 workaround */
+# define WA_05000204_CHECK_AVOID_FOR_REV <1
+#else
+/* do not check at RT for 0.4 revs when doing 204 workaround */
+#endif
+
+/* 05-00-0258 - "Instruction Cache is corrupted when bit 9 and 12 of
+ * the ICPLB Data registers differ"
+ *
+ * When bit 9 and bit 12 of the ICPLB Data MMR differ, the cache may
+ * not update properly. For example, for a particular cache line,
+ * the cache tag may be valid while the contents of that cache line
+ * are not present in the cache.
+ *
+ * Impacted:
+ *
+ * BF531/2/3 - 0.0-0.4 (fixed 0.5)
+ * BF534/6/7/8/9 - 0.0-0.2 (fixed 0.3)
+ * BF561 - 0.0-0.4 (fixed 0.5)
+ * BF535/AD6532/AD6900 - all revs
+ */
+
+#define WA_05000258 \
+ defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || \
+ !defined(__ADSPLPBLACKFIN__) || \
+ ((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__)) && \
+ (__SILICON_REVISION__ <= 0x4)) || \
+ ((defined(__ADSPBF534__) || \
+ defined(__ADSPBF536__) || \
+ defined(__ADSPBF537__) || \
+ defined(__ADSPBF538__) || \
+ defined(__ADSPBF539__)) && \
+ (__SILICON_REVISION__ <= 0x2)) || \
+ ((defined(__ADSPBF561__)) && \
+ (__SILICON_REVISION__ <= 0x4)) || \
+ ((defined(__ADSPBF561__)) && \
+ (__SILICON_REVISION__ < 0x1)))
+
+/* 05-00-0259 - "Non-deterministic ICPLB descriptors delivered to
+ * hardware". Whenever ICPLBs are disabled via an MMR write, immediately
+ * follow this write with a CSYNC, and locate the MMR write and CSYNC
+ * within the same aligned 64 bit word.
+ *
+ * This problem impacts all revisions of Blackfins.
+ */
+
+#define WA_05000259 \
+ (defined(__ADSPBLACKFIN__) && defined(__SILICON_REVISION__))
+
+
+/* 05-00-0261 - "DCPLB_FAULT_ADDR MMR may be corrupted".
+ * The DCPLB_FAULT_ADDR MMR may contain the fault address of a
+ * aborted memory access which generated both a protection exception
+ * and a stall.
+ *
+ * We work around this by initially ignoring a DCPLB miss exception
+ * on the assumption that the faulting address might be invalid.
+ * We return without servicing. The exception will be raised
+ * again when the faulting instruction is re-executed. The fault
+ * address is correct this time round so the miss exception can
+ * be serviced as normal. The only complication is we have to
+ * ensure that we are about to service the same miss rather than
+ * a miss raised within a higher-priority interrupt handler, where
+ * the fault address could again be invalid. We therefore record
+ * the last seen RETX and only service an exception when RETX and
+ * the last seen RETX are equal.
+ *
+ * This problem impacts:
+ * BF531/2/3 - rev 0.0-0.4 (fixed 0.5)
+ * BF534/6/7/8/9 - rev 0.0-0.2 (fixed 0.3)
+ * BF561 - rev 0.0-0.4 (fixed 0.5)
+ *
+ */
+
+#define WA_05000261 \
+ defined(__SILICON_REVISION__) && \
+ (__SILICON_REVISION__ == 0xffff || \
+ ((defined(__ADSPBF531__) || \
+ defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__)) && \
+ (__SILICON_REVISION__ <= 0x4)) || \
+ ((defined(__ADSPBF534__) || \
+ defined(__ADSPBF536__) || \
+ defined(__ADSPBF537__) || \
+ defined(__ADSPBF538__) || \
+ defined(__ADSPBF539__)) && \
+ (__SILICON_REVISION__ <= 0x2)) || \
+ ((defined(__ADSPBF561__)) && \
+ (__SILICON_REVISION__ <= 0x4)) || \
+ ((defined(__ADSPBF561__)) && \
+ (__SILICON_REVISION__ < 0x1)))
+
+/* 05-00-0229 - "SPI Slave Boot Mode Modifies Registers".
+ * When the SPI slave boot completes, the final DMA IRQ is cleared
+ * but the DMA5_CONFIG and SPI_CTL registers are not reset to their
+ * default states.
+ *
+ * We work around this by resetting the registers to their default
+ * values at the beginning of the CRT. The only issue would be when
+ * users boot from flash and make use of the DMA or serial port.
+ * In this case, users would need to modify the CRT.
+ *
+ * This problem impacts all revisions of ADSP-BF531/2/3/8/9
+ */
+
+#define WA_05000229 \
+ (defined(__ADSPBLACKFIN__) && defined (__SILICON_REVISION__) && \
+ (defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
+ defined(__ADSPBF533__) || defined(__ADSPBF538__) || \
+ defined(__ADSPBF539__)))
+
+/* 05-00-0283 - "A system MMR write is stalled indefinitely when killed in a
+ * particular stage".
+ *
+ * Where an interrupt occurs killing a stalled system MMR write, and the ISR
+ * executes an SSYNC, execution execution may stall indefinitely".
+ *
+ * The workaround is to execute a mispredicted jump over a dummy MMR read,
+ * thus killing the read. Also to avoid a system MMR write in two slots
+ * after a not predicted conditional jump.
+ *
+ * This problem impacts:
+ * BF531/2/3 - all revs
+ * BF534/6/7/8/9 - all revs
+ * BF561/6 - all revs
+ */
+
+#define WA_05000283 \
+ defined(__ADSPLPBLACKFIN__) && defined(__SILICON_REVISION__)
+
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * excause.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/*
+** Definitions of constants for the four user-level bits in EXCAUSE,
+** the field from SYSSTAT that is set when the EXCPT instruction is
+** invoked.
+*/
+
+#ifndef _EXCAUSE_H
+#define _EXCAUSE_H
+
+/*
+** Value 0x0 - exit program. (halt)
+** R0 => exit status.
+*/
+
+#define EX_EXIT_PROG 0x0
+
+/*
+** Value 0x1 - abnormal exit (abort)
+*/
+
+#define EX_ABORT_PROG 0x1
+
+/*
+** Value 0x2 - invoke system service.
+** R0 => command.
+** R1 => first arg
+** R2 => second arg
+*/
+
+#define EX_SYS_REQ 0x2
+
+/*
+** Available commands:
+*/
+
+#define EX_SYSREQ_NONE 0x00 /* Do nothing */
+#define EX_SYSREQ_REG_ISR 0x01 /* Register an interrupt handler.
+ R1==EVT entry, R2==func ptr
+ Returns previous entry in R0. */
+#define EX_SYSREQ_RAISE_INT 0x02 /* Cause an interrupt
+ R1 = int number */
+/*
+** Values 0x3 to 0x4 currently undefined.
+*/
+
+/*
+** Value 0x5 - File I/O
+** R0 => first arg
+** R1 => second arg
+** R2 => third arg
+** R4 => command
+** result => R0
+*/
+
+#define EX_FILE_IO 0x5
+
+/*
+** Available commands:
+** XXX stdout/stderr are handled separately for writing.
+*/
+
+#define EX_FILEIO_OPEN 0x00 /* R0 => dev, R1=> path, R2=>mode */
+#define EX_FILEIO_CLOSE 0x01 /* R0=> fid */
+#define EX_FILEIO_WRITE 0x02 /* R0=>fid, R1=>data, R2=>length */
+#define EX_FILEIO_READ 0x03 /* R0=>fid, R1=>data, R2=>length */
+#define EX_FILEIO_SEEK 0x04 /* R0=>fid, R1=>offset, R2=>mode */
+#define EX_FILEIO_DUP 0x05 /* R0=>fid */
+
+/*
+** Values 0x6 to 0xF currently undefined.
+*/
+
+#endif /* _EXCAUSE_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#pragma once
+#ifndef __NO_BUILTIN
+#pragma system_header /* exception.h */
+#endif
+/************************************************************************
+ *
+ * exception.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifndef _EXCEPTION_H
+#define _EXCEPTION_H
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_5_7)
+#pragma diag(suppress:misra_rule_6_3)
+#pragma diag(suppress:misra_rule_19_4)
+#pragma diag(suppress:misra_rule_19_7)
+#pragma diag(suppress:misra_rule_19_10)
+#pragma diag(suppress:misra_rule_19_13)
+#endif /* _MISRA_RULES */
+
+
+
+/*
+** Definitions for user-friendly interrupt handling.
+*/
+
+/*
+** Memory-Mapped Registers (MMRs) - these record what causes address
+** exceptions.
+*/
+
+#define EX_DATA_FAULT_STATUS 0xFFE00008
+#define EX_DATA_FAULT_ADDR 0xFFE0000C
+#define EX_CODE_FAULT_STATUS 0xFFE01008
+#define EX_CODE_FAULT_ADDR 0xFFE0100C
+
+/*
+** Event Vector Table
+*/
+
+#define EX_EVENT_VECTOR_TABLE 0xFFE02000
+
+/*
+** Meaning of the various bits in EXCAUSE field in SEQSTAT register.
+*/
+
+#define EX_BITS 0x3F /* All EXCAUSE bits */
+#define EX_TYPE 0x30 /* The bits which define the type */
+#define EX_DEBUG 0x10 /* If set, is a debug exception type */
+#define EX_SYS 0x20 /* If set, is a system exception type */
+ /* If neither set, is from EXCPT instr */
+
+#define EX_IS_DEBUG_EXCEPTION(E) (((E)&EX_TYPE)==EX_DEBUG)
+#define EX_IS_SYSTEM_EXCEPTION(E) (((E)&EX_TYPE)==EX_SYS)
+#define EX_IS_USER_EXCEPTION(E) (((E)&EX_TYPE)==0)
+
+/*
+** Service exceptions continue from the instruction after the one
+** that raised the exception.
+** Error exceptions restart the instruction that raised the exception.
+*/
+
+#define EX_IS_SERVICE_EXCEPTION(E) (!EX_IS_SYSTEM_EXCEPTION(E))
+#define EX_IS_ERROR_EXCEPTION(E) (EX_IS_SYSTEM_EXCEPTION(E))
+
+#define EX_DB_SINGLE_STEP 0x10 /* Processor is single-stepping */
+#define EX_DB_EMTRCOVRFLW 0x11 /* Emulation Trace buffer overflowed */
+
+#define EX_SYS_UNDEFINSTR 0x21 /* Undefined instruction */
+#define EX_SYS_ILLINSTRC 0x22 /* Illegal instruction combination */
+#define EX_SYS_DCPLBPROT 0x23 /* Data CPLB Protection violation */
+#define EX_SYS_DALIGN 0x24 /* Data access misaligned address violation */
+#define EX_SYS_UNRECEVT 0x25 /* Unrecoverable event */
+#define EX_SYS_DCPLBMISS 0x26 /* Data access CPLB Miss */
+#define EX_SYS_DCPLBMHIT 0x27 /* Data access CPLB Multiple Hits */
+#define EX_SYS_EMWATCHPT 0x28 /* Emulation watch point match */
+#define EX_SYS_CACCESSEX 0x29 /* Code fetch access exception */
+#define EX_SYS_CALIGN 0x2A /* Attempted misaligned instr cache fetch */
+#define EX_SYS_CCPLBPROT 0x2B /* Code fetch CPLB Protection */
+#define EX_SYS_CCPLBMISS 0x2C /* CPLB miss on an instruction fetch */
+#define EX_SYS_CCPLBMHIT 0x2D /* Code fetch CPLB Multiple Hits */
+#define EX_SYS_ILLUSESUP 0x2E /* Illegal use of Supervisor Resource */
+
+/*
+** Meaning of the various bits in HWERRCAUSE in SEQSTAT
+*/
+
+#define EX_HWBITS (0x1F<<14) /* bits 18:14 */
+
+#if !defined(__ADSPLPBLACKFIN__)
+#define EX_HW_NOMEM1 (0x16<<14)
+#define EX_HW_NOMEM2 (0x17<<14)
+#else
+#define EX_HW_SYSMMR (0x02<<14)
+#define EX_HW_EXTMEM (0x03<<14)
+#endif
+#define EX_HW_DMAHIT (0x01<<14)
+#define EX_HW_PERFMON (0x12<<14)
+#define EX_HW_RAISE (0x18<<14)
+
+/*
+** Meaning of the bits in DATA_FAULT_STATUS and CODE_FAULT_STATUS
+*/
+
+#define EX_DATA_FAULT_ILLADDR (1<<19) /* non-existent memory */
+#define EX_DATA_FAULT_DAG (1<<18) /* 0=>DAG0, 1=>DAG1 */
+#define EX_DATA_FAULT_USERSUPV (1<<17) /* 0=>user mode, 1=> supervisor */
+#define EX_DATA_FAULT_READWRITE (1<<16) /* 0=>read, 1=>write */
+#define EX_DATA_FAULT_CPLB 0xFFFF /* 0=>CPLB0, 1=>CPLB1, etc */
+
+#define EX_CODE_FAULT_ILLADDR (1<<19) /* non-existent memory */
+#define EX_CODE_FAULT_USERSUPV (1<<17) /* 0=>user mode, 1=> supervisor */
+#define EX_CODE_FAULT_CPLB 0xFFFF /* 0=>CPLB0, 1=>CPLB1, etc */
+
+/*
+** The kinds of interrupt that can occur. These are also the
+** indices into the Event Vector Table.
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ik_err=-1,
+ ik_emulation,
+ ik_reset,
+ ik_nmi,
+ ik_exception,
+ ik_global_int_enable,
+ ik_hardware_err,
+ ik_timer,
+ ik_ivg7,
+ ik_ivg8,
+ ik_ivg9,
+ ik_ivg10,
+ ik_ivg11,
+ ik_ivg12,
+ ik_ivg13,
+ ik_ivg14,
+ ik_ivg15,
+ num_interrupt_kind
+} interrupt_kind;
+
+/*
+** Structure for recording details of an exception or interrupt
+** that has occurred.
+*/
+
+typedef struct {
+ interrupt_kind kind; /* whether interrupt, exception, etc. */
+ int value; /* interrupt number, exception type, etc. */
+ void *pc; /* PC at point where exception occurred */
+ void *addr; /* if an address faulted, which one. */
+ unsigned status; /* if an address faulted, why. */
+} interrupt_info;
+
+/*
+** Macro for defining an interrupt routine
+*/
+
+typedef void (*ex_handler_fn)();
+
+#define EX_HANDLER(KIND,NAME) \
+_Pragma(#KIND) \
+void NAME ()
+
+#define EX_HANDLER_PROTO(KIND, NAME) EX_HANDLER(KIND, NAME)
+
+#define EX_INTERRUPT_HANDLER(NAME) EX_HANDLER(interrupt,NAME)
+#define EX_EXCEPTION_HANDLER(NAME) EX_HANDLER(exception,NAME)
+#define EX_NMI_HANDLER(NAME) EX_HANDLER(nmi,NAME)
+#define EX_REENTRANT_HANDLER(NAME) \
+_Pragma("interrupt_reentrant") \
+EX_HANDLER(interrupt,NAME)
+
+/*
+** A convenience function for setting up the interrupt_info contents.
+** Must be called from immediately with the interrupt handler.
+*/
+
+void get_interrupt_info(interrupt_kind int_kind, interrupt_info *int_info);
+
+/*
+** Diagnostics function for reporting unexpected events.
+*/
+
+void _ex_report_event(interrupt_info *int_info);
+
+/*
+** Register an interrupt handler within the EVT.
+** Return previous value if there was one.
+*/
+ex_handler_fn register_handler(interrupt_kind int_kind, ex_handler_fn handler);
+
+/*
+** Some magic values for registering default and null handlers.
+*/
+
+#define EX_INT_DEFAULT ((ex_handler_fn)-1)
+#define EX_INT_IGNORE ((ex_handler_fn)0)
+
+/*
+** Extended function to register an interrupt handler within the EVT.
+** Returns the old handler.
+**
+** If enabled == EX_INT_ALWAYS_ENABLE, install fn (if fn != EX_INT_IGNORE
+** and fn != EX_INT_DISABLE), and then enable the interrupt in IMASK then
+** return
+**
+** If fn == EX_INT_IGNORE, disable the interrupt
+** If fn == EX_INT_DEFAULT, delete the handler entry in the EVT and disable
+** the interrupt in IMASK
+** Otherwise, install the new interrupt handler. Then,
+** If enabled == EX_INT_DISABLE, disable the interrupt in IMASK
+** If enabled == EX_INT_ENABLE, enable the interrupt in IMASK
+** otherwise leave the interrupt status alone.
+*/
+ex_handler_fn register_handler_ex(interrupt_kind kind, ex_handler_fn fn,
+ int enable);
+
+/* Constants for the enabled parameter of register_handler_ex */
+#define EX_INT_DISABLE 0
+#define EX_INT_ENABLE 1
+#define EX_INT_KEEP_IMASK -1
+#define EX_INT_ALWAYS_ENABLE 2
+
+/*
+** Allow the user to raise exceptions from C.
+*/
+
+int raise_interrupt(interrupt_kind kind, int which,
+ int cmd, int arg1, int arg2);
+
+#ifdef __cplusplus
+ } /* extern "C" */
+#endif
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _EXCEPTION_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#pragma once
+#ifndef __NO_BUILTIN
+#pragma system_header /* sys/mc_typedef.h */
+#endif
+/************************************************************************
+ *
+ * sys/mc_typedef.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+/* Define testset_t. */
+
+#ifndef _SYS_MC_TYPEDEF_H
+#define _SYS_MC_TYPEDEF_H
+
+#if !defined(__ADSPLPBLACKFIN__)
+typedef volatile unsigned char testset_t;
+#elif defined(__WORKAROUND_TESTSET_ALIGN) /* require 32-bit aligned address */
+typedef volatile unsigned int testset_t;
+#else
+typedef volatile unsigned short testset_t;
+#endif
+
+#endif /* _SYS_MC_TYPEDEF_H */
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#ifndef _PLATFORM_H
+#define _PLATFORM_H
+/* Generic Wrapper for platform specific header file.
+ Copyright (C) 2008 Analog Devices, Inc.
+ */
+#include <sys/_adi_platform.h>
+#endif
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/************************************************************************
+ *
+ * pll.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ************************************************************************/
+
+#ifdef __ASSEMBLY__
+#pragma once
+#pragma system_header
+#endif
+
+#ifndef _PLL_H
+#define _PLL_H
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_6_3)
+#endif /* _MISRA_RULES */
+
+#define NO_STARTUP_SET 0
+#define MAX_IN_STARTUP 1
+
+#ifdef __ASSEMBLY__
+
+enum clkctrl_t {
+ /* no modification of PLL rates in CRT startup - default */
+ no_startup_set=NO_STARTUP_SET,
+
+ /* CRT startup sets PLL rates to suitable maximum values */
+ max_in_startup=MAX_IN_STARTUP
+};
+
+/*
+** Define __clk_ctrl to 1 to cause startup to set PLL rates for maximum
+** speed performance rates. The default version defined in the runtime-
+** libraries defines __clk_ctrl to 0 which disables the feature.
+*/
+extern enum clkctrl_t __clk_ctrl;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ADSPLPBLACKFIN__)
+
+/* Sets SSEL and CSEL bits in PLL_DIV to passed values.
+** Returns -1 on failure.
+*/
+int pll_set_system_clocks(int _csel, int _ssel);
+
+/*
+** Sets MSEL and DF bits in PLL_CTL and LOCKCNT in PLL_LOCKCNT.
+** Returns -1 on failure.
+*/
+int pll_set_system_vco(int _msel, int _df, int _lockcnt);
+
+#endif /* __ADSPLPBLACKFIN__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _PLL_H */
+
--- /dev/null
+/*
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/* This file must be used with compiler version 8.0.1.5 */
+
+#ifdef __VERSIONNUM__
+#if __VERSIONNUM__ != 0x08000105
+#error The compiler version does not match the version of the sysreg.h include
+#endif
+#endif
+
+/************************************************************************
+ *
+ * sysreg.h
+ *
+ * Copyright (C) 2008 Analog Devices, Inc.
+ *
+ ***********************************************************************/
+
+#pragma once
+#ifndef __NO_BUILTIN
+#pragma system_header /* sysreg.h */
+#endif
+
+/* sysreg definitions for use in sysreg_read and sysreg_write calls. */
+
+#ifndef _SYSREG_H
+#define _SYSREG_H
+
+#ifdef _MISRA_RULES
+#pragma diag(push)
+#pragma diag(suppress:misra_rule_2_4)
+#pragma diag(suppress:misra_rule_6_3)
+#pragma diag(suppress:misra_rule_19_10)
+#endif /* _MISRA_RULES */
+
+enum {
+ /* the following can be used in word-sized sysreg reads and writes */
+ reg_I0,
+ reg_I1,
+ reg_I2,
+ reg_I3,
+ reg_M0,
+ reg_M1,
+ reg_M2,
+ reg_M3,
+ reg_B0,
+ reg_B1,
+ reg_B2,
+ reg_B3,
+ reg_L0,
+ reg_L1,
+ reg_L2,
+ reg_L3,
+ reg_LC0,
+ reg_LC1,
+ reg_LT0,
+ reg_LT1,
+ reg_LB0,
+ reg_LB1,
+ reg_RETS,
+ reg_RETI,
+ reg_RETX,
+ reg_RETN,
+ reg_RETE,
+ reg_SEQSTAT,
+ reg_SYSCFG,
+ reg_CYCLES,
+ reg_CYCLES2,
+ reg_A0W,
+ reg_A0X,
+ reg_A1W,
+ reg_A1X,
+ reg_FP,
+ reg_SP,
+ reg_ASTAT,
+
+ /* the following can be used in double-word sysreg reads and writes */
+ reg_A0,
+ reg_A1,
+ __num_SysRegs
+};
+
+#define STACKPOINTER reg_SP
+#define FRAMEPOINTER reg_FP
+
+#ifdef _MISRA_RULES
+#pragma diag(pop)
+#endif /* _MISRA_RULES */
+
+#endif /* _SYSREG_H */
static inline int
do_syscall (int reason, void *arg)
{
- int result;
- asm volatile ("[--sp] = %1; [--sp] = %2; \
- r1 = [sp++]; r0 = [sp++]; \
- raise 0; %0 = r0;"
- : "=r" (result)
- : "r" (reason), "r" (arg)
- : "R0", "R1", "memory", "cc");
+ register int r asm ("P0") = reason;
+ register void *a asm ("R0") = arg;
+ register int result asm ("R0");
+ asm volatile ("excpt 0;" : "=r" (result) : "a" (r), "r" (a) : "memory", "CC");
return result;
}
;;
strongarm-*-*)
;;
+ bfin-*-*)
+ ;;
cris-*-* | crisv32-*-*)
;;
d10v*)
;;
strongarm-*-*)
;;
+ bfin-*-*)
+ ;;
cris-*-* | crisv32-*-*)
;;
d10v*)
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