drm/i915/psr: Make MASK_DISP_REG_WRITE reserved in PSR_MASK for ICL

ICL spec states that this bit is now reserved.

Bspec: 7722

v2(Dhinakaran and Jani):
- instead of remove bit in gen11 now only setting if if gen < 11
- changed commit title

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181003205031.32474-2-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a71c507..aff6f67 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4195,7 +4195,7 @@ enum {
 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
 #define   EDP_PSR_DEBUG_MASK_HPD               (1 << 25)
-#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1 << 16) /* Reserved in ICL+ */
 #define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1 << 15) /* SKL+ */
 
 #define EDP_PSR2_CTL                   _MMIO(0x6f900)
@@ -4232,7 +4232,7 @@ enum {
 #define  PSR_EVENT_FRONT_BUFFER_MODIFY         (1 << 9)
 #define  PSR_EVENT_WD_TIMER_EXPIRE             (1 << 8)
 #define  PSR_EVENT_PIPE_REGISTERS_UPDATE       (1 << 6)
-#define  PSR_EVENT_REGISTER_UPDATE             (1 << 5)
+#define  PSR_EVENT_REGISTER_UPDATE             (1 << 5) /* Reserved in ICL+ */
 #define  PSR_EVENT_HDCP_ENABLE                 (1 << 4)
 #define  PSR_EVENT_KVMR_SESSION_ENABLE         (1 << 3)
 #define  PSR_EVENT_VBI_ENABLE                  (1 << 2)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 102da7a..5006b30 100644 (file)
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -563,6 +563,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+       u32 mask;
 
        /* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
         * use hardcoded values PSR AUX transactions
@@ -588,12 +589,15 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
         * runtime_pm besides preventing  other hw tracking issues now we
         * can rely on frontbuffer tracking.
         */
-       I915_WRITE(EDP_PSR_DEBUG,
-                  EDP_PSR_DEBUG_MASK_MEMUP |
-                  EDP_PSR_DEBUG_MASK_HPD |
-                  EDP_PSR_DEBUG_MASK_LPSP |
-                  EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
-                  EDP_PSR_DEBUG_MASK_MAX_SLEEP);
+       mask = EDP_PSR_DEBUG_MASK_MEMUP |
+              EDP_PSR_DEBUG_MASK_HPD |
+              EDP_PSR_DEBUG_MASK_LPSP |
+              EDP_PSR_DEBUG_MASK_MAX_SLEEP;
+
+       if (INTEL_GEN(dev_priv) < 11)
+               mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
+
+       I915_WRITE(EDP_PSR_DEBUG, mask);
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,