[X86][SSE] Match bitcasted BUILD_VECTOR of constants for v2i64 shifts on 64-bit targe...

Extension to rL315155, generate constant shifts on 64-bits as well as 32-bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315156 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 6e45621..9037a37 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -22150,9 +22150,9 @@ static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
     }
   }
 
-  // Special case in 32-bit mode, where i64 is expanded into high and low parts.
+  // Check cases (mainly 32-bit) where i64 is expanded into high and low parts.
   // TODO: Replace constant extraction with getTargetConstantBitsFromNode.
-  if (!Subtarget.is64Bit() && !Subtarget.hasXOP() &&
+  if (!Subtarget.hasXOP() &&
       (VT == MVT::v2i64 || (Subtarget.hasInt256() && VT == MVT::v4i64) ||
        (Subtarget.hasAVX512() && VT == MVT::v8i64))) {
 

diff --git a/test/CodeGen/X86/pr34855.ll b/test/CodeGen/X86/pr34855.ll
index 286d7d2..989c943 100644 (file)
--- a/test/CodeGen/X86/pr34855.ll
+++ b/test/CodeGen/X86/pr34855.ll
@@ -18,12 +18,6 @@ define void @PR34855(<2 x i32> *%p0, <2 x i32> *%p1, <2 x i32> *%p2) {
 ; X64-NEXT:    movslq (%rdi), %rax
 ; X64-NEXT:    movq %rax, %xmm1
 ; X64-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; X64-NEXT:    pxor %xmm0, %xmm0
-; X64-NEXT:    movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
-; X64-NEXT:    psrlq %xmm0, %xmm2
-; X64-NEXT:    psrlq %xmm0, %xmm1
-; X64-NEXT:    pxor %xmm2, %xmm1
-; X64-NEXT:    psubq %xmm2, %xmm1
 ; X64-NEXT:    pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
 ; X64-NEXT:    movq %xmm0, (%rdx)
 ; X64-NEXT:    retq