code resutructure update

diff --git a/simulation/cpu/Makefile b/simulation/cpu/Makefile
index 01127fd..4f46fa6 100644 (file)
--- a/simulation/cpu/Makefile
+++ b/simulation/cpu/Makefile
@@ -1,5 +1,5 @@
 
-MODULES=cpu_registers.vhd decoder.vhd data_latch.vhd \
+MODULES=cpu_registers.vhd decoder.vhd \
                mos6502.vhd 
                #cpu_timing.vhd 
 

diff --git a/simulation/cpu/cpu_registers.vhd b/simulation/cpu/cpu_registers.vhd
index 45f9598..87d0c20 100644 (file)
--- a/simulation/cpu/cpu_registers.vhd
+++ b/simulation/cpu/cpu_registers.vhd
@@ -16,11 +16,11 @@ entity pc is
     port (  
             trig_clk        : in std_logic;
             res_n           : in std_logic;
-            dbus_in_n       : in std_logic;
-            dbus_out_n      : in std_logic;
-            abus_out_n      : in std_logic;
+            we_n            : in std_logic;
+            dbus_oe_n       : in std_logic;
+            abus_oe_n       : in std_logic;
             addr_inc_n      : in std_logic;
-            addr_page_nxt_n : out std_logic;
+            addr_carry_n    : out std_logic;
             int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
             int_a_bus       : out std_logic_vector (dsize - 1 downto 0)
         );
@@ -31,9 +31,9 @@ architecture rtl of pc is
 signal val : std_logic_vector (dsize - 1 downto 0);
 
 begin
-    int_a_bus <= val when abus_out_n = '0' else
+    int_a_bus <= val when abus_oe_n = '0' else
                 (others => 'Z');
-    int_d_bus <= val when (dbus_out_n = '0' and dbus_in_n /= '0') else
+    int_d_bus <= val when (dbus_oe_n = '0' and we_n /= '0') else
                 (others => 'Z');
 
     set_p : process (trig_clk, res_n)
@@ -42,10 +42,10 @@ begin
         if ( trig_clk'event and trig_clk = '1') then
             if (addr_inc_n = '0') then
                 add_val := ('0' & val) + 1;
-                addr_page_nxt_n <= not add_val(dsize);
+                addr_carry_n <= not add_val(dsize);
                 val <= add_val(dsize - 1 downto 0);
             end if;
-            if (dbus_in_n = '0') then
+            if (we_n = '0') then
                 val <= int_d_bus;
             end if;
         elsif (res_n'event and res_n = '0') then
@@ -62,24 +62,31 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.conv_std_logic_vector;
 
-entity instruction_reg is 
+entity dff is 
     generic (
             dsize : integer := 8
             );
     port (  
-            trig_clk        : in std_logic;
-            cpu_d_bus       : in std_logic_vector (dsize - 1 downto 0);
-            to_decoder      : out std_logic_vector (dsize - 1 downto 0)
+            clk     : in std_logic;
+            we_n    : in std_logic;
+            oe_n    : in std_logic;
+            d       : in std_logic_vector (dsize - 1 downto 0);
+            q       : out std_logic_vector (dsize - 1 downto 0)
         );
-end instruction_reg;
+end dff;
 
-architecture rtl of instruction_reg is
+architecture rtl of dff is
+signal val : std_logic_vector (dsize - 1 downto 0);
 begin
-    process (trig_clk)
+
+    process (clk)
     begin
-        if ( trig_clk'event and trig_clk = '1') then
-            to_decoder <= cpu_d_bus;
+        if ( clk'event and clk = '1'and we_n = '0') then
+            val <= d;
         end if;
     end process;
+
+    q <= val when oe_n = '0' else
+        (others => 'Z');
 end rtl;
 

diff --git a/simulation/cpu/decoder.vhd b/simulation/cpu/decoder.vhd
index ae029f2..972619b 100644 (file)
--- a/simulation/cpu/decoder.vhd
+++ b/simulation/cpu/decoder.vhd
@@ -16,13 +16,15 @@ entity decoder is
             rdy             : in std_logic;
             instruction     : in std_logic_vector (dsize - 1 downto 0);
             status_reg      : in std_logic_vector (dsize - 1 downto 0);
-            pcl_d_i_n       : out std_logic;
-            pcl_d_o_n       : out std_logic;
-            pcl_a_o_n       : out std_logic;
-            pch_d_i_n       : out std_logic;
-            pch_d_o_n       : out std_logic;
-            pch_a_o_n       : out std_logic;
+            pcl_we_n        : out std_logic;
+            pcl_d_oe_n      : out std_logic;
+            pcl_a_oe_n      : out std_logic;
+            pch_we_n        : out std_logic;
+            pch_d_oe_n      : out std_logic;
+            pch_a_oe_n      : out std_logic;
             pc_inc_n        : out std_logic;
+            inst_we_n       : out std_logic;
+            inst_oe_n       : out std_logic;
             r_nw            : out std_logic
         );
 end decoder;
@@ -52,6 +54,37 @@ begin
     writeline(output, out_l);
 end  procedure;
 
+---ival : 0x0000 - 0xffff
+function conv_hex16(ival : integer) return string is
+variable tmp1, tmp2, tmp3, tmp4 : integer;
+--variable ret : string (1 to 4) := "0000";
+variable hex_chr: string (1 to 16) := "0123456789abcdef";
+begin
+    tmp4 := ival / 16 ** 3;
+    tmp3 := (ival mod 16 ** 3) / 16 ** 2;
+    tmp2 := (ival mod 16 ** 2) / 16 ** 1;
+    tmp1 := ival mod 16 ** 1;
+--    d_print("hex_chr");
+--    d_print("ival: ", ival);
+--    d_print("tmp4: ", tmp4);
+--    d_print("tmp3: ", tmp3);
+--    d_print("tmp2: ", tmp2);
+--    d_print("tmp1: ", tmp1);
+
+    return hex_chr(tmp4 + 1) & hex_chr(tmp3 + 1) 
+        & hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
+end;
+
+function conv_hex8(ival : integer) return string is
+variable tmp1, tmp2 : integer;
+variable hex_chr: string (1 to 16) := "0123456789abcdef";
+begin
+    tmp2 := (ival mod 16 ** 2) / 16 ** 1;
+    tmp1 := ival mod 16 ** 1;
+    return hex_chr(tmp2 + 1) & hex_chr(tmp1 + 1);
+end;
+
+
 type dec_status is (reset0, reset1, reset2, reset3, reset4, reset5, 
                     fetch, exec, 
                     sei,
@@ -73,7 +106,7 @@ begin
         end if;
 
         if (set_clk'event and set_clk = '1') then
-            d_print(string'("*"));
+            d_print(string'("-"));
 
             case cur_status is
                 when reset0 => 
@@ -90,8 +123,10 @@ begin
                     cur_status <= fetch;
                 when fetch => 
                     d_print(string'("fetch"));
-                    pcl_a_o_n <= '0';
-                    pch_a_o_n <= '0';
+                    pcl_a_oe_n <= '0';
+                    pch_a_oe_n <= '0';
+                    inst_we_n <= '0';
+                    inst_oe_n <= '0';
                     r_nw <= '1';
                     pc_inc_n <= '0';
                     cur_status <= exec;
@@ -101,24 +136,24 @@ begin
                     if instruction = conv_std_logic_vector(16#78#, dsize) then
                         --0x78 = 120
                         d_print(string'("   sei"));
-                        pcl_a_o_n <= '1';
-                        pch_a_o_n <= '1';
+                        pcl_a_oe_n <= '1';
+                        pch_a_oe_n <= '1';
                         pc_inc_n <= '1';
                         ---set flag operation here.
                         cur_status <= fetch;
                     elsif instruction = conv_std_logic_vector(16#a2#, dsize) then
                         --0xa2 = 162 
                         d_print(string'("   ldx 0"));
-                        pcl_a_o_n <= '0';
-                        pch_a_o_n <= '0';
+                        pcl_a_oe_n <= '0';
+                        pch_a_oe_n <= '0';
                         pc_inc_n <= '0';
                         ---load X operation here.
                         cur_status <= fetch;
                     elsif instruction = conv_std_logic_vector(16#9a#, dsize) then
                         --0x9a = 154
                         d_print(string'("   txs"));
-                        pcl_a_o_n <= '1';
-                        pch_a_o_n <= '1';
+                        pcl_a_oe_n <= '1';
+                        pch_a_oe_n <= '1';
                         pc_inc_n <= '1';
                         cur_status <= fetch;
                     elsif instruction = conv_std_logic_vector(16#4c#, dsize) then
@@ -126,16 +161,16 @@ begin
                         cur_status <= jmp1;
                         d_print(string'("   jmp 0"));
                         pc_inc_n <= '0';
-                        pcl_a_o_n <= '0';
-                        pch_a_o_n <= '0';
+                        pcl_a_oe_n <= '0';
+                        pch_a_oe_n <= '0';
                         cur_status <= jmp1;
 
                     else
                         cur_status <= unknown_stat;
                         d_print(string'("unknown inst."));
                         pc_inc_n <= '1';
-                        pcl_a_o_n <= '1';
-                        pch_a_o_n <= '1';
+                        pcl_a_oe_n <= '1';
+                        pch_a_oe_n <= '1';
                     end if;
 
                 when ldx1 => 
@@ -144,8 +179,8 @@ begin
                 when jmp1 => 
                     d_print(string'("   jmp 1"));
                     pc_inc_n <= '0';
-                    pcl_a_o_n <= '1';
-                    pch_a_o_n <= '1';
+                    pcl_a_oe_n <= '1';
+                    pch_a_oe_n <= '1';
                     cur_status <= fetch;
                 when jmp2 => 
                     d_print(string'("   jmp 2"));

diff --git a/simulation/cpu/mos6502.vhd b/simulation/cpu/mos6502.vhd
index bea8a23..d74e086 100644 (file)
--- a/simulation/cpu/mos6502.vhd
+++ b/simulation/cpu/mos6502.vhd
@@ -29,11 +29,11 @@ architecture rtl of mos6502 is
         port (  
                 trig_clk        : in std_logic;
                 res_n           : in std_logic;
-                dbus_in_n       : in std_logic;
-                dbus_out_n      : in std_logic;
-                abus_out_n      : in std_logic;
+                we_n            : in std_logic;
+                dbus_oe_n       : in std_logic;
+                abus_oe_n       : in std_logic;
                 addr_inc_n      : in std_logic;
-                addr_page_nxt_n : out std_logic;
+                addr_carry_n    : out std_logic;
                 int_d_bus       : inout std_logic_vector (dsize - 1 downto 0);
                 int_a_bus       : out std_logic_vector (dsize - 1 downto 0)
             );
@@ -49,41 +49,48 @@ architecture rtl of mos6502 is
                 rdy             : in std_logic;
                 instruction     : in std_logic_vector (dsize - 1 downto 0);
                 status_reg      : in std_logic_vector (dsize - 1 downto 0);
-                pcl_d_i_n       : out std_logic;
-                pcl_d_o_n       : out std_logic;
-                pcl_a_o_n       : out std_logic;
-                pch_d_i_n       : out std_logic;
-                pch_d_o_n       : out std_logic;
-                pch_a_o_n       : out std_logic;
+                pcl_we_n        : out std_logic;
+                pcl_d_oe_n      : out std_logic;
+                pcl_a_oe_n      : out std_logic;
+                pch_we_n        : out std_logic;
+                pch_d_oe_n      : out std_logic;
+                pch_a_oe_n      : out std_logic;
                 pc_inc_n        : out std_logic;
+                inst_we_n       : out std_logic;
+                inst_oe_n       : out std_logic;
                 r_nw            : out std_logic
             );
     end component;
 
-    component instruction_reg
+    component dff
         generic (
                 dsize : integer := 8
                 );
         port (  
-                trig_clk         : in std_logic;
-                cpu_d_bus       : in std_logic_vector (dsize - 1 downto 0);
-                to_decoder      : out std_logic_vector (dsize - 1 downto 0)
+                clk     : in std_logic;
+                we_n    : in std_logic;
+                oe_n    : in std_logic;
+                d       : in std_logic_vector (dsize - 1 downto 0);
+                q       : out std_logic_vector (dsize - 1 downto 0)
             );
     end component;
 
     signal set_clk : std_logic;
     signal trigger_clk : std_logic;
 
-    signal pcl_d_in_n : std_logic;
-    signal pcl_d_out_n : std_logic;
-    signal pcl_a_out_n : std_logic;
-    signal pch_d_in_n : std_logic;
-    signal pch_d_out_n : std_logic;
-    signal pch_a_out_n : std_logic;
+    signal pcl_d_we_n : std_logic;
+    signal pcl_d_oe_n : std_logic;
+    signal pcl_a_oe_n : std_logic;
+    signal pch_d_we_n : std_logic;
+    signal pch_d_oe_n : std_logic;
+    signal pch_a_oe_n : std_logic;
     signal pc_inc_n : std_logic;
-    signal pc_page_nxt_n : std_logic;
+    signal pc_cry_n : std_logic;
     signal dum_terminate : std_logic := 'Z';
 
+    signal inst_we_n : std_logic;
+    signal inst_oe_n : std_logic;
+
     --internal bus (address hi/lo, data)
     signal internal_abus_h : std_logic_vector (dsize - 1 downto 0);
     signal internal_abus_l : std_logic_vector (dsize - 1 downto 0);
@@ -95,22 +102,22 @@ begin
 
     ---instances....
     pc_l : pc generic map (dsize, 16#00#) 
-            port map(trigger_clk, rst_n, pcl_d_in_n, pcl_d_out_n, pcl_a_out_n, 
-                    pc_inc_n, pc_page_nxt_n, internal_dbus, internal_abus_l);
+            port map(trigger_clk, rst_n, pcl_d_we_n, pcl_d_oe_n, pcl_a_oe_n, 
+                    pc_inc_n, pc_cry_n, internal_dbus, internal_abus_l);
     pc_h : pc generic map (dsize, 16#80#) 
-            port map(trigger_clk, rst_n, pch_d_in_n, pch_d_out_n, pch_a_out_n, 
-                    pc_page_nxt_n, dum_terminate, internal_dbus, internal_abus_h);
+            port map(trigger_clk, rst_n, pch_d_we_n, pch_d_oe_n, pch_a_oe_n, 
+                    pc_cry_n, dum_terminate, internal_dbus, internal_abus_h);
 
     dec_inst : decoder generic map (dsize) 
             port map(set_clk, trigger_clk, rst_n, irq_n, nmi_n, 
                     rdy, instruction, status_reg,
-                    pcl_d_in_n, pcl_d_out_n, pcl_a_out_n,
-                    pch_d_in_n, pch_d_out_n, pch_a_out_n,
-                    pc_inc_n, r_nw
+                    pcl_d_we_n, pcl_d_oe_n, pcl_a_oe_n,
+                    pch_d_we_n, pch_d_oe_n, pch_a_oe_n,
+                    pc_inc_n, inst_we_n, inst_oe_n, r_nw
                     );
 
-    instruction_register : instruction_reg generic map (dsize) 
-            port map(trigger_clk, d_io, instruction);
+    instruction_register : dff generic map (dsize) 
+            port map(trigger_clk, inst_we_n, inst_oe_n, d_io, instruction);
 
     -- clock generate.
     phi1 <= input_clk;