#include "llvm/Pass.h"
#include "llvm/Constant.h"
+#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
namespace llvm {
- class SelectionDAG;
class SelectionDAGLowering;
class SDOperand;
class SSARegMap;
SSARegMap *RegMap;
SelectionDAG *CurDAG;
MachineBasicBlock *BB;
+ std::vector<SDNode*> TopOrder;
+ unsigned DAGSize;
- SelectionDAGISel(TargetLowering &tli) : TLI(tli), JT(0,0,0,0) {}
+ SelectionDAGISel(TargetLowering &tli) : TLI(tli), DAGSize(0), JT(0,0,0,0) {}
TargetLowering &getTargetLowering() { return TLI; }
virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
+ virtual void SelectRootInit() {
+ DAGSize = CurDAG->AssignTopologicalOrder(TopOrder);
+ }
/// SelectInlineAsmMemoryOperand - Select the specified address as a target
/// addressing mode, according to the specified constraint code. If this does