arm64: dts: renesas: r9a07g044: Rename SDHI clocks

Rename the below SDHI clocks to match with the clocks used in driver.

     imclk->core
     clk_hs->clkh
     imclk2->cd

Also re-arrange the clocks to match with the sorting order used in the
binding document.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20211122103905.14439-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index be9e5c4..71f1701 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -613,10 +613,10 @@
                        interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
-                                <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
                                 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
+                                <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
                                 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
-                       clock-names = "imclk", "imclk2", "clk_hs", "aclk";
+                       clock-names = "core", "clkh", "cd", "aclk";
                        resets = <&cpg R9A07G044_SDHI0_IXRST>;
                        power-domains = <&cpg>;
                        status = "disabled";
@@ -629,10 +629,10 @@
                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
-                                <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
                                 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
+                                <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
                                 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
-                       clock-names = "imclk", "imclk2", "clk_hs", "aclk";
+                       clock-names = "core", "clkh", "cd", "aclk";
                        resets = <&cpg R9A07G044_SDHI1_IXRST>;
                        power-domains = <&cpg>;
                        status = "disabled";