ARM: fix IT decoding

mask == 0 -> UNPRED

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184702 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 186bc9c..bc874f4 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -4667,10 +4667,8 @@ static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
     S = MCDisassembler::SoftFail;
   }
 
-  if (mask == 0x0) {
-    mask |= 0x8;
-    S = MCDisassembler::SoftFail;
-  }
+  if (mask == 0x0)
+    return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::CreateImm(pred));
   Inst.addOperand(MCOperand::CreateImm(mask));

diff --git a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt
index 1a8ff48..360d20a 100644 (file)
--- a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt
+++ b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt
@@ -1,3 +1,7 @@
-# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown 2>&1 | grep "potentially undefined instruction encoding"
+# CHECK-UNPRED: potentially undefined instruction encoding
+# CHECK-UNDEF: invalid instruction encoding
 
-0xff 0xbf 0x6b 0x80 0x00 0x75
+# RUN: echo "0xff 0xbf 0x6b 0x80 0x00 0x75" | llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK-UNPRED
+
+# mask = 0
+# RUN: echo "0x50 0xbf 0x00 0x00" | llvm-mc -disassemble -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK-UNDEF