8 bit adder test bench ok

diff --git a/simulation/test/testbench_adder8.vhd b/simulation/test/testbench_adder8.vhd
index 060efa2..865e9ea 100644 (file)
--- a/simulation/test/testbench_adder8.vhd
+++ b/simulation/test/testbench_adder8.vhd
@@ -2,6 +2,9 @@
 library IEEE;
 use IEEE.std_logic_1164.all;
 use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use std.textio.all;
+
 
 entity testbench_adder8 is
 end testbench_adder8;
@@ -20,17 +23,39 @@ architecture stimulus of testbench_adder8 is
 begin
     dut : adder8 port map (aa, bb, ss, cc);
 
-    p1 : process
+    p : process
+    variable out_line : line;
+    variable i,j : integer;
     begin
-        aa <= "00000000"; wait for 10 ns;
-        aa <= "00000001"; wait for 10 ns;
-    end process;
+        for i in 0 to 255 loop
+            aa <= conv_std_logic_vector(i, 8);
+            for j in 0 to 255 loop
 
-    p2 : process
-    begin
-        bb <= "00000000"; wait for 20 ns;
-        bb <= "00000001"; wait for 20 ns;
+                bb <= conv_std_logic_vector(j, 8);
+                write(out_line, string'("test "));
+                write(out_line, i);
+                write(out_line, string'(", "));
+                write(out_line, j);
+                writeline(output, out_line);
+
+                wait for 10 ns;
+            end loop;
+
+            wait for 10 ns;
+        end loop;
     end process;
 
+--    p1 : process
+--    begin
+--        aa <= "00000000"; wait for 10 ns;
+--        aa <= "00000001"; wait for 10 ns;
+--    end process;
+--
+--    p2 : process
+--    begin
+--        bb <= "00000000"; wait for 20 ns;
+--        bb <= "00000001"; wait for 20 ns;
+--    end process;
+
 end stimulus ;