drm/amd/display: Add Renoir clock registers list

These are the registers used to program the clock hw.

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
index adae03b..43c1bf6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h
@@ -78,6 +78,23 @@
                SRII(PIXEL_RATE_CNTL, OTG, 5)
 #endif
 
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \
+               SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
+               SRII(PHASE, DP_DTO, 0),\
+               SRII(PHASE, DP_DTO, 1),\
+               SRII(PHASE, DP_DTO, 2),\
+               SRII(PHASE, DP_DTO, 3),\
+               SRII(MODULO, DP_DTO, 0),\
+               SRII(MODULO, DP_DTO, 1),\
+               SRII(MODULO, DP_DTO, 2),\
+               SRII(MODULO, DP_DTO, 3),\
+               SRII(PIXEL_RATE_CNTL, OTG, 0),\
+               SRII(PIXEL_RATE_CNTL, OTG, 1),\
+               SRII(PIXEL_RATE_CNTL, OTG, 2),\
+               SRII(PIXEL_RATE_CNTL, OTG, 3)
+#endif
+
 #if defined(CONFIG_DRM_AMD_DC_DCN2_0)
 #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
        CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\