drm/amd/display: Fix MPO & pipe split on 3-pipe dcn2x

[WHY]
DML is incorrectly initialized with 4 pipes on 3 pipe configs
RequiredDPPCLK is halved on unsplit pipe due to an incorrectly handled 3 pipe
case, causing underflow with 2 planes & pipe split (MPO, 8K + 2nd display)

[HOW]
Set correct number of DPP/OTGs for dml init to generate correct DPP topology
Double RequiredDPPCLK after clock is halved for pipe split
and find_secondary_pipe fails to fix underflow

Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 9bc0ffa..2596d4a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2482,9 +2482,10 @@ bool dcn20_fast_validate_bw(
                                /* pipe not split previously needs split */
                                hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
                                ASSERT(hsplit_pipe);
-                               if (!hsplit_pipe)
+                               if (!hsplit_pipe) {
+                                       context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
                                        continue;
-
+                               }
                                if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
                                        if (!dcn20_split_stream_for_odm(
                                                        &context->res_ctx, dc->res_pool,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index d2e851e..23c1f38 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1609,6 +1609,7 @@ static bool construct(
        struct dc_context *ctx = dc->ctx;
        struct irq_service_init_data init_data;
        uint32_t pipe_fuses = read_pipe_fuses(ctx);
+       uint32_t num_pipes;
 
        ctx->dc_bios->regs = &bios_regs;
 
@@ -1722,6 +1723,14 @@ static bool construct(
 
        pool->base.pp_smu = dcn21_pp_smu_create(ctx);
 
+       num_pipes = dcn2_1_ip.max_num_dpp;
+
+       for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
+               if (pipe_fuses & 1 << i)
+                       num_pipes--;
+       dcn2_1_ip.max_num_dpp = num_pipes;
+       dcn2_1_ip.max_num_otg = num_pipes;
+
        dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
 
        init_data.ctx = dc->ctx;