{
u32 val;
+ const u32 cio_err_mask =
+ CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK |
+ CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK |
+ CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK |
+ CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK;
+
+ /* Enable CIO error irqs */
+ reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(1),
+ CAL_HL_IRQ_CIO_MASK(ctx->csi2_port));
+ reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_IRQENABLE(ctx->csi2_port),
+ cio_err_mask);
+
+ /* Always enable OCPO error */
+ reg_write(ctx->dev, CAL_HL_IRQENABLE_SET(1), CAL_HL_IRQ_OCPO_ERR_MASK);
+
/* Enable IRQ_WDMA_END 0/1 */
val = 0;
set_field(&val, CAL_HL_IRQ_ENABLE, CAL_HL_IRQ_MASK(ctx->csi2_port));
{
u32 val;
+ /* Disable CIO error irqs */
+ reg_write(ctx->dev, CAL_HL_IRQENABLE_CLR(1),
+ CAL_HL_IRQ_CIO_MASK(ctx->csi2_port));
+ reg_write(ctx->dev, CAL_CSI2_COMPLEXIO_IRQENABLE(ctx->csi2_port),
+ 0);
+
/* Disable IRQ_WDMA_END 0/1 */
val = 0;
set_field(&val, CAL_HL_IRQ_CLEAR, CAL_HL_IRQ_MASK(ctx->csi2_port));
struct cal_dev *dev = (struct cal_dev *)data;
struct cal_ctx *ctx;
struct cal_dmaqueue *dma_q;
- u32 irqst2, irqst3;
+ u32 irqst1, irqst2, irqst3;
+
+ irqst1 = reg_read(dev, CAL_HL_IRQSTATUS(1));
+ if (irqst1) {
+ int i;
+
+ reg_write(dev, CAL_HL_IRQSTATUS(1), irqst1);
+
+ if (irqst1 & CAL_HL_IRQ_OCPO_ERR_MASK)
+ dev_err_ratelimited(&dev->pdev->dev, "OCPO ERROR\n");
+
+ for (i = 1; i <= 2; ++i) {
+ if (irqst1 & CAL_HL_IRQ_CIO_MASK(i)) {
+ u32 cio_stat = reg_read(dev,
+ CAL_CSI2_COMPLEXIO_IRQSTATUS(i));
+
+ dev_err_ratelimited(&dev->pdev->dev,
+ "CIO%d error: %#08x\n", i, cio_stat);
+
+ reg_write(dev, CAL_CSI2_COMPLEXIO_IRQSTATUS(i),
+ cio_stat);
+ }
+ }
+ }
/* Check which DMA just finished */
irqst2 = reg_read(dev, CAL_HL_IRQSTATUS(2));
#define CAL_HL_IRQ_ENABLED 0x1
#define CAL_HL_IRQ_PENDING 0x1
+#define CAL_HL_IRQ_OCPO_ERR_MASK BIT(6)
+
+#define CAL_HL_IRQ_CIO_MASK(i) BIT(16 + ((i) - 1) * 8)
+#define CAL_HL_IRQ_VC_MASK(i) BIT(17 + ((i) - 1) * 8)
+
#define CAL_PIX_PROC_EN_MASK BIT(0)
#define CAL_PIX_PROC_EXTRACT_MASK GENMASK(4, 1)
#define CAL_PIX_PROC_EXTRACT_B6 0x0
#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL3_MASK BIT(17)
#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL4_MASK BIT(18)
#define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL5_MASK BIT(19)
+#define CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK GENMASK(19, 0)
#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM1_MASK BIT(20)
#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM2_MASK BIT(21)
#define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM3_MASK BIT(22)