From: astoria-d Date: Wed, 4 Sep 2013 14:23:39 +0000 (+0900) Subject: cpu, decoder and rom/ram integrated. X-Git-Tag: motonesfpga-gate-0.2.0~126^2~19 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;ds=sidebyside;h=6ac6a1656e743e15ba629ce0fc9be9854e8e2f06;p=motonesfpga%2Fmotonesfpga.git cpu, decoder and rom/ram integrated. --- diff --git a/de1_nes/cpu/alu.vhd b/de1_nes/cpu/alu.vhd index a00cb48..841d889 100644 --- a/de1_nes/cpu/alu.vhd +++ b/de1_nes/cpu/alu.vhd @@ -199,7 +199,7 @@ begin pcl_inc_n, pch_inc_n, sp_oe_n, sp_push_n, sp_pop_n, abs_xy_n, pg_next_n, zp_n, zp_xy_n, rel_calc_n, indir_n, indir_x_n, indir_y_n, - index_bus, bal, bal, addr_c_in, addr_out, addr_c, + index_bus, bal, bah, addr_c_in, addr_out, addr_c, --for arithmatic operation. arith_en_n, @@ -632,29 +632,29 @@ end procedure; d1 <= arith_reg_out; int_d_bus <= d_out; - if (clk = '0') then - --d_print("clk hi"); - if (m2m_stat_1 = '0') then - --first cycle. keep input variable. - --d_print("inc first."); - m2m_stat_1 <= '1'; - arith_buf_we_n <= '0'; - arith_buf_oe_n <= '1'; - d_oe_n <= '1'; - - end if; - end if; - - if (clk'event and clk = '0') then - if (m2m_stat_2 = '0') then - --second cycle read from register, output modified data. - --d_print("inc second..."); - m2m_stat_2 <= '1'; - arith_buf_we_n <= '1'; - arith_buf_oe_n <= '0'; - d_oe_n <= '0'; - end if; - end if; +-- if (clk = '0') then +-- --d_print("clk hi"); +-- if (m2m_stat_1 = '0') then +-- --first cycle. keep input variable. +-- --d_print("inc first."); +-- m2m_stat_1 <= '1'; +-- arith_buf_we_n <= '0'; +-- arith_buf_oe_n <= '1'; +-- d_oe_n <= '1'; +-- +-- end if; +-- end if; +-- +-- if (clk'event and clk = '0') then +-- if (m2m_stat_2 = '0') then +-- --second cycle read from register, output modified data. +-- --d_print("inc second..."); +-- m2m_stat_2 <= '1'; +-- arith_buf_we_n <= '1'; +-- arith_buf_oe_n <= '0'; +-- d_oe_n <= '0'; +-- end if; +-- end if; if instruction (7 downto 5) = "000" then diff --git a/de1_nes/cpu/cpu_registers.vhd b/de1_nes/cpu/cpu_registers.vhd index 7021c0a..27e2aaa 100644 --- a/de1_nes/cpu/cpu_registers.vhd +++ b/de1_nes/cpu/cpu_registers.vhd @@ -77,7 +77,7 @@ end rtl; library ieee; use ieee.std_logic_1164.all; -entity latch is +entity data_latch is generic ( dsize : integer := 8 ); @@ -86,9 +86,9 @@ entity latch is d : in std_logic_vector (dsize - 1 downto 0); q : out std_logic_vector (dsize - 1 downto 0) ); -end latch; +end data_latch; -architecture rtl of latch is +architecture rtl of data_latch is begin process (clk, d) @@ -222,7 +222,7 @@ entity data_bus_buffer is end data_bus_buffer; architecture rtl of data_bus_buffer is -component latch +component data_latch generic ( dsize : integer := 8 ); @@ -253,12 +253,12 @@ begin wr_clk <= (not r_nw) and clk; --read from i/o to cpu - latch_r : latch generic map (dsize) + latch_r : data_latch generic map (dsize) port map(rd_clk, ext_dbus, read_buf); read_tsb : tri_state_buffer generic map (dsize) port map(int_oe_n, read_buf, int_dbus); --write from cpu to io - latch_w : latch generic map (dsize) + latch_w : data_latch generic map (dsize) port map(wr_clk, int_dbus, write_buf); write_tsb : tri_state_buffer generic map (dsize) port map(r_nw, write_buf, ext_dbus); @@ -286,7 +286,7 @@ end input_data_latch; architecture rtl of input_data_latch is -component latch +component data_latch generic ( dsize : integer := 8 ); @@ -313,7 +313,7 @@ signal latch_buf : std_logic_vector (dsize - 1 downto 0); begin latch_clk <= (not we_n) and clk; - latch_inst : latch generic map (dsize) + latch_inst : data_latch generic map (dsize) port map(latch_clk, int_dbus, latch_buf); iput_data_tsb : tri_state_buffer generic map (dsize) port map(oe_n, latch_buf, alu_bus); diff --git a/de1_nes/cpu/decoder.vhd b/de1_nes/cpu/decoder.vhd index 78dffbb..cdb78fb 100644 --- a/de1_nes/cpu/decoder.vhd +++ b/de1_nes/cpu/decoder.vhd @@ -977,20 +977,20 @@ end procedure; begin - if (res_n = '0') then - --pc l/h is reset vector. - pcl_cmd <= "1110"; - pch_cmd <= "1110"; - next_cycle <= R0; - elsif (res_n'event and res_n = '1') then - pcl_cmd <= "1111"; - pch_cmd <= "1111"; - end if; - - if (nmi_n'event and nmi_n = '1') then - --reset nmi handle status - nmi_handled_n := '1'; - end if; +-- if (res_n = '0') then +-- --pc l/h is reset vector. +-- pcl_cmd <= "1110"; +-- pch_cmd <= "1110"; +-- next_cycle <= R0; +-- elsif (res_n'event and res_n = '1') then +-- pcl_cmd <= "1111"; +-- pch_cmd <= "1111"; +-- end if; +-- +-- if (nmi_n'event and nmi_n = '1') then +-- --reset nmi handle status +-- nmi_handled_n := '1'; +-- end if; -- if (a2_abs_xy_next_cycle'event) then @@ -1025,7 +1025,10 @@ end procedure; --if (set_clk'event and set_clk = '1' and res_n = '1') then if (res_n = '0') then - --nothing... + --pc l/h is reset vector. + pcl_cmd <= "1110"; + pch_cmd <= "1110"; + next_cycle <= R0; elsif (rising_edge(set_clk)) then d_print(string'("-")); diff --git a/de1_nes/de1_nes.qsf b/de1_nes/de1_nes.qsf index c5a18ab..1cad207 100644 --- a/de1_nes/de1_nes.qsf +++ b/de1_nes/de1_nes.qsf @@ -43,14 +43,14 @@ set_location_assignment PIN_R22 -to rst_n set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE de1_nes.vwf set_global_assignment -name VHDL_FILE mem/prg_rom.vhd set_global_assignment -name VHDL_FILE mem/ram.vhd +set_global_assignment -name VHDL_FILE ppu/ppu_registers.vhd +set_global_assignment -name VHDL_FILE cpu/cpu_registers.vhd +set_global_assignment -name VHDL_FILE clock/clock_divider.vhd set_global_assignment -name VHDL_FILE ppu/ppu.vhd set_global_assignment -name VHDL_FILE ppu/render.vhd -set_global_assignment -name VHDL_FILE cpu/mos6502.vhd set_global_assignment -name VHDL_FILE cpu/decoder.vhd set_global_assignment -name VHDL_FILE cpu/alu.vhd -set_global_assignment -name VHDL_FILE ppu/ppu_registers.vhd -set_global_assignment -name VHDL_FILE cpu/cpu_registers.vhd -set_global_assignment -name VHDL_FILE clock/clock_divider.vhd +set_global_assignment -name VHDL_FILE cpu/mos6502.vhd set_global_assignment -name VHDL_FILE address_decoder.vhd set_global_assignment -name VHDL_FILE de1_nes.vhd set_global_assignment -name VECTOR_WAVEFORM_FILE de1_nes.vwf \ No newline at end of file diff --git a/de1_nes/de1_nes.vhd b/de1_nes/de1_nes.vhd index ac1bfba..a84ab35 100644 --- a/de1_nes/de1_nes.vhd +++ b/de1_nes/de1_nes.vhd @@ -128,10 +128,10 @@ begin clock_inst : clock_divider port map (base_clk, rst_n, cpu_clk, ppu_clk, vga_clk); --- --mos 6502 cpu instance --- cpu_inst : mos6502 generic map (data_size, addr_size) --- port map (cpu_clk, rdy, rst_n, irq_n, nmi_n, dbe, r_nw, --- phi1, phi2, addr, d_io); + --mos 6502 cpu instance + cpu_inst : mos6502 generic map (data_size, addr_size) + port map (cpu_clk, rdy, rst_n, irq_n, nmi_n, dbe, r_nw, + phi1, phi2, addr, d_io); addr_dec_inst : address_decoder generic map (addr_size, data_size) port map (phi2, r_nw, addr, d_io, ppu_ce_n); diff --git a/de1_nes/mem/prg_rom.vhd b/de1_nes/mem/prg_rom.vhd index b766fcf..b7d2931 100644 --- a/de1_nes/mem/prg_rom.vhd +++ b/de1_nes/mem/prg_rom.vhd @@ -1,7 +1,8 @@ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.conv_integer; -use ieee.std_logic_arith.conv_std_logic_vector; +--use ieee.std_logic_arith.conv_std_logic_vector; +use ieee.numeric_std.to_unsigned; use std.textio.all; --asyncronous rom @@ -23,32 +24,53 @@ type rom_array is array (0 to 2**abus_size - 1) of rom_data; constant ROM_TACE : time := 100 ns; --output enable access time constant ROM_TOH : time := 10 ns; --output hold time ---function is called only once at the array initialize. -function rom_fill return rom_array is - type binary_file is file of character; - FILE nes_file : binary_file OPEN read_mode IS "rom-file.nes" ; - variable read_data : character; - variable i : integer; - variable out_line : line; - variable ret : rom_array; - begin - --skip first 16 bit data(NES cardridge header part.) - for i in 0 to 15 loop - read(nes_file, read_data); - end loop; - - for i in ret'range loop - read(nes_file, read_data); - ret(i) := - conv_std_logic_vector(character'pos(read_data), 8); - end loop; - write(out_line, string'("file load success.")); - writeline(output, out_line); - return ret; - end rom_fill; +----function is called only once at the array initialize. +--function rom_fill return rom_array is +-- type binary_file is file of character; +-- FILE nes_file : binary_file OPEN read_mode IS "rom-file.nes" ; +-- variable read_data : character; +-- variable i : integer; +-- variable out_line : line; +-- variable ret : rom_array; +-- begin +-- --skip first 16 bit data(NES cardridge header part.) +-- for i in 0 to 15 loop +-- read(nes_file, read_data); +-- end loop; +-- +-- for i in ret'range loop +-- read(nes_file, read_data); +-- ret(i) := +-- conv_std_logic_vector(character'pos(read_data), 8); +-- end loop; +-- write(out_line, string'("file load success.")); +-- writeline(output, out_line); +-- return ret; +-- end rom_fill; + + function init_rom + return rom_array is + variable tmp : rom_array := (others => (others => '0')); + begin + for addr_pos in 0 to 2**abus_size - 1 loop + -- Initialize each address with the address itself + tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos, dbus_size)); + end loop; + return tmp; + end init_rom; + + -- Declare the ROM signal and specify a default value. Quartus II + -- will create a memory initialization file (.mif) based on the + -- default value. --itinialize with the rom_fill function. -constant p_rom : rom_array := rom_fill; +--constant p_rom : rom_array := rom_fill; +signal p_rom : rom_array := init_rom; + +attribute ram_init_file : string; +attribute ram_init_file of p_rom : signal is "sample1-prg.hex11111"; + + begin diff --git a/de1_nes/ppu/ppu_registers.vhd b/de1_nes/ppu/ppu_registers.vhd index bca7ea2..54c4acd 100644 --- a/de1_nes/ppu/ppu_registers.vhd +++ b/de1_nes/ppu/ppu_registers.vhd @@ -137,7 +137,7 @@ end ls373; architecture rtl of ls373 is -component latch +component data_latch generic ( dsize : integer := 8 ); @@ -162,7 +162,7 @@ end component; signal q_out : std_logic_vector (dsize - 1 downto 0); begin - ls373_inst : latch generic map (dsize) + ls373_inst : data_latch generic map (dsize) port map (c, d, q_out); tsb_inst : tri_state_buffer generic map (dsize) port map (oc_n, q_out, q);