From: Richard Henderson Date: Fri, 7 Feb 2020 14:04:21 +0000 (+0000) Subject: target/arm: Enable HCR_E2H for VHE X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=03c76131bc494366a4357a1d265c5eb5cc820754;p=qmiga%2Fqemu.git target/arm: Enable HCR_E2H for VHE Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2a53f5d09b..0e68704a90 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1424,13 +1424,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define HCR_ATA (1ULL << 56) #define HCR_DCT (1ULL << 57) -/* - * When we actually implement ARMv8.1-VHE we should add HCR_E2H to - * HCR_MASK and then clear it again if the feature bit is not set in - * hcr_write(). - */ -#define HCR_MASK ((1ULL << 34) - 1) - #define SCR_NS (1U << 0) #define SCR_IRQ (1U << 1) #define SCR_FIQ (1U << 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index 19a57a17da..f5ce05fdf3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4721,7 +4721,8 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = { static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = env_archcpu(env); - uint64_t valid_mask = HCR_MASK; + /* Begin with bits defined in base ARMv8.0. */ + uint64_t valid_mask = MAKE_64BIT_MASK(0, 34); if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &= ~HCR_HCD; @@ -4735,6 +4736,9 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) */ valid_mask &= ~HCR_TSC; } + if (cpu_isar_feature(aa64_vh, cpu)) { + valid_mask |= HCR_E2H; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |= HCR_TLOR; }