From: Nick Clifton <nickc@redhat.com>
Date: Mon, 8 Nov 2004 13:17:39 +0000 (+0000)
Subject: Add support fpr MAXQ processor
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=102c8940bec28327d31bb28e00020b00662e74cb;p=pf3gnuchains%2Fpf3gnuchains3x.git

Add support fpr MAXQ processor
---

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index dbd2d536d2..e1a4e8781c 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,20 @@
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* coff-maxq.c: New File.
+        * cpu-maxq.c: New File.
+        * coffcode.h: Likewise.
+        * config.bfd: Likewise.
+        * configure.in (maxqcoff_vec): New target vector.
+	* Makefile.am: Add support for maxq target.
+	* configure.in: Likewise.
+        * archures.c:. Likewise.
+        * targets.c: Likewise.
+        * bfd_in2.h : Regenerated.
+	* Makefile.in: Regenerated.
+	* configure: Regenerated.
+	* doc/Makefile.in: Regenerated.
+
 2004-11-08  Aaron W. LaFramboise <aaron98wiridge9@aaronwl.com>
 
 	* coff-i386.c (coff_i386_reloc): Fix weak symbols.
diff --git a/bfd/Makefile.am b/bfd/Makefile.am
index 46d77f2f39..714f2d0226 100644
--- a/bfd/Makefile.am
+++ b/bfd/Makefile.am
@@ -83,6 +83,7 @@ ALL_MACHINES = \
 	cpu-m88k.lo \
 	cpu-m10200.lo \
 	cpu-m10300.lo \
+	cpu-maxq.lo \
 	cpu-mcore.lo \
 	cpu-mips.lo \
 	cpu-mmix.lo \
@@ -140,6 +141,7 @@ ALL_MACHINES_CFILES = \
 	cpu-m88k.c \
 	cpu-m10200.c \
 	cpu-m10300.c \
+	cpu-mawq.c \
 	cpu-mcore.c \
 	cpu-mips.c \
 	cpu-mmix.c \
@@ -194,6 +196,7 @@ BFD32_BACKENDS = \
 	coff-i960.lo \
 	coff-m68k.lo \
 	coff-m88k.lo \
+	coff-maxq.lo \
 	coff-mips.lo \
 	coff-or32.lo \
 	coff-rs6000.lo \
@@ -362,6 +365,7 @@ BFD32_BACKENDS_CFILES = \
 	coff-i960.c \
 	coff-m68k.c \
 	coff-m88k.c \
+	coff-maxq.c \
 	coff-mips.c \
 	coff-or32.c \
 	coff-rs6000.c \
@@ -967,6 +971,7 @@ cpu-m88k.lo: cpu-m88k.c $(INCDIR)/filenames.h
 cpu-m10200.lo: cpu-m10200.c $(INCDIR)/filenames.h
 cpu-m10300.lo: cpu-m10300.c $(INCDIR)/filenames.h
 cpu-mcore.lo: cpu-mcore.c $(INCDIR)/filenames.h
+cpu-maxq.lo: cpu-maxq.c $(INCDIR)/filenames.h
 cpu-mips.lo: cpu-mips.c $(INCDIR)/filenames.h
 cpu-mmix.lo: cpu-mmix.c $(INCDIR)/filenames.h
 cpu-msp430.lo: cpu-msp430.c $(INCDIR)/filenames.h
@@ -1075,6 +1080,9 @@ coff-m68k.lo: coff-m68k.c $(INCDIR)/filenames.h $(INCDIR)/coff/m68k.h \
 coff-m88k.lo: coff-m88k.c $(INCDIR)/filenames.h $(INCDIR)/coff/m88k.h \
   $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
   libcoff.h $(INCDIR)/bfdlink.h coffcode.h coffswap.h
+coff-maxq.lo: coff-maxq.c $(INCDIR)/filenames.h $(INCDIR)/coff/maxq.h \
+  $(INCDIR)/coff/internal.h libcoff.h $(INCDIR)/libiberty.h \
+  coffcode.h coffswap.h
 coff-mips.lo: coff-mips.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h \
   $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/mips.h $(INCDIR)/coff/external.h \
diff --git a/bfd/Makefile.in b/bfd/Makefile.in
index 339a672eb3..ba9005b05c 100644
--- a/bfd/Makefile.in
+++ b/bfd/Makefile.in
@@ -320,6 +320,7 @@ ALL_MACHINES = \
 	cpu-m88k.lo \
 	cpu-m10200.lo \
 	cpu-m10300.lo \
+	cpu-maxq.lo \
 	cpu-mcore.lo \
 	cpu-mips.lo \
 	cpu-mmix.lo \
@@ -377,6 +378,7 @@ ALL_MACHINES_CFILES = \
 	cpu-m88k.c \
 	cpu-m10200.c \
 	cpu-m10300.c \
+	cpu-mawq.c \
 	cpu-mcore.c \
 	cpu-mips.c \
 	cpu-mmix.c \
@@ -432,6 +434,7 @@ BFD32_BACKENDS = \
 	coff-i960.lo \
 	coff-m68k.lo \
 	coff-m88k.lo \
+	coff-maxq.lo \
 	coff-mips.lo \
 	coff-or32.lo \
 	coff-rs6000.lo \
@@ -600,6 +603,7 @@ BFD32_BACKENDS_CFILES = \
 	coff-i960.c \
 	coff-m68k.c \
 	coff-m88k.c \
+	coff-maxq.c \
 	coff-mips.c \
 	coff-or32.c \
 	coff-rs6000.c \
@@ -905,15 +909,15 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__confi
 	@for dep in $?; do \
 	  case '$(am__configure_deps)' in \
 	    *$$dep*) \
-	      echo ' cd $(srcdir) && $(AUTOMAKE) --cygnus '; \
-	      cd $(srcdir) && $(AUTOMAKE) --cygnus  \
+	      echo ' cd $(srcdir) && $(AUTOMAKE) --foreign '; \
+	      cd $(srcdir) && $(AUTOMAKE) --foreign  \
 		&& exit 0; \
 	      exit 1;; \
 	  esac; \
 	done; \
-	echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus  Makefile'; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  Makefile'; \
 	cd $(top_srcdir) && \
-	  $(AUTOMAKE) --cygnus  Makefile
+	  $(AUTOMAKE) --foreign  Makefile
 .PRECIOUS: Makefile
 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	@case '$?' in \
@@ -1522,6 +1526,7 @@ cpu-m88k.lo: cpu-m88k.c $(INCDIR)/filenames.h
 cpu-m10200.lo: cpu-m10200.c $(INCDIR)/filenames.h
 cpu-m10300.lo: cpu-m10300.c $(INCDIR)/filenames.h
 cpu-mcore.lo: cpu-mcore.c $(INCDIR)/filenames.h
+cpu-maxq.lo: cpu-maxq.c $(INCDIR)/filenames.h
 cpu-mips.lo: cpu-mips.c $(INCDIR)/filenames.h
 cpu-mmix.lo: cpu-mmix.c $(INCDIR)/filenames.h
 cpu-msp430.lo: cpu-msp430.c $(INCDIR)/filenames.h
@@ -1630,6 +1635,9 @@ coff-m68k.lo: coff-m68k.c $(INCDIR)/filenames.h $(INCDIR)/coff/m68k.h \
 coff-m88k.lo: coff-m88k.c $(INCDIR)/filenames.h $(INCDIR)/coff/m88k.h \
   $(INCDIR)/coff/external.h $(INCDIR)/coff/internal.h \
   libcoff.h $(INCDIR)/bfdlink.h coffcode.h coffswap.h
+coff-maxq.lo: coff-maxq.c $(INCDIR)/filenames.h $(INCDIR)/coff/maxq.h \
+  $(INCDIR)/coff/internal.h libcoff.h $(INCDIR)/libiberty.h \
+  coffcode.h coffswap.h
 coff-mips.lo: coff-mips.c $(INCDIR)/filenames.h $(INCDIR)/bfdlink.h \
   $(INCDIR)/coff/internal.h $(INCDIR)/coff/sym.h $(INCDIR)/coff/symconst.h \
   $(INCDIR)/coff/ecoff.h $(INCDIR)/coff/mips.h $(INCDIR)/coff/external.h \
diff --git a/bfd/archures.c b/bfd/archures.c
index c8375bbc70..9a83fa45c6 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -234,6 +234,10 @@ DESCRIPTION
 .#define bfd_mach_sh_dsp     0x2d
 .#define bfd_mach_sh2a       0x2a
 .#define bfd_mach_sh2a_nofpu 0x2b
+.#define bfd_mach_sh2a_fake1 0x2a1
+.#define bfd_mach_sh2a_fake2 0x2a2
+.#define bfd_mach_sh2a_fake3 0x2a3
+.#define bfd_mach_sh2a_fake4 0x2a4
 .#define bfd_mach_sh2e       0x2e
 .#define bfd_mach_sh3        0x30
 .#define bfd_mach_sh3_nommu  0x31
@@ -350,6 +354,7 @@ DESCRIPTION
 .#define bfd_mach_msp44          44
 .  bfd_arch_xtensa,    {* Tensilica's Xtensa cores.  *}
 .#define bfd_mach_xtensa	1
+.   bfd_arch_maxq,     {* Dallas MAXQ 10/20 *}
 .  bfd_arch_last
 .  };
 */
@@ -416,6 +421,7 @@ extern const bfd_arch_info_type bfd_m68hc11_arch;
 extern const bfd_arch_info_type bfd_m68hc12_arch;
 extern const bfd_arch_info_type bfd_m68k_arch;
 extern const bfd_arch_info_type bfd_m88k_arch;
+extern const bfd_arch_info_type bfd_maxq_arch;
 extern const bfd_arch_info_type bfd_mcore_arch;
 extern const bfd_arch_info_type bfd_mips_arch;
 extern const bfd_arch_info_type bfd_mmix_arch;
@@ -478,6 +484,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] =
     &bfd_m68hc12_arch,
     &bfd_m68k_arch,
     &bfd_m88k_arch,
+    &bfd_maxq_arch,
     &bfd_mcore_arch,
     &bfd_mips_arch,
     &bfd_mmix_arch,
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 0ee36a7061..c39e4f8779 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1685,6 +1685,10 @@ enum bfd_architecture
 #define bfd_mach_sh_dsp     0x2d
 #define bfd_mach_sh2a       0x2a
 #define bfd_mach_sh2a_nofpu 0x2b
+#define bfd_mach_sh2a_fake1 0x2a1
+#define bfd_mach_sh2a_fake2 0x2a2
+#define bfd_mach_sh2a_fake3 0x2a3
+#define bfd_mach_sh2a_fake4 0x2a4
 #define bfd_mach_sh2e       0x2e
 #define bfd_mach_sh3        0x30
 #define bfd_mach_sh3_nommu  0x31
@@ -1801,6 +1805,7 @@ enum bfd_architecture
 #define bfd_mach_msp44          44
   bfd_arch_xtensa,    /* Tensilica's Xtensa cores.  */
 #define bfd_mach_xtensa        1
+   bfd_arch_maxq,     /* Dallas MAXQ 10/20 */
   bfd_arch_last
   };
 
diff --git a/bfd/coff-maxq.c b/bfd/coff-maxq.c
new file mode 100644
index 0000000000..2279c5c9cd
--- /dev/null
+++ b/bfd/coff-maxq.c
@@ -0,0 +1,458 @@
+/* BFD back-end for MAXQ COFF binaries.
+   Copyright 2004    Free Software Foundation, Inc.
+
+   Contributed by Vineet Sharma (vineets@noida.hcltech.com) Inderpreet S.
+   (inderpreetb@noida.hcltech.com)
+
+   HCL Technologies Ltd.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the Free 
+   Software Foundation; either version 2 of the License, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc., 59 
+   Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+#include "coff/maxq.h"
+#include "coff/internal.h"
+#include "libcoff.h"
+#include "libiberty.h"
+
+#ifndef MAXQ20
+#define MAXQ20 1
+#endif
+
+#define RTYPE2HOWTO(cache_ptr, dst)                                     \
+  ((cache_ptr)->howto =                                                 \
+   ((dst)->r_type < 48 							\
+    ? howto_table + (((dst)->r_type==47) ? 6: ((dst)->r_type))		\
+    : NULL))
+
+#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (2)
+
+/* Code to swap in the reloc offset.  */
+#define SWAP_IN_RELOC_OFFSET    H_GET_16
+#define SWAP_OUT_RELOC_OFFSET   H_PUT_16
+
+#define SHORT_JUMP 	        BFD_RELOC_16_PCREL_S2
+#define LONG_JUMP 	        BFD_RELOC_14
+#define ABSOLUTE_ADDR_FOR_DATA  BFD_RELOC_24
+
+/* checks the range of short jump -127 to 128 */
+#define IS_SJUMP_RANGE(x) ((x > -128) && (x < 129))
+#define HIGH_WORD_MASK    0xff00
+#define LOW_WORD_MASK     0x00ff
+
+static long
+get_symbol_value (asymbol *symbol)
+{
+  long relocation = 0;
+
+  if (bfd_is_com_section (symbol->section))
+    relocation = 0;
+  else
+    relocation = symbol->value +
+      symbol->section->output_section->vma + symbol->section->output_offset;
+
+  return relocation;
+}
+
+/* This function performs all the maxq relocations.
+   FIXME:  The handling of the addend in the 'BFD_*'
+   relocations types.  */
+
+static bfd_reloc_status_type
+coff_maxq20_reloc (bfd *      abfd,
+		   arelent *  reloc_entry,
+		   asymbol *  symbol_in,
+		   void *     data,
+		   asection * input_section ATTRIBUTE_UNUSED,
+		   bfd *      output_bfd    ATTRIBUTE_UNUSED,
+		   char **    error_message ATTRIBUTE_UNUSED)
+{
+  reloc_howto_type *howto = NULL;
+  unsigned char *addr = NULL;
+  unsigned long x = 0;
+  long call_addr = 0;
+  short addend = 0;
+  long diff = 0;
+
+  /* If this is an undefined symbol, return error.  */
+  if (symbol_in->section == &bfd_und_section
+      && (symbol_in->flags & BSF_WEAK) == 0)
+    return bfd_reloc_continue;
+
+  if (data && reloc_entry)
+    {
+      howto = reloc_entry->howto;
+      addr = (unsigned char *) data + reloc_entry->address;
+      call_addr = call_addr - call_addr;
+      call_addr = get_symbol_value (symbol_in);
+
+      /* Over here the value val stores the 8 bit/16 bit value. We will put a 
+         check if we are moving a 16 bit immediate value into an 8 bit
+         register. In that case we will generate a Upper bytes into PFX[0]
+         and move the lower 8 bits as SRC.  */
+
+      switch (reloc_entry->howto->type)
+	{
+	  /* BFD_RELOC_16_PCREL_S2 47 Handles all the relative jumps and
+	     calls Note: Every relative jump or call is in words.  */
+	case SHORT_JUMP:
+	  /* Handle any addend.  */
+	  addend = reloc_entry->addend;
+
+	  if (addend > call_addr || addend > 0)
+	    call_addr = symbol_in->section->output_section->vma + addend;
+	  else if (addend < call_addr && addend > 0)
+	    call_addr = call_addr + addend;
+	  else if (addend < 0)
+	    call_addr = call_addr + addend;
+
+	  diff = ((call_addr << 1) - (reloc_entry->address << 1));
+
+	  if (!IS_SJUMP_RANGE (diff))
+	    {
+	      bfd_perror (_("Can't Make it a Short Jump"));
+	      return bfd_reloc_outofrange;
+	    }
+
+	  x = bfd_get_16 (abfd, addr);
+
+	  x = x & LOW_WORD_MASK;
+	  x = x | (diff << 8);
+	  bfd_put_16 (abfd, (bfd_vma) x, addr);
+
+	  return bfd_reloc_ok;
+
+	case ABSOLUTE_ADDR_FOR_DATA:
+	case LONG_JUMP:
+	  /* BFD_RELOC_14 Handles intersegment or long jumps which might be
+	     from code to code or code to data segment jumps. Note: When this 
+	     fucntion is called by gas the section flags somehow do not
+	     contain the info about the section type(CODE or DATA). Thus the
+	     user needs to evoke the linker after assembling the files
+	     because the Code-Code relocs are word aligned but code-data are
+	     byte aligned.  */
+	  addend = (reloc_entry->addend - reloc_entry->addend);
+
+	  /* Handle any addend.  */
+	  addend = reloc_entry->addend;
+
+	  /* For relocation involving multiple file added becomes zero thus
+	     this fails - check for zero added. In another case when we try
+	     to add a stub to a file the addend shows the offset from the
+	     start od this file.  */
+	  addend = 0;
+
+	  if (!bfd_is_com_section (symbol_in->section) &&
+	      ((symbol_in->flags & BSF_OLD_COMMON) == 0))
+	    {
+	      if (reloc_entry->addend > symbol_in->value)
+		addend = reloc_entry->addend - symbol_in->value;
+
+	      if ((reloc_entry->addend < symbol_in->value)
+		  && (reloc_entry->addend != 0))
+		addend = reloc_entry->addend - symbol_in->value;
+
+	      if (reloc_entry->addend == symbol_in->value)
+		addend = 0;
+	    }
+
+	  if (bfd_is_com_section (symbol_in->section) ||
+	      ((symbol_in->flags & BSF_OLD_COMMON) != 0))
+	    addend = reloc_entry->addend;
+
+	  if (addend < 0
+	      &&  (call_addr < (long) (addend * (-1))))
+	    addend = 0;
+
+	  call_addr += addend;
+
+	  /* FIXME: This check does not work well with the assembler,
+	     linker needs to be run always.  */
+	  if ((symbol_in->section->flags & SEC_CODE) == SEC_CODE)
+	    {
+	      /* Convert it into words.  */
+	      call_addr = call_addr >> 1;
+
+	      if (call_addr > 0xFFFF)	/* Intersegment Jump.  */
+		{
+		  bfd_perror (_("Exceeds Long Jump Range"));
+		  return bfd_reloc_outofrange;
+		}
+	    }
+	  else
+	    {
+	      /* case ABSOLUTE_ADDR_FOR_DATA : Resolves any code-data
+		 segemnt relocs. These are NOT word aligned.  */
+
+	      if (call_addr > 0xFFFF)	/* Intersegment Jump.  */
+		{
+		  bfd_perror (_("Absolute address Exceeds 16 bit Range"));
+		  return bfd_reloc_outofrange;
+		}
+	    }
+
+	  x = bfd_get_32 (abfd, addr);
+
+	  x = (x & 0xFF00FF00);
+	  x = (x | ((call_addr & HIGH_WORD_MASK) >> 8));
+	  x = (x | (call_addr & LOW_WORD_MASK) << 16);
+
+	  bfd_put_32 (abfd, (bfd_vma) x, addr);
+	  return bfd_reloc_ok;
+
+	case BFD_RELOC_8:
+	  addend = (reloc_entry->addend - reloc_entry->addend);
+
+	  if (!bfd_is_com_section (symbol_in->section) &&
+	      ((symbol_in->flags & BSF_OLD_COMMON) == 0))
+	    {
+	      if (reloc_entry->addend > symbol_in->value)
+		addend = reloc_entry->addend - symbol_in->value;
+	      if (reloc_entry->addend < symbol_in->value)
+		addend = reloc_entry->addend - symbol_in->value;
+	      if (reloc_entry->addend == symbol_in->value)
+		addend = 0;
+	    }
+
+	  if (bfd_is_com_section (symbol_in->section) ||
+	      ((symbol_in->flags & BSF_OLD_COMMON) != 0))
+	    addend = reloc_entry->addend;
+
+	  if (addend < 0
+	      && (call_addr < (long) (addend * (-1))))
+	    addend = 0;
+
+	  if (call_addr + addend > 0xFF)
+	    {
+	      bfd_perror (_("Absolute address Exceeds 8 bit Range"));
+	      return bfd_reloc_outofrange;
+	    }
+
+	  x = bfd_get_8 (abfd, addr);
+	  x = x & 0x00;
+	  x = x | (call_addr + addend);
+
+	  bfd_put_8 (abfd, (bfd_vma) x, addr);
+	  return bfd_reloc_ok;
+
+	case BFD_RELOC_16:
+	  addend = (reloc_entry->addend - reloc_entry->addend);
+	  if (!bfd_is_com_section (symbol_in->section) &&
+	      ((symbol_in->flags & BSF_OLD_COMMON) == 0))
+	    {
+	      if (reloc_entry->addend > symbol_in->value)
+		addend = reloc_entry->addend - symbol_in->value;
+
+	      if (reloc_entry->addend < symbol_in->value)
+		addend = reloc_entry->addend - symbol_in->value;
+
+	      if (reloc_entry->addend == symbol_in->value)
+		addend = 0;
+	    }
+
+	  if (bfd_is_com_section (symbol_in->section) ||
+	      ((symbol_in->flags & BSF_OLD_COMMON) != 0))
+	    addend = reloc_entry->addend;
+
+	  if (addend < 0
+	      && (call_addr < (long) (addend * (-1))))
+	    addend = 0;
+
+	  if ((call_addr + addend) > 0xFFFF)
+	    {
+	      bfd_perror (_("Absolute address Exceeds 16 bit Range"));
+	      return bfd_reloc_outofrange;
+	    }
+	  else
+	    {
+	      unsigned short val = (call_addr + addend);
+
+	      x = bfd_get_16 (abfd, addr);
+
+	      /* LE */
+	      x = (x & 0x0000);	/* Flush garbage value.  */
+	      x = val;
+	      if ((symbol_in->section->flags & SEC_CODE) == SEC_CODE)
+		x = x >> 1;	/* Convert it into words.  */
+	    }
+
+	  bfd_put_16 (abfd, (bfd_vma) x, addr);
+	  return bfd_reloc_ok;
+
+	case BFD_RELOC_32:
+	  addend = (reloc_entry->addend - reloc_entry->addend);
+
+	  if (!bfd_is_com_section (symbol_in->section) &&
+	      ((symbol_in->flags & BSF_OLD_COMMON) == 0))
+	    {
+	      if (reloc_entry->addend > symbol_in->value)
+		addend = reloc_entry->addend - symbol_in->value;
+	      if (reloc_entry->addend < symbol_in->value)
+		addend = reloc_entry->addend - symbol_in->value;
+	      if (reloc_entry->addend == symbol_in->value)
+		addend = 0;
+	    }
+
+	  if (bfd_is_com_section (symbol_in->section) ||
+	      ((symbol_in->flags & BSF_OLD_COMMON) != 0))
+	    addend = reloc_entry->addend;
+
+	  if (addend < 0
+	      && (call_addr < (long) (addend * (-1))))
+	    addend = 0;
+
+	  if ((call_addr + addend) < 0)
+	    {
+	      bfd_perror ("Absolute address Exceeds 32 bit Range");
+	      return bfd_reloc_outofrange;
+	    }
+
+	  x = bfd_get_32 (abfd, addr);
+	  x = (x & 0x0000);	/* Flush garbage value.  */
+	  x = call_addr + addend;
+	  if ((symbol_in->section->flags & SEC_CODE) == SEC_CODE)
+	    x = x >> 1;	/* Convert it into words.  */
+
+	  bfd_put_32 (abfd, (bfd_vma) x, addr);
+	  return bfd_reloc_ok;
+
+	default:
+	  bfd_perror (_("Unrecognized Reloc Type"));
+	  return bfd_reloc_notsupported;
+	}
+    }
+
+  return bfd_reloc_notsupported;
+}
+
+static reloc_howto_type howto_table[] =
+{
+  EMPTY_HOWTO (0),
+  EMPTY_HOWTO (1),
+  {
+   BFD_RELOC_32, 0, 1, 8, FALSE, 0, complain_overflow_bitfield,
+   coff_maxq20_reloc, "32Bit", TRUE, 0x000000ff, 0x000000ff, TRUE
+  },
+  {
+   SHORT_JUMP, 0, 1, 8, FALSE, 0, complain_overflow_bitfield,
+   coff_maxq20_reloc, "SHORT_JMP", TRUE, 0x000000ff, 0x000000ff, TRUE
+  },
+  {
+   ABSOLUTE_ADDR_FOR_DATA, 0, 2, 32, FALSE, 0, complain_overflow_bitfield,
+   coff_maxq20_reloc, "INTERSEGMENT_RELOC", TRUE, 0x00000000, 0x00000000,
+   FALSE
+  },
+  {
+   BFD_RELOC_16, 0, 1, 8, FALSE, 0, complain_overflow_bitfield,
+   coff_maxq20_reloc, "16Bit", TRUE, 0x000000ff, 0x000000ff, TRUE
+  },
+  {
+   LONG_JUMP, 0, 2, 32, FALSE, 0, complain_overflow_bitfield,
+   coff_maxq20_reloc, "LONG_JUMP", TRUE, 0x00000000, 0x00000000, FALSE
+  },
+  {
+   BFD_RELOC_8, 0, 1, 8, FALSE, 0, complain_overflow_bitfield,
+   coff_maxq20_reloc, "8bit", TRUE, 0x000000ff, 0x000000ff, TRUE
+  },
+  EMPTY_HOWTO (8),
+  EMPTY_HOWTO (9),
+  EMPTY_HOWTO (10),
+};
+
+/* Map BFD reloc types to MAXQ COFF reloc types.  */
+
+typedef struct maxq_reloc_map
+{
+  bfd_reloc_code_real_type  bfd_reloc_val;
+  unsigned int              maxq_reloc_val;
+  reloc_howto_type *        table;
+}
+reloc_map;
+
+static const reloc_map maxq_reloc_map[] =
+{
+  {BFD_RELOC_16_PCREL_S2, SHORT_JUMP, howto_table},
+  {BFD_RELOC_16,          LONG_JUMP,  howto_table},
+};
+
+static reloc_howto_type *
+maxq_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+			bfd_reloc_code_real_type code)
+{
+  unsigned int i;
+
+  for (i = 0; i < ARRAY_SIZE (maxq_reloc_map); i++)
+    {
+      const reloc_map *entry;
+
+      entry = maxq_reloc_map + i;
+
+      switch (code)
+	{
+	  /* SHORT JUMP */
+	case BFD_RELOC_16_PCREL_S2:
+	  return howto_table + 3;
+
+	  /* INTERSEGMENT JUMP */
+	case BFD_RELOC_24:
+	  return howto_table + 4;
+
+	  /* BYTE RELOC */
+	case BFD_RELOC_8:
+	  return howto_table + 7;
+
+	  /* WORD RELOC */
+	case BFD_RELOC_16:
+	  return howto_table + 5;
+
+	  /* LONG RELOC */
+	case BFD_RELOC_32:
+	  return howto_table + 2;
+
+	  /* LONG JUMP */
+	case BFD_RELOC_14:
+	  return howto_table + 6;
+
+	default:
+	  return NULL;
+	}
+    }
+
+  return NULL;
+}
+
+#define coff_bfd_reloc_type_lookup maxq_reloc_type_lookup
+
+/* Perform any necessary magic to the addend in a reloc entry.  */
+#define CALC_ADDEND(abfd, symbol, ext_reloc, cache_ptr) \
+ cache_ptr->addend =  ext_reloc.r_offset;
+
+#include "coffcode.h"
+
+#ifndef TARGET_UNDERSCORE
+#define TARGET_UNDERSCORE 1
+#endif
+
+#ifndef EXTRA_S_FLAGS
+#define EXTRA_S_FLAGS 0
+#endif
+
+/* Forward declaration for use initialising alternative_target field.  */
+CREATE_LITTLE_COFF_TARGET_VEC (maxqcoff_vec, "coff-maxq", 0, EXTRA_S_FLAGS,
+			       TARGET_UNDERSCORE, NULL, COFF_SWAP_TABLE);
+
diff --git a/bfd/coffcode.h b/bfd/coffcode.h
index 7bfdc6b175..63a2c639b6 100644
--- a/bfd/coffcode.h
+++ b/bfd/coffcode.h
@@ -1986,6 +1986,12 @@ coff_set_arch_mach_hook (abfd, filehdr)
       machine = bfd_mach_m68020;
       break;
 #endif
+#ifdef MAXQ20MAGIC
+    case MAXQ20MAGIC:
+      arch = bfd_arch_maxq;
+      machine = 0;
+      break;
+#endif
 #ifdef MC88MAGIC
     case MC88MAGIC:
     case MC88DMAGIC:
@@ -2919,6 +2925,13 @@ coff_set_flags (abfd, magicp, flagsp)
       return TRUE;
 #endif
 
+#ifdef MAXQ20MAGIC
+    case bfd_arch_maxq:
+        *magicp = MAXQ20MAGIC;
+      return TRUE;
+      break;
+#endif
+
     default:			/* Unknown architecture.  */
       /* Fall through to "return FALSE" below, to avoid
 	 "statement never reached" errors on the one below.  */
@@ -4063,6 +4076,11 @@ coff_write_object_contents (abfd)
     internal_a.magic = NMAGIC; /* Assume separate i/d.  */
 #endif
 
+#ifdef MAXQ20MAGIC
+#define __A_MAGIC_SET__
+      internal_a.magic = MAXQ20MAGIC;
+#endif
+ 
 #ifndef __A_MAGIC_SET__
 #include "Your aouthdr magic number is not being set!"
 #else
diff --git a/bfd/config.bfd b/bfd/config.bfd
index 5051a6d127..cc8d4769f3 100644
--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -71,6 +71,7 @@ m6811*|m68hc11*) targ_archs="bfd_m68hc11_arch bfd_m68hc12_arch" ;;
 m6812*|m68hc12*) targ_archs="bfd_m68hc12_arch bfd_m68hc11_arch" ;;
 m68*)		 targ_archs=bfd_m68k_arch ;;
 m88*)		 targ_archs=bfd_m88k_arch ;;
+maxq*)		 targ_archs=bfd_maxq_arch ;;
 mips*)		 targ_archs=bfd_mips_arch ;;
 or32*)		 targ_archs=bfd_or32_arch ;;
 pdp11*)		 targ_archs=bfd_pdp11_arch ;;
@@ -786,6 +787,10 @@ case "${targ}" in
     targ_underscore=yes
     ;;
 
+  maxq-*-coff)
+    targ_defvec=maxqcoff_vec
+    ;;
+
   mcore-*-elf)
     targ_defvec=bfd_elf32_mcore_big_vec
     targ_selvecs="bfd_elf32_mcore_big_vec bfd_elf32_mcore_little_vec"
diff --git a/bfd/configure b/bfd/configure
index fed139abd6..2658d95246 100755
--- a/bfd/configure
+++ b/bfd/configure
@@ -973,7 +973,7 @@ esac
     else
       echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2
     fi
-    cd "$ac_popdir"
+    cd $ac_popdir
   done
 fi
 
@@ -1997,7 +1997,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2055,7 +2056,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2171,7 +2173,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2225,7 +2228,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2270,7 +2274,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2314,7 +2319,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2392,7 +2398,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -2446,7 +2453,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -3966,7 +3974,7 @@ test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic"
 case $host in
 *-*-irix6*)
   # Find out which ABI we are using.
-  echo '#line 3969 "configure"' > conftest.$ac_ext
+  echo '#line 3977 "configure"' > conftest.$ac_ext
   if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   (eval $ac_compile) 2>&5
   ac_status=$?
@@ -4062,7 +4070,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -4739,7 +4748,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -4797,7 +4807,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -4913,7 +4924,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -4967,7 +4979,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5012,7 +5025,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5056,7 +5070,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5460,7 +5475,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5667,7 +5683,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5727,7 +5744,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5806,7 +5824,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5871,7 +5890,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -5936,7 +5956,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6000,7 +6021,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6081,7 +6103,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6222,7 +6245,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6360,7 +6384,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6544,7 +6569,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6795,7 +6821,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -6989,7 +7016,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7092,7 +7120,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7163,7 +7192,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7265,7 +7295,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7401,7 +7432,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7465,7 +7497,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7520,7 +7553,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7660,7 +7694,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -7793,7 +7828,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8061,7 +8097,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8333,7 +8370,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8392,7 +8430,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8464,7 +8503,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8600,7 +8640,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8751,7 +8792,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8899,7 +8941,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -8970,7 +9013,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9042,7 +9086,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9096,7 +9141,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9167,7 +9213,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9221,7 +9268,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9330,7 +9378,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9431,7 +9480,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9517,7 +9567,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9592,7 +9643,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9667,7 +9719,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9742,7 +9795,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -9817,7 +9871,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10037,7 +10092,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10157,7 +10213,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10304,7 +10361,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10368,7 +10426,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10432,7 +10491,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10496,7 +10556,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10560,7 +10621,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10624,7 +10686,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10688,7 +10751,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10752,7 +10816,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10816,7 +10881,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10880,7 +10946,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -10944,7 +11011,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -11008,7 +11076,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -11072,7 +11141,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -11136,7 +11206,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -11200,7 +11271,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -11264,7 +11336,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -11612,6 +11685,7 @@ do
     m88kbcs_vec)		tb="$tb coff-m88k.lo" ;;
     m88kmach3_vec)		tb="$tb m88kmach3.lo aout32.lo" ;;
     m88kopenbsd_vec)		tb="$tb m88kopenbsd.lo aout32.lo" ;;
+    maxqcoff_vec)               tb="$tb coff-maxq.lo" ;;
     mach_o_be_vec)              tb="$tb mach-o.lo" ;;
     mach_o_le_vec)              tb="$tb mach-o.lo" ;;
     mach_o_fat_vec)             tb="$tb mach-o.lo" ;;
@@ -11878,7 +11952,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -11944,7 +12019,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -12040,7 +12116,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -12224,7 +12301,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -12501,7 +12579,8 @@ if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
   cat conftest.err >&5
   echo "$as_me:$LINENO: \$? = $ac_status" >&5
   (exit $ac_status); } &&
-	 { ac_try='test -z "$ac_c_werror_flag"			 || test ! -s conftest.err'
+	 { ac_try='test -z "$ac_c_werror_flag"
+			 || test ! -s conftest.err'
   { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
   (eval $ac_try) 2>&5
   ac_status=$?
@@ -13481,6 +13560,11 @@ esac
   *) ac_INSTALL=$ac_top_builddir$INSTALL ;;
   esac
 
+  if test x"$ac_file" != x-; then
+    { echo "$as_me:$LINENO: creating $ac_file" >&5
+echo "$as_me: creating $ac_file" >&6;}
+    rm -f "$ac_file"
+  fi
   # Let's still pretend it is `configure' which instantiates (i.e., don't
   # use $as_me), people would be surprised to read:
   #    /* config.h.  Generated by config.status.  */
@@ -13519,12 +13603,6 @@ echo "$as_me: error: cannot find input file: $f" >&2;}
 	 fi;;
       esac
     done` || { (exit 1); exit 1; }
-
-  if test x"$ac_file" != x-; then
-    { echo "$as_me:$LINENO: creating $ac_file" >&5
-echo "$as_me: creating $ac_file" >&6;}
-    rm -f "$ac_file"
-  fi
 _ACEOF
 cat >>$CONFIG_STATUS <<_ACEOF
   sed "$ac_vpsub
diff --git a/bfd/configure.in b/bfd/configure.in
index 2cb019dba8..b4715388bd 100644
--- a/bfd/configure.in
+++ b/bfd/configure.in
@@ -736,6 +736,7 @@ do
     m88kbcs_vec)		tb="$tb coff-m88k.lo" ;;
     m88kmach3_vec)		tb="$tb m88kmach3.lo aout32.lo" ;;
     m88kopenbsd_vec)		tb="$tb m88kopenbsd.lo aout32.lo" ;;
+    maxqcoff_vec)               tb="$tb coff-maxq.lo" ;;
     mach_o_be_vec)              tb="$tb mach-o.lo" ;;
     mach_o_le_vec)              tb="$tb mach-o.lo" ;;
     mach_o_fat_vec)             tb="$tb mach-o.lo" ;;
diff --git a/bfd/cpu-maxq.c b/bfd/cpu-maxq.c
new file mode 100644
index 0000000000..9c36a16180
--- /dev/null
+++ b/bfd/cpu-maxq.c
@@ -0,0 +1,42 @@
+/* BFD support for the MAXQ20/10 architecture.
+   Copyright  2004  Free Software Foundation, Inc.
+
+   Written by Vineet Sharma(vineets@noida.hcltech.com)
+	      Inderpreet Singh(inderpreetb@noida.hcltech.com)		
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "bfd.h"
+#include "sysdep.h"
+#include "libbfd.h"
+
+/* MAXQ Archtecture info.  */
+const bfd_arch_info_type bfd_maxq_arch =
+{
+  16,				/* 16 bits in a word */
+  16,				/* 16 bits in an address */
+  8,				/* 16 bits in a byte */
+  bfd_arch_maxq,		/* enum bfd_archtecture arch */
+  0,				/* only 1 machine */
+  "maxq",			/* arch_name */
+  "maxq",			/* printable name */
+  0,				/* section align power */
+  TRUE,				/* the_default: if this is the machine */
+  bfd_default_compatible,	/* bfd_arch_info */
+  bfd_default_scan,
+  NULL
+};
diff --git a/bfd/doc/Makefile.in b/bfd/doc/Makefile.in
index 38c57da42e..f0801cd31d 100644
--- a/bfd/doc/Makefile.in
+++ b/bfd/doc/Makefile.in
@@ -322,9 +322,9 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__confi
 	      exit 1;; \
 	  esac; \
 	done; \
-	echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus  doc/Makefile'; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  doc/Makefile'; \
 	cd $(top_srcdir) && \
-	  $(AUTOMAKE) --cygnus  doc/Makefile
+	  $(AUTOMAKE) --foreign  doc/Makefile
 .PRECIOUS: Makefile
 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	@case '$?' in \
diff --git a/bfd/targets.c b/bfd/targets.c
index ea2302a3de..b6c31f800c 100644
--- a/bfd/targets.c
+++ b/bfd/targets.c
@@ -687,6 +687,7 @@ extern const bfd_target m88kopenbsd_vec;
 extern const bfd_target mach_o_be_vec;
 extern const bfd_target mach_o_le_vec;
 extern const bfd_target mach_o_fat_vec;
+extern const bfd_target maxqcoff_vec;
 extern const bfd_target mcore_pe_big_vec;
 extern const bfd_target mcore_pe_little_vec;
 extern const bfd_target mcore_pei_big_vec;
@@ -1015,6 +1016,7 @@ static const bfd_target * const _bfd_target_vector[] = {
 	&mach_o_be_vec,
 	&mach_o_le_vec,
 	&mach_o_fat_vec,
+	&maxqcoff_vec,
 	&mcore_pe_big_vec,
 	&mcore_pe_little_vec,
 	&mcore_pei_big_vec,
diff --git a/include/ChangeLog b/include/ChangeLog
index ede6fe2ce0..7ee396b191 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* dis-asm.h: Add prototype for print_insn_maxq_little.
+
 2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 	
 	* opcode/crx.h (enum argtype): Rename types, remove unused types.
diff --git a/include/coff/ChangeLog b/include/coff/ChangeLog
index d107734e92..533e59b07a 100644
--- a/include/coff/ChangeLog
+++ b/include/coff/ChangeLog
@@ -1,3 +1,8 @@
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* maxqh: New file: Defintions for the maxq port.
+
 2004-11-08  Aaron W. LaFramboise <aaron98wiridge9@aaronwl.com>
 
 	* pe.h (IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY): Define.
diff --git a/include/coff/maxq.h b/include/coff/maxq.h
new file mode 100644
index 0000000000..a7be9cb1ed
--- /dev/null
+++ b/include/coff/maxq.h
@@ -0,0 +1,51 @@
+/* COFF spec for MAXQ
+
+   Copyright 2004 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the Free 
+   Software Foundation; either version 2 of the License, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc., 59 
+   Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+   Contributed by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+   S.(inderpreetb@noida.hcltech.com) HCL Technologies Ltd.  */
+
+#define L_LNNO_SIZE 2
+
+#include "coff/external.h"
+
+/* Bits for f_flags: F_RELFLG relocation info stripped from file F_EXEC file
+   is executable (no unresolved external references) F_LNNO line numbers
+   stripped from file F_LSYMS local symbols stripped from file F_AR32WR file
+   has byte ordering of an AR32WR machine (e.g. vax).  */
+
+#define F_RELFLG        (0x0001)
+#define F_EXEC          (0x0002)
+#define F_LNNO          (0x0004)
+#define F_LSYMS         (0x0008)
+
+/* Magic numbers for maxq.  */
+#define MAXQ20MAGIC      0xa0
+#define MAXQ20BADMAG(x) (((x).f_magic != MAXQ20MAGIC))
+#define BADMAG(x)        MAXQ20BADMAG (x)
+
+/* Relocation information declaration and related definitions.  */
+struct external_reloc
+{
+  char r_vaddr[4];		/* (Virtual) address of reference.  */
+  char r_symndx[4];		/* Index into symbol table.  */
+  char r_type[2];		/* Relocation type.  */
+  char r_offset[2];		/* Addend.  */
+};
+
+#define	RELOC		struct external_reloc
+#define	RELSZ		(10 + 2)	/* sizeof (RELOC) */
diff --git a/include/dis-asm.h b/include/dis-asm.h
index 7171c847a5..aa8e2b5084 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -1,6 +1,6 @@
 /* Interface between the opcode library and its callers.
 
-   Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
+   Copyright 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
    
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ -218,6 +218,8 @@ extern int print_insn_i960		(bfd_vma, disassemble_info *);
 extern int print_insn_ip2k		(bfd_vma, disassemble_info *);
 extern int print_insn_m32r		(bfd_vma, disassemble_info *);
 extern int print_insn_m88k		(bfd_vma, disassemble_info *);
+extern int print_insn_maxq_little	(bfd_vma, disassemble_info *);
+extern int print_insn_maxq_big		(bfd_vma, disassemble_info *);
 extern int print_insn_mcore		(bfd_vma, disassemble_info *);
 extern int print_insn_mmix		(bfd_vma, disassemble_info *);
 extern int print_insn_mn10200		(bfd_vma, disassemble_info *);
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index b79f68c1df..9e6a656d54 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* maxq.h: New file: Disassembly information for the maxq port.
+
 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386.h (i386_optab): Put back "movzb".
diff --git a/include/opcode/maxq.h b/include/opcode/maxq.h
new file mode 100644
index 0000000000..f4fcb30a80
--- /dev/null
+++ b/include/opcode/maxq.h
@@ -0,0 +1,1132 @@
+/* maxq.h -- Header file for MAXQ opcode table.
+
+   Copyright (C) 2004 Free Software Foundation, Inc.
+
+   This file is part of GDB, GAS, and the GNU binutils.
+
+   Written by Vineet Sharma(vineets@noida.hcltech.com)
+   Inderpreet Singh (inderpreetb@noida.hcltech.com)
+
+   GDB, GAS, and the GNU binutils are free software; you can redistribute
+   them and/or modify them under the terms of the GNU General Public License
+   as published by the Free Software Foundation; either version 2, or (at
+   your option) any later version.
+
+   GDB, GAS, and the GNU binutils are distributed in the hope that they will
+   be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General
+   Public License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this file; see the file COPYING.  If not, write to the Free Software
+   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef _MAXQ20_H_
+#define  _MAXQ20_H_
+
+/* This file contains the opcode table for the MAXQ10/20 processor. The table
+   has been designed on the lines of the SH processor with the following 
+   fields:
+   (1) Instruction Name
+   (2) Instruction arguments description
+   (3) Description of the breakup of the opcode (1+7+8|8+8|1+4+4|1+7+1+3+4
+       |1+3+4+1+3+4|1+3+4+8|1+1+2+4+8)  
+   (4) Architecture supported
+
+   The Register table is also defined. It contains the following fields
+   (1) Register name
+   (2) Module Number
+   (3) Module Index
+   (4) Opcode
+   (5) Regtype
+
+   The Memory access table is defined containing the various opcodes for 
+   memory access containing the following fields
+   (1) Memory access Operand Name
+   (2) Memory access Operand opcode.  */
+
+# define MAXQ10 0x0001
+# define MAXQ20 0x0002
+# define MAX    (MAXQ10 | MAXQ20)
+
+/* This is for the NOP instruction Specify : 1st bit : NOP_FMT 1st byte:
+   NOP_DST 2nd byte: NOP_SRC.  */
+# define NOP_FMT  1
+# define NOP_SRC  0x3A
+# define NOP_DST  0x5A
+
+typedef enum
+{
+  ZEROBIT = 0x1,		/* A zero followed by 3 bits.  */
+  ONEBIT = 0x2,			/* A one followed by 3 bits.  */
+  REG = 0x4,			/* Register.  */
+  MEM = 0x8,			/* Memory access.  */
+  IMM = 0x10,			/* Immediate value.  */
+  DISP = 0x20,			/* Displacement value.  */
+  BIT = 0x40,			/* Bit value.  */
+  FMT = 0x80,			/* The format bit.  */
+  IMMBIT = 0x100,		/* An immediate bit.  */
+  FLAG = 0x200,			/* A Flag.  */
+  DATA = 0x400,			/* Symbol in the data section.  */
+  BIT_BUCKET = 0x800,		/* FOr BIT BUCKET.  */
+}
+UNKNOWN_OP;
+
+typedef enum
+{
+  NO_ARG = 0,
+  A_IMM = 0x01,			/* An 8 bit immediate value.  */
+  A_REG = 0x2,			/* An 8 bit source register.  */
+  A_MEM = 0x4,			/* A 7 bit destination register.  */
+  FLAG_C = 0x8,			/* Carry Flag.  */
+  FLAG_NC = 0x10,		/* No Carry (~C) flag.  */
+  FLAG_Z = 0x20,		/* Zero Flag.  */
+  FLAG_NZ = 0x40,		/* Not Zero Flag.  */
+  FLAG_S = 0x80,		/* Sign Flag.  */
+  FLAG_E = 0x100,		/* Equals Flag.  */
+  FLAG_NE = 0x200,		/* Not Equal Flag.  */
+  ACC_BIT = 0x400,		/* One of the 16 accumulator bits of the form Acc.<b>.  */
+  DST_BIT = 0x800,		/* One of the 8 bits of the specified SRC.  */
+  SRC_BIT = 0x1000,		/* One of the 8 bits of the specified source register.  */
+  A_BIT_0 = 0x2000,		/* #0.  */
+  A_BIT_1 = 0x4000,		/* #1.  */
+  A_DISP = 0x8000,		/* Displacement Operand.  */
+  A_DATA = 0x10000,		/* Data in the data section.  */
+  A_BIT_BUCKET = 0x200000,
+}
+MAX_ARG_TYPE;
+
+typedef struct
+{
+  char * name;			/* Name of the instruction.  */
+  unsigned int op_number;	/* Operand Number or the number of operands.  */
+  MAX_ARG_TYPE arg[2];		/* Types of operands.  */
+  int format;			/* Format bit.  */
+  int dst[2];			/* Destination in the move instruction.  */
+  int src[2];			/* Source in the move instruction.  */
+  int arch;			/* The Machine architecture.  */
+  unsigned int instr_id;	/* Added for decode and dissassembly.  */
+}
+MAXQ20_OPCODE_INFO;
+
+/* Structure for holding opcodes of the same name.  */
+typedef struct
+{
+  const MAXQ20_OPCODE_INFO *start;	/* The first opcode.  */
+  const MAXQ20_OPCODE_INFO *end;	/* The last opcode.  */
+}
+MAXQ20_OPCODES;
+
+/* The entry into the hash table will be of the type MAXX_OPCODES.  */
+
+/* The definition of the table.  */
+const MAXQ20_OPCODE_INFO op_table[] =
+{
+  /* LOGICAL OPERATIONS */
+  /* AND src : f001 1010 ssss ssss */
+  {"AND", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x1a, 0},
+   {REG | MEM | IMM | DISP, 0}, MAX, 0x11},
+  /* AND Acc.<b> : 1111 1010 bbbb 1010 */
+  {"AND", 1, {ACC_BIT, 0}, 1, {0x1a, 0}, {BIT, 0xa}, MAX, 0x39},
+  /* OR src : f010 1010 ssss ssss */
+  {"OR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x2a, 0},
+   {REG | MEM | IMM | DISP, 0}, MAX, 0x12},
+  /* OR Acc.<b> : 1010 1010 bbbb 1010 */
+  {"OR", 1, {ACC_BIT, 0}, 1, {0x2a, 0}, {BIT, 0xa}, MAX, 0x3A},
+  /* XOR src : f011 1010 ssss ssss */
+  {"XOR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3a, 0},
+   {REG | MEM | IMM | DISP, 0}, MAX, 0x13},
+  /* XOR Acc.<b> : 1011 1010 bbbb 1010 */
+  {"XOR", 1, {ACC_BIT, 0}, 1, {0x3a, 0}, {BIT, 0xa}, MAX, 0x3B},
+  /* LOGICAL OPERATIONS INVOLVING ONLY THE ACCUMULATOR */
+  /* CPL : 1000 1010 0001 1010 */
+  {"CPL", 0, {0, 0}, 1, {0x0a, 0}, {0x1a, 0}, MAX, 0x21},
+  /* CPL C : 1101 1010 0010 1010 */
+  {"CPL", 1, {FLAG_C, 0}, 1, {0x5a, 0}, {0x2a, 0}, MAX, 0x3D},
+  /* NEG : 1000 1010 1001 1010 */
+  {"NEG", 0, {0, 0}, 1, {0x0a, 0}, {0x9a, 0}, MAX, 0x29},
+  /* SLA : 1000 1010 0010 1010 */
+  {"SLA", 0, {0, 0}, 1, {0x0a, 0}, {0x2a, 0}, MAX, 0x22},
+  /* SLA2: 1000 1010 0011 1010 */
+  {"SLA2", 0, {0, 0}, 1, {0x0a, 0}, {0x3a, 0}, MAX, 0x23},
+  /* SLA4: 1000 1010 0110 1010 */
+  {"SLA4", 0, {0, 0}, 1, {0x0a, 0}, {0x6a, 0}, MAX, 0x26},
+  /* RL : 1000 1010 0100 1010 */
+  {"RL", 0, {0, 0}, 1, {0x0a, 0}, {0x4a, 0}, MAX, 0x24},
+  /* RLC : 1000 1010 0101 1010 */
+  {"RLC", 0, {0, 0}, 1, {0x0a, 0}, {0x5a, 0}, MAX, 0x25},
+  /* SRA : 1000 1010 1111 1010 */
+  {"SRA", 0, {0, 0}, 1, {0x0a, 0}, {0xfa, 0}, MAX, 0x2F},
+  /* SRA2: 1000 1010 1110 1010 */
+  {"SRA2", 0, {0, 0}, 1, {0x0a, 0}, {0xea, 0}, MAX, 0x2E},
+  /* SRA4: 1000 1010 1011 1010 */
+  {"SRA4", 0, {0, 0}, 1, {0x0a, 0}, {0xba, 0}, MAX, 0x2B},
+  /* SR : 1000 1010 1010 1010 */
+  {"SR", 0, {0, 0}, 1, {0x0a, 0}, {0xaa, 0}, MAX, 0x2A},
+  /* RR : 1000 1010 1100 1010 */
+  {"RR", 0, {0, 0}, 1, {0x0a, 0}, {0xca, 0}, MAX, 0x2C},
+  /* RRC : 1000 1010 1101 1010 */
+  {"RRC", 0, {0, 0}, 1, {0x0a, 0}, {0xda, 0}, MAX, 0x2D},
+  /* MATH OPERATIONS */
+  /* ADD src : f100 1010 ssss ssss */
+  {"ADD", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x4a, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0x14},
+  /* ADDC src : f110 1010 ssss ssss */
+  {"ADDC", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x6a, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0x16},
+  /* SUB src : f101 1010 ssss ssss */
+  {"SUB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x5a, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0x15},
+  /* SUBB src : f111 1010 ssss ssss */
+  {"SUBB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x7a, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0x17},
+  /* BRANCHING OPERATIONS */
+
+  /* DJNZ LC[0] src: f100 1101 ssss ssss */
+  {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4d, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0xA4},
+  /* DJNZ LC[1] src: f101 1101 ssss ssss */
+  {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5d, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0xA5},
+  /* CALL src : f011 1101 ssss ssss */
+  {"CALL", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3d, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0xA3},
+  /* JUMP src : f000 1100 ssss ssss */
+  {"JUMP", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x0c, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0x50},
+  /* JUMP C,src : f010 1100 ssss ssss */
+  {"JUMP", 2, {FLAG_C, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x2c, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0x52},
+  /* JUMP NC,src: f110 1100 ssss ssss */
+  {"JUMP", 2, {FLAG_NC, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x6c, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0x56},
+  /* JUMP Z,src : f001 1100 ssss ssss */
+  {"JUMP", 2, {FLAG_Z, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x1c, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0x51},
+  /* JUMP NZ,src: f101 1100 ssss ssss */
+  {"JUMP", 2, {FLAG_NZ, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5c, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0x55},
+  /* JUMP E,src : 0011 1100 ssss ssss */
+  {"JUMP", 2, {FLAG_E, A_IMM | A_DISP}, 0, {0x3c, 0}, {IMM, 0}, MAX, 0x53},
+  /* JUMP NE,src: 0111 1100 ssss ssss */
+  {"JUMP", 2, {FLAG_NE, A_IMM | A_DISP}, 0, {0x7c, 0}, {IMM, 0}, MAX, 0x57},
+  /* JUMP S,src : f100 1100 ssss ssss */
+  {"JUMP", 2, {FLAG_S, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4c, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0x54},
+  /* RET : 1000 1100 0000 1101 */
+  {"RET", 0, {0, 0}, 1, {0x0c, 0}, {0x0d, 0}, MAX, 0x68},
+  /* RET C : 1010 1100 0000 1101 */
+  {"RET", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x0d, 0}, MAX, 0x6A},
+  /* RET NC : 1110 1100 0000 1101 */
+  {"RET", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x0d, 0}, MAX, 0x6E},
+  /* RET Z : 1001 1100 0000 1101 */
+  {"RET", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x0d, 0}, MAX, 0x69},
+  /* RET NZ : 1101 1100 0000 1101 */
+  {"RET", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x0d, 0}, MAX, 0x6D},
+  /* RET S : 1100 1100 0000 1101 */
+  {"RET", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x0d, 0}, MAX, 0x6C},
+  /* RETI : 1000 1100 1000 1101 */
+  {"RETI", 0, {0, 0}, 1, {0x0c, 0}, {0x8d, 0}, MAX, 0x78},
+  /* ADDED ACCORDING TO NEW SPECIFICATION */
+
+  /* RETI C : 1010 1100 1000 1101 */
+  {"RETI", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x8d, 0}, MAX, 0x7A},
+  /* RETI NC : 1110 1100 1000 1101 */
+  {"RETI", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x8d, 0}, MAX, 0x7E},
+  /* RETI Z : 1001 1100 1000 1101 */
+  {"RETI", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x8d, 0}, MAX, 0x79},
+  /* RETI NZ : 1101 1100 1000 1101 */
+  {"RETI", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x8d, 0}, MAX, 0x7D},
+  /* RETI S : 1100 1100 1000 1101 */
+  {"RETI", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x8d, 0}, MAX, 0x7C},
+  /* MISCELLANEOUS INSTRUCTIONS */
+  /* CMP src : f111 1000 ssss ssss */
+  {"CMP", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x78, 0},
+   {REG | MEM | IMM | DISP, 0}, MAX, 0xD7},
+  /* DATA TRANSFER OPERATIONS */
+  /* XCH : 1000 1010 1000 1010 */
+  {"XCH", 0, {0, 0}, 1, {0x0a, 0}, {0x8a, 0}, MAXQ20, 0x28},
+  /* XCHN : 1000 1010 0111 1010 */
+  {"XCHN", 0, {0, 0}, 1, {0x0a, 0}, {0x7a, 0}, MAX, 0x27},
+  /* PUSH src : f000 1101 ssss ssss */
+  {"PUSH", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x0d, 0},
+   {IMM | REG | MEM | DISP, 0}, MAX, 0xA0},
+  /* POP dst : 1ddd dddd 0000 1101 */
+  {"POP", 1, {A_REG, 0}, 1, {REG, 0}, {0x0d, 0}, MAX, 0xB0},
+  /* Added according to new spec */
+  /* POPI dst : 1ddd dddd 1000 1101 */
+  {"POPI", 1, {A_REG, 0}, 1, {REG, 0}, {0x8d, 0}, MAX, 0xC0},
+  /* MOVE dst,src: fddd dddd ssss ssss */
+  {"MOVE", 2, {A_REG | A_MEM, A_REG | A_IMM | A_MEM | A_DATA | A_DISP}, FMT,
+   {REG | MEM, 0}, {REG | IMM | MEM | DATA | A_DISP, 0}, MAX, 0x80},
+  /* BIT OPERATIONS */
+  /* MOVE C,Acc.<b> : 1110 1010 bbbb 1010 */
+  {"MOVE", 2, {FLAG_C, ACC_BIT}, 1, {0x6a, 0}, {BIT, 0xa}, MAX, 0x3E},
+  /* MOVE C,#0 : 1101 1010 0000 1010 */
+  {"MOVE", 2, {FLAG_C, A_BIT_0}, 1, {0x5a, 0}, {0x0a, 0}, MAX, 0x3D},
+  /* MOVE C,#1 : 1101 1010 0001 1010 */
+  {"MOVE", 2, {FLAG_C, A_BIT_1}, 1, {0x5a, 0}, {0x1a, 0}, MAX, 0x3D},
+  /* MOVE Acc.<b>,C : 1111 1010 bbbb 1010 */
+  {"MOVE", 2, {ACC_BIT, FLAG_C}, 1, {0x7a, 0}, {BIT, 0xa}, MAX, 0x3F},
+  /* MOVE dst.<b>,#0 : 1ddd dddd 0bbb 0111 */
+  {"MOVE", 2, {DST_BIT, A_BIT_0}, 1, {REG, 0}, {ZEROBIT, 0x7}, MAX, 0x40},
+  /* MOVE dst.<b>,#1 : 1ddd dddd 1bbb 0111 */
+  {"MOVE", 2, {DST_BIT, A_BIT_1}, 1, {REG, 0}, {ONEBIT, 0x7}, MAX, 0x41},
+  /* MOVE C,src.<b> : fbbb 0111 ssss ssss */
+  {"MOVE", 2, {FLAG_C, SRC_BIT}, FMT, {BIT, 0x7}, {REG, 0}, MAX, 0x97},
+  /* NOP : 1101 1010 0011 1010 */
+  {"NOP", 0, {0, 0}, NOP_FMT, {NOP_DST, 0}, {NOP_SRC, 0}, MAX, 0x3D},
+  {NULL, 0, {0, 0}, 0, {0, 0}, {0, 0}, 0, 0x00}
+};
+
+/* All the modules.  */
+
+#define	MOD0 0x0
+#define MOD1 0x1
+#define MOD2 0x2
+#define MOD3 0x3
+#define MOD4 0x4
+#define MOD5 0x5
+#define MOD6 0x6
+#define MOD7 0x7
+#define MOD8 0x8
+#define MOD9 0x9
+#define MODA 0xa
+#define MODB 0xb
+#define MODC 0xc
+#define MODD 0xd
+#define MODE 0xe
+#define MODF 0xf
+
+/* Added according to new specification.  */
+#define MOD10 0x10
+#define MOD11 0x11
+#define MOD12 0x12
+#define MOD13 0x13
+#define MOD14 0x14
+#define MOD15 0x15
+#define MOD16 0x16
+#define MOD17 0x17
+#define MOD18 0x18
+#define MOD19 0x19
+#define MOD1A 0x1a
+#define MOD1B 0x1b
+#define MOD1C 0x1c
+#define MOD1D 0x1d
+#define MOD1E 0x1e
+#define MOD1F 0x1f
+
+/* - Peripheral Register Modules - */
+/* Serial Register Modules.  */
+#define CTRL		MOD8	/* For the module containing the control registers.  */
+#define ACC	 	MOD9	/* For the module containing the 16 accumulators.  */
+#define Act_ACC 	MODA	/* For the module containing the active accumulator.  */
+#define PFX  		MODB	/* For the module containing the prefix registers.  */
+#define IP	 	MODC	/* For the module containing the instruction pointer register.  */
+#define SPIV 		MODD	/* For the module containing the stack pointer and the interrupt vector.  */
+#define	LC 		MODD	/* For the module containing the loop counters and HILO registers.  */
+#define DP 		MODF	/* For the module containig the data pointer registers.  */
+
+/* Register Types.  */
+typedef enum _Reg_type
+{ Reg_8R,			/* 8 bit register. read only.  */
+  Reg_16R,			/* 16 bit register, read only.  */
+  Reg_8W,			/* 8 bit register, both read and write.  */
+  Reg_16W			/* 16 bit register, both read and write.  */
+}
+Reg_type;
+
+/* Register Structure.  */
+typedef struct reg
+{
+  char *reg_name;		/* Register name.  */
+  short int Mod_name;		/* The module name.  */
+  short int Mod_index;		/* The module index.  */
+  int opcode;			/* The opcode of the register.  */
+  Reg_type rtype;		/* 8 bit/16 bit and read only/read write.  */
+  int arch;			/* The Machine architecture.  */
+}
+reg_entry;
+
+reg_entry *new_reg_table = NULL;
+int num_of_reg = 0;
+
+typedef struct
+{
+  char *rname;
+  int rindex;
+}
+reg_index;
+
+/* Register Table description.  */
+reg_entry system_reg_table[] =
+{
+  /* Serial Registers */
+  /* MODULE 8 Registers : I call them the control registers.  */
+  /* Accumulator Pointer CTRL[0h] */
+  {
+   "AP", CTRL, 0x0, 0x00 | CTRL, Reg_8W, MAX},
+  /* Accumulator Pointer Control Register : CTRL[1h] */
+
+  {
+   "APC", CTRL, 0x1, 0x10 | CTRL, Reg_8W, MAX},
+  /* Processor Status Flag Register CTRL[4h] Note: Bits 6 and 7 read only */
+  {
+   "PSF", CTRL, 0x4, 0x40 | CTRL, Reg_8W, MAX},
+  /* Interrupt and Control Register : CTRL[5h] */
+  {
+   "IC", CTRL, 0x5, 0x50 | CTRL, Reg_8W, MAX},
+  /* Interrupt Mask Register : CTRL[6h] */
+  {
+   "IMR", CTRL, 0x6, 0x60 | CTRL, Reg_8W, MAX},
+  /* Interrupt System Control : CTRL[8h] */
+  {
+   "SC", CTRL, 0x8, 0x80 | CTRL, Reg_8W, MAX},
+  /* Interrupt Identification Register : CTRL[Bh] */
+  {
+   "IIR", CTRL, 0xb, 0xb0 | CTRL, Reg_8R, MAX},
+  /* System Clock Control Register : CTRL[Eh] Note: Bit 5 is read only */
+  {
+   "CKCN", CTRL, 0xe, 0xe0 | CTRL, Reg_8W, MAX},
+  /* Watchdog Control Register : CTRL[Fh] */
+  {
+   "WDCN", CTRL, 0xf, 0xf0 | CTRL, Reg_8W, MAX},
+  /* The 16 accumulator registers : ACC[0h-Fh] */
+  {
+   "A[0]", ACC, 0x0, 0x00 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[1]", ACC, 0x1, 0x10 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[2]", ACC, 0x2, 0x20 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[3]", ACC, 0x3, 0x30 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[4]", ACC, 0x4, 0x40 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[5]", ACC, 0x5, 0x50 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[6]", ACC, 0x6, 0x60 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[7]", ACC, 0x7, 0x70 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[8]", ACC, 0x8, 0x80 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[9]", ACC, 0x9, 0x90 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_16W, MAXQ20},
+  {
+   "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_16W, MAXQ20},
+  /* The Active Accumulators : Act_Acc[0h-1h] */
+  {
+   "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_16W, MAXQ20},
+  {
+   "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_16W, MAXQ20},
+  /* The 16 accumulator registers : ACC[0h-Fh] */
+  {
+   "A[0]", ACC, 0x0, 0x00 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[1]", ACC, 0x1, 0x10 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[2]", ACC, 0x2, 0x20 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[3]", ACC, 0x3, 0x30 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[4]", ACC, 0x4, 0x40 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[5]", ACC, 0x5, 0x50 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[6]", ACC, 0x6, 0x60 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[7]", ACC, 0x7, 0x70 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[8]", ACC, 0x8, 0x80 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[9]", ACC, 0x9, 0x90 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_8W, MAXQ10},
+  {
+   "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_8W, MAXQ10},
+  /* The Active Accumulators : Act_Acc[0h-1h] */
+  {
+   "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_8W, MAXQ10},
+  /* The Active Accumulators : Act_Acc[0h-1h] */
+  {
+   "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_8W, MAXQ10},
+  /* The Prefix Registers : PFX[0h,2h] */
+  {
+   "PFX[0]", PFX, 0x0, 0x00 | PFX, Reg_16W, MAX},
+  {
+   "PFX[1]", PFX, 0x1, 0x10 | PFX, Reg_16W, MAX},
+  {
+   "PFX[2]", PFX, 0x2, 0x20 | PFX, Reg_16W, MAX},
+  {
+   "PFX[3]", PFX, 0x3, 0x30 | PFX, Reg_16W, MAX},
+  {
+   "PFX[4]", PFX, 0x4, 0x40 | PFX, Reg_16W, MAX},
+  {
+   "PFX[5]", PFX, 0x5, 0x50 | PFX, Reg_16W, MAX},
+  {
+   "PFX[6]", PFX, 0x6, 0x60 | PFX, Reg_16W, MAX},
+  {
+   "PFX[7]", PFX, 0x7, 0x70 | PFX, Reg_16W, MAX},
+  /* The Instruction Pointer Registers : IP[0h,8h] */
+  {
+   "IP", IP, 0x0, 0x00 | IP, Reg_16W, MAX},
+  /* The Stack Pointer Registers : SPIV[1h,9h] */
+  {
+   "SP", SPIV, 0x1, 0x10 | SPIV, Reg_16W, MAX},
+  /* The Interrupt Vector Registers : SPIV[2h,Ah] */
+  {
+   "IV", SPIV, 0x2, 0x20 | SPIV, Reg_16W, MAX},
+  /* ADDED for New Specification */
+
+  /* The Loop Counter Registers : LCHILO[0h-4h,8h-Bh] */
+  {
+   "LC[0]", LC, 0x6, 0x60 | LC, Reg_16W, MAX},
+  {
+   "LC[1]", LC, 0x7, 0x70 | LC, Reg_16W, MAX},
+  /* MODULE Eh Whole Column has changed */
+
+  {
+   "OFFS", MODE, 0x3, 0x30 | MODE, Reg_8W, MAX},
+  {
+   "DPC", MODE, 0x4, 0x40 | MODE, Reg_16W, MAX},
+  {
+   "GR", MODE, 0x5, 0x50 | MODE, Reg_16W, MAX},
+  {
+   "GRL", MODE, 0x6, 0x60 | MODE, Reg_8W, MAX},
+  {
+   "BP", MODE, 0x7, 0x70 | MODE, Reg_16W, MAX},
+  {
+   "GRS", MODE, 0x8, 0x80 | MODE, Reg_16W, MAX},
+  {
+   "GRH", MODE, 0x9, 0x90 | MODE, Reg_8W, MAX},
+  {
+   "GRXL", MODE, 0xA, 0xA0 | MODE, Reg_8R, MAX},
+  {
+   "FP", MODE, 0xB, 0xB0 | MODE, Reg_16R, MAX},
+  /* The Data Pointer registers : DP[3h,7h,Bh,Fh] */
+  {
+   "DP[0]", DP, 0x3, 0x30 | DP, Reg_16W, MAX},
+  {
+   "DP[1]", DP, 0x7, 0x70 | DP, Reg_16W, MAX},
+};
+typedef struct
+{
+  char *name;
+  int type;
+}
+match_table;
+
+#define GPIO0   	0x00	/* Gerneral Purpose I/O Module 0.  */
+#define GPIO1   	0x01	/* Gerneral Purpose I/O Module 1.  */
+#define RTC	  	0x00	/* Real Time Clock Module.  */
+#define MAC	  	0x02	/* Hardware Multiplier Module.  */
+#define SER0	  	0x02	/* Contains the UART Registers.  */
+#define SPI	  	0x03	/* Serial Pheripheral Interface Module.  */
+#define OWBM  		0x03	/* One Wire Bus Module.  */
+#define SER1	  	0x03	/* Contains the UART Registers.  */
+#define TIMER20		0x03	/* Timer Counter Module 2.  */
+#define TIMER21		0x04	/* Timer Counter Module 2.  */
+#define JTAGD 		0x03	/* In-Circuit Debugging Support.  */
+#define LCD		0x03	/* LCD register Modules.  */
+
+/* Plugable modules register table f.  */
+
+reg_entry peripheral_reg_table[] =
+{
+  /* -------- The GPIO Module Registers -------- */
+  /* Port n Output Registers : GPIO[0h-4h] */
+  {
+   "PO0", GPIO0, 0x0, 0x00 | MOD0, Reg_8W, MAX},
+  {
+   "PO1", GPIO0, 0x1, 0x10 | MOD0, Reg_8W, MAX},
+  {
+   "PO2", GPIO0, 0x2, 0x20 | MOD0, Reg_8W, MAX},
+  {
+   "PO3", GPIO0, 0x3, 0x30 | MOD0, Reg_8W, MAX},
+  /* External Interrupt Flag Register : GPIO[6h] */
+  {
+   "EIF0", GPIO0, 0x6, 0x60 | MOD0, Reg_8W, MAX},
+  /* External Interrupt Enable Register : GPIO[7h] */
+  {
+   "EIE0", GPIO0, 0x7, 0x70 | MOD0, Reg_8W, MAX},
+  /* Port n Input Registers : GPIO[8h-Bh] */
+  {
+   "PI0", GPIO0, 0x8, 0x80 | MOD0, Reg_8W, MAX},
+  {
+   "PI1", GPIO0, 0x9, 0x90 | MOD0, Reg_8W, MAX},
+  {
+   "PI2", GPIO0, 0xa, 0xa0 | MOD0, Reg_8W, MAX},
+  {
+   "PI3", GPIO0, 0xb, 0xb0 | MOD0, Reg_8W, MAX},
+  {
+   "EIES0", GPIO0, 0xc, 0xc0 | MOD0, Reg_8W, MAX},
+  /* Port n Direction Registers : GPIO[Ch-Fh] */
+  {
+   "PD0", GPIO0, 0x10, 0x10 | MOD0, Reg_8W, MAX},
+  {
+   "PD1", GPIO0, 0x11, 0x11 | MOD0, Reg_8W, MAX},
+  {
+   "PD2", GPIO0, 0x12, 0x12 | MOD0, Reg_8W, MAX},
+  {
+   "PD3", GPIO0, 0x13, 0x13 | MOD0, Reg_8W, MAX},
+  /* -------- Real Time Counter Module RTC -------- */
+  /* RTC Control Register : [01h] */
+  {
+   "RCNT", RTC, 0x19, 0x19 | MOD0, Reg_16W, MAX},
+  /* RTC Seconds High [02h] */
+  {
+   "RTSS", RTC, 0x1A, 0x1A | MOD0, Reg_8W, MAX},
+  /* RTC Seconds Low [03h] */
+  {
+   "RTSH", RTC, 0x1b, 0x1b | MOD0, Reg_16W, MAX},
+  /* RTC Subsecond Register [04h] */
+  {
+   "RTSL", RTC, 0x1C, 0x1C | MOD0, Reg_16W, MAX},
+  /* RTC Alarm seconds high [05h] */
+  {
+   "RSSA", RTC, 0x1D, 0x1D | MOD0, Reg_8W, MAX},
+  /* RTC Alarm seconds high [06h] */
+  {
+   "RASH", RTC, 0x1E, 0x1E | MOD0, Reg_8W, MAX},
+  /* RTC Subsecond Alarm Register [07h] */
+  {
+   "RASL", RTC, 0x1F, 0x1F | MOD0, Reg_16W, MAX},
+  /* -------- The GPIO Module Registers -------- */
+  /* Port n Output Registers : GPIO[0h-4h] */
+  {
+   "PO4", GPIO1, 0x0, 0x00 | MOD1, Reg_8W, MAX},
+  {
+   "PO5", GPIO1, 0x1, 0x10 | MOD1, Reg_8W, MAX},
+  {
+   "PO6", GPIO1, 0x2, 0x20 | MOD1, Reg_8W, MAX},
+  {
+   "PO7", GPIO1, 0x3, 0x30 | MOD1, Reg_8W, MAX},
+  /* External Interrupt Flag Register : GPIO[6h] */
+  {
+   "EIF1", GPIO0, 0x6, 0x60 | MOD1, Reg_8W, MAX},
+  /* External Interrupt Enable Register : GPIO[7h] */
+  {
+   "EIE1", GPIO0, 0x7, 0x70 | MOD1, Reg_8W, MAX},
+  /* Port n Input Registers : GPIO[8h-Bh] */
+  {
+   "PI4", GPIO1, 0x8, 0x80 | MOD1, Reg_8W, MAX},
+  {
+   "PI5", GPIO1, 0x9, 0x90 | MOD1, Reg_8W, MAX},
+  {
+   "PI6", GPIO1, 0xa, 0xa0 | MOD1, Reg_8W, MAX},
+  {
+   "PI7", GPIO1, 0xb, 0xb0 | MOD1, Reg_8W, MAX},
+  {
+   "EIES1", GPIO1, 0xc, 0xc0 | MOD1, Reg_8W, MAX},
+  /* Port n Direction Registers : GPIO[Ch-Fh] */
+  {
+   "PD4", GPIO1, 0x10, 0x10 | MOD1, Reg_8W, MAX},
+  {
+   "PD5", GPIO1, 0x11, 0x11 | MOD1, Reg_8W, MAX},
+  {
+   "PD6", GPIO1, 0x12, 0x12 | MOD1, Reg_8W, MAX},
+  {
+   "PD7", GPIO1, 0x13, 0x13 | MOD1, Reg_8W, MAX},
+#if 0
+  /* Supply Boltage Check Register */
+  {
+   "SVS", GPIO1, 0x1e, 0x1e | GPIO1, Reg_8W, MAX},
+  /* Wake up output register */
+  {
+   "WK0", GPIO1, 0x1f, 0x1f | GPIO1, Reg_8W, MAX},
+#endif /* */
+
+  /* -------- MAC Hardware multiplier module -------- */
+  /* MAC Hardware Multiplier control register: [01h] */
+  {
+   "MCNT", MAC, 0x1, 0x10 | MOD2, Reg_8W, MAX},
+  /* MAC Multiplier Operand A Register [02h] */
+  {
+   "MA", MAC, 0x2, 0x20 | MOD2, Reg_16W, MAX},
+  /* MAC Multiplier Operand B Register [03h] */
+  {
+   "MB", MAC, 0x3, 0x30 | MOD2, Reg_16W, MAX},
+  /* MAC Multiplier Accumulator 2 Register [04h] */
+  {
+   "MC2", MAC, 0x4, 0x40 | MOD2, Reg_16W, MAX},
+  /* MAC Multiplier Accumulator 1 Register [05h] */
+  {
+   "MC1", MAC, 0x5, 0x50 | MOD2, Reg_16W, MAX},
+  /* MAC Multiplier Accumulator 0 Register [06h] */
+  {
+   "MC0", MAC, 0x6, 0x60 | MOD2, Reg_16W, MAX},
+  /* -------- The Serial I/O module SER -------- */
+  /* UART registers */
+  /* Serial Port Control Register : SER[6h] */
+  {
+   "SCON0", SER0, 0x6, 0x60 | MOD2, Reg_8W, MAX},
+  /* Serial Data Buffer Register : SER[7h] */
+  {
+   "SBUF0", SER0, 0x7, 0x70 | MOD2, Reg_8W, MAX},
+  /* Serial Port Mode Register : SER[4h] */
+  {
+   "SMD0", SER0, 0x8, 0x80 | MOD2, Reg_8W, MAX},
+  /* Serial Port Phase Register : SER[4h] */
+  {
+   "PR0", SER1, 0x9, 0x90 | MOD2, Reg_16W, MAX},
+  /* ------ LCD Display Module ---------- */
+  {
+   "LCRA", LCD, 0xd, 0xd0 | MOD2, Reg_16W, MAX},
+  {
+   "LCFG", LCD, 0xe, 0xe0 | MOD2, Reg_8W, MAX},
+  {
+   "LCD16", LCD, 0xf, 0xf0 | MOD2, Reg_8W, MAX},
+  {
+   "LCD0", LCD, 0x10, 0x10 | MOD2, Reg_8W, MAX},
+  {
+   "LCD1", LCD, 0x11, 0x11 | MOD2, Reg_8W, MAX},
+  {
+   "LCD2", LCD, 0x12, 0x12 | MOD2, Reg_8W, MAX},
+  {
+   "LCD3", LCD, 0x13, 0x13 | MOD2, Reg_8W, MAX},
+  {
+   "LCD4", LCD, 0x14, 0x14 | MOD2, Reg_8W, MAX},
+  {
+   "LCD5", LCD, 0x15, 0x15 | MOD2, Reg_8W, MAX},
+  {
+   "LCD6", LCD, 0x16, 0x16 | MOD2, Reg_8W, MAX},
+  {
+   "LCD7", LCD, 0x17, 0x17 | MOD2, Reg_8W, MAX},
+  {
+   "LCD8", LCD, 0x18, 0x18 | MOD2, Reg_8W, MAX},
+  {
+   "LCD9", LCD, 0x19, 0x19 | MOD2, Reg_8W, MAX},
+  {
+   "LCD10", LCD, 0x1a, 0x1a | MOD2, Reg_8W, MAX},
+  {
+   "LCD11", LCD, 0x1b, 0x1b | MOD2, Reg_8W, MAX},
+  {
+   "LCD12", LCD, 0x1c, 0x1c | MOD2, Reg_8W, MAX},
+  {
+   "LCD13", LCD, 0x1d, 0x1d | MOD2, Reg_8W, MAX},
+  {
+   "LCD14", LCD, 0x1e, 0x1e | MOD2, Reg_8W, MAX},
+  {
+   "LCD15", LCD, 0x1f, 0x1f | MOD2, Reg_8W, MAX},
+  /* -------- SPI registers -------- */
+  /* SPI data buffer Register : SER[7h] */
+  {
+   "SPIB", SPI, 0x5, 0x50 | MOD3, Reg_16W, MAX},
+  /* SPI Control Register : SER[8h] Note : Bit 7 is a read only bit */
+  {
+   "SPICN", SPI, 0x15, 0x15 | MOD3, Reg_8W, MAX},
+  /* SPI Configuration Register : SER[9h] Note : Bits 4,3 and 2 are read
+     only.  */
+  {
+   "SPICF", SPI, 0x16, 0x16 | MOD3, Reg_8W, MAX},
+  /* SPI Clock Register : SER[Ah] */
+  {
+   "SPICK", SPI, 0x17, 0x17 | MOD3, Reg_8W, MAX},
+  /* -------- One Wire Bus Master OWBM -------- */
+  /* OWBM One Wire address Register register: [01h] */
+  {
+   "OWA", OWBM, 0x13, 0x13 | MOD3, Reg_8W, MAX},
+  /* OWBM One Wire Data register: [02h] */
+  {
+   "OWD", OWBM, 0x14, 0x14 | MOD3, Reg_8W, MAX},
+  /* -------- The Serial I/O module SER -------- */
+  /* UART registers */
+  /* Serial Port Control Register : SER[6h] */
+  {
+   "SCON1", SER1, 0x6, 0x60 | MOD3, Reg_8W, MAX},
+  /* Serial Data Buffer Register : SER[7h] */
+  {
+   "SBUF1", SER1, 0x7, 0x70 | MOD3, Reg_8W, MAX},
+  /* Serial Port Mode Register : SER[4h] */
+  {
+   "SMD1", SER1, 0x8, 0x80 | MOD3, Reg_8W, MAX},
+  /* Serial Port Phase Register : SER[4h] */
+  {
+   "PR1", SER1, 0x9, 0x90 | MOD3, Reg_16W, MAX},
+  /* -------- Timer/Counter 2 Module -------- */
+  /* Timer 2 configuration Register : TC[3h] */
+  {
+   "T2CNA0", TIMER20, 0x0, 0x00 | MOD3, Reg_8W, MAX},
+  {
+   "T2H0", TIMER20, 0x1, 0x10 | MOD3, Reg_8W, MAX},
+  {
+   "T2RH0", TIMER20, 0x2, 0x20 | MOD3, Reg_8W, MAX},
+  {
+   "T2CH0", TIMER20, 0x3, 0x30 | MOD3, Reg_8W, MAX},
+  {
+   "T2CNB0", TIMER20, 0xc, 0xc0 | MOD3, Reg_8W, MAX},
+  {
+   "T2V0", TIMER20, 0xd, 0xd0 | MOD3, Reg_16W, MAX},
+  {
+   "T2R0", TIMER20, 0xe, 0xe0 | MOD3, Reg_16W, MAX},
+  {
+   "T2C0", TIMER20, 0xf, 0xf0 | MOD3, Reg_16W, MAX},
+  {
+   "T2CFG0", TIMER20, 0x10, 0x10 | MOD3, Reg_8W, MAX},
+  /* Timer 2-1 configuration Register : TC[4h] */
+
+  {
+   "T2CNA1", TIMER21, 0x0, 0x00 | MOD4, Reg_8W, MAX},
+  {
+   "T2H1", TIMER21, 0x1, 0x10 | MOD4, Reg_8W, MAX},
+  {
+   "T2RH1", TIMER21, 0x2, 0x20 | MOD4, Reg_8W, MAX},
+  {
+   "T2CH1", TIMER21, 0x3, 0x30 | MOD4, Reg_8W, MAX},
+  {
+   "T2CNA2", TIMER21, 0x4, 0x40 | MOD4, Reg_8W, MAX},
+  {
+   "T2H2", TIMER21, 0x5, 0x50 | MOD4, Reg_8W, MAX},
+  {
+   "T2RH2", TIMER21, 0x6, 0x60 | MOD4, Reg_8W, MAX},
+  {
+   "T2CH2", TIMER21, 0x7, 0x70 | MOD4, Reg_8W, MAX},
+  {
+   "T2CNB1", TIMER21, 0x8, 0x80 | MOD4, Reg_8W, MAX},
+  {
+   "T2V1", TIMER21, 0x9, 0x90 | MOD4, Reg_16W, MAX},
+  {
+   "T2R1", TIMER21, 0xa, 0xa0 | MOD4, Reg_16W, MAX},
+  {
+   "T2C1", TIMER21, 0xb, 0xb0 | MOD4, Reg_16W, MAX},
+  {
+   "T2CNB2", TIMER21, 0xc, 0xc0 | MOD4, Reg_8W, MAX},
+  {
+   "T2V2", TIMER21, 0xd, 0xd0 | MOD4, Reg_16W, MAX},
+  {
+   "T2R2", TIMER21, 0xe, 0xe0 | MOD4, Reg_16W, MAX},
+  {
+   "T2C2", TIMER21, 0xf, 0xf0 | MOD4, Reg_16W, MAX},
+  {
+   "T2CFG1", TIMER21, 0x10, 0x10 | MOD4, Reg_8W, MAX},
+  {
+   "T2CFG2", TIMER21, 0x11, 0x11 | MOD4, Reg_8W, MAX},
+  {
+   NULL, 0, 0, 0, 0, 0}
+};
+
+/* Memory access argument.  */
+struct mem_access
+{
+  char *name;			/* Name of the Memory access operand.  */
+  int opcode;			/* Its corresponding opcode.  */
+};
+typedef struct mem_access mem_access;
+
+/* The Memory table for accessing the data memory through particular registers.  */
+struct mem_access mem_table[] =
+{
+  /* The Pop Operation on the stack.  */
+  {"@SP--", 0x0d},
+  /* Data Pointer 0 */
+  {"@DP[0]", 0x0f},
+  /* Data Ponter 1 */
+  {"@DP[1]", 0x4f},
+  /* Data Pointer 0 post increment */
+  {"@DP[0]++", 0x1f},
+  /* Data Pointer 1 post increment */
+  {"@DP[1]++", 0x5f},
+  /* Data Pointer 0 post decrement */
+  {"@DP[0]--", 0x2f},
+  /* Data Pointer 1 post decrement */
+  {"@DP[1]--", 0x6f},
+  /* ADDED According to New Specification.  */
+
+  {"@BP[OFFS]", 0x0E},
+  {"@BP[OFFS++]", 0x1E},
+  {"@BP[OFFS--]", 0x2E},
+  {"NUL", 0x76},
+  {"@++SP", 0x0D},
+  {"@BP[++OFFS]", 0x1E},
+  {"@BP[--OFFS]", 0x2E},
+  {"@++DP[0]", 0x1F},
+  {"@++DP[1]", 0x5F}, {"@--DP[0]", 0x2F}, {"@--DP[1]", 0x6F}
+};
+
+/* Register bit argument.  */
+struct reg_bit
+{
+  reg_entry *reg;
+  int bit;
+};
+typedef struct reg_bit reg_bit;
+
+/* There are certain names given to particular bits of some registers.
+   These will be taken care of here.  */
+struct bit_name
+{
+  char *name;
+  char *reg_bit;
+};
+typedef struct bit_name bit_name;
+
+bit_name bit_table[] =
+{
+  {
+   "RI", "SCON.0"},
+  /* FOr APC */
+  {
+   "MOD0", "APC.0"},
+  {
+   "MOD1", "APC.1"},
+  {
+   "MOD2", "APC.2"},
+  {
+   "IDS", "APC.6"},
+  {
+   "CLR", "APC.6"},
+  /* For PSF */
+  {
+   "E", "PSF.0"},
+  {
+   "C", "PSF.1"},
+  {
+   "OV", "PSF.2"},
+  {
+   "S", "PSF.6"},
+  {
+   "Z", "PSF.7"},
+  /* For IC */
+
+  {
+   "IGE", "IC.0"},
+  {
+   "INS", "IC.1"},
+  {
+   "CGDS", "IC.5"},
+  /* For IMR */
+
+  {
+   "IM0", "IMR.0"},
+  {
+   "IM1", "IMR.1"},
+  {
+   "IM2", "IMR.2"},
+  {
+   "IM3", "IMR.3"},
+  {
+   "IM4", "IMR.4"},
+  {
+   "IM5", "IMR.5"},
+  {
+   "IMS", "IMR.7"},
+  /* For SC */
+  {
+   "PWL", "SC.1"},
+  {
+   "ROD", "SC.2"},
+  {
+   "UPA", "SC.3"},
+  {
+   "CDA0", "SC.4"},
+  {
+   "CDA1", "SC.5"},
+  /* For IIR */
+
+  {
+   "II0", "IIR.0"},
+  {
+   "II1", "IIR.1"},
+  {
+   "II2", "IIR.2"},
+  {
+   "II3", "IIR.3"},
+  {
+   "II4", "IIR.4"},
+  {
+   "II5", "IIR.5"},
+  {
+   "IIS", "IIR.7"},
+  /* For CKCN */
+
+  {
+   "CD0", "CKCN.0"},
+  {
+   "CD1", "CKCN.1"},
+  {
+   "PMME", "CKCN.2"},
+  {
+   "SWB", "CKCN.3"},
+  {
+   "STOP", "CKCN.4"},
+  {
+   "RGMD", "CKCN.5"},
+  {
+   "RGSL", "CKCN.6"},
+  /* For WDCN */
+
+  {
+   "RWT", "WDCN.0"},
+  {
+   "EWT", "WDCN.1"},
+  {
+   "WTRF", "WDCN.2"},
+  {
+   "WDIF", "WDCN.3"},
+  {
+   "WD0", "WDCN.4"},
+  {
+   "WD1", "WDCN.5"},
+  {
+   "EWDI", "WDCN.6"},
+  {
+   "POR", "WDCN.7"},
+  /* For DPC */
+
+  {
+   "DPS0", "DPC.0"},
+  {
+   "DPS1", "DPC.1"},
+  {
+   "WBS0", "DPC.2"},
+  {
+   "WBS1", "DPC.3"},
+  {
+   "WBS2", "DPC.4"},
+
+   /* For SCON */  
+  {
+   "TI", "SCON.1"},
+  {
+   "RB8", "SCON.2"},
+  {
+   "TB8", "SCON.3"},
+  {
+   "REN", "SCON.4"},
+  {
+   "SM2", "SCON.5"},
+  {
+   "SM1", "SCON.6"},
+  {
+   "SM0", "SCON.7"},
+  {
+   "FE", "SCON.7"}
+};
+
+const char *LSInstr[] =
+{
+  "LJUMP", "SJUMP", "LDJNZ", "SDJNZ", "LCALL", "SCALL", "JUMP",
+  "DJNZ", "CALL", NULL
+};
+
+typedef enum
+{
+  DST,
+  SRC,
+  BOTH,
+}
+type1;
+
+struct mem_access_syntax
+{
+  char name[12];		/* Name of the Memory access operand.  */
+  type1 type;
+  char *invalid_op[5];
+};
+typedef struct mem_access_syntax mem_access_syntax;
+
+/* The Memory Access table for accessing the data memory through particular
+   registers.  */
+const mem_access_syntax mem_access_syntax_table[] =
+{
+  {
+   "@SP--", SRC,
+   {
+    NULL, NULL, NULL, NULL, NULL}},
+  /* Data Pointer 0 */
+  {
+   "@DP[0]", BOTH,
+   {
+    "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}},
+  /* Data Ponter 1 */
+  {
+   "@DP[1]", BOTH,
+   {
+    "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}},
+  /* Data Pointer 0 post increment */
+  {
+   "@DP[0]++", SRC,
+   {
+    NULL, NULL, NULL, NULL, NULL}},
+  /* Data Pointer 1 post increment */
+  {
+   "@DP[1]++", SRC,
+   {
+    NULL, NULL, NULL, NULL, NULL}},
+  /* Data Pointer 0 post decrement */
+  {
+   "@DP[0]--", SRC,
+   {
+    NULL, NULL, NULL, NULL, NULL}},
+  /* Data Pointer 1 post decrement */
+  {
+   "@DP[1]--", SRC,
+   {
+    NULL, NULL, NULL, NULL, NULL}},
+  /* ADDED According to New Specification */
+
+  {
+   "@BP[OFFS]", BOTH,
+   {
+    "@BP[OFFS++]", "@BP[OFFS--]", NULL, NULL, NULL}},
+  {
+   "@BP[OFFS++]", SRC,
+   {
+    NULL, NULL, NULL, NULL, NULL}},
+  {
+   "@BP[OFFS--]", SRC,
+   {
+    NULL, NULL, NULL, NULL, NULL}},
+  {
+   "NUL", DST,
+   {
+    NULL, NULL, NULL, NULL, NULL}},
+  {
+   "@++SP", DST,
+   {
+    NULL, NULL, NULL, NULL, NULL}},
+  {
+   "@BP[++OFFS]", DST,
+   {
+    "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}},
+  {
+   "@BP[--OFFS]", DST,
+   {
+    "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}},
+  {
+   "@++DP[0]", DST,
+   {
+    "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}},
+  {
+   "@++DP[1]", DST,
+   {
+    "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}},
+  {
+   "@--DP[0]", DST,
+   {
+    "@DP[0]++", "@DP[0]--", NULL, NULL, NULL}},
+  {
+   "@--DP[1]", DST,
+   {
+    "@DP[1]++", "@DP[1]--", NULL, NULL, NULL}}
+};
+
+#endif
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index b7d4cba02c..eb2ee2db1a 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -116,6 +116,7 @@ CFILES = \
 	m68k-dis.c \
 	m68k-opc.c \
 	m88k-dis.c \
+	maxq-dis.c \
 	mcore-dis.c \
 	mips-dis.c \
 	mips-opc.c \
@@ -233,6 +234,7 @@ ALL_MACHINES = \
 	m10200-opc.lo \
 	m10300-dis.lo \
 	m10300-opc.lo \
+	maxq-dis.lo \
 	mcore-dis.lo \
 	mips-dis.lo \
 	mips-opc.lo \
@@ -717,6 +719,8 @@ m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
 m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/m88k.h \
   opintl.h $(INCDIR)/libiberty.h
+maxq-dis.lo: maxq-dis.c sysdep.h config.h $(INCDIR)/opcode/maxq.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
 mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
 mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 19aee60b55..614fe8297a 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -1,4 +1,4 @@
-# Makefile.in generated by automake 1.9.1 from Makefile.am.
+# Makefile.in generated by automake 1.9.2 from Makefile.am.
 # @configure_input@
 
 # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
@@ -338,6 +338,7 @@ CFILES = \
 	m68k-dis.c \
 	m68k-opc.c \
 	m88k-dis.c \
+	maxq-dis.c \
 	mcore-dis.c \
 	mips-dis.c \
 	mips-opc.c \
@@ -455,6 +456,7 @@ ALL_MACHINES = \
 	m10200-opc.lo \
 	m10300-dis.lo \
 	m10300-opc.lo \
+	maxq-dis.lo \
 	mcore-dis.lo \
 	mips-dis.lo \
 	mips-opc.lo \
@@ -565,15 +567,15 @@ $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am  $(am__confi
 	@for dep in $?; do \
 	  case '$(am__configure_deps)' in \
 	    *$$dep*) \
-	      echo ' cd $(srcdir) && $(AUTOMAKE) --cygnus '; \
-	      cd $(srcdir) && $(AUTOMAKE) --cygnus  \
+	      echo ' cd $(srcdir) && $(AUTOMAKE) --foreign '; \
+	      cd $(srcdir) && $(AUTOMAKE) --foreign  \
 		&& exit 0; \
 	      exit 1;; \
 	  esac; \
 	done; \
-	echo ' cd $(top_srcdir) && $(AUTOMAKE) --cygnus  Makefile'; \
+	echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign  Makefile'; \
 	cd $(top_srcdir) && \
-	  $(AUTOMAKE) --cygnus  Makefile
+	  $(AUTOMAKE) --foreign  Makefile
 .PRECIOUS: Makefile
 Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
 	@case '$?' in \
@@ -1247,6 +1249,8 @@ m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
 m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/m88k.h \
   opintl.h $(INCDIR)/libiberty.h
+maxq-dis.lo: maxq-dis.c sysdep.h config.h $(INCDIR)/opcode/maxq.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
 mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
   mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
 mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
diff --git a/opcodes/aclocal.m4 b/opcodes/aclocal.m4
index 49e8d5bac9..211f208148 100644
--- a/opcodes/aclocal.m4
+++ b/opcodes/aclocal.m4
@@ -1,4 +1,4 @@
-# generated automatically by aclocal 1.9.1 -*- Autoconf -*-
+# generated automatically by aclocal 1.9.2 -*- Autoconf -*-
 
 # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
 # Free Software Foundation, Inc.
@@ -40,7 +40,7 @@ AC_DEFUN([AM_AUTOMAKE_VERSION], [am__api_version="1.9"])
 # Call AM_AUTOMAKE_VERSION so it can be traced.
 # This function is AC_REQUIREd by AC_INIT_AUTOMAKE.
 AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION],
-	 [AM_AUTOMAKE_VERSION([1.9.1])])
+	 [AM_AUTOMAKE_VERSION([1.9.2])])
 
 # AM_AUX_DIR_EXPAND
 
diff --git a/opcodes/configure b/opcodes/configure
index c803c94860..05e49e60a6 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -8617,6 +8617,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_m68hc12_arch)	ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
 	bfd_m68k_arch)		ta="$ta m68k-dis.lo m68k-opc.lo" ;;
 	bfd_m88k_arch)		ta="$ta m88k-dis.lo" ;;
+	bfd_maxq_arch)		ta="$ta maxq-dis.lo" ;;
 	bfd_mcore_arch)		ta="$ta mcore-dis.lo" ;;
 	bfd_mips_arch)		ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
 	bfd_mmix_arch)		ta="$ta mmix-dis.lo mmix-opc.lo" ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 8c165fcf27..bbe5aa3ad1 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -198,6 +198,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_m68hc12_arch)	ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;;
 	bfd_m68k_arch)		ta="$ta m68k-dis.lo m68k-opc.lo" ;;
 	bfd_m88k_arch)		ta="$ta m88k-dis.lo" ;;
+	bfd_maxq_arch)		ta="$ta maxq-dis.lo" ;;
 	bfd_mcore_arch)		ta="$ta mcore-dis.lo" ;;
 	bfd_mips_arch)		ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;;
 	bfd_mmix_arch)		ta="$ta mmix-dis.lo mmix-opc.lo" ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 1bcd322228..19de8f6f84 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -1,20 +1,20 @@
 /* Select disassembly routine for specified architecture.
-   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2004
    Free Software Foundation, Inc.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #include "sysdep.h"
 #include "dis-asm.h"
@@ -45,6 +45,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #define ARCH_m68hc11
 #define ARCH_m68hc12
 #define ARCH_m88k
+#define ARCH_maxq
 #define ARCH_mcore
 #define ARCH_mips
 #define ARCH_mmix
@@ -227,6 +228,11 @@ disassembler (abfd)
       disassemble = print_insn_m88k;
       break;
 #endif
+#ifdef ARCH_maxq
+    case bfd_arch_maxq:
+      disassemble = print_insn_maxq_little;
+      break;
+#endif
 #ifdef ARCH_msp430
     case bfd_arch_msp430:
       disassemble = print_insn_msp430;
diff --git a/opcodes/maxq-dis.c b/opcodes/maxq-dis.c
new file mode 100644
index 0000000000..b3a7c4678c
--- /dev/null
+++ b/opcodes/maxq-dis.c
@@ -0,0 +1,717 @@
+/* Instruction printing code for the MAXQ
+
+   Copyright 2004 Free Software Foundation, Inc.
+
+   Written by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
+   S.(inderpreetb@noida.hcltech.com)
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the Free 
+   Software Foundation; either version 2 of the License, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+   for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc., 59 
+   Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sysdep.h"
+#include "dis-asm.h"
+#include "opcode/maxq.h"
+
+struct _group_info
+{
+  unsigned char group_no;
+  unsigned char sub_opcode;
+  unsigned char src;
+  unsigned char dst;
+  unsigned char fbit;
+  unsigned char bit_no;
+  unsigned char flag;
+
+};
+
+typedef struct _group_info group_info;
+
+#define SRC	0x01
+#define DST	0x02
+#define FORMAT	0x04
+#define BIT_NO	0x08
+#define SUB_OP	0x10
+
+#define MASK_LOW_BYTE 0x0f
+#define MASK_HIGH_BYTE 0xf0
+
+/* Flags for retrieving the bits from the op-code.  */
+#define _DECODE_LOWNIB_LOWBYTE  0x000f
+#define _DECODE_HIGHNIB_LOWBYTE 0x00f0
+#define _DECODE_LOWNIB_HIGHBYTE 0x0f00
+#define _DECODE_HIGHNIB_HIGHBYTE 0xf000
+#define _DECODE_HIGHBYTE 0xff00
+#define _DECODE_LOWBYTE  0x00ff
+#define _DECODE_4TO6_HIGHBYTE 0x7000
+#define _DECODE_4TO6_LOWBYTE 0x0070
+#define _DECODE_0TO6_HIGHBYTE 0x7f00
+#define _DECODE_0TO2_HIGHBYTE 0x0700
+#define _DECODE_GET_F_HIGHBYTE 0x8000
+#define _DECODE_BIT7_HIGHBYTE 0x8000
+#define _DECODE_BIT7_LOWBYTE 0x0080
+#define _DECODE_GET_CARRY 0x10000
+#define _DECODE_BIT0_LOWBYTE 0x1
+#define _DECODE_BIT6AND7_HIGHBYTE 0xc000
+
+/* Module and Register Indexed of System Registers.  */
+#define _CURR_ACC_MODINDEX 0xa
+#define _CURR_ACC_REGINDEX 0x0
+#define _PSF_REG_MODINDEX  0x8
+#define _PSF_REG_REGINDEX  0x4
+#define _PFX_REG_MODINDEX  0xb
+#define _PFX0_REG_REGINDEX 0x0
+#define _PFX2_REG_REGINDEX 0x2
+#define _DP_REG_MODINDEX   0xf
+#define _DP0_REG_REGINDEX  0x3
+#define _DP1_REG_REGINDEX  0x7
+#define _IP_REG_MODINDEX   0xc
+#define _IP_REG_REGINDEX   0x0
+#define _IIR_REG_MODINDEX  0x8
+#define _IIR_REG_REGINDEX  0xb
+#define _SP_REG_MODINDEX   0xd
+#define _SP_REG_REGINDEX   0x1
+#define _IC_REG_MODINDEX   0x8
+#define _IC_REG_REGINDEX   0x5
+#define _LC_REG_MODINDEX   0xe
+#define _LC0_REG_REGINDEX  0x0
+#define _LC1_REG_REGINDEX  0x1
+#define _LC2_REG_REGINDEX  0x2
+#define _LC3_REG_REGINDEX  0x3
+
+/* Flags for finding the bits in PSF Register.  */
+#define SIM_ALU_DECODE_CARRY_BIT_POS  0x2
+#define SIM_ALU_DECODE_SIGN_BIT_POS   0x40
+#define SIM_ALU_DECODE_ZERO_BIT_POS   0x80
+#define SIM_ALU_DECODE_EQUAL_BIT_POS  0x1
+#define SIM_ALU_DECODE_IGE_BIT_POS    0x1
+
+/* Number Of Op-code Groups.  */
+unsigned char const SIM_ALU_DECODE_OPCODE_GROUPS = 11;
+
+/* Op-code Groups.  */
+unsigned char const SIM_ALU_DECODE_LOGICAL_XCHG_OP_GROUP = 1;
+
+/* Group1: AND/OR/XOR/ADD/SUB Operations: fxxx 1010 ssss ssss.  */
+unsigned char const SIM_ALU_DECODE_AND_OR_ADD_SUB_OP_GROUP = 2;
+
+/* Group2: Logical Operations: 1000 1010 xxxx 1010.  */
+unsigned char const SIM_ALU_DECODE_BIT_OP_GROUP = 3;
+
+/* XCHG/Bit Operations: 1xxx 1010 xxxx 1010.  */
+unsigned char const SIM_ALU_DECODE_SET_DEST_BIT_GROUP = 4;
+
+/* Move value in bit of destination register: 1ddd dddd xbbb 0111.  */
+unsigned char const SIM_ALU_DECODE_JUMP_OP_GROUP = 5;
+
+#define JUMP_CHECK(insn)   \
+   (   ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000) \
+    || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x2000) \
+    || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x6000) \
+    || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x1000) \
+    || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000) \
+    || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000) \
+    || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x7000) \
+    || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000) )
+
+/* JUMP operations: fxxx 1100 ssss ssss */
+unsigned char const SIM_ALU_DECODE_RET_OP_GROUP = 6;
+
+/* RET Operations: 1xxx 1100 0000 1101 */
+unsigned char const SIM_ALU_DECODE_MOVE_SRC_DST_GROUP = 7;
+
+/* Move src into dest register: fddd dddd ssss ssss */
+unsigned char const SIM_ALU_DECODE_SET_SRC_BIT_GROUP = 8;
+
+/* Move value in bit of source register: fbbb 0111 ssss ssss */
+unsigned char const SIM_ALU_DECODE_DJNZ_CALL_PUSH_OP_GROUP = 9;
+
+/* PUSH, DJNZ and CALL operations: fxxx 1101 ssss ssss */
+unsigned char const SIM_ALU_DECODE_POP_OP_GROUP = 10;
+
+/* POP operation: 1ddd dddd 0000 1101 */
+unsigned char const SIM_ALU_DECODE_CMP_SRC_OP_GROUP = 11;
+
+/* GLOBAL */
+unsigned char unres_reg_name[20];
+
+static unsigned char *
+get_reg_name (unsigned char reg_code, type1 arg_pos)
+{
+  unsigned char module;
+  unsigned char index;
+  int ix = 0;
+  reg_entry const *reg_x;
+  mem_access_syntax const *syntax;
+  mem_access *mem_acc;
+
+  module = 0;
+  index = 0;
+  module = (reg_code & MASK_LOW_BYTE);
+  index = (reg_code & MASK_HIGH_BYTE);
+  index = index >> 4;
+
+  /* Search the system register table.  */
+  for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL; ++reg_x)
+    if ((reg_x->Mod_name == module) && (reg_x->Mod_index == index))
+      return reg_x->reg_name;
+
+  /* Serch pheripheral table.  */
+  for (ix = 0; ix < num_of_reg; ix++)
+    {
+      reg_x = &new_reg_table[ix];
+
+      if ((reg_x->Mod_name == module) && (reg_x->Mod_index == index))
+	return reg_x->reg_name;
+    }
+
+  for (mem_acc = &mem_table[0]; mem_acc->name != NULL || !mem_acc; ++mem_acc)
+    {
+      if (reg_code == mem_acc->opcode)
+	{
+	  for (syntax = mem_access_syntax_table;
+	       mem_access_syntax_table != NULL || mem_access_syntax_table->name;
+	       ++syntax)
+	    if (!strcmp (mem_acc->name, syntax->name))
+	      {
+		if ((arg_pos == syntax->type) || (syntax->type == BOTH))
+		  return mem_acc->name;
+
+		break;
+	      }
+	}
+    }
+
+  memset (unres_reg_name, 0, 20);
+  sprintf (unres_reg_name, "%01x%01xh", index, module);
+
+  return unres_reg_name;
+}
+
+static bfd_boolean
+check_move (unsigned char insn0, unsigned char insn8)
+{
+  bfd_boolean first = FALSE;
+  bfd_boolean second = FALSE;
+  char *first_reg;
+  char *second_reg;
+  reg_entry const *reg_x;
+  const unsigned char module1 = insn0 & MASK_LOW_BYTE;
+  const unsigned char index1 = ((insn0 & 0x70) >> 4);
+  const unsigned char module2 = insn8 & MASK_LOW_BYTE;
+  const unsigned char index2 = ((insn8 & MASK_HIGH_BYTE) >> 4);
+
+  /* DST */
+  if (((insn0 & MASK_LOW_BYTE) == MASK_LOW_BYTE)
+      && ((index1 == 0) || (index1 == 1) || (index1 == 2) || (index1 == 5)
+	  || (index1 == 4) || (index1 == 6)))
+    first = TRUE;
+
+  else if (((insn0 & MASK_LOW_BYTE) == 0x0D) && (index1 == 0))
+    first = TRUE;
+
+  else if ((module1 == 0x0E)
+	   && ((index1 == 0) || (index1 == 1) || (index1 == 2)))
+    first = TRUE;
+
+  else
+    {
+      for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL && reg_x;
+	   ++reg_x)
+	{
+	  if ((reg_x->Mod_name == module1) && (reg_x->Mod_index == index1)
+	      && ((reg_x->rtype == Reg_16W) || (reg_x->rtype == Reg_8W)))
+	    {
+	      /* IP not allowed.  */
+	      if ((reg_x->Mod_name == 0x0C) && (reg_x->Mod_index == 0x00))
+		continue;
+
+	      /* A[AP] not allowed.  */
+	      if ((reg_x->Mod_name == 0x0A) && (reg_x->Mod_index == 0x01))
+		continue;
+	      first_reg = reg_x->reg_name;
+	      first = TRUE;
+	      break;
+	    }
+	}
+    }
+
+  if (!first)
+    /* No need to check further.  */
+    return FALSE;
+
+  if (insn0 & 0x80)
+    {
+      /* SRC */
+      if (((insn8 & MASK_LOW_BYTE) == MASK_LOW_BYTE)
+	  && ((index2 == 0) || (index2 == 1) || (index2 == 2) || (index2 == 4)
+	      || (index2 == 5) || (index2 == 6)))
+	second = TRUE;
+
+      else if (((insn8 & MASK_LOW_BYTE) == 0x0D) && (index2 == 0))
+	second = TRUE;
+
+      else if ((module2 == 0x0E)
+	       && ((index2 == 0) || (index2 == 1) || (index2 == 2)))
+	second = TRUE;
+
+      else
+	{
+	  for (reg_x = &system_reg_table[0];
+	       reg_x->reg_name != NULL && reg_x;
+	       ++reg_x)
+	    {
+	      if ((reg_x->Mod_name == (insn8 & MASK_LOW_BYTE))
+		  && (reg_x->Mod_index == (((insn8 & 0xf0) >> 4))))
+		{
+		  second = TRUE;
+		  second_reg = reg_x->reg_name;
+		  break;
+		}
+	    }
+	}	
+
+      if (second)
+	{
+	  if ((module1 == 0x0A && index1 == 0x0)
+	      && (module2 == 0x0A && index2 == 0x01))
+	    return FALSE;
+
+	  return TRUE;
+	}
+
+      return FALSE;
+    }
+
+  return first;
+}
+
+static void
+maxq_print_arg (MAX_ARG_TYPE              arg,
+		struct disassemble_info * info,
+		group_info                grp)
+{
+  switch (arg)
+    {
+    case FLAG_C:
+      info->fprintf_func (info->stream, "C");
+      break;
+    case FLAG_NC:
+      info->fprintf_func (info->stream, "NC");
+      break;
+
+    case FLAG_Z:
+      info->fprintf_func (info->stream, "Z");
+      break;
+
+    case FLAG_NZ:
+      info->fprintf_func (info->stream, "NZ");
+      break;
+
+    case FLAG_S:
+      info->fprintf_func (info->stream, "S");
+      break;
+
+    case FLAG_E:
+      info->fprintf_func (info->stream, "E");
+      break;
+
+    case FLAG_NE:
+      info->fprintf_func (info->stream, "NE");
+      break;
+
+    case ACC_BIT:
+      info->fprintf_func (info->stream, "Acc");
+      if ((grp.flag & BIT_NO) == BIT_NO)
+	info->fprintf_func (info->stream, ".%d", grp.bit_no);
+      break;
+
+    case A_BIT_0:
+      info->fprintf_func (info->stream, "#0");
+      break;
+    case A_BIT_1:
+      info->fprintf_func (info->stream, "#1");
+      break;
+
+    default:
+      break;
+    }
+}
+
+static unsigned char
+get_group (const unsigned int insn)
+{
+  if (check_move ((insn >> 8), (insn & _DECODE_LOWBYTE)))
+    return 8;
+
+  if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0A00)
+    {
+      /* && condition with sec part added on 26 May for resoveing 2 & 3 grp
+         conflict.  */
+      if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x000A)
+	  && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
+	{
+	  if ((insn & _DECODE_HIGHNIB_HIGHBYTE) == 0x8000)
+	    return 2;
+	  else
+	    return 3;
+	}
+
+      return 1;
+    }
+  else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0C00)
+    {
+      if (((insn & _DECODE_LOWBYTE) == 0x000D) && JUMP_CHECK (insn)
+	  && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
+	return 6;
+      else if ((insn & _DECODE_LOWBYTE) == 0x008D)
+	return 7;
+
+      return 5;
+    }
+  else if (((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0D00)
+	   && (((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000)
+	       || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000)
+	       || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000)
+	       || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000)))
+    return 10;
+
+  else if ((insn & _DECODE_LOWBYTE) == 0x000D)
+    return 11;
+
+  else if ((insn & _DECODE_LOWBYTE) == 0x008D)
+    return 12;
+
+  else if ((insn & _DECODE_0TO6_HIGHBYTE) == 0x7800)
+    return 13;
+
+  else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0700)
+    return 9;
+
+  else if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x0007)
+	   && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
+    return 4;
+
+  return 8;
+}
+
+static void
+get_insn_opcode (const unsigned int insn, group_info *i)
+{
+  static unsigned char pfx_flag = 0;
+  static unsigned char count_for_pfx = 0;
+
+  i->flag ^= i->flag;
+  i->bit_no ^= i->bit_no;
+  i->dst ^= i->dst;
+  i->fbit ^= i->fbit;
+  i->group_no ^= i->group_no;
+  i->src ^= i->src;
+  i->sub_opcode ^= i->sub_opcode;
+
+  if (count_for_pfx > 0)
+    count_for_pfx++;
+
+  if (((insn >> 8) == 0x0b) || ((insn >> 8) == 0x2b))
+    {
+      pfx_flag = 1;
+      count_for_pfx = 1;
+    }
+
+  i->group_no = get_group (insn);
+
+  if (pfx_flag && (i->group_no == 0x0D) && (count_for_pfx == 2)
+      && ((insn & _DECODE_0TO6_HIGHBYTE) == 0x7800))
+    {
+      i->group_no = 0x08;
+      count_for_pfx = 0;
+      pfx_flag ^= pfx_flag;
+    }
+
+  switch (i->group_no)
+    {
+    case 1:
+      i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
+      i->flag |= SUB_OP;
+      i->src = ((insn & _DECODE_LOWBYTE));
+      i->flag |= SRC;
+      i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+      i->flag |= FORMAT;
+      break;
+
+    case 2:
+      i->sub_opcode = ((insn & _DECODE_HIGHNIB_LOWBYTE) >> 4);
+      i->flag |= SUB_OP;
+      break;
+
+    case 3:
+      i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
+      i->flag |= SUB_OP;
+      i->bit_no = ((insn & _DECODE_HIGHNIB_LOWBYTE) >> 4);
+      i->flag |= BIT_NO;
+      break;
+
+    case 4:
+      i->sub_opcode = ((insn & _DECODE_BIT7_LOWBYTE) >> 7);
+      i->flag |= SUB_OP;
+      i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
+      i->flag |= DST;
+      i->bit_no = ((insn & _DECODE_4TO6_LOWBYTE) >> 4);
+      i->flag |= BIT_NO;
+      break;
+
+    case 5:
+      i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
+      i->flag |= SUB_OP;
+      i->src = ((insn & _DECODE_LOWBYTE));
+      i->flag |= SRC;
+      i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+      i->flag |= FORMAT;
+      break;
+
+    case 6:
+      i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
+      i->flag |= SUB_OP;
+      break;
+
+    case 7:
+      i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
+      i->flag |= SUB_OP;
+      break;
+
+    case 8:
+      i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
+      i->flag |= DST;
+      i->src = ((insn & _DECODE_LOWBYTE));
+      i->flag |= SRC;
+      i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+      i->flag |= FORMAT;
+      break;
+
+    case 9:
+      i->sub_opcode = ((insn & _DECODE_0TO2_HIGHBYTE) >> 8);
+      i->flag |= SUB_OP;
+      i->bit_no = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
+      i->flag |= BIT_NO;
+      i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+      i->flag |= FORMAT;
+      i->src = ((insn & _DECODE_LOWBYTE));
+      i->flag |= SRC;
+      break;
+
+    case 10:
+      i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
+      i->flag |= SUB_OP;
+      i->src = ((insn & _DECODE_LOWBYTE));
+      i->flag |= SRC;
+      i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+      i->flag |= FORMAT;
+      break;
+
+    case 11:
+      i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
+      i->flag |= DST;
+      break;
+
+    case 12:
+      i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
+      i->flag |= DST;
+      break;
+
+    case 13:
+      i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
+      i->flag |= SUB_OP;
+      i->src = ((insn & _DECODE_LOWBYTE));
+      i->flag |= SRC;
+      i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
+      i->flag |= FORMAT;
+      break;
+
+    }
+  return;
+}
+
+
+/* Print one instruction from MEMADDR on INFO->STREAM. Return the size of the 
+   instruction (always 2 on MAXQ20).  */
+
+static int
+print_insn (bfd_vma memaddr, struct disassemble_info *info,
+	    enum bfd_endian endianess)
+{
+  /* The raw instruction.  */
+  unsigned char insn[2], insn0, insn8, derived_code;
+  unsigned int format;
+  unsigned int actual_operands;
+  unsigned int i;
+  /* The group_info collected/decoded.  */
+  group_info grp;
+  MAXQ20_OPCODE_INFO const *opcode;
+  int status;
+
+  format = 0;
+
+  status = info->read_memory_func (memaddr, (bfd_byte *) & insn[0], 2, info);
+
+  if (status != 0)
+    {
+      info->memory_error_func (status, memaddr, info);
+      return -1;
+    }
+
+  insn8 = insn[1];
+  insn0 = insn[0];
+
+  /* FIXME: Endianness always little.  */
+  if (endianess == BFD_ENDIAN_BIG)
+    get_insn_opcode (((insn[0] << 8) | (insn[1])), &grp);
+  else
+    get_insn_opcode (((insn[1] << 8) | (insn[0])), &grp);
+
+  derived_code = ((grp.group_no << 4) | grp.sub_opcode);
+
+  if (insn[0] == 0 && insn[1] == 0)
+    {
+      info->fprintf_func (info->stream, "00 00");
+      return 2;
+    }
+
+  /* The opcode is always in insn0.  */
+  for (opcode = &op_table[0]; opcode->name != NULL; ++opcode)
+    {
+      if (opcode->instr_id == derived_code)
+	{
+	  if (opcode->instr_id == 0x3D)
+	    {
+	      if ((grp.bit_no == 0) && (opcode->arg[1] != A_BIT_0))
+		continue;
+	      if ((grp.bit_no == 1) && (opcode->arg[1] != A_BIT_1))
+		continue;
+	      if ((grp.bit_no == 3) && (opcode->arg[0] != 0))
+		continue;
+	    }
+
+	  info->fprintf_func (info->stream, "%s ", opcode->name);
+
+	  actual_operands = 0;
+
+	  if ((grp.flag & SRC) == SRC)
+	    actual_operands++;
+
+	  if ((grp.flag & DST) == DST)
+	    actual_operands++;
+
+	  /* If Implict FLAG in the Instruction.  */
+	  if ((opcode->op_number > actual_operands)
+	      && !((grp.flag & SRC) == SRC) && !((grp.flag & DST) == DST))
+	    {
+	      for (i = 0; i < opcode->op_number; i++)
+		{
+		  if (i == 1 && (opcode->arg[1] != NO_ARG))
+		    info->fprintf_func (info->stream, ",");
+		  maxq_print_arg (opcode->arg[i], info, grp);
+		}
+	    }
+
+	  /* DST is ABSENT in the grp.  */
+	  if ((opcode->op_number > actual_operands)
+	      && ((grp.flag & SRC) == SRC))
+	    {
+	      maxq_print_arg (opcode->arg[0], info, grp);
+	      info->fprintf_func (info->stream, " ");
+
+	      if (opcode->instr_id == 0xA4)
+		info->fprintf_func (info->stream, "LC[0]");
+
+	      if (opcode->instr_id == 0xA5)
+		info->fprintf_func (info->stream, "LC[1]");
+
+	      if ((grp.flag & SRC) == SRC)
+		info->fprintf_func (info->stream, ",");
+	    }
+
+	  if ((grp.flag & DST) == DST)
+	    {
+	      if ((grp.flag & BIT_NO) == BIT_NO)
+		{
+		  info->fprintf_func (info->stream, " %s.%d",
+				      get_reg_name (grp.dst,
+						    (type1) 0 /*DST*/),
+				      grp.bit_no);
+		}
+	      else
+		info->fprintf_func (info->stream, " %s", get_reg_name (grp.dst, (type1) 0));
+	    }
+
+	  /* SRC is ABSENT in the grp.  */
+	  if ((opcode->op_number > actual_operands)
+	      && ((grp.flag & DST) == DST))
+	    {
+	      info->fprintf_func (info->stream, ",");
+	      maxq_print_arg (opcode->arg[1], info, grp);
+	      info->fprintf_func (info->stream, " ");
+	    }
+
+	  if ((grp.flag & SRC) == SRC)
+	    {
+	      if ((grp.flag & DST) == DST)
+		info->fprintf_func (info->stream, ",");
+
+	      if ((grp.flag & BIT_NO) == BIT_NO)
+		{
+		  format = opcode->format;
+
+		  if ((grp.flag & FORMAT) == FORMAT)
+		    format = grp.fbit;
+		  if (format == 1)
+		    info->fprintf_func (info->stream, " %s.%d",
+					get_reg_name (grp.src,
+						      (type1) 1 /*SRC*/),
+					grp.bit_no);
+		  if (format == 0)
+		    info->fprintf_func (info->stream, " #%02xh.%d",
+					(grp.src, SRC), grp.bit_no);
+		}
+	      else
+		{
+		  format = opcode->format;
+
+		  if ((grp.flag & FORMAT) == FORMAT)
+		    format = grp.fbit;
+		  if (format == 1)
+		    info->fprintf_func (info->stream, " %s",
+					   get_reg_name (grp.src,
+							 (type1) 1 /*SRC*/));
+		  if (format == 0)
+		    info->fprintf_func (info->stream, " #%02xh",
+					   (grp.src));
+		}
+	    }
+
+	  return 2;
+	}
+    }
+
+  info->fprintf_func (info->stream, "Unable to Decode :  %02x %02x",
+			 insn[0], insn[1]);
+  return 2;			
+}
+
+int
+print_insn_maxq_little (bfd_vma memaddr, struct disassemble_info *info)
+{
+  return print_insn (memaddr, info, BFD_ENDIAN_LITTLE);
+}
+