From: Craig Topper <craig.topper@intel.com>
Date: Mon, 15 Oct 2018 05:31:24 +0000 (+0000)
Subject: [X86] Autogenerate checks. NFC
X-Git-Tag: android-x86-9.0-r1~11818
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=15ca92098aa137c257b7dfea86c7b4daa8eaf1af;p=android-x86%2Fexternal-llvm.git

[X86] Autogenerate checks. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@344490 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/CodeGen/X86/fold-vex.ll b/test/CodeGen/X86/fold-vex.ll
index 006db6effdf..c7b376a053d 100644
--- a/test/CodeGen/X86/fold-vex.ll
+++ b/test/CodeGen/X86/fold-vex.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Use CPU parameters to ensure that a CPU-specific attribute is not overriding the AVX definition.
 
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown                  -mattr=+avx | FileCheck %s
@@ -14,18 +15,20 @@
 ; unless specially configured on some CPUs such as AMD Family 10H.
 
 define <4 x i32> @test1(<4 x i32>* %p0, <4 x i32> %in1) nounwind {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vandps (%rdi), %xmm0, %xmm0
+; CHECK-NEXT:    retq
+;
+; SSE-LABEL: test1:
+; SSE:       # %bb.0:
+; SSE-NEXT:    movups (%rdi), %xmm1
+; SSE-NEXT:    andps %xmm1, %xmm0
+; SSE-NEXT:    retq
   %in0 = load <4 x i32>, <4 x i32>* %p0, align 2
   %a = and <4 x i32> %in0, %in1
   ret <4 x i32> %a
 
-; CHECK-LABEL: @test1
-; CHECK-NOT:   vmovups
-; CHECK:       vandps (%rdi), %xmm0, %xmm0
-; CHECK-NEXT:  ret
 
-; SSE-LABEL: @test1
-; SSE:       movups (%rdi), %xmm1
-; SSE-NEXT:  andps %xmm1, %xmm0
-; SSE-NEXT:  ret
 }