From: Marek Olšák <marek.olsak@amd.com>
Date: Thu, 6 Sep 2018 01:30:44 +0000 (-0400)
Subject: gallium/u_cpu_detect: get the number of cores per L3 cache for AMD Zen
X-Git-Tag: android-x86-8.1-r1~1042
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=15fa2c5e359149a0b67b8572cd7dab87626b48ae;p=android-x86%2Fexternal-mesa.git

gallium/u_cpu_detect: get the number of cores per L3 cache for AMD Zen

Reviewed-by: Brian Paul <brianp@vmware.com>
---

diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c b/src/gallium/auxiliary/util/u_cpu_detect.c
index 29f4ce98203..751443f06f9 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.c
+++ b/src/gallium/auxiliary/util/u_cpu_detect.c
@@ -368,6 +368,28 @@ check_os_arm_support(void)
 #endif /* PIPE_ARCH_ARM */
 
 static void
+get_cpu_topology(void)
+{
+   uint32_t regs[4];
+
+   /* Default. This is correct if L3 is not present or there is only one. */
+   util_cpu_caps.cores_per_L3 = util_cpu_caps.nr_cpus;
+
+#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
+   /* AMD Zen */
+   if (util_cpu_caps.x86_cpu_type == 0x17) {
+      /* Query the L3 cache topology information. */
+      cpuid_count(0x8000001D, 3, regs);
+      unsigned cache_level = (regs[0] >> 5) & 0x7;
+      unsigned cores_per_cache = ((regs[0] >> 14) & 0xfff) + 1;
+
+      if (cache_level == 3)
+         util_cpu_caps.cores_per_L3 = cores_per_cache;
+   }
+#endif
+}
+
+static void
 util_cpu_detect_once(void)
 {
    memset(&util_cpu_caps, 0, sizeof util_cpu_caps);
@@ -520,6 +542,8 @@ util_cpu_detect_once(void)
    check_os_altivec_support();
 #endif /* PIPE_ARCH_PPC */
 
+   get_cpu_topology();
+
 #ifdef DEBUG
    if (debug_get_option_dump_cpu()) {
       debug_printf("util_cpu_caps.nr_cpus = %u\n", util_cpu_caps.nr_cpus);
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.h b/src/gallium/auxiliary/util/u_cpu_detect.h
index 19f5567ca7b..efc910d1473 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.h
+++ b/src/gallium/auxiliary/util/u_cpu_detect.h
@@ -51,6 +51,7 @@ struct util_cpu_caps {
    /* Feature flags */
    int x86_cpu_type;
    unsigned cacheline;
+   unsigned cores_per_L3;
 
    unsigned has_intel:1;
    unsigned has_tsc:1;