From: Daniel Baluta <daniel.baluta@nxp.com>
Date: Wed, 16 Jan 2019 13:21:36 +0000 (+0000)
Subject: arm64: dts: imx8qxp: Fix MU4_INT number
X-Git-Tag: v5.1-rc1~157^2~21^2~14
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=179cbdb8747ca551e57dc10271eb1f540499c8cf;p=tomoyo%2Ftomoyo-test1.git

arm64: dts: imx8qxp: Fix MU4_INT number

MU4_INT correct number is 180, while 179 is for MU3_INT.

Fixes: 3d91ba65fecd ("arm64: dts: imx: add imx8qxp support")
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index bb877cf25edc..4c3dd95ed488 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -350,7 +350,7 @@
 		lsio_mu4: mailbox@5d1f0000 {
 			compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 			reg = <0x5d1f0000 0x10000>;
-			interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 			#mbox-cells = <0>;
 			status = "disabled";
 		};