From: Craig Topper <craig.topper@intel.com>
Date: Mon, 20 Nov 2017 23:08:50 +0000 (+0000)
Subject: [SelectionDAG] When promoting the result of a VSELECT, make sure we promote the condi... 
X-Git-Tag: android-x86-7.1-r4~8305
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=1bf38b1457d74e97b115436f47daf9ea4f55336d;p=android-x86%2Fexternal-llvm.git

[SelectionDAG] When promoting the result of a VSELECT, make sure we promote the condition to the SetCC type for the final result type not the original type.

Normally this would be cleaned up by promoting the condition operand next. But in the attached case we promoted the result from v2i48 to v2i64 and the condition from v2i1 to v2i48. Then we tried to "promote" the v2i48 condition back to v2i1 because that's what the SetCC result type for v2i64 is on X86 with VLX. But promote is either a NOP or SIGN_EXTEND and this would need a truncation.

With the change here we now get the SetCC type of v2i1 when we're handling the result promotion and the operand no longer needs to be promoted itself.

Fixes PR35272.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318706 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 68cac22a99e..03a20dbca49 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -570,12 +570,11 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
 
 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
   SDValue Mask = N->getOperand(0);
-  EVT OpTy = N->getOperand(1).getValueType();
 
-  // Promote all the way up to the canonical SetCC type.
-  Mask = PromoteTargetBoolean(Mask, OpTy);
   SDValue LHS = GetPromotedInteger(N->getOperand(1));
   SDValue RHS = GetPromotedInteger(N->getOperand(2));
+  // Promote all the way up to the canonical SetCC type.
+  Mask = PromoteTargetBoolean(Mask, LHS.getValueType());
   return DAG.getNode(ISD::VSELECT, SDLoc(N),
                      LHS.getValueType(), Mask, LHS, RHS);
 }
diff --git a/test/CodeGen/X86/pr35272.ll b/test/CodeGen/X86/pr35272.ll
new file mode 100644
index 00000000000..e121ec8a3c9
--- /dev/null
+++ b/test/CodeGen/X86/pr35272.ll
@@ -0,0 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s
+
+define <2 x i48> @PR35272(<2 x i64> %a0, <2 x i48> %a1, <2 x i48> %a2) {
+; CHECK-LABEL: PR35272:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpxor %xmm3, %xmm3, %xmm3
+; CHECK-NEXT:    vpcmpeqq %xmm3, %xmm0, %k1
+; CHECK-NEXT:    vpblendmq %xmm1, %xmm2, %xmm0 {%k1}
+; CHECK-NEXT:    retq
+  %1 = icmp eq <2 x i64> %a0, zeroinitializer
+  %2 = select <2 x i1> %1, <2 x i48> %a1, <2 x i48> %a2
+  ret <2 x i48> %2
+}