From: Aart Bik Date: Wed, 16 Dec 2015 19:11:38 +0000 (+0000) Subject: Merge "Revert "X86: Use locked add rather than mfence"" X-Git-Tag: android-x86-7.1-r1~881 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=1c70f18dce;p=android-x86%2Fart.git Merge "Revert "X86: Use locked add rather than mfence"" --- 1c70f18dce7705ff70147ddebf65a97f66df8d5c diff --cc compiler/optimizing/code_generator_x86_64.h index e5a487c76,7351fed0f..dda9ea22d --- a/compiler/optimizing/code_generator_x86_64.h +++ b/compiler/optimizing/code_generator_x86_64.h @@@ -480,28 -423,7 +479,16 @@@ class CodeGeneratorX86_64 : public Code int64_t v, HInstruction* instruction); - // Ensure that prior stores complete to memory before subsequent loads. - // The locked add implementation will avoid serializing device memory, but will - // touch (but not change) the top of the stack. The locked add should not be used for - // ordering non-temporal stores. - void MemoryFence(bool force_mfence = false) { - if (!force_mfence && isa_features_.PrefersLockedAddSynchronization()) { - assembler_.lock()->addl(Address(CpuRegister(RSP), 0), Immediate(0)); - } else { - assembler_.mfence(); - } - } - private: + // Factored implementation of GenerateFieldLoadWithBakerReadBarrier + // and GenerateArrayLoadWithBakerReadBarrier. + void GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction, + Location ref, + CpuRegister obj, + const Address& src, + Location temp, + bool needs_null_check); + struct PcRelativeDexCacheAccessInfo { PcRelativeDexCacheAccessInfo(const DexFile& dex_file, uint32_t element_off) : target_dex_file(dex_file), element_offset(element_off), label() { }