From: Jozef Kolek <jozef.kolek@imgtec.com>
Date: Wed, 18 Feb 2015 17:33:56 +0000 (+0000)
Subject: [mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator
X-Git-Tag: android-x86-7.1-r4~51621
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=2032d755e7db0513b8ef7311febc8c5c3f2fa2b3;p=android-x86%2Fexternal-llvm.git

[mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator

Differential Revision: http://reviews.llvm.org/D7609


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229706 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td
index e20df2f4e62..19120202af7 100644
--- a/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -642,8 +642,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
                      LW_FM_MM<0xc>;
 
   /// Arithmetic Instructions (3-Operand, R-Type)
-  def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
-  def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;
+  def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
+                 ADD_FM_MM<0, 0x150>;
+  def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
+                 ADD_FM_MM<0, 0x1d0>;
   def MUL_MM   : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>;
   def ADD_MM   : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>;
   def SUB_MM   : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>;
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 9a35a2dfb50..28ab114d039 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -1140,12 +1140,13 @@ def XORi  : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
                                xor>,
             ADDI_FM<0xe>;
 def LUi   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
-
+let AdditionalPredicates = [NotInMicroMips] in {
 /// Arithmetic Instructions (3-Operand, R-Type)
 def ADDu  : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
             ADD_FM<0, 0x21>;
 def SUBu  : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
             ADD_FM<0, 0x23>;
+}
 let Defs = [HI0, LO0] in
 def MUL   : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
             ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
diff --git a/test/CodeGen/Mips/micromips-addu16.ll b/test/CodeGen/Mips/micromips-addu16.ll
new file mode 100644
index 00000000000..adebaf03bcf
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-addu16.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32* %b, align 4
+  %1 = load i32* %c, align 4
+  %add = add nsw i32 %0, %1
+  store i32 %add, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: addu16
diff --git a/test/CodeGen/Mips/micromips-subu16.ll b/test/CodeGen/Mips/micromips-subu16.ll
new file mode 100644
index 00000000000..4ca16ef7c61
--- /dev/null
+++ b/test/CodeGen/Mips/micromips-subu16.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
+; RUN:   -relocation-model=pic -O3 < %s | FileCheck %s
+
+define i32 @main() {
+entry:
+  %retval = alloca i32, align 4
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 0, i32* %retval
+  %0 = load i32* %b, align 4
+  %1 = load i32* %c, align 4
+  %sub = sub nsw i32 %0, %1
+  store i32 %sub, i32* %a, align 4
+  ret i32 0
+}
+
+; CHECK: subu16