From: Evan Cheng Date: Sun, 25 Oct 2009 08:01:41 +0000 (+0000) Subject: Add a couple of ARM cross-rc coalescing tests. X-Git-Tag: android-x86-6.0-r1~1003^2~13808 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=21a45557c61d40ecff292101325918c44ed868d2;p=android-x86%2Fexternal-llvm.git Add a couple of ARM cross-rc coalescing tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85051 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll new file mode 100644 index 00000000000..572f1e8975a --- /dev/null +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 + +%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } +%struct.__sFILEX = type opaque +%struct.__sbuf = type { i8*, i32 } + +declare arm_apcscc i32 @fgetc(%struct.FILE* nocapture) nounwind + +define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind { +entry: + br i1 undef, label %bb, label %bb1 + +bb: ; preds = %entry + unreachable + +bb1: ; preds = %entry + br i1 undef, label %bb.i1, label %bb1.i2 + +bb.i1: ; preds = %bb1 + unreachable + +bb1.i2: ; preds = %bb1 + %0 = call arm_apcscc i32 @fgetc(%struct.FILE* undef) nounwind ; [#uses=0] + br i1 undef, label %bb2.i3, label %bb3.i4 + +bb2.i3: ; preds = %bb1.i2 + br i1 undef, label %bb4.i, label %bb3.i4 + +bb3.i4: ; preds = %bb2.i3, %bb1.i2 + unreachable + +bb4.i: ; preds = %bb2.i3 + br i1 undef, label %bb5.i, label %get_image.exit + +bb5.i: ; preds = %bb4.i + unreachable + +get_image.exit: ; preds = %bb4.i + br i1 undef, label %bb28, label %bb27 + +bb27: ; preds = %get_image.exit + br label %bb.i + +bb.i: ; preds = %bb.i, %bb27 + %1 = fptrunc double undef to float ; [#uses=1] + %2 = fptoui float %1 to i8 ; [#uses=1] + store i8 %2, i8* undef, align 1 + br label %bb.i + +bb28: ; preds = %get_image.exit + unreachable +} diff --git a/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll new file mode 100644 index 00000000000..ea88a2680f3 --- /dev/null +++ b/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -0,0 +1,67 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep fcpys | count 5 + +define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind { +entry: + br label %bb5 + +bb5: ; preds = %bb5, %entry + br i1 undef, label %bb5, label %bb.nph + +bb.nph: ; preds = %bb5 + br label %bb7 + +bb7: ; preds = %bb9, %bb.nph + %s1.02 = phi float [ undef, %bb.nph ], [ %35, %bb9 ] ; [#uses=3] + %tmp79 = add i32 undef, undef ; [#uses=1] + %tmp53 = sub i32 undef, undef ; [#uses=1] + %0 = fadd float 0.000000e+00, 1.000000e+00 ; [#uses=2] + %1 = fmul float 0.000000e+00, 0.000000e+00 ; [#uses=2] + br label %bb8 + +bb8: ; preds = %bb8, %bb7 + %tmp54 = add i32 0, %tmp53 ; [#uses=0] + %fi.1 = getelementptr float* %fz, i32 undef ; [#uses=2] + %tmp80 = add i32 0, %tmp79 ; [#uses=1] + %scevgep81 = getelementptr float* %fz, i32 %tmp80 ; [#uses=1] + %2 = load float* undef, align 4 ; [#uses=1] + %3 = fmul float %2, %1 ; [#uses=1] + %4 = load float* null, align 4 ; [#uses=2] + %5 = fmul float %4, %0 ; [#uses=1] + %6 = fsub float %3, %5 ; [#uses=1] + %7 = fmul float %4, %1 ; [#uses=1] + %8 = fadd float undef, %7 ; [#uses=2] + %9 = load float* %fi.1, align 4 ; [#uses=2] + %10 = fsub float %9, %8 ; [#uses=1] + %11 = fadd float %9, %8 ; [#uses=1] + %12 = fsub float 0.000000e+00, %6 ; [#uses=1] + %13 = fsub float 0.000000e+00, undef ; [#uses=2] + %14 = fmul float undef, %0 ; [#uses=1] + %15 = fadd float %14, undef ; [#uses=2] + %16 = load float* %scevgep81, align 4 ; [#uses=2] + %17 = fsub float %16, %15 ; [#uses=1] + %18 = fadd float %16, %15 ; [#uses=2] + %19 = load float* undef, align 4 ; [#uses=2] + %20 = fsub float %19, %13 ; [#uses=2] + %21 = fadd float %19, %13 ; [#uses=1] + %22 = fmul float %s1.02, %18 ; [#uses=1] + %23 = fmul float 0.000000e+00, %20 ; [#uses=1] + %24 = fsub float %22, %23 ; [#uses=1] + %25 = fmul float 0.000000e+00, %18 ; [#uses=1] + %26 = fmul float %s1.02, %20 ; [#uses=1] + %27 = fadd float %25, %26 ; [#uses=1] + %28 = fadd float %11, %27 ; [#uses=1] + store float %28, float* %fi.1, align 4 + %29 = fadd float %12, %24 ; [#uses=1] + store float %29, float* null, align 4 + %30 = fmul float 0.000000e+00, %21 ; [#uses=1] + %31 = fmul float %s1.02, %17 ; [#uses=1] + %32 = fsub float %30, %31 ; [#uses=1] + %33 = fsub float %10, %32 ; [#uses=1] + store float %33, float* undef, align 4 + %34 = icmp slt i32 undef, undef ; [#uses=1] + br i1 %34, label %bb8, label %bb9 + +bb9: ; preds = %bb8 + %35 = fadd float 0.000000e+00, undef ; [#uses=1] + br label %bb7 +}