From: Andrew Gacek <andrew.gacek@gmail.com>
Date: Tue, 27 Dec 2016 14:59:23 +0000 (+0000)
Subject: cadence_uart: Check if receiver timeout counter is disabled
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=2494c9f6405a1979319f12d1bb4e9a6eb28a529d;p=qmiga%2Fqemu.git

cadence_uart: Check if receiver timeout counter is disabled

When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to
0, the receiver timeout counter should be disabled. See page 1801 of
"Zynq-7000 AP SoC Technical Reference Manual". This commit adds a
such a check before setting the receive timeout interrupt.

Signed-off-by: Andrew Gacek <andrew.gacek@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index dba1c53586..4dcee571c0 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -138,9 +138,10 @@ static void fifo_trigger_update(void *opaque)
 {
     CadenceUARTState *s = opaque;
 
-    s->r[R_CISR] |= UART_INTR_TIMEOUT;
-
-    uart_update_status(s);
+    if (s->r[R_RTOR]) {
+        s->r[R_CISR] |= UART_INTR_TIMEOUT;
+        uart_update_status(s);
+    }
 }
 
 static void uart_rx_reset(CadenceUARTState *s)