From: Chris Lattner <sabre@nondot.org>
Date: Wed, 15 Sep 2010 04:04:33 +0000 (+0000)
Subject: add a bunch of aliases for fp operations with no operand,
X-Git-Tag: android-x86-6.0-r1~1003^2~2384
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=2d592d10a57887ebe7c43a5e610f4278dd6c5d20;p=android-x86%2Fexternal-llvm.git

add a bunch of aliases for fp operations with no operand,
rdar://8431422


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113929 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 50529313403..dde34631ef4 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -923,6 +923,24 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
       std::swap(Operands[1], Operands[2]);
     }
   
+  // The assembler accepts these instructions with no operand as a synonym for
+  // an instruction acting on st(1).  e.g. "fxch" -> "fxch %st(1)".
+  if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" ||
+       Name == "faddp" || Name == "fsubp" || Name == "fsubrp" || 
+       Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") &&
+      Operands.size() == 1) {
+    Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
+                                             NameLoc, NameLoc));
+  }
+  
+  // The assembler accepts these instructions with no operand as a synonym for
+  // an instruction acting on st,st(1).  e.g. "faddp" -> "faddp %st(0),%st(1)".
+  //if (() &&
+  //    Operands.size() == 1) {
+  //  Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
+  //                                           NameLoc, NameLoc));
+  //}
+  
   return false;
 }
 
@@ -959,11 +977,10 @@ bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
 }
 
 
-bool
-X86ATTAsmParser::MatchInstruction(SMLoc IDLoc,
-                                  const SmallVectorImpl<MCParsedAsmOperand*>
-                                    &Operands,
-                                  MCInst &Inst) {
+bool X86ATTAsmParser::
+MatchInstruction(SMLoc IDLoc,
+                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
+                 MCInst &Inst) {
   assert(!Operands.empty() && "Unexpect empty operand list!");
 
   bool WasOriginallyInvalidOperand = false;
diff --git a/test/MC/AsmParser/X86/x86_instructions.s b/test/MC/AsmParser/X86/x86_instructions.s
index d4444f89523..4bdd171445d 100644
--- a/test/MC/AsmParser/X86/x86_instructions.s
+++ b/test/MC/AsmParser/X86/x86_instructions.s
@@ -210,3 +210,28 @@ inl	%dx
 out %al, (%dx)
 out %ax, (%dx)
 outl %eax, (%dx)
+
+
+// rdar://8431422
+
+// CHECK: fxch	%st(1)
+// CHECK: fucom	%st(1)
+// CHECK: fucomp	%st(1)
+// CHECK: faddp	%st(1)
+// CHECK: faddp	%st(0)
+// CHECK: fsubp	%st(1)
+// CHECK: fsubrp	%st(1)
+// CHECK: fmulp	%st(1)
+// CHECK: fdivp	%st(1)
+// CHECK: fdivrp	%st(1)
+
+fxch
+fucom
+fucomp
+faddp
+faddp %st
+fsubp
+fsubrp
+fmulp
+fdivp
+fdivrp