From: Dmitry Preobrazhensky Date: Fri, 17 Jul 2020 16:48:36 +0000 (+0300) Subject: [AMDGPU] Removed s_mov_regrd and mov_fed opcodes X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=2e87acac9b88e06a9a7a0b63fb3f426a5535f11c;p=android-x86%2Fexternal-llvm-project.git [AMDGPU] Removed s_mov_regrd and mov_fed opcodes These opcodes are not intended for public use. Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D81659 --- diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h index c833bfbcf93..6b238304912 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -1041,10 +1041,6 @@ public: return CIInsts; } - bool hasSMovFedHazard() const { - return getGeneration() == AMDGPUSubtarget::GFX9; - } - bool hasReadM0MovRelInterpHazard() const { return getGeneration() == AMDGPUSubtarget::GFX9; } diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index 22292318708..8b446a43429 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -191,9 +191,6 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { if (MI->isInlineAsm() && checkInlineAsmHazards(MI) > 0) return NoopHazard; - if (checkAnyInstHazards(MI) > 0) - return NoopHazard; - return NoHazard; } @@ -241,7 +238,7 @@ unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) { if (MI->isBundle()) return 0; - int WaitStates = std::max(0, checkAnyInstHazards(MI)); + int WaitStates = 0; if (SIInstrInfo::isSMRD(*MI)) return std::max(WaitStates, checkSMRDHazards(MI)); @@ -821,34 +818,6 @@ int GCNHazardRecognizer::checkRFEHazards(MachineInstr *RFE) { return RFEWaitStates - WaitStatesNeeded; } -int GCNHazardRecognizer::checkAnyInstHazards(MachineInstr *MI) { - if (MI->isDebugInstr()) - return 0; - - const SIRegisterInfo *TRI = ST.getRegisterInfo(); - if (!ST.hasSMovFedHazard()) - return 0; - - // Check for any instruction reading an SGPR after a write from - // s_mov_fed_b32. - int MovFedWaitStates = 1; - int WaitStatesNeeded = 0; - - for (const MachineOperand &Use : MI->uses()) { - if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg())) - continue; - auto IsHazardFn = [] (MachineInstr *MI) { - return MI->getOpcode() == AMDGPU::S_MOV_FED_B32; - }; - int WaitStatesNeededForUse = - MovFedWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardFn, - MovFedWaitStates); - WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse); - } - - return WaitStatesNeeded; -} - int GCNHazardRecognizer::checkReadM0Hazards(MachineInstr *MI) { const SIInstrInfo *TII = ST.getInstrInfo(); const int SMovRelWaitStates = 1; diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h index cd17f2755bd..59d6d4f9075 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h @@ -83,7 +83,6 @@ private: int checkRWLaneHazards(MachineInstr *RWLane); int checkRFEHazards(MachineInstr *RFE); int checkInlineAsmHazards(MachineInstr *IA); - int checkAnyInstHazards(MachineInstr *MI); int checkReadM0Hazards(MachineInstr *SMovRel); int checkNSAtoVMEMHazard(MachineInstr *MI); int checkFPAtomicToDenormModeHazard(MachineInstr *MI); diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 9d7b25d5521..d60fa58a0a7 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -288,13 +288,11 @@ def S_MOVRELD_B64 : SOP1_64_movreld <"s_movreld_b64">; let SubtargetPredicate = isGFX6GFX7GFX8GFX9 in { def S_CBRANCH_JOIN : SOP1_0_32R <"s_cbranch_join">; -def S_MOV_REGRD_B32 : SOP1_32 <"s_mov_regrd_b32">; } // End SubtargetPredicate = isGFX6GFX7GFX8GFX9 let Defs = [SCC] in { def S_ABS_I32 : SOP1_32 <"s_abs_i32">; } // End Defs = [SCC] -def S_MOV_FED_B32 : SOP1_32 <"s_mov_fed_b32">; let SubtargetPredicate = HasVGPRIndexMode in { def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set_gpr_idx_idx"> { @@ -1381,7 +1379,6 @@ multiclass SOP1_Real_gfx6_gfx7_gfx10 op> : SOP1_Real_gfx6_gfx7, SOP1_Real_gfx10; defm S_CBRANCH_JOIN : SOP1_Real_gfx6_gfx7<0x032>; -defm S_MOV_REGRD_B32 : SOP1_Real_gfx6_gfx7<0x033>; defm S_MOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x003>; defm S_MOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x004>; @@ -1430,7 +1427,6 @@ defm S_MOVRELS_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02f>; defm S_MOVRELD_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x030>; defm S_MOVRELD_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x031>; defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>; -defm S_MOV_FED_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x035>; //===----------------------------------------------------------------------===// // SOP2 - GFX10. @@ -1643,9 +1639,7 @@ def S_MOVRELS_B64_vi : SOP1_Real_vi <0x2b, S_MOVRELS_B64>; def S_MOVRELD_B32_vi : SOP1_Real_vi <0x2c, S_MOVRELD_B32>; def S_MOVRELD_B64_vi : SOP1_Real_vi <0x2d, S_MOVRELD_B64>; def S_CBRANCH_JOIN_vi : SOP1_Real_vi <0x2e, S_CBRANCH_JOIN>; -def S_MOV_REGRD_B32_vi : SOP1_Real_vi <0x2f, S_MOV_REGRD_B32>; def S_ABS_I32_vi : SOP1_Real_vi <0x30, S_ABS_I32>; -def S_MOV_FED_B32_vi : SOP1_Real_vi <0x31, S_MOV_FED_B32>; def S_SET_GPR_IDX_IDX_vi : SOP1_Real_vi <0x32, S_SET_GPR_IDX_IDX>; def S_ADD_U32_vi : SOP2_Real_vi <0x00, S_ADD_U32>; diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index 17f334f62a3..11ec2953e1e 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -338,8 +338,6 @@ defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_MOVRELS>; defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_MOVRELSD>; } // End Uses = [M0, EXEC] -defm V_MOV_FED_B32 : VOP1Inst <"v_mov_fed_b32", VOP_I32_I32>; - let SubtargetPredicate = isGFX6GFX7 in { let SchedRW = [WriteTrans32] in { defm V_LOG_CLAMP_F32 : @@ -650,7 +648,6 @@ defm V_CVT_F32_I32 : VOP1_Real_gfx6_gfx7_gfx10<0x005>; defm V_CVT_F32_U32 : VOP1_Real_gfx6_gfx7_gfx10<0x006>; defm V_CVT_U32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x007>; defm V_CVT_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x008>; -defm V_MOV_FED_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x009>; defm V_CVT_F16_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x00a>; defm V_CVT_F32_F16 : VOP1_Real_gfx6_gfx7_gfx10<0x00b>; defm V_CVT_RPI_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x00c>; @@ -754,7 +751,6 @@ defm V_CVT_F32_I32 : VOP1_Real_vi <0x5>; defm V_CVT_F32_U32 : VOP1_Real_vi <0x6>; defm V_CVT_U32_F32 : VOP1_Real_vi <0x7>; defm V_CVT_I32_F32 : VOP1_Real_vi <0x8>; -defm V_MOV_FED_B32 : VOP1_Real_vi <0x9>; defm V_CVT_F16_F32 : VOP1_Real_vi <0xa>; defm V_CVT_F32_F16 : VOP1_Real_vi <0xb>; defm V_CVT_RPI_I32_F32 : VOP1_Real_vi <0xc>; diff --git a/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir index 64b7299c45d..1922adf5ee6 100644 --- a/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir +++ b/llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir @@ -10,38 +10,9 @@ define amdgpu_kernel void @vmem_gt_8dw_store() { ret void } define amdgpu_kernel void @readwrite_lane() { ret void } define amdgpu_kernel void @rfe() { ret void } - define amdgpu_kernel void @s_mov_fed_b32() { ret void } define amdgpu_kernel void @s_movrel() { ret void } define amdgpu_kernel void @v_interp() { ret void } define amdgpu_kernel void @dpp() { ret void } - - define amdgpu_kernel void @mov_fed_hazard_crash_on_dbg_value(i32 addrspace(1)* %A) { - entry: - %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5) - store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4 - call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !5, metadata !11), !dbg !12 - ret void - } - - declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 - - !llvm.dbg.cu = !{!0} - !llvm.module.flags = !{!3, !4} - - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 (trunk 268929)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) - !1 = !DIFile(filename: "test01.cl", directory: "/dev/null") - !2 = !{} - !3 = !{i32 2, !"Dwarf Version", i32 2} - !4 = !{i32 2, !"Debug Info Version", i32 3} - !5 = !DILocalVariable(name: "A", arg: 1, scope: !6, file: !1, line: 1, type: !9) - !6 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !7, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, retainedNodes: !2) - !7 = !DISubroutineType(types: !8) - !8 = !{null, !9} - !9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, align: 32) - !10 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) - !11 = !DIExpression() - !12 = !DILocation(line: 1, column: 30, scope: !6) - ... --- # GCN-LABEL: name: div_fmas @@ -356,35 +327,6 @@ body: | ... --- -# GCN-LABEL: name: s_mov_fed_b32 - -# GCN-LABEL: bb.0: -# GCN: S_MOV_FED_B32 -# GFX9: S_NOP -# GCN-NEXT: S_MOV_B32 - -# GCN-LABEL: bb.1: -# GCN: S_MOV_FED_B32 -# GFX9: S_NOP -# GCN-NEXT: V_MOV_B32 -name: s_mov_fed_b32 - -body: | - bb.0: - $sgpr0 = S_MOV_FED_B32 $sgpr0 - $sgpr0 = S_MOV_B32 $sgpr0 - S_BRANCH %bb.1 - - bb.1: - $sgpr0 = S_MOV_FED_B32 $sgpr0 - $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec - S_ENDPGM 0 - -... - -... ---- - # GCN-LABEL: name: s_movrel # GCN-LABEL: bb.0: @@ -513,51 +455,3 @@ body: | $vgpr3 = V_MOV_B32_dpp $vgpr3, $vgpr0, 0, 15, 15, 0, implicit $exec S_ENDPGM 0 ... ---- -name: mov_fed_hazard_crash_on_dbg_value -alignment: 1 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: true -liveins: - - { reg: '$sgpr4_sgpr5' } - - { reg: '$sgpr6_sgpr7' } - - { reg: '$sgpr9' } - - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 16 - offsetAdjustment: 0 - maxAlignment: 8 - adjustsStack: false - hasCalls: false - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -stack: - - { id: 0, name: A.addr, offset: 0, size: 8, alignment: 8, local-offset: 0 } - - { id: 1, offset: 8, size: 4, alignment: 4 } -body: | - bb.0.entry: - liveins: $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr9, $sgpr0_sgpr1_sgpr2_sgpr3 - - $flat_scr_lo = S_ADD_U32 $sgpr6, $sgpr9, implicit-def $scc - $flat_scr_hi = S_ADDC_U32 $sgpr7, 0, implicit-def $scc, implicit $scc - DBG_VALUE $noreg, 2, !5, !11, debug-location !12 - $sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed $sgpr4_sgpr5, 0, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`) - dead $sgpr6_sgpr7 = KILL $sgpr4_sgpr5 - $sgpr8 = S_MOV_B32 $sgpr5 - $vgpr0 = V_MOV_B32_e32 killed $sgpr8, implicit $exec - BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.A.addr + 4) - $sgpr8 = S_MOV_B32 $sgpr4, implicit killed $sgpr4_sgpr5 - $vgpr0 = V_MOV_B32_e32 killed $sgpr8, implicit $exec - BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr9, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.A.addr) - S_ENDPGM 0 - -... diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_all.s b/llvm/test/MC/AMDGPU/gfx10_asm_all.s index 99fcf0ac8ed..d1bbde65394 100644 --- a/llvm/test/MC/AMDGPU/gfx10_asm_all.s +++ b/llvm/test/MC/AMDGPU/gfx10_asm_all.s @@ -12805,66 +12805,6 @@ s_abs_i32 s0, 0x3f717273 s_abs_i32 s0, 0xaf123456 // GFX10: encoding: [0xff,0x34,0x80,0xbe,0x56,0x34,0x12,0xaf] -s_mov_fed_b32 s0, s1 -// GFX10: encoding: [0x01,0x35,0x80,0xbe] - -s_mov_fed_b32 s105, s104 -// GFX10: encoding: [0x68,0x35,0xe9,0xbe] - -s_mov_fed_b32 s0, s104 -// GFX10: encoding: [0x68,0x35,0x80,0xbe] - -s_mov_fed_b32 s105, s1 -// GFX10: encoding: [0x01,0x35,0xe9,0xbe] - -s_mov_fed_b32 exec_lo, s1 -// GFX10: encoding: [0x01,0x35,0xfe,0xbe] - -s_mov_fed_b32 exec_hi, s1 -// GFX10: encoding: [0x01,0x35,0xff,0xbe] - -s_mov_fed_b32 vcc_lo, s1 -// GFX10: encoding: [0x01,0x35,0xea,0xbe] - -s_mov_fed_b32 vcc_hi, s1 -// GFX10: encoding: [0x01,0x35,0xeb,0xbe] - -s_mov_fed_b32 m0, s1 -// GFX10: encoding: [0x01,0x35,0xfc,0xbe] - -s_mov_fed_b32 s0, exec_lo -// GFX10: encoding: [0x7e,0x35,0x80,0xbe] - -s_mov_fed_b32 s0, exec_hi -// GFX10: encoding: [0x7f,0x35,0x80,0xbe] - -s_mov_fed_b32 s0, vcc_lo -// GFX10: encoding: [0x6a,0x35,0x80,0xbe] - -s_mov_fed_b32 s0, vcc_hi -// GFX10: encoding: [0x6b,0x35,0x80,0xbe] - -s_mov_fed_b32 s0, m0 -// GFX10: encoding: [0x7c,0x35,0x80,0xbe] - -s_mov_fed_b32 s0, 0 -// GFX10: encoding: [0x80,0x35,0x80,0xbe] - -s_mov_fed_b32 s0, -1 -// GFX10: encoding: [0xc1,0x35,0x80,0xbe] - -s_mov_fed_b32 s0, 0.5 -// GFX10: encoding: [0xf0,0x35,0x80,0xbe] - -s_mov_fed_b32 s0, -4.0 -// GFX10: encoding: [0xf7,0x35,0x80,0xbe] - -s_mov_fed_b32 s0, 0x3f717273 -// GFX10: encoding: [0xff,0x35,0x80,0xbe,0x73,0x72,0x71,0x3f] - -s_mov_fed_b32 s0, 0xaf123456 -// GFX10: encoding: [0xff,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf] - s_andn1_saveexec_b64 s[0:1], s[2:3] // GFX10: encoding: [0x02,0x37,0x80,0xbe] @@ -22278,258 +22218,6 @@ v_cvt_i32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0 v_cvt_i32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0 // GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x6f,0x01,0x00] -v_mov_fed_b32_e32 v5, v1 -// GFX10: encoding: [0x01,0x13,0x0a,0x7e] - -v_mov_fed_b32_e32 v255, v1 -// GFX10: encoding: [0x01,0x13,0xfe,0x7f] - -v_mov_fed_b32_e32 v5, v255 -// GFX10: encoding: [0xff,0x13,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, s1 -// GFX10: encoding: [0x01,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, s103 -// GFX10: encoding: [0x67,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, vcc_lo -// GFX10: encoding: [0x6a,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, vcc_hi -// GFX10: encoding: [0x6b,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, ttmp11 -// GFX10: encoding: [0x77,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, m0 -// GFX10: encoding: [0x7c,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, exec_lo -// GFX10: encoding: [0x7e,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, exec_hi -// GFX10: encoding: [0x7f,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, 0 -// GFX10: encoding: [0x80,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, -1 -// GFX10: encoding: [0xc1,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, 0.5 -// GFX10: encoding: [0xf0,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, -4.0 -// GFX10: encoding: [0xf7,0x12,0x0a,0x7e] - -v_mov_fed_b32_e32 v5, 0xaf123456 -// GFX10: encoding: [0xff,0x12,0x0a,0x7e,0x56,0x34,0x12,0xaf] - -v_mov_fed_b32_e32 v5, 0x3f717273 -// GFX10: encoding: [0xff,0x12,0x0a,0x7e,0x73,0x72,0x71,0x3f] - -v_mov_fed_b32_e64 v5, v1 -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0x01,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v255, v1 -// GFX10: encoding: [0xff,0x00,0x89,0xd5,0x01,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v5, v255 -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0xff,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v5, s1 -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0x01,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, s101 -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0x65,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, vcc_lo -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0x6a,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, vcc_hi -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0x6b,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, m0 -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0x7c,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, exec_lo -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0x7e,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, exec_hi -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0x7f,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, 0 -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0x80,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, -1 -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0xc1,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, 0.5 -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0xf0,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, -4.0 -// GFX10: encoding: [0x05,0x00,0x89,0xd5,0xf7,0x00,0x00,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0xfe,0x7f,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0xff,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x65,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x6a,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x6b,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x7c,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x7e,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x7f,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x00,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x01,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x02,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x03,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x04,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x05,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x0e,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x00,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x01,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x02,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x03,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x04,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x05,0x00] - -v_mov_fed_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// GFX10: encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x0e,0x00] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x00] - -v_mov_fed_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0xfe,0x7f,0x01,0xe4,0x00,0x00] - -v_mov_fed_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0xff,0xe4,0x00,0x00] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x1b,0x00,0x00] - -v_mov_fed_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x40,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x41,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x01,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x0f,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x11,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x1f,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x21,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x2f,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x10] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x30] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x01] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x03] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x08,0x00] - -v_mov_fed_b32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x51,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x5f,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x61,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0 -// GFX10: encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x6f,0x01,0x00] - v_cvt_f16_f32 v5, v1 // GFX10: encoding: [0x01,0x15,0x0a,0x7e] diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s b/llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s index 70d779a047b..b8ede28ec07 100644 --- a/llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx10_asm_dpp8.s @@ -18,9 +18,6 @@ v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] v_cvt_i32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] // GFX10: encoding: [0xe9,0x10,0x0a,0x7e,0x01,0x88,0xc6,0xfa] -v_mov_fed_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] -// GFX10: encoding: [0xe9,0x12,0x0a,0x7e,0x01,0x88,0xc6,0xfa] - v_cvt_f16_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] // GFX10: encoding: [0xe9,0x14,0x0a,0x7e,0x01,0x88,0xc6,0xfa] @@ -273,9 +270,6 @@ v_cvt_u32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 v_cvt_i32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 // GFX10: encoding: [0xea,0x10,0x0a,0x7e,0x01,0x88,0xc6,0xfa] -v_mov_fed_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 -// GFX10: encoding: [0xea,0x12,0x0a,0x7e,0x01,0x88,0xc6,0xfa] - v_cvt_f16_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 // GFX10: encoding: [0xea,0x14,0x0a,0x7e,0x01,0x88,0xc6,0xfa] diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_err.s b/llvm/test/MC/AMDGPU/gfx10_asm_err.s index eff0cff4272..251dde827b7 100644 --- a/llvm/test/MC/AMDGPU/gfx10_asm_err.s +++ b/llvm/test/MC/AMDGPU/gfx10_asm_err.s @@ -130,9 +130,6 @@ s_set_gpr_idx_idx s0 s_cbranch_join s0 // GFX10: error: instruction not supported on this GPU -s_mov_regrd_b32 s0, s1 -// GFX10: error: instruction not supported on this GPU - //===----------------------------------------------------------------------===// // ENC_SOP2. //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_all.s b/llvm/test/MC/AMDGPU/gfx7_asm_all.s index 434c64b72ff..73247d17aed 100644 --- a/llvm/test/MC/AMDGPU/gfx7_asm_all.s +++ b/llvm/test/MC/AMDGPU/gfx7_asm_all.s @@ -14148,105 +14148,6 @@ s_abs_i32 s5, 0xaf123456 s_abs_i32 s5, 0x3f717273 // CHECK: [0xff,0x34,0x85,0xbe,0x73,0x72,0x71,0x3f] -s_mov_fed_b32 s5, s1 -// CHECK: [0x01,0x35,0x85,0xbe] - -s_mov_fed_b32 s103, s1 -// CHECK: [0x01,0x35,0xe7,0xbe] - -s_mov_fed_b32 flat_scratch_lo, s1 -// CHECK: [0x01,0x35,0xe8,0xbe] - -s_mov_fed_b32 flat_scratch_hi, s1 -// CHECK: [0x01,0x35,0xe9,0xbe] - -s_mov_fed_b32 vcc_lo, s1 -// CHECK: [0x01,0x35,0xea,0xbe] - -s_mov_fed_b32 vcc_hi, s1 -// CHECK: [0x01,0x35,0xeb,0xbe] - -s_mov_fed_b32 tba_lo, s1 -// CHECK: [0x01,0x35,0xec,0xbe] - -s_mov_fed_b32 tba_hi, s1 -// CHECK: [0x01,0x35,0xed,0xbe] - -s_mov_fed_b32 tma_lo, s1 -// CHECK: [0x01,0x35,0xee,0xbe] - -s_mov_fed_b32 tma_hi, s1 -// CHECK: [0x01,0x35,0xef,0xbe] - -s_mov_fed_b32 ttmp11, s1 -// CHECK: [0x01,0x35,0xfb,0xbe] - -s_mov_fed_b32 m0, s1 -// CHECK: [0x01,0x35,0xfc,0xbe] - -s_mov_fed_b32 exec_lo, s1 -// CHECK: [0x01,0x35,0xfe,0xbe] - -s_mov_fed_b32 exec_hi, s1 -// CHECK: [0x01,0x35,0xff,0xbe] - -s_mov_fed_b32 s5, s103 -// CHECK: [0x67,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, flat_scratch_lo -// CHECK: [0x68,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, flat_scratch_hi -// CHECK: [0x69,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, vcc_lo -// CHECK: [0x6a,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, vcc_hi -// CHECK: [0x6b,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, tba_lo -// CHECK: [0x6c,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, tba_hi -// CHECK: [0x6d,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, tma_lo -// CHECK: [0x6e,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, tma_hi -// CHECK: [0x6f,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, ttmp11 -// CHECK: [0x7b,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, m0 -// CHECK: [0x7c,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, exec_lo -// CHECK: [0x7e,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, exec_hi -// CHECK: [0x7f,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, 0 -// CHECK: [0x80,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, -1 -// CHECK: [0xc1,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, 0.5 -// CHECK: [0xf0,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, -4.0 -// CHECK: [0xf7,0x35,0x85,0xbe] - -s_mov_fed_b32 s5, 0xaf123456 -// CHECK: [0xff,0x35,0x85,0xbe,0x56,0x34,0x12,0xaf] - -s_mov_fed_b32 s5, 0x3f717273 -// CHECK: [0xff,0x35,0x85,0xbe,0x73,0x72,0x71,0x3f] - s_add_u32 s5, s1, s2 // CHECK: [0x01,0x02,0x05,0x80] @@ -24318,138 +24219,6 @@ v_cvt_i32_f32_e64 v5, -v1 v_cvt_i32_f32_e64 v5, |v1| // CHECK: [0x05,0x01,0x10,0xd3,0x01,0x01,0x00,0x00] -v_mov_fed_b32 v5, v1 -// CHECK: [0x01,0x13,0x0a,0x7e] - -v_mov_fed_b32 v255, v1 -// CHECK: [0x01,0x13,0xfe,0x7f] - -v_mov_fed_b32 v5, v255 -// CHECK: [0xff,0x13,0x0a,0x7e] - -v_mov_fed_b32 v5, s1 -// CHECK: [0x01,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, s103 -// CHECK: [0x67,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, flat_scratch_lo -// CHECK: [0x68,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, flat_scratch_hi -// CHECK: [0x69,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, vcc_lo -// CHECK: [0x6a,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, vcc_hi -// CHECK: [0x6b,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, tba_lo -// CHECK: [0x6c,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, tba_hi -// CHECK: [0x6d,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, tma_lo -// CHECK: [0x6e,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, tma_hi -// CHECK: [0x6f,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, ttmp11 -// CHECK: [0x7b,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, m0 -// CHECK: [0x7c,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, exec_lo -// CHECK: [0x7e,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, exec_hi -// CHECK: [0x7f,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, 0 -// CHECK: [0x80,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, -1 -// CHECK: [0xc1,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, 0.5 -// CHECK: [0xf0,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, -4.0 -// CHECK: [0xf7,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, 0xaf123456 -// CHECK: [0xff,0x12,0x0a,0x7e,0x56,0x34,0x12,0xaf] - -v_mov_fed_b32 v5, 0x3f717273 -// CHECK: [0xff,0x12,0x0a,0x7e,0x73,0x72,0x71,0x3f] - -v_mov_fed_b32_e64 v5, v1 -// CHECK: [0x05,0x00,0x12,0xd3,0x01,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v255, v1 -// CHECK: [0xff,0x00,0x12,0xd3,0x01,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v5, v255 -// CHECK: [0x05,0x00,0x12,0xd3,0xff,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v5, s1 -// CHECK: [0x05,0x00,0x12,0xd3,0x01,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, s103 -// CHECK: [0x05,0x00,0x12,0xd3,0x67,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, flat_scratch_lo -// CHECK: [0x05,0x00,0x12,0xd3,0x68,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, flat_scratch_hi -// CHECK: [0x05,0x00,0x12,0xd3,0x69,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, vcc_lo -// CHECK: [0x05,0x00,0x12,0xd3,0x6a,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, vcc_hi -// CHECK: [0x05,0x00,0x12,0xd3,0x6b,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, tba_lo -// CHECK: [0x05,0x00,0x12,0xd3,0x6c,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, tba_hi -// CHECK: [0x05,0x00,0x12,0xd3,0x6d,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, tma_lo -// CHECK: [0x05,0x00,0x12,0xd3,0x6e,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, tma_hi -// CHECK: [0x05,0x00,0x12,0xd3,0x6f,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, ttmp11 -// CHECK: [0x05,0x00,0x12,0xd3,0x7b,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, m0 -// CHECK: [0x05,0x00,0x12,0xd3,0x7c,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, exec_lo -// CHECK: [0x05,0x00,0x12,0xd3,0x7e,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, exec_hi -// CHECK: [0x05,0x00,0x12,0xd3,0x7f,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, 0 -// CHECK: [0x05,0x00,0x12,0xd3,0x80,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, -1 -// CHECK: [0x05,0x00,0x12,0xd3,0xc1,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, 0.5 -// CHECK: [0x05,0x00,0x12,0xd3,0xf0,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, -4.0 -// CHECK: [0x05,0x00,0x12,0xd3,0xf7,0x00,0x00,0x00] - v_cvt_f16_f32 v5, v1 // CHECK: [0x01,0x15,0x0a,0x7e] diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_all.s b/llvm/test/MC/AMDGPU/gfx8_asm_all.s index 369faf09a63..1610bfa7d92 100644 --- a/llvm/test/MC/AMDGPU/gfx8_asm_all.s +++ b/llvm/test/MC/AMDGPU/gfx8_asm_all.s @@ -14926,105 +14926,6 @@ s_abs_i32 s5, 0xaf123456 s_abs_i32 s5, 0x3f717273 // CHECK: [0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f] -s_mov_fed_b32 s5, s1 -// CHECK: [0x01,0x31,0x85,0xbe] - -s_mov_fed_b32 s101, s1 -// CHECK: [0x01,0x31,0xe5,0xbe] - -s_mov_fed_b32 flat_scratch_lo, s1 -// CHECK: [0x01,0x31,0xe6,0xbe] - -s_mov_fed_b32 flat_scratch_hi, s1 -// CHECK: [0x01,0x31,0xe7,0xbe] - -s_mov_fed_b32 vcc_lo, s1 -// CHECK: [0x01,0x31,0xea,0xbe] - -s_mov_fed_b32 vcc_hi, s1 -// CHECK: [0x01,0x31,0xeb,0xbe] - -s_mov_fed_b32 tba_lo, s1 -// CHECK: [0x01,0x31,0xec,0xbe] - -s_mov_fed_b32 tba_hi, s1 -// CHECK: [0x01,0x31,0xed,0xbe] - -s_mov_fed_b32 tma_lo, s1 -// CHECK: [0x01,0x31,0xee,0xbe] - -s_mov_fed_b32 tma_hi, s1 -// CHECK: [0x01,0x31,0xef,0xbe] - -s_mov_fed_b32 ttmp11, s1 -// CHECK: [0x01,0x31,0xfb,0xbe] - -s_mov_fed_b32 m0, s1 -// CHECK: [0x01,0x31,0xfc,0xbe] - -s_mov_fed_b32 exec_lo, s1 -// CHECK: [0x01,0x31,0xfe,0xbe] - -s_mov_fed_b32 exec_hi, s1 -// CHECK: [0x01,0x31,0xff,0xbe] - -s_mov_fed_b32 s5, s101 -// CHECK: [0x65,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, flat_scratch_lo -// CHECK: [0x66,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, flat_scratch_hi -// CHECK: [0x67,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, vcc_lo -// CHECK: [0x6a,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, vcc_hi -// CHECK: [0x6b,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, tba_lo -// CHECK: [0x6c,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, tba_hi -// CHECK: [0x6d,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, tma_lo -// CHECK: [0x6e,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, tma_hi -// CHECK: [0x6f,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, ttmp11 -// CHECK: [0x7b,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, m0 -// CHECK: [0x7c,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, exec_lo -// CHECK: [0x7e,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, exec_hi -// CHECK: [0x7f,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, 0 -// CHECK: [0x80,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, -1 -// CHECK: [0xc1,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, 0.5 -// CHECK: [0xf0,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, -4.0 -// CHECK: [0xf7,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, 0xaf123456 -// CHECK: [0xff,0x31,0x85,0xbe,0x56,0x34,0x12,0xaf] - -s_mov_fed_b32 s5, 0x3f717273 -// CHECK: [0xff,0x31,0x85,0xbe,0x73,0x72,0x71,0x3f] - s_set_gpr_idx_idx s1 // CHECK: [0x01,0x32,0x80,0xbe] @@ -25642,138 +25543,6 @@ v_cvt_i32_f32_e64 v5, -v1 v_cvt_i32_f32_e64 v5, |v1| // CHECK: [0x05,0x01,0x48,0xd1,0x01,0x01,0x00,0x00] -v_mov_fed_b32 v5, v1 -// CHECK: [0x01,0x13,0x0a,0x7e] - -v_mov_fed_b32 v255, v1 -// CHECK: [0x01,0x13,0xfe,0x7f] - -v_mov_fed_b32 v5, v255 -// CHECK: [0xff,0x13,0x0a,0x7e] - -v_mov_fed_b32 v5, s1 -// CHECK: [0x01,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, s101 -// CHECK: [0x65,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, flat_scratch_lo -// CHECK: [0x66,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, flat_scratch_hi -// CHECK: [0x67,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, vcc_lo -// CHECK: [0x6a,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, vcc_hi -// CHECK: [0x6b,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, tba_lo -// CHECK: [0x6c,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, tba_hi -// CHECK: [0x6d,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, tma_lo -// CHECK: [0x6e,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, tma_hi -// CHECK: [0x6f,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, ttmp11 -// CHECK: [0x7b,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, m0 -// CHECK: [0x7c,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, exec_lo -// CHECK: [0x7e,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, exec_hi -// CHECK: [0x7f,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, 0 -// CHECK: [0x80,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, -1 -// CHECK: [0xc1,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, 0.5 -// CHECK: [0xf0,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, -4.0 -// CHECK: [0xf7,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, 0xaf123456 -// CHECK: [0xff,0x12,0x0a,0x7e,0x56,0x34,0x12,0xaf] - -v_mov_fed_b32 v5, 0x3f717273 -// CHECK: [0xff,0x12,0x0a,0x7e,0x73,0x72,0x71,0x3f] - -v_mov_fed_b32_e64 v5, v1 -// CHECK: [0x05,0x00,0x49,0xd1,0x01,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v255, v1 -// CHECK: [0xff,0x00,0x49,0xd1,0x01,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v5, v255 -// CHECK: [0x05,0x00,0x49,0xd1,0xff,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v5, s1 -// CHECK: [0x05,0x00,0x49,0xd1,0x01,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, s101 -// CHECK: [0x05,0x00,0x49,0xd1,0x65,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, flat_scratch_lo -// CHECK: [0x05,0x00,0x49,0xd1,0x66,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, flat_scratch_hi -// CHECK: [0x05,0x00,0x49,0xd1,0x67,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, vcc_lo -// CHECK: [0x05,0x00,0x49,0xd1,0x6a,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, vcc_hi -// CHECK: [0x05,0x00,0x49,0xd1,0x6b,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, tba_lo -// CHECK: [0x05,0x00,0x49,0xd1,0x6c,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, tba_hi -// CHECK: [0x05,0x00,0x49,0xd1,0x6d,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, tma_lo -// CHECK: [0x05,0x00,0x49,0xd1,0x6e,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, tma_hi -// CHECK: [0x05,0x00,0x49,0xd1,0x6f,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, ttmp11 -// CHECK: [0x05,0x00,0x49,0xd1,0x7b,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, m0 -// CHECK: [0x05,0x00,0x49,0xd1,0x7c,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, exec_lo -// CHECK: [0x05,0x00,0x49,0xd1,0x7e,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, exec_hi -// CHECK: [0x05,0x00,0x49,0xd1,0x7f,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, 0 -// CHECK: [0x05,0x00,0x49,0xd1,0x80,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, -1 -// CHECK: [0x05,0x00,0x49,0xd1,0xc1,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, 0.5 -// CHECK: [0x05,0x00,0x49,0xd1,0xf0,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, -4.0 -// CHECK: [0x05,0x00,0x49,0xd1,0xf7,0x00,0x00,0x00] - v_cvt_f16_f32 v5, v1 // CHECK: [0x01,0x15,0x0a,0x7e] @@ -95656,150 +95425,6 @@ v_cvt_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 v_cvt_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 // CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00] -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0xfe,0x7f,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0xff,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x00,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x01,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x02,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x03,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x04,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x05,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x0e,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x00,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x01,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x02,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x03,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x04,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x05,0x00] - -v_mov_fed_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x0e,0x00] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x00] - -v_mov_fed_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0xfe,0x7f,0x01,0xe4,0x00,0x00] - -v_mov_fed_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0xff,0xe4,0x00,0x00] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x1b,0x00,0x00] - -v_mov_fed_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x40,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x41,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x42,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x43,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x30,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x34,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x38,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x3c,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x01,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x0f,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x11,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x1f,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x21,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x2f,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x10] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x30] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x01] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x03] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x08,0x00] - v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD // CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_all.s b/llvm/test/MC/AMDGPU/gfx9_asm_all.s index 70771291545..b3b8bf86a13 100644 --- a/llvm/test/MC/AMDGPU/gfx9_asm_all.s +++ b/llvm/test/MC/AMDGPU/gfx9_asm_all.s @@ -14273,75 +14273,6 @@ s_abs_i32 s5, 0xaf123456 s_abs_i32 s5, 0x3f717273 // CHECK: [0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f] -s_mov_fed_b32 s5, s1 -// CHECK: [0x01,0x31,0x85,0xbe] - -s_mov_fed_b32 s101, s1 -// CHECK: [0x01,0x31,0xe5,0xbe] - -s_mov_fed_b32 flat_scratch_lo, s1 -// CHECK: [0x01,0x31,0xe6,0xbe] - -s_mov_fed_b32 flat_scratch_hi, s1 -// CHECK: [0x01,0x31,0xe7,0xbe] - -s_mov_fed_b32 vcc_lo, s1 -// CHECK: [0x01,0x31,0xea,0xbe] - -s_mov_fed_b32 vcc_hi, s1 -// CHECK: [0x01,0x31,0xeb,0xbe] - -s_mov_fed_b32 m0, s1 -// CHECK: [0x01,0x31,0xfc,0xbe] - -s_mov_fed_b32 exec_lo, s1 -// CHECK: [0x01,0x31,0xfe,0xbe] - -s_mov_fed_b32 exec_hi, s1 -// CHECK: [0x01,0x31,0xff,0xbe] - -s_mov_fed_b32 s5, s101 -// CHECK: [0x65,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, flat_scratch_lo -// CHECK: [0x66,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, flat_scratch_hi -// CHECK: [0x67,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, vcc_lo -// CHECK: [0x6a,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, vcc_hi -// CHECK: [0x6b,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, m0 -// CHECK: [0x7c,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, exec_lo -// CHECK: [0x7e,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, exec_hi -// CHECK: [0x7f,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, 0 -// CHECK: [0x80,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, -1 -// CHECK: [0xc1,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, 0.5 -// CHECK: [0xf0,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, -4.0 -// CHECK: [0xf7,0x31,0x85,0xbe] - -s_mov_fed_b32 s5, 0xaf123456 -// CHECK: [0xff,0x31,0x85,0xbe,0x56,0x34,0x12,0xaf] - -s_mov_fed_b32 s5, 0x3f717273 -// CHECK: [0xff,0x31,0x85,0xbe,0x73,0x72,0x71,0x3f] - s_set_gpr_idx_idx s1 // CHECK: [0x01,0x32,0x80,0xbe] @@ -22541,108 +22472,6 @@ v_cvt_i32_f32_e64 v5, |v1| v_cvt_i32_f32_e64 v5, v1 clamp // CHECK: [0x05,0x80,0x48,0xd1,0x01,0x01,0x00,0x00] -v_mov_fed_b32 v5, v1 -// CHECK: [0x01,0x13,0x0a,0x7e] - -v_mov_fed_b32 v255, v1 -// CHECK: [0x01,0x13,0xfe,0x7f] - -v_mov_fed_b32 v5, v255 -// CHECK: [0xff,0x13,0x0a,0x7e] - -v_mov_fed_b32 v5, s1 -// CHECK: [0x01,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, s101 -// CHECK: [0x65,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, flat_scratch_lo -// CHECK: [0x66,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, flat_scratch_hi -// CHECK: [0x67,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, vcc_lo -// CHECK: [0x6a,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, vcc_hi -// CHECK: [0x6b,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, m0 -// CHECK: [0x7c,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, exec_lo -// CHECK: [0x7e,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, exec_hi -// CHECK: [0x7f,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, 0 -// CHECK: [0x80,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, -1 -// CHECK: [0xc1,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, 0.5 -// CHECK: [0xf0,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, -4.0 -// CHECK: [0xf7,0x12,0x0a,0x7e] - -v_mov_fed_b32 v5, 0xaf123456 -// CHECK: [0xff,0x12,0x0a,0x7e,0x56,0x34,0x12,0xaf] - -v_mov_fed_b32 v5, 0x3f717273 -// CHECK: [0xff,0x12,0x0a,0x7e,0x73,0x72,0x71,0x3f] - -v_mov_fed_b32_e64 v5, v1 -// CHECK: [0x05,0x00,0x49,0xd1,0x01,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v255, v1 -// CHECK: [0xff,0x00,0x49,0xd1,0x01,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v5, v255 -// CHECK: [0x05,0x00,0x49,0xd1,0xff,0x01,0x00,0x00] - -v_mov_fed_b32_e64 v5, s1 -// CHECK: [0x05,0x00,0x49,0xd1,0x01,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, s101 -// CHECK: [0x05,0x00,0x49,0xd1,0x65,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, flat_scratch_lo -// CHECK: [0x05,0x00,0x49,0xd1,0x66,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, flat_scratch_hi -// CHECK: [0x05,0x00,0x49,0xd1,0x67,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, vcc_lo -// CHECK: [0x05,0x00,0x49,0xd1,0x6a,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, vcc_hi -// CHECK: [0x05,0x00,0x49,0xd1,0x6b,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, m0 -// CHECK: [0x05,0x00,0x49,0xd1,0x7c,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, exec_lo -// CHECK: [0x05,0x00,0x49,0xd1,0x7e,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, exec_hi -// CHECK: [0x05,0x00,0x49,0xd1,0x7f,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, 0 -// CHECK: [0x05,0x00,0x49,0xd1,0x80,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, -1 -// CHECK: [0x05,0x00,0x49,0xd1,0xc1,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, 0.5 -// CHECK: [0x05,0x00,0x49,0xd1,0xf0,0x00,0x00,0x00] - -v_mov_fed_b32_e64 v5, -4.0 -// CHECK: [0x05,0x00,0x49,0xd1,0xf7,0x00,0x00,0x00] - v_cvt_f16_f32 v5, v1 // CHECK: [0x01,0x15,0x0a,0x7e] @@ -84467,189 +84296,6 @@ v_cvt_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 v_cvt_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 // CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00] -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0xfe,0x7f,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0xff,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x65,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x66,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x67,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x6a,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x6b,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x7c,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x7e,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x7f,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x80,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0xc1,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0xf0,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0xf7,0x06,0x86,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x00,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x01,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x02,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x03,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x04,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x05,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x0e,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x00,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x01,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x02,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x03,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x04,0x00] - -v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x05,0x00] - -v_mov_fed_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD -// CHECK: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x0e,0x00] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x00] - -v_mov_fed_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0xfe,0x7f,0x01,0xe4,0x00,0x00] - -v_mov_fed_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0xff,0xe4,0x00,0x00] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x1b,0x00,0x00] - -v_mov_fed_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x40,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x41,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x42,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x43,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x30,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x34,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x38,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x3c,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x01,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x0f,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x11,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x1f,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x21,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0x2f,0x01,0x00] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x10] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x30] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x01] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x03] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f] - -v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 -// CHECK: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x08,0x00] - v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD // CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00] diff --git a/llvm/test/MC/AMDGPU/lds_direct.s b/llvm/test/MC/AMDGPU/lds_direct.s index 6a879ee03d1..e677f59ad74 100644 --- a/llvm/test/MC/AMDGPU/lds_direct.s +++ b/llvm/test/MC/AMDGPU/lds_direct.s @@ -16,12 +16,6 @@ v_cvt_f64_i32 v[0:1], src_lds_direct v_cvt_f64_i32_e64 v[0:1], src_lds_direct // GFX9: v_cvt_f64_i32_e64 v[0:1], src_lds_direct ; encoding: [0x00,0x00,0x44,0xd1,0xfe,0x00,0x00,0x00] -v_mov_fed_b32 v0, src_lds_direct -// GFX9: v_mov_fed_b32_e32 v0, src_lds_direct ; encoding: [0xfe,0x12,0x00,0x7e] - -v_mov_fed_b32_e64 v0, src_lds_direct -// GFX9: v_mov_fed_b32_e64 v0, src_lds_direct ; encoding: [0x00,0x00,0x49,0xd1,0xfe,0x00,0x00,0x00] - v_fract_f32 v0, src_lds_direct // GFX9: v_fract_f32_e32 v0, src_lds_direct ; encoding: [0xfe,0x36,0x00,0x7e] diff --git a/llvm/test/MC/AMDGPU/sop1.s b/llvm/test/MC/AMDGPU/sop1.s index 97920ac7051..76525b943ca 100644 --- a/llvm/test/MC/AMDGPU/sop1.s +++ b/llvm/test/MC/AMDGPU/sop1.s @@ -259,9 +259,6 @@ s_abs_i32 s1, s2 // SICI: s_abs_i32 s1, s2 ; encoding: [0x02,0x34,0x81,0xbe] // GFX89: s_abs_i32 s1, s2 ; encoding: [0x02,0x30,0x81,0xbe] -s_mov_fed_b32 s1, s2 -// SICI: s_mov_fed_b32 s1, s2 ; encoding: [0x02,0x35,0x81,0xbe] - s_set_gpr_idx_idx s0 // GFX89: s_set_gpr_idx_idx s0 ; encoding: [0x00,0x32,0x80,0xbe] // NOSICI: error: instruction not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/vop1.s b/llvm/test/MC/AMDGPU/vop1.s index 8ef640caa61..e9d288418c4 100644 --- a/llvm/test/MC/AMDGPU/vop1.s +++ b/llvm/test/MC/AMDGPU/vop1.s @@ -55,10 +55,6 @@ v_cvt_u32_f32_e32 v1, v2 // GCN: v_cvt_i32_f32_e32 v1, v2 ; encoding: [0x02,0x11,0x02,0x7e] v_cvt_i32_f32_e32 v1, v2 -// SICI: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e] -// VI: v_mov_fed_b32_e32 v1, v2 ; encoding: [0x02,0x13,0x02,0x7e] -v_mov_fed_b32_e32 v1, v2 - // GCN: v_cvt_f16_f32_e32 v1, v2 ; encoding: [0x02,0x15,0x02,0x7e] v_cvt_f16_f32_e32 v1, v2 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt index 72477fecdb1..fe9986c05ee 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt @@ -15707,66 +15707,6 @@ # GFX10: s_mov_b64 vcc, s[2:3] ; encoding: [0x02,0x04,0xea,0xbe] 0x02,0x04,0xea,0xbe -# GFX10: s_mov_fed_b32 exec_hi, s1 ; encoding: [0x01,0x35,0xff,0xbe] -0x01,0x35,0xff,0xbe - -# GFX10: s_mov_fed_b32 exec_lo, s1 ; encoding: [0x01,0x35,0xfe,0xbe] -0x01,0x35,0xfe,0xbe - -# GFX10: s_mov_fed_b32 m0, s1 ; encoding: [0x01,0x35,0xfc,0xbe] -0x01,0x35,0xfc,0xbe - -# GFX10: s_mov_fed_b32 s0, -1 ; encoding: [0xc1,0x35,0x80,0xbe] -0xc1,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s0, -4.0 ; encoding: [0xf7,0x35,0x80,0xbe] -0xf7,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s0, 0 ; encoding: [0x80,0x35,0x80,0xbe] -0x80,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s0, 0.5 ; encoding: [0xf0,0x35,0x80,0xbe] -0xf0,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s0, 0x3f717273 ; encoding: [0xff,0x35,0x80,0xbe,0x73,0x72,0x71,0x3f] -0xff,0x35,0x80,0xbe,0x73,0x72,0x71,0x3f - -# GFX10: s_mov_fed_b32 s0, 0xaf123456 ; encoding: [0xff,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf] -0xff,0x35,0x80,0xbe,0x56,0x34,0x12,0xaf - -# GFX10: s_mov_fed_b32 s0, exec_hi ; encoding: [0x7f,0x35,0x80,0xbe] -0x7f,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s0, exec_lo ; encoding: [0x7e,0x35,0x80,0xbe] -0x7e,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s0, m0 ; encoding: [0x7c,0x35,0x80,0xbe] -0x7c,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s0, s1 ; encoding: [0x01,0x35,0x80,0xbe] -0x01,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s0, s104 ; encoding: [0x68,0x35,0x80,0xbe] -0x68,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s0, vcc_hi ; encoding: [0x6b,0x35,0x80,0xbe] -0x6b,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s0, vcc_lo ; encoding: [0x6a,0x35,0x80,0xbe] -0x6a,0x35,0x80,0xbe - -# GFX10: s_mov_fed_b32 s105, s1 ; encoding: [0x01,0x35,0xe9,0xbe] -0x01,0x35,0xe9,0xbe - -# GFX10: s_mov_fed_b32 s105, s104 ; encoding: [0x68,0x35,0xe9,0xbe] -0x68,0x35,0xe9,0xbe - -# GFX10: s_mov_fed_b32 vcc_hi, s1 ; encoding: [0x01,0x35,0xeb,0xbe] -0x01,0x35,0xeb,0xbe - -# GFX10: s_mov_fed_b32 vcc_lo, s1 ; encoding: [0x01,0x35,0xea,0xbe] -0x01,0x35,0xea,0xbe - # GFX10: s_movk_i32 exec_hi, 0x1234 ; encoding: [0x34,0x12,0x7f,0xb0] 0x34,0x12,0x7f,0xb0 @@ -86004,243 +85944,6 @@ # GFX10: v_mov_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x02,0x0a,0x7e,0x6a,0x06,0x86,0x00] 0xf9,0x02,0x0a,0x7e,0x6a,0x06,0x86,0x00 -# GFX10: v_mov_fed_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0xfe,0x7f,0x01,0xe4,0x00,0x00] -0xfa,0x12,0xfe,0x7f,0x01,0xe4,0x00,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x08,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x08,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x01] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x01 - -# GFX10: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x03] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x03 - -# GFX10: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f - -# GFX10: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x10] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x10 - -# GFX10: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x30] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x30 - -# GFX10: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0 - -# GFX10: v_mov_fed_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x1b,0x00,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x1b,0x00,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x41,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x41,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x40,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x40,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x21,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x21,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x2f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x2f,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x51,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x51,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x5f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x5f,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x01,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x01,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x0f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x0f,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x11,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x11,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x1f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x1f,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x61,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x61,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x6f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x6f,0x01,0x00 - -# GFX10: v_mov_fed_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0xff,0xe4,0x00,0x00] -0xfa,0x12,0x0a,0x7e,0xff,0xe4,0x00,0x00 - -# GFX10: v_mov_fed_b32_e32 v255, v1 ; encoding: [0x01,0x13,0xfe,0x7f] -0x01,0x13,0xfe,0x7f - -# GFX10: v_mov_fed_b32_e32 v5, -1 ; encoding: [0xc1,0x12,0x0a,0x7e] -0xc1,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, -4.0 ; encoding: [0xf7,0x12,0x0a,0x7e] -0xf7,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, 0 ; encoding: [0x80,0x12,0x0a,0x7e] -0x80,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, 0.5 ; encoding: [0xf0,0x12,0x0a,0x7e] -0xf0,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, 0x3f717273 ; encoding: [0xff,0x12,0x0a,0x7e,0x73,0x72,0x71,0x3f] -0xff,0x12,0x0a,0x7e,0x73,0x72,0x71,0x3f - -# GFX10: v_mov_fed_b32_e32 v5, 0xaf123456 ; encoding: [0xff,0x12,0x0a,0x7e,0x56,0x34,0x12,0xaf] -0xff,0x12,0x0a,0x7e,0x56,0x34,0x12,0xaf - -# GFX10: v_mov_fed_b32_e32 v5, exec_hi ; encoding: [0x7f,0x12,0x0a,0x7e] -0x7f,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, exec_lo ; encoding: [0x7e,0x12,0x0a,0x7e] -0x7e,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, m0 ; encoding: [0x7c,0x12,0x0a,0x7e] -0x7c,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, s1 ; encoding: [0x01,0x12,0x0a,0x7e] -0x01,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, s103 ; encoding: [0x67,0x12,0x0a,0x7e] -0x67,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, ttmp11 ; encoding: [0x77,0x12,0x0a,0x7e] -0x77,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, v1 ; encoding: [0x01,0x13,0x0a,0x7e] -0x01,0x13,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, v255 ; encoding: [0xff,0x13,0x0a,0x7e] -0xff,0x13,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, vcc_hi ; encoding: [0x6b,0x12,0x0a,0x7e] -0x6b,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e32 v5, vcc_lo ; encoding: [0x6a,0x12,0x0a,0x7e] -0x6a,0x12,0x0a,0x7e - -# GFX10: v_mov_fed_b32_e64 v255, v1 ; encoding: [0xff,0x00,0x89,0xd5,0x01,0x01,0x00,0x00] -0xff,0x00,0x89,0xd5,0x01,0x01,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, -1 ; encoding: [0x05,0x00,0x89,0xd5,0xc1,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0xc1,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, -4.0 ; encoding: [0x05,0x00,0x89,0xd5,0xf7,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0xf7,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, 0 ; encoding: [0x05,0x00,0x89,0xd5,0x80,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0x80,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, 0.5 ; encoding: [0x05,0x00,0x89,0xd5,0xf0,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0xf0,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, exec_hi ; encoding: [0x05,0x00,0x89,0xd5,0x7f,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0x7f,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, exec_lo ; encoding: [0x05,0x00,0x89,0xd5,0x7e,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0x7e,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, m0 ; encoding: [0x05,0x00,0x89,0xd5,0x7c,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0x7c,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, s1 ; encoding: [0x05,0x00,0x89,0xd5,0x01,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0x01,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, s101 ; encoding: [0x05,0x00,0x89,0xd5,0x65,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0x65,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, v1 ; encoding: [0x05,0x00,0x89,0xd5,0x01,0x01,0x00,0x00] -0x05,0x00,0x89,0xd5,0x01,0x01,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, v255 ; encoding: [0x05,0x00,0x89,0xd5,0xff,0x01,0x00,0x00] -0x05,0x00,0x89,0xd5,0xff,0x01,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, vcc_hi ; encoding: [0x05,0x00,0x89,0xd5,0x6b,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0x6b,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_e64 v5, vcc_lo ; encoding: [0x05,0x00,0x89,0xd5,0x6a,0x00,0x00,0x00] -0x05,0x00,0x89,0xd5,0x6a,0x00,0x00,0x00 - -# GFX10: v_mov_fed_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0xfe,0x7f,0x01,0x06,0x06,0x00] -0xf9,0x12,0xfe,0x7f,0x01,0x06,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x7f,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x7f,0x06,0x86,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x7e,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x7e,0x06,0x86,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x7c,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x7c,0x06,0x86,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x86,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x65,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x65,0x06,0x86,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x0e,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x0e,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x00,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x00,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x01,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x01,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x02,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x02,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x03,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x03,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x00,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x00,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x01,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x01,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x02,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x02,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x03,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x03,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x04,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x04,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x05,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x05,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x0e,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x0e,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x04,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x04,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x05,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x05,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0xff,0x06,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0xff,0x06,0x06,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x6b,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x6b,0x06,0x86,0x00 - -# GFX10: v_mov_fed_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x6a,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x6a,0x06,0x86,0x00 - # GFX10: v_movreld_b32_e32 v255, v1 ; encoding: [0x01,0x85,0xfe,0x7f] 0x01,0x85,0xfe,0x7f diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_dpp8.txt index afd0e63f3b6..f77ac1247b9 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_dpp8.txt @@ -16,9 +16,6 @@ # GFX10: v_cvt_i32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0x10,0x0a,0x7e,0x01,0x88,0xc6,0xfa] 0xe9,0x10,0x0a,0x7e,0x01,0x88,0xc6,0xfa -# GFX10: v_mov_fed_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0x12,0x0a,0x7e,0x01,0x88,0xc6,0xfa] -0xe9,0x12,0x0a,0x7e,0x01,0x88,0xc6,0xfa - # GFX10: v_cvt_f16_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] ; encoding: [0xe9,0x14,0x0a,0x7e,0x01,0x88,0xc6,0xfa] 0xe9,0x14,0x0a,0x7e,0x01,0x88,0xc6,0xfa @@ -268,9 +265,6 @@ # GFX10: v_cvt_i32_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x10,0x0a,0x7e,0x01,0x88,0xc6,0xfa] 0xea,0x10,0x0a,0x7e,0x01,0x88,0xc6,0xfa -# GFX10: v_mov_fed_b32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x12,0x0a,0x7e,0x01,0x88,0xc6,0xfa] -0xea,0x12,0x0a,0x7e,0x01,0x88,0xc6,0xfa - # GFX10: v_cvt_f16_f32_dpp v5, v1 dpp8:[0,1,2,3,4,5,6,7] fi:1 ; encoding: [0xea,0x14,0x0a,0x7e,0x01,0x88,0xc6,0xfa] 0xea,0x14,0x0a,0x7e,0x01,0x88,0xc6,0xfa diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt index 3171355ed3d..d790254a7ae 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt @@ -14295,105 +14295,6 @@ # CHECK: s_abs_i32 s5, 0x3f717273 ; encoding: [0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f] 0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f -# CHECK: s_mov_fed_b32 s5, s1 ; encoding: [0x01,0x31,0x85,0xbe] -0x01,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s101, s1 ; encoding: [0x01,0x31,0xe5,0xbe] -0x01,0x31,0xe5,0xbe - -# CHECK: s_mov_fed_b32 flat_scratch_lo, s1 ; encoding: [0x01,0x31,0xe6,0xbe] -0x01,0x31,0xe6,0xbe - -# CHECK: s_mov_fed_b32 flat_scratch_hi, s1 ; encoding: [0x01,0x31,0xe7,0xbe] -0x01,0x31,0xe7,0xbe - -# CHECK: s_mov_fed_b32 vcc_lo, s1 ; encoding: [0x01,0x31,0xea,0xbe] -0x01,0x31,0xea,0xbe - -# CHECK: s_mov_fed_b32 vcc_hi, s1 ; encoding: [0x01,0x31,0xeb,0xbe] -0x01,0x31,0xeb,0xbe - -# CHECK: s_mov_fed_b32 tba_lo, s1 ; encoding: [0x01,0x31,0xec,0xbe] -0x01,0x31,0xec,0xbe - -# CHECK: s_mov_fed_b32 tba_hi, s1 ; encoding: [0x01,0x31,0xed,0xbe] -0x01,0x31,0xed,0xbe - -# CHECK: s_mov_fed_b32 tma_lo, s1 ; encoding: [0x01,0x31,0xee,0xbe] -0x01,0x31,0xee,0xbe - -# CHECK: s_mov_fed_b32 tma_hi, s1 ; encoding: [0x01,0x31,0xef,0xbe] -0x01,0x31,0xef,0xbe - -# CHECK: s_mov_fed_b32 ttmp11, s1 ; encoding: [0x01,0x31,0xfb,0xbe] -0x01,0x31,0xfb,0xbe - -# CHECK: s_mov_fed_b32 m0, s1 ; encoding: [0x01,0x31,0xfc,0xbe] -0x01,0x31,0xfc,0xbe - -# CHECK: s_mov_fed_b32 exec_lo, s1 ; encoding: [0x01,0x31,0xfe,0xbe] -0x01,0x31,0xfe,0xbe - -# CHECK: s_mov_fed_b32 exec_hi, s1 ; encoding: [0x01,0x31,0xff,0xbe] -0x01,0x31,0xff,0xbe - -# CHECK: s_mov_fed_b32 s5, s101 ; encoding: [0x65,0x31,0x85,0xbe] -0x65,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, flat_scratch_lo ; encoding: [0x66,0x31,0x85,0xbe] -0x66,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, flat_scratch_hi ; encoding: [0x67,0x31,0x85,0xbe] -0x67,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, vcc_lo ; encoding: [0x6a,0x31,0x85,0xbe] -0x6a,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, vcc_hi ; encoding: [0x6b,0x31,0x85,0xbe] -0x6b,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, tba_lo ; encoding: [0x6c,0x31,0x85,0xbe] -0x6c,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, tba_hi ; encoding: [0x6d,0x31,0x85,0xbe] -0x6d,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, tma_lo ; encoding: [0x6e,0x31,0x85,0xbe] -0x6e,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, tma_hi ; encoding: [0x6f,0x31,0x85,0xbe] -0x6f,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, ttmp11 ; encoding: [0x7b,0x31,0x85,0xbe] -0x7b,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, m0 ; encoding: [0x7c,0x31,0x85,0xbe] -0x7c,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, exec_lo ; encoding: [0x7e,0x31,0x85,0xbe] -0x7e,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, exec_hi ; encoding: [0x7f,0x31,0x85,0xbe] -0x7f,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, 0 ; encoding: [0x80,0x31,0x85,0xbe] -0x80,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, -1 ; encoding: [0xc1,0x31,0x85,0xbe] -0xc1,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, 0.5 ; encoding: [0xf0,0x31,0x85,0xbe] -0xf0,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, -4.0 ; encoding: [0xf7,0x31,0x85,0xbe] -0xf7,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, 0xaf123456 ; encoding: [0xff,0x31,0x85,0xbe,0x56,0x34,0x12,0xaf] -0xff,0x31,0x85,0xbe,0x56,0x34,0x12,0xaf - -# CHECK: s_mov_fed_b32 s5, 0x3f717273 ; encoding: [0xff,0x31,0x85,0xbe,0x73,0x72,0x71,0x3f] -0xff,0x31,0x85,0xbe,0x73,0x72,0x71,0x3f - # CHECK: s_set_gpr_idx_idx s1 ; encoding: [0x01,0x32,0x80,0xbe] 0x01,0x32,0x80,0xbe @@ -25011,138 +24912,6 @@ # CHECK: v_cvt_i32_f32_e64 v5, |v1| ; encoding: [0x05,0x01,0x48,0xd1,0x01,0x01,0x00,0x00] 0x05,0x01,0x48,0xd1,0x01,0x01,0x00,0x00 -# CHECK: v_mov_fed_b32_e32 v5, v1 ; encoding: [0x01,0x13,0x0a,0x7e] -0x01,0x13,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v255, v1 ; encoding: [0x01,0x13,0xfe,0x7f] -0x01,0x13,0xfe,0x7f - -# CHECK: v_mov_fed_b32_e32 v5, v255 ; encoding: [0xff,0x13,0x0a,0x7e] -0xff,0x13,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, s1 ; encoding: [0x01,0x12,0x0a,0x7e] -0x01,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, s101 ; encoding: [0x65,0x12,0x0a,0x7e] -0x65,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, flat_scratch_lo ; encoding: [0x66,0x12,0x0a,0x7e] -0x66,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, flat_scratch_hi ; encoding: [0x67,0x12,0x0a,0x7e] -0x67,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, vcc_lo ; encoding: [0x6a,0x12,0x0a,0x7e] -0x6a,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, vcc_hi ; encoding: [0x6b,0x12,0x0a,0x7e] -0x6b,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, tba_lo ; encoding: [0x6c,0x12,0x0a,0x7e] -0x6c,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, tba_hi ; encoding: [0x6d,0x12,0x0a,0x7e] -0x6d,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, tma_lo ; encoding: [0x6e,0x12,0x0a,0x7e] -0x6e,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, tma_hi ; encoding: [0x6f,0x12,0x0a,0x7e] -0x6f,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, ttmp11 ; encoding: [0x7b,0x12,0x0a,0x7e] -0x7b,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, m0 ; encoding: [0x7c,0x12,0x0a,0x7e] -0x7c,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, exec_lo ; encoding: [0x7e,0x12,0x0a,0x7e] -0x7e,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, exec_hi ; encoding: [0x7f,0x12,0x0a,0x7e] -0x7f,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, 0 ; encoding: [0x80,0x12,0x0a,0x7e] -0x80,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, -1 ; encoding: [0xc1,0x12,0x0a,0x7e] -0xc1,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, 0.5 ; encoding: [0xf0,0x12,0x0a,0x7e] -0xf0,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, -4.0 ; encoding: [0xf7,0x12,0x0a,0x7e] -0xf7,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, 0xaf123456 ; encoding: [0xff,0x12,0x0a,0x7e,0x56,0x34,0x12,0xaf] -0xff,0x12,0x0a,0x7e,0x56,0x34,0x12,0xaf - -# CHECK: v_mov_fed_b32_e32 v5, 0x3f717273 ; encoding: [0xff,0x12,0x0a,0x7e,0x73,0x72,0x71,0x3f] -0xff,0x12,0x0a,0x7e,0x73,0x72,0x71,0x3f - -# CHECK: v_mov_fed_b32_e64 v5, v1 ; encoding: [0x05,0x00,0x49,0xd1,0x01,0x01,0x00,0x00] -0x05,0x00,0x49,0xd1,0x01,0x01,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v255, v1 ; encoding: [0xff,0x00,0x49,0xd1,0x01,0x01,0x00,0x00] -0xff,0x00,0x49,0xd1,0x01,0x01,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, v255 ; encoding: [0x05,0x00,0x49,0xd1,0xff,0x01,0x00,0x00] -0x05,0x00,0x49,0xd1,0xff,0x01,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, s1 ; encoding: [0x05,0x00,0x49,0xd1,0x01,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x01,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, s101 ; encoding: [0x05,0x00,0x49,0xd1,0x65,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x65,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, flat_scratch_lo ; encoding: [0x05,0x00,0x49,0xd1,0x66,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x66,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, flat_scratch_hi ; encoding: [0x05,0x00,0x49,0xd1,0x67,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x67,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, vcc_lo ; encoding: [0x05,0x00,0x49,0xd1,0x6a,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x6a,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, vcc_hi ; encoding: [0x05,0x00,0x49,0xd1,0x6b,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x6b,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, tba_lo ; encoding: [0x05,0x00,0x49,0xd1,0x6c,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x6c,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, tba_hi ; encoding: [0x05,0x00,0x49,0xd1,0x6d,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x6d,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, tma_lo ; encoding: [0x05,0x00,0x49,0xd1,0x6e,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x6e,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, tma_hi ; encoding: [0x05,0x00,0x49,0xd1,0x6f,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x6f,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, ttmp11 ; encoding: [0x05,0x00,0x49,0xd1,0x7b,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x7b,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, m0 ; encoding: [0x05,0x00,0x49,0xd1,0x7c,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x7c,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, exec_lo ; encoding: [0x05,0x00,0x49,0xd1,0x7e,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x7e,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, exec_hi ; encoding: [0x05,0x00,0x49,0xd1,0x7f,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x7f,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, 0 ; encoding: [0x05,0x00,0x49,0xd1,0x80,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x80,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, -1 ; encoding: [0x05,0x00,0x49,0xd1,0xc1,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0xc1,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, 0.5 ; encoding: [0x05,0x00,0x49,0xd1,0xf0,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0xf0,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, -4.0 ; encoding: [0x05,0x00,0x49,0xd1,0xf7,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0xf7,0x00,0x00,0x00 - # CHECK: v_cvt_f16_f32_e32 v5, v1 ; encoding: [0x01,0x15,0x0a,0x7e] 0x01,0x15,0x0a,0x7e @@ -94950,135 +94719,6 @@ # CHECK: v_cvt_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00] 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00 -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0xfe,0x7f,0x01,0x06,0x06,0x00] -0xf9,0x12,0xfe,0x7f,0x01,0x06,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0xff,0x06,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0xff,0x06,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x00,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x00,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x01,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x01,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x02,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x02,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x03,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x03,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x04,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x04,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x05,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x05,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x0e,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x0e,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x00,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x00,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x01,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x01,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x02,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x02,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x03,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x03,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x04,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x04,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x05,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x05,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x0e,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x0e,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x00 - -# CHECK: v_mov_fed_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0xfe,0x7f,0x01,0xe4,0x00,0x00] -0xfa,0x12,0xfe,0x7f,0x01,0xe4,0x00,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0xff,0xe4,0x00,0x00] -0xfa,0x12,0x0a,0x7e,0xff,0xe4,0x00,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x1b,0x00,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x1b,0x00,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x40,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x40,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x41,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x41,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x42,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x42,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x43,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x43,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x30,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x30,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x34,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x34,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x38,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x38,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x3c,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x3c,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x01,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x01,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x0f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x0f,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x11,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x11,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x1f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x1f,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x21,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x21,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x2f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x2f,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x10] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x10 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x30] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x30 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x01] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x01 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x03] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x03 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x08,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x08,0x00 - # CHECK: v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00] 0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt index d4552dceb77..c60d4850279 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt @@ -13383,75 +13383,6 @@ # CHECK: s_abs_i32 s5, 0x3f717273 ; encoding: [0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f] 0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f -# CHECK: s_mov_fed_b32 s5, s1 ; encoding: [0x01,0x31,0x85,0xbe] -0x01,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s101, s1 ; encoding: [0x01,0x31,0xe5,0xbe] -0x01,0x31,0xe5,0xbe - -# CHECK: s_mov_fed_b32 flat_scratch_lo, s1 ; encoding: [0x01,0x31,0xe6,0xbe] -0x01,0x31,0xe6,0xbe - -# CHECK: s_mov_fed_b32 flat_scratch_hi, s1 ; encoding: [0x01,0x31,0xe7,0xbe] -0x01,0x31,0xe7,0xbe - -# CHECK: s_mov_fed_b32 vcc_lo, s1 ; encoding: [0x01,0x31,0xea,0xbe] -0x01,0x31,0xea,0xbe - -# CHECK: s_mov_fed_b32 vcc_hi, s1 ; encoding: [0x01,0x31,0xeb,0xbe] -0x01,0x31,0xeb,0xbe - -# CHECK: s_mov_fed_b32 m0, s1 ; encoding: [0x01,0x31,0xfc,0xbe] -0x01,0x31,0xfc,0xbe - -# CHECK: s_mov_fed_b32 exec_lo, s1 ; encoding: [0x01,0x31,0xfe,0xbe] -0x01,0x31,0xfe,0xbe - -# CHECK: s_mov_fed_b32 exec_hi, s1 ; encoding: [0x01,0x31,0xff,0xbe] -0x01,0x31,0xff,0xbe - -# CHECK: s_mov_fed_b32 s5, s101 ; encoding: [0x65,0x31,0x85,0xbe] -0x65,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, flat_scratch_lo ; encoding: [0x66,0x31,0x85,0xbe] -0x66,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, flat_scratch_hi ; encoding: [0x67,0x31,0x85,0xbe] -0x67,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, vcc_lo ; encoding: [0x6a,0x31,0x85,0xbe] -0x6a,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, vcc_hi ; encoding: [0x6b,0x31,0x85,0xbe] -0x6b,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, m0 ; encoding: [0x7c,0x31,0x85,0xbe] -0x7c,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, exec_lo ; encoding: [0x7e,0x31,0x85,0xbe] -0x7e,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, exec_hi ; encoding: [0x7f,0x31,0x85,0xbe] -0x7f,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, 0 ; encoding: [0x80,0x31,0x85,0xbe] -0x80,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, -1 ; encoding: [0xc1,0x31,0x85,0xbe] -0xc1,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, 0.5 ; encoding: [0xf0,0x31,0x85,0xbe] -0xf0,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, -4.0 ; encoding: [0xf7,0x31,0x85,0xbe] -0xf7,0x31,0x85,0xbe - -# CHECK: s_mov_fed_b32 s5, 0xaf123456 ; encoding: [0xff,0x31,0x85,0xbe,0x56,0x34,0x12,0xaf] -0xff,0x31,0x85,0xbe,0x56,0x34,0x12,0xaf - -# CHECK: s_mov_fed_b32 s5, 0x3f717273 ; encoding: [0xff,0x31,0x85,0xbe,0x73,0x72,0x71,0x3f] -0xff,0x31,0x85,0xbe,0x73,0x72,0x71,0x3f - # CHECK: s_set_gpr_idx_idx s1 ; encoding: [0x01,0x32,0x80,0xbe] 0x01,0x32,0x80,0xbe @@ -21651,108 +21582,6 @@ # CHECK: v_cvt_i32_f32_e64 v5, v1 clamp ; encoding: [0x05,0x80,0x48,0xd1,0x01,0x01,0x00,0x00] 0x05,0x80,0x48,0xd1,0x01,0x01,0x00,0x00 -# CHECK: v_mov_fed_b32_e32 v5, v1 ; encoding: [0x01,0x13,0x0a,0x7e] -0x01,0x13,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v255, v1 ; encoding: [0x01,0x13,0xfe,0x7f] -0x01,0x13,0xfe,0x7f - -# CHECK: v_mov_fed_b32_e32 v5, v255 ; encoding: [0xff,0x13,0x0a,0x7e] -0xff,0x13,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, s1 ; encoding: [0x01,0x12,0x0a,0x7e] -0x01,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, s101 ; encoding: [0x65,0x12,0x0a,0x7e] -0x65,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, flat_scratch_lo ; encoding: [0x66,0x12,0x0a,0x7e] -0x66,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, flat_scratch_hi ; encoding: [0x67,0x12,0x0a,0x7e] -0x67,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, vcc_lo ; encoding: [0x6a,0x12,0x0a,0x7e] -0x6a,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, vcc_hi ; encoding: [0x6b,0x12,0x0a,0x7e] -0x6b,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, m0 ; encoding: [0x7c,0x12,0x0a,0x7e] -0x7c,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, exec_lo ; encoding: [0x7e,0x12,0x0a,0x7e] -0x7e,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, exec_hi ; encoding: [0x7f,0x12,0x0a,0x7e] -0x7f,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, 0 ; encoding: [0x80,0x12,0x0a,0x7e] -0x80,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, -1 ; encoding: [0xc1,0x12,0x0a,0x7e] -0xc1,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, 0.5 ; encoding: [0xf0,0x12,0x0a,0x7e] -0xf0,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, -4.0 ; encoding: [0xf7,0x12,0x0a,0x7e] -0xf7,0x12,0x0a,0x7e - -# CHECK: v_mov_fed_b32_e32 v5, 0xaf123456 ; encoding: [0xff,0x12,0x0a,0x7e,0x56,0x34,0x12,0xaf] -0xff,0x12,0x0a,0x7e,0x56,0x34,0x12,0xaf - -# CHECK: v_mov_fed_b32_e32 v5, 0x3f717273 ; encoding: [0xff,0x12,0x0a,0x7e,0x73,0x72,0x71,0x3f] -0xff,0x12,0x0a,0x7e,0x73,0x72,0x71,0x3f - -# CHECK: v_mov_fed_b32_e64 v5, v1 ; encoding: [0x05,0x00,0x49,0xd1,0x01,0x01,0x00,0x00] -0x05,0x00,0x49,0xd1,0x01,0x01,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v255, v1 ; encoding: [0xff,0x00,0x49,0xd1,0x01,0x01,0x00,0x00] -0xff,0x00,0x49,0xd1,0x01,0x01,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, v255 ; encoding: [0x05,0x00,0x49,0xd1,0xff,0x01,0x00,0x00] -0x05,0x00,0x49,0xd1,0xff,0x01,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, s1 ; encoding: [0x05,0x00,0x49,0xd1,0x01,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x01,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, s101 ; encoding: [0x05,0x00,0x49,0xd1,0x65,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x65,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, flat_scratch_lo ; encoding: [0x05,0x00,0x49,0xd1,0x66,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x66,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, flat_scratch_hi ; encoding: [0x05,0x00,0x49,0xd1,0x67,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x67,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, vcc_lo ; encoding: [0x05,0x00,0x49,0xd1,0x6a,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x6a,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, vcc_hi ; encoding: [0x05,0x00,0x49,0xd1,0x6b,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x6b,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, m0 ; encoding: [0x05,0x00,0x49,0xd1,0x7c,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x7c,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, exec_lo ; encoding: [0x05,0x00,0x49,0xd1,0x7e,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x7e,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, exec_hi ; encoding: [0x05,0x00,0x49,0xd1,0x7f,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x7f,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, 0 ; encoding: [0x05,0x00,0x49,0xd1,0x80,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0x80,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, -1 ; encoding: [0x05,0x00,0x49,0xd1,0xc1,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0xc1,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, 0.5 ; encoding: [0x05,0x00,0x49,0xd1,0xf0,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0xf0,0x00,0x00,0x00 - -# CHECK: v_mov_fed_b32_e64 v5, -4.0 ; encoding: [0x05,0x00,0x49,0xd1,0xf7,0x00,0x00,0x00] -0x05,0x00,0x49,0xd1,0xf7,0x00,0x00,0x00 - # CHECK: v_cvt_f16_f32_e32 v5, v1 ; encoding: [0x01,0x15,0x0a,0x7e] 0x01,0x15,0x0a,0x7e @@ -83355,174 +83184,6 @@ # CHECK: v_cvt_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00] 0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00 -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0xfe,0x7f,0x01,0x06,0x06,0x00] -0xf9,0x12,0xfe,0x7f,0x01,0x06,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0xff,0x06,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0xff,0x06,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x65,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x65,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x66,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x66,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x67,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x67,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x6a,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x6a,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x6b,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x6b,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x7c,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x7c,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x7e,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x7e,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x7f,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x7f,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x80,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0x80,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0xc1,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0xc1,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0xf0,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0xf0,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0xf7,0x06,0x86,0x00] -0xf9,0x12,0x0a,0x7e,0xf7,0x06,0x86,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x00,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x00,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x01,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x01,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x02,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x02,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x03,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x03,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x04,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x04,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x05,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x05,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x0e,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x0e,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x16,0x06,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x00,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x00,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x01,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x01,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x02,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x02,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x03,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x03,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x04,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x04,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x05,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x05,0x00 - -# CHECK: v_mov_fed_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x12,0x0a,0x7e,0x01,0x06,0x0e,0x00] -0xf9,0x12,0x0a,0x7e,0x01,0x06,0x0e,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x00 - -# CHECK: v_mov_fed_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0xfe,0x7f,0x01,0xe4,0x00,0x00] -0xfa,0x12,0xfe,0x7f,0x01,0xe4,0x00,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0xff,0xe4,0x00,0x00] -0xfa,0x12,0x0a,0x7e,0xff,0xe4,0x00,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x1b,0x00,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x1b,0x00,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x40,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x40,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x41,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x41,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x42,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x42,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x43,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x43,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x30,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x30,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x34,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x34,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x38,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x38,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x3c,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x3c,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x01,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x01,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x0f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x0f,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x11,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x11,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x1f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x1f,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x21,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x21,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0x2f,0x01,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0x2f,0x01,0x00 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x10] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x10 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x30] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x30 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0xf0 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x01] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x01 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x03] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x03 - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x00,0x0f - -# CHECK: v_mov_fed_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 ; encoding: [0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x08,0x00] -0xfa,0x12,0x0a,0x7e,0x01,0xe4,0x08,0x00 - # CHECK: v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00] 0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00