From: Huihui Zhang Date: Wed, 19 Jun 2019 17:31:39 +0000 (+0000) Subject: [InstCombine] Fold icmp eq/ne (and %x, signbit), 0 -> %x s>=/s< 0 earlier X-Git-Tag: android-x86-9.0-r1~1651 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=3104139a5ba4bccd13dde463032c69c6e8500ada;p=android-x86%2Fexternal-llvm.git [InstCombine] Fold icmp eq/ne (and %x, signbit), 0 -> %x s>=/s< 0 earlier Summary: To generate simplified IR, make sure fold ``` (X & signbit) ==/!= 0) -> X s>=/s< 0; ``` is scheduled before fold ``` ((X << Y) & C) == 0 -> (X & (C >> Y)) == 0. ``` https://rise4fun.com/Alive/fbdh Reviewers: lebedev.ri, efriedma, spatel, craig.topper Reviewed By: lebedev.ri Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363845 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Transforms/InstCombine/InstCombineCompares.cpp b/lib/Transforms/InstCombine/InstCombineCompares.cpp index 0cfd930003a..5493b4a85b3 100644 --- a/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -1626,20 +1626,34 @@ Instruction *InstCombiner::foldICmpAndShift(ICmpInst &Cmp, BinaryOperator *And, Instruction *InstCombiner::foldICmpAndConstConst(ICmpInst &Cmp, BinaryOperator *And, const APInt &C1) { + bool isICMP_NE = Cmp.getPredicate() == ICmpInst::ICMP_NE; + // For vectors: icmp ne (and X, 1), 0 --> trunc X to N x i1 // TODO: We canonicalize to the longer form for scalars because we have // better analysis/folds for icmp, and codegen may be better with icmp. - if (Cmp.getPredicate() == CmpInst::ICMP_NE && Cmp.getType()->isVectorTy() && - C1.isNullValue() && match(And->getOperand(1), m_One())) + if (isICMP_NE && Cmp.getType()->isVectorTy() && C1.isNullValue() && + match(And->getOperand(1), m_One())) return new TruncInst(And->getOperand(0), Cmp.getType()); const APInt *C2; - if (!match(And->getOperand(1), m_APInt(C2))) + Value *X; + if (!match(And, m_And(m_Value(X), m_APInt(C2)))) return nullptr; + // Don't perform the following transforms if the AND has multiple uses if (!And->hasOneUse()) return nullptr; + if (Cmp.isEquality() && C1.isNullValue()) { + // Restrict this fold to single-use 'and' (PR10267). + // Replace (and X, (1 << size(X)-1) != 0) with X s< 0 + if (C2->isSignMask()) { + Constant *Zero = Constant::getNullValue(X->getType()); + auto NewPred = isICMP_NE ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_SGE; + return new ICmpInst(NewPred, X, Zero); + } + } + // If the LHS is an 'and' of a truncate and we can widen the and/compare to // the input width without changing the value produced, eliminate the cast: // @@ -2788,13 +2802,6 @@ Instruction *InstCombiner::foldICmpBinOpEqualityWithConstant(ICmpInst &Cmp, if (!BO->hasOneUse()) break; - // Replace (and X, (1 << size(X)-1) != 0) with x s< 0 - if (BOC->isSignMask()) { - Constant *Zero = Constant::getNullValue(BOp0->getType()); - auto NewPred = isICMP_NE ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_SGE; - return new ICmpInst(NewPred, BOp0, Zero); - } - // ((X & ~7) == 0) --> X < 8 if (C.isNullValue() && (~(*BOC) + 1).isPowerOf2()) { Constant *NegBOC = ConstantExpr::getNeg(cast(BOp1)); diff --git a/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll b/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll index b28ca6c5d26..34cb558818d 100644 --- a/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll +++ b/test/Transforms/InstCombine/lshr-and-signbit-icmpeq-zero.ll @@ -9,9 +9,8 @@ define i1 @scalar_i8_lshr_and_signbit_eq(i8 %x, i8 %y) { ; CHECK-LABEL: @scalar_i8_lshr_and_signbit_eq( -; CHECK-NEXT: [[TMP1:%.*]] = shl i8 -128, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[TMP2]], 0 +; CHECK-NEXT: [[LSHR:%.*]] = lshr i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[LSHR]], -1 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i8 %x, %y @@ -22,9 +21,8 @@ define i1 @scalar_i8_lshr_and_signbit_eq(i8 %x, i8 %y) { define i1 @scalar_i16_lshr_and_signbit_eq(i16 %x, i16 %y) { ; CHECK-LABEL: @scalar_i16_lshr_and_signbit_eq( -; CHECK-NEXT: [[TMP1:%.*]] = shl i16 -32768, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[TMP2]], 0 +; CHECK-NEXT: [[LSHR:%.*]] = lshr i16 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i16 [[LSHR]], -1 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i16 %x, %y @@ -35,9 +33,8 @@ define i1 @scalar_i16_lshr_and_signbit_eq(i16 %x, i16 %y) { define i1 @scalar_i32_lshr_and_signbit_eq(i32 %x, i32 %y) { ; CHECK-LABEL: @scalar_i32_lshr_and_signbit_eq( -; CHECK-NEXT: [[TMP1:%.*]] = shl i32 -2147483648, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[TMP2]], 0 +; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[LSHR]], -1 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i32 %x, %y @@ -48,9 +45,8 @@ define i1 @scalar_i32_lshr_and_signbit_eq(i32 %x, i32 %y) { define i1 @scalar_i64_lshr_and_signbit_eq(i64 %x, i64 %y) { ; CHECK-LABEL: @scalar_i64_lshr_and_signbit_eq( -; CHECK-NEXT: [[TMP1:%.*]] = shl i64 -9223372036854775808, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i64 [[TMP2]], 0 +; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i64 [[LSHR]], -1 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i64 %x, %y @@ -61,9 +57,8 @@ define i1 @scalar_i64_lshr_and_signbit_eq(i64 %x, i64 %y) { define i1 @scalar_i32_lshr_and_signbit_ne(i32 %x, i32 %y) { ; CHECK-LABEL: @scalar_i32_lshr_and_signbit_ne( -; CHECK-NEXT: [[TMP1:%.*]] = shl i32 -2147483648, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP2]], 0 +; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[LSHR]], 0 ; CHECK-NEXT: ret i1 [[R]] ; %lshr = lshr i32 %x, %y @@ -76,9 +71,8 @@ define i1 @scalar_i32_lshr_and_signbit_ne(i32 %x, i32 %y) { define <4 x i1> @vec_4xi32_lshr_and_signbit_eq(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: @vec_4xi32_lshr_and_signbit_eq( -; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> , [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[TMP2]], zeroinitializer +; CHECK-NEXT: [[LSHR:%.*]] = lshr <4 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i32> [[LSHR]], ; CHECK-NEXT: ret <4 x i1> [[R]] ; %lshr = lshr <4 x i32> %x, %y diff --git a/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll b/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll index d9d8f0ea8f0..9fb17cdb97f 100644 --- a/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll +++ b/test/Transforms/InstCombine/shl-and-signbit-icmpeq-zero.ll @@ -9,9 +9,8 @@ define i1 @scalar_i8_shl_and_signbit_eq(i8 %x, i8 %y) { ; CHECK-LABEL: @scalar_i8_shl_and_signbit_eq( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i8 -128, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[TMP2]], 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i8 [[SHL]], -1 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i8 %x, %y @@ -22,9 +21,8 @@ define i1 @scalar_i8_shl_and_signbit_eq(i8 %x, i8 %y) { define i1 @scalar_i16_shl_and_signbit_eq(i16 %x, i16 %y) { ; CHECK-LABEL: @scalar_i16_shl_and_signbit_eq( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i16 -32768, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i16 [[TMP2]], 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i16 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i16 [[SHL]], -1 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i16 %x, %y @@ -35,9 +33,8 @@ define i1 @scalar_i16_shl_and_signbit_eq(i16 %x, i16 %y) { define i1 @scalar_i32_shl_and_signbit_eq(i32 %x, i32 %y) { ; CHECK-LABEL: @scalar_i32_shl_and_signbit_eq( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 -2147483648, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[TMP2]], 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i32 [[SHL]], -1 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i32 %x, %y @@ -48,9 +45,8 @@ define i1 @scalar_i32_shl_and_signbit_eq(i32 %x, i32 %y) { define i1 @scalar_i64_shl_and_signbit_eq(i64 %x, i64 %y) { ; CHECK-LABEL: @scalar_i64_shl_and_signbit_eq( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 -9223372036854775808, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq i64 [[TMP2]], 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt i64 [[SHL]], -1 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i64 %x, %y @@ -61,9 +57,8 @@ define i1 @scalar_i64_shl_and_signbit_eq(i64 %x, i64 %y) { define i1 @scalar_i32_shl_and_signbit_ne(i32 %x, i32 %y) { ; CHECK-LABEL: @scalar_i32_shl_and_signbit_ne( -; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 -2147483648, [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP2]], 0 +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[SHL]], 0 ; CHECK-NEXT: ret i1 [[R]] ; %shl = shl i32 %x, %y @@ -76,9 +71,8 @@ define i1 @scalar_i32_shl_and_signbit_ne(i32 %x, i32 %y) { define <4 x i1> @vec_4xi32_shl_and_signbit_eq(<4 x i32> %x, <4 x i32> %y) { ; CHECK-LABEL: @vec_4xi32_shl_and_signbit_eq( -; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> , [[Y:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i32> [[TMP2]], zeroinitializer +; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i32> [[X:%.*]], [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = icmp sgt <4 x i32> [[SHL]], ; CHECK-NEXT: ret <4 x i1> [[R]] ; %shl = shl <4 x i32> %x, %y