From: Mauro Rossi <issor.oruam@gmail.com>
Date: Sun, 10 Feb 2019 17:33:56 +0000 (+0100)
Subject: android: [AMDGPU] update cpp sources
X-Git-Tag: android-x86-8.1-r6~61
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=31f77a19ac1babb0ecd234c0504e19817441c61c;p=android-x86%2Fexternal-llvm.git

android: [AMDGPU] update cpp sources

Porting of the following commits:

b461f4d ("[AMDGPU] Add an AMDGPU specific atomic optimizer.")
92794ee ("[AMDGPU] Add a pass to promote bitcast calls")
322a807 ("[AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST")
d339265 ("[AMDGPU] Combine DPP mov with use instructions (VOP1/2/3)")
c9d081f ("[AMDGPU] Add new Mode Register pass")
1da08e2 ("[AMDGPU] Add support for TFE/LWE in image intrinsics. 2nd try")
---

diff --git a/lib/Target/AMDGPU/Android.mk b/lib/Target/AMDGPU/Android.mk
index 014ad60958c..04038613fa7 100644
--- a/lib/Target/AMDGPU/Android.mk
+++ b/lib/Target/AMDGPU/Android.mk
@@ -31,7 +31,9 @@ amdgpu_codegen_SRC_FILES := \
   AMDGPUAnnotateUniformValues.cpp \
   AMDGPUArgumentUsageInfo.cpp \
   AMDGPUAsmPrinter.cpp \
+  AMDGPUAtomicOptimizer.cpp \
   AMDGPUCodeGenPrepare.cpp \
+  AMDGPUFixFunctionBitcasts.cpp \
   AMDGPUFrameLowering.cpp \
   AMDGPUHSAMetadataStreamer.cpp \
   AMDGPUInstrInfo.cpp \
@@ -81,9 +83,11 @@ amdgpu_codegen_SRC_FILES := \
   R600OptimizeVectorRegisters.cpp \
   R600Packetizer.cpp \
   R600RegisterInfo.cpp \
+  SIAddIMGInit.cpp \
   SIAnnotateControlFlow.cpp \
   SIDebuggerInsertNops.cpp \
   SIFixSGPRCopies.cpp \
+  SIFixupVectorISel.cpp \
   SIFixVGPRCopies.cpp \
   SIFixWWMLiveness.cpp \
   SIFoldOperands.cpp \
@@ -105,7 +109,9 @@ amdgpu_codegen_SRC_FILES := \
   SIRegisterInfo.cpp \
   SIShrinkInstructions.cpp \
   SIWholeQuadMode.cpp \
-  GCNILPSched.cpp
+  GCNILPSched.cpp \
+  GCNDPPCombine.cpp \
+  SIModeRegister.cpp
 
 ifeq ($(FORCE_BUILD_LLVM_GLOBAL_ISEL),true)
 amdgpu_codegen_TBLGEN_TABLES70 += \