From: Dmitry Baryshkov Date: Sat, 20 May 2023 20:01:03 +0000 (+0300) Subject: drm/msm/dsi: use mult_frac for pclk_bpp calculation X-Git-Tag: v6.5-rc1~28^2~6^2~57^5~6 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=374918d2c396c7099c4bcd04ee044e8b0456afce;p=tomoyo%2Ftomoyo-test1.git drm/msm/dsi: use mult_frac for pclk_bpp calculation Simplify calculations around pixel_clk_rate division. Replace common pattern of doing 64-bit multiplication and then a do_div() call with simpler mult_frac() invocation. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/538273/ Link: https://lore.kernel.org/r/20230520200103.4019607-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 2b257b459974..744f2398a6d6 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -585,7 +585,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_d u8 lanes = msm_host->lanes; u32 bpp = dsi_get_bpp(msm_host->format); unsigned long pclk_rate = dsi_get_pclk_rate(mode, is_bonded_dsi); - u64 pclk_bpp = (u64)pclk_rate * bpp; + unsigned long pclk_bpp; if (lanes == 0) { pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); @@ -594,9 +594,9 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_d /* CPHY "byte_clk" is in units of 16 bits */ if (msm_host->cphy_mode) - do_div(pclk_bpp, (16 * lanes)); + pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); else - do_div(pclk_bpp, (8 * lanes)); + pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); return pclk_bpp; } @@ -627,15 +627,12 @@ int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) { u32 bpp = dsi_get_bpp(msm_host->format); - u64 pclk_bpp; unsigned int esc_mhz, esc_div; unsigned long byte_mhz; dsi_calc_pclk(msm_host, is_bonded_dsi); - pclk_bpp = (u64)msm_host->pixel_clk_rate * bpp; - do_div(pclk_bpp, 8); - msm_host->src_clk_rate = pclk_bpp; + msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); /* * esc clock is byte clock followed by a 4 bit divider,