From: Chen Zheng <shchenz@cn.ibm.com>
Date: Fri, 20 Jul 2018 12:53:45 +0000 (+0000)
Subject: [NFC][testcases] more testcases for folding srem if its two operands are negatived.
X-Git-Tag: android-x86-8.1-r1~589
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=3876c1deaeffab88f7cfb98f69dd9dd09ccb6639;p=android-x86%2Fexternal-llvm.git

[NFC][testcases] more testcases for folding srem if its two operands are negatived.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337543 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/test/Transforms/InstSimplify/srem.ll b/test/Transforms/InstSimplify/srem.ll
index e77b5f96a3b..40062ec6e31 100644
--- a/test/Transforms/InstSimplify/srem.ll
+++ b/test/Transforms/InstSimplify/srem.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instsimplify -S | FileCheck %s
 
 define i32 @negated_operand(i32 %x) {
@@ -47,3 +48,36 @@ define <2 x i32> @knownnegation_commute_vec(<2 x i32> %x, <2 x i32> %y) {
   %rem = srem <2 x i32> %xy, %yx
   ret <2 x i32> %rem
 }
+
+define <3 x i32> @negated_operand_vec_undef(<3 x i32> %x) {
+; CHECK-LABEL: @negated_operand_vec_undef(
+; CHECK-NEXT:    [[NEGX:%.*]] = sub <3 x i32> <i32 0, i32 undef, i32 0>, [[X:%.*]]
+; CHECK-NEXT:    [[REM:%.*]] = srem <3 x i32> [[NEGX]], [[X]]
+; CHECK-NEXT:    ret <3 x i32> [[REM]]
+;
+  %negx = sub <3 x i32> <i32 0, i32 undef, i32 0>, %x
+  %rem = srem <3 x i32> %negx, %x
+  ret <3 x i32> %rem
+}
+
+define <2 x i32> @negated_operand_vec_nonsplat(<2 x i32> %x) {
+; CHECK-LABEL: @negated_operand_vec_nonsplat(
+; CHECK-NEXT:    [[NEGX:%.*]] = sub <2 x i32> <i32 0, i32 1>, [[X:%.*]]
+; CHECK-NEXT:    [[REM:%.*]] = srem <2 x i32> [[NEGX]], [[X]]
+; CHECK-NEXT:    ret <2 x i32> [[REM]]
+;
+  %negx = sub <2 x i32> <i32 0, i32 1>, %x ; not 0, don't fold
+  %rem = srem <2 x i32> %negx, %x
+  ret <2 x i32> %rem
+}
+
+define i32 @negated_operand_commute(i32 %x) {
+; CHECK-LABEL: @negated_operand_commute(
+; CHECK-NEXT:    [[NEGX:%.*]] = sub i32 0, [[X:%.*]]
+; CHECK-NEXT:    [[REM:%.*]] = srem i32 [[X]], [[NEGX]]
+; CHECK-NEXT:    ret i32 [[REM]]
+;
+  %negx = sub i32 0, %x
+  %rem = srem i32 %x, %negx
+  ret i32 %rem
+}